© COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_gpio.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if(GPIOx == GPIOA)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
- }
- else if(GPIOx == GPIOB)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
- }
- else if(GPIOx == GPIOC)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
- }
- else if(GPIOx == GPIOD)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
- }
- else if(GPIOx == GPIOE)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
- }
- else
- {
- if(GPIOx == GPIOF)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
- * contains the configuration information for the specified GPIO
- * peripheral.
- * @note GPIO_Pin: selects the pin to be configured:
- * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
- * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
- * and GPIO_Pin_10 for GPIOF.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
- uint32_t tmpreg = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /*-------------------------- Configure the port pins -----------------------*/
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration */
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- /* Use temporary variable to update PUPDR register configuration, to avoid
- unexpected transition in the GPIO pin configuration. */
- tmpreg = GPIOx->PUPDR;
- tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- GPIOx->PUPDR = tmpreg;
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval The input port pin value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BRR = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enumeration values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port output data
- * register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
- * @brief GPIO Alternate functions configuration functions
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AF: selects the pin to be used as Alternate function.
- * This parameter can be one of the following value:
- * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
- * TRACED, TRACECK.
- * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
- * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
- * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
- * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
- * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
- * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
- * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
- * USART2, USART3.
- * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
- * COMP6_OUT.
- * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
- * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
- * @arg GPIO_AF_11: TIM1, TIM8.
- * @arg GPIO_AF_12: TIM1, HRTIM.
- * @arg GPIO_AF_13: HRTIM, AOP2_OUT.
- * @arg GPIO_AF_14: USBDM, USBDP.
- * @arg GPIO_AF_15: OUT.
- * @note The pin should already been configured in Alternate Function mode(AF)
- * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * @note Refer to the Alternate function mapping table in the device datasheet
- * for the detailed mapping of the system and peripherals alternate
- * function I/O pins.
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_gpio.h b/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_gpio.h
deleted file mode 100644
index 64e998defd9..00000000000
--- a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_gpio.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_gpio.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_GPIO_H
-#define __STM32F30x_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOD))
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
- GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
- GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
- ((SPEED) == GPIO_Speed_Level_3))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternate_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
- MCO, NJTRST, TRACED, TRACECK */
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
- USART1, USART2, USART3 */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
- COMP5_OUT, COMP6_OUT */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
- ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
- ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
- ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
- ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
- ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
- ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
- ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Speed_Legacy
- * @{
- */
-
-#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
-#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.c b/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.c
deleted file mode 100644
index 98808110fc5..00000000000
--- a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.c
+++ /dev/null
@@ -1,1951 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_rcc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
- all peripherals are off except internal SRAM, Flash and SWD.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the SWD pins which
- are assigned to be used for debug purpose.
- [..] Once the device starts from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance).
- (+) Configure the System clock frequency and Flash settings.
- (+) Configure the AHB and APB busses prescalers.
- (+) Enable the clock for the peripheral(s) to be used.
- (+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG).
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of USBPRE bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x04)
-#define USBPRE_BitNumber 0x16
-#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
-/* Alias word address of I2SSRC bit */
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x20)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x24)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CFGR register byte 3 (Bits[31:23]) base address */
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the internal/external
- clocks, PLL, CSS and MCO.
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
- or through the PLL as System clock source.
- The HSI clock can be used also to clock the USART and I2C peripherals.
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- LSE can be used also to clock the USART peripherals.
- (#) PLL (clocked by HSI or HSE), for System clock.
- (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
- PLL clock on PA8 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * @note HSI ON and used as system clock source
- * @note HSE and PLL OFF
- * @note AHB, APB1 and APB2 prescalers set to 1.
- * @note CSS and MCO OFF
- * @note All interrupts disabled
- * @note However, this function doesn't modify the configuration of the
- * @note Peripheral clocks
- * @note LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFC000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
- /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFC000;
-
- /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
- RCC->CFGR3 &= (uint32_t)0xF00ECCC;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function resets the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
-
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This function waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if timeout is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN3300 for more details on how to
- * calibrate the HSI.
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the PLL and/or system clock.
- * @note HSI can not be stopped if it is used directly or through the PLL
- * as system clock. In this case, you have to select another source
- * of the system clock then stop the HSI.
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to this
- * domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEON);
-
- /* Reset LSEBYP bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
-
- /* Configure LSE */
- RCC->BDCR |= RCC_LSE;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE) drive capability.
- * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
- * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
- * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
- * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
- * @retval None
- */
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
-
- /* Clear LSEDRV[1:0] bits */
- RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
-
- /* Set the LSE Drive */
- RCC->BDCR |= RCC_LSEDrive;
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLL clock source and multiplication factor.
- * @note This function must be used only when the PLL is disabled.
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
- * PLL source).
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
- * PLL clock entry
- * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
- * This parameter can be RCC_PLLMul_x where x:[2,16]
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
- /* Clear PLL Source [16] and Multiplier [21:18] bits */
- RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
-
- /* Set the PLL Source and Multiplier */
- RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
-}
-
-/**
- * @brief Enables or disables the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PREDIV1 division factor.
- * @note This function must be used only when the PLL is disabled.
- * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
- * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
- * @retval None
- */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
- tmpreg = RCC->CFGR2;
- /* Clear PREDIV1[3:0] bits */
- tmpreg &= ~(RCC_CFGR2_PREDIV1);
-
- /* Set the PREDIV1 division factor */
- tmpreg |= RCC_PREDIV1_Div;
-
- /* Store the new value */
- RCC->CFGR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-#ifdef STM32F303xC
-/**
- * @brief Selects the clock source to output on MCO pin (PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCO[3:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource */
- tmpreg |= RCC_MCOSource<<24;
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#else
-
-/**
- * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
- * prescsaler.
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
- * This parameter can be one of the following values:
- * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
- * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
- * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
- * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
- * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
- * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
- * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
- * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
- assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCOPRE[2:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource and RCC_MCOPrescaler */
- tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#endif /* STM32F303xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
- Depending on the maximum frequency, the FLASH wait states (WS) should be
- adapted accordingly:
- +---------------------------------+
- | Wait states | HCLK clock |
- | (Latency) | frequency (MHz) |
- |-------------- |-----------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|-----------------|
- |1WS(2CPU cycle)|24 < HCLK <=48 |
- |---------------|-----------------|
- |2WS(3CPU cycle)|48 < HCLK <= 72 |
- +---------------------------------+
-
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
- [..]
- (@) All the peripheral clocks are derived from the System clock (SYSCLK)
- except:
- (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
- (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
- (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
- (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
- (+@) The ADC clock which is derived from PLL output.
- (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
- (HSE divided by a programmable prescaler). The System clock (SYSCLK)
- frequency must be higher or equal to the RTC clock frequency.
- (+@) IWDG clock which is always the LSI clock.
- [..] It is recommended to use the following software sequences to tune the number
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).
- (+) Increasing the CPU frequency
- (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
- function
- (++) Check that Flash Prefetch buffer activation is taken into account by
- reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
- (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (+) Decreasing the CPU frequency
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (++) Program the new number of WS, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
- function
- (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
- using the FLASH_GetPrefetchBufferStatus() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following values:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that the system frequency does not exceed the
- * maximum allowed frequency (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions").
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
- *
- * @note This function returns the frequencies of :
- * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
- * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
- *
- * @note The frequency returned by this function is not the real frequency
- * in the chip. It is calculated based on the predefined constant and
- * the source selected by RCC_SYSCLKConfig().
- *
- * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
- *
- * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
- *
- * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
- *
- * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * return wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
- uint32_t apb2presc = 0, ahbpresc = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- pllclk = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- pllclk = (HSE_VALUE / prediv1factor) * pllmull;
- }
- RCC_Clocks->SYSCLK_Frequency = pllclk;
- break;
- default: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- ahbpresc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 11;
- apb2presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
-
- /* Get ADC12CLK prescaler */
- tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
- tmp = tmp >> 4;
- presc = ADCPrescTable[tmp & 0x0F];
- if (((tmp & 0x10) != 0) && (presc != 0))
- {
- /* ADC12CLK clock frequency is derived from PLL clock */
- RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
- }
- else
- {
- /* ADC12CLK clock frequency is AHB clock */
- RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* Get ADC34CLK prescaler */
- tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
- tmp = tmp >> 9;
- presc = ADCPrescTable[tmp & 0x0F];
- if (((tmp & 0x10) != 0) && (presc != 0))
- {
- /* ADC34CLK clock frequency is derived from PLL clock */
- RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
- }
- else
- {
- /* ADC34CLK clock frequency is AHB clock */
- RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
- {
- /* I2C1 Clock is HSI Osc. */
- RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C1 Clock is System Clock */
- RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
- {
- /* I2C2 Clock is HSI Osc. */
- RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C2 Clock is System Clock */
- RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C3CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
- {
- /* I2C3 Clock is HSI Osc. */
- RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C3 Clock is System Clock */
- RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* TIM1CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM1 Clock is 2 * pllclk */
- RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM1 Clock is APB2 clock. */
- RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM1CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* HRTIM1 Clock is 2 * pllclk */
- RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* HRTIM1 Clock is APB2 clock. */
- RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM8CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM8 Clock is 2 * pllclk */
- RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM8 Clock is APB2 clock. */
- RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM15CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM15 Clock is 2 * pllclk */
- RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM15 Clock is APB2 clock. */
- RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM16CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM16 Clock is 2 * pllclk */
- RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM16 Clock is APB2 clock. */
- RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM17CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM17 Clock is 2 * pllclk */
- RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM17 Clock is APB2 clock. */
- RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* USART1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
- {
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
- /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
- STM32F302/01/34 x4/x6/x8 respective erratasheets) */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
-#else
- /* USART Clock is PCLK2 */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
-#endif
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
- }
-
- /* USART2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
- }
-
- /* USART3CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
- }
-
- /* UART4CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
- }
-
- /* UART5CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the Peripheral clocks.
- (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
- (HSE divided by 32).
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are
- off except internal SRAM, Flash and SWD. Before to start using
- a peripheral you have to enable its interface clock. You can do this
- using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
- and RCC_APB1PeriphClockCmd() functions.
- (#) To reset the peripherals configuration (to the default state after
- device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
- and RCC_APB1PeriphResetCmd() functions.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the ADC clock (ADCCLK).
- * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
- * the PLL Clock.
- * This parameter can be one of the following values:
- * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
- * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
- * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
- * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
- * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
- * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
- * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
- * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
- * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
- * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
- * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
- * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
- * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
- * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
- * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
- * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
- * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
- * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
- * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
- * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
- * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
- * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
- * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
- * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
- * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
- * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
- * @retval None
- */
-void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
-
- tmp = (RCC_PLLCLK >> 28);
-
- /* Clears ADCPRE34 bits */
- if (tmp != 0)
- {
- RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
- }
- /* Clears ADCPRE12 bits */
- else
- {
- RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
- }
- /* Set ADCPRE bits according to RCC_PLLCLK value */
- RCC->CFGR2 |= RCC_PLLCLK;
-}
-
-/**
- * @brief Configures the I2C clock (I2CCLK).
- * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
- * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
- * (x can be 1 or 2 or 3).
- * @retval None
- */
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
-
- tmp = (RCC_I2CCLK >> 28);
-
- /* Clear I2CSW bit */
- switch (tmp)
- {
- case 0x00:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
- break;
- case 0x01:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
- break;
- case 0x02:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
- break;
- default:
- break;
- }
-
- /* Set I2CSW bits according to RCC_I2CCLK value */
- RCC->CFGR3 |= RCC_I2CCLK;
-}
-
-/**
- * @brief Configures the TIMx clock sources(TIMCLK).
- * @note The configuration of the TIMx clock source is only possible when the
- * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
- * @note If one of the previous conditions is missed, the TIM clock source
- * configuration is lost and calling again this function becomes mandatory.
- * @param RCC_TIMCLK: defines the TIMx clock source.
- * This parameter can be one of the following values:
- * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
- * when prescaled)
- * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
- * (x can be 1, 8, 15, 16, 17).
- * @retval None
- */
-void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
-
- tmp = (RCC_TIMCLK >> 28);
-
- /* Clear TIMSW bit */
-
- switch (tmp)
- {
- case 0x00:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
- break;
- case 0x01:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
- break;
- case 0x02:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
- break;
- case 0x03:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
- break;
- case 0x04:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
- break;
- default:
- break;
- }
-
- /* Set I2CSW bits according to RCC_TIMCLK value */
- RCC->CFGR3 |= RCC_TIMCLK;
-}
-
-/**
- * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
- * @note The configuration of the HRTIM1 clock source is only possible when the
- * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
- * @note If one of the previous conditions is missed, the TIM clock source
- * configuration is lost and calling again this function becomes mandatory.
- * @param RCC_HRTIMCLK: defines the TIMx clock source.
- * This parameter can be one of the following values:
- * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
- * when prescaled)
- * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
- * (x can be 1 or 8).
- * @retval None
- */
-void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
-
- /* Clear HRTIMSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
-
- /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
- RCC->CFGR3 |= RCC_HRTIMCLK;
-}
-
-/**
- * @brief Configures the USART clock (USARTCLK).
- * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
- * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
- * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
- * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
- * (x can be 1, 2, 3, 4 or 5).
- * @retval None
- */
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
-
- tmp = (RCC_USARTCLK >> 28);
-
- /* Clear USARTSW[1:0] bit */
- switch (tmp)
- {
- case 0x01: /* clear USART1SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
- break;
- case 0x02: /* clear USART2SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
- break;
- case 0x03: /* clear USART3SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
- break;
- case 0x04: /* clear UART4SW */
- RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
- break;
- case 0x05: /* clear UART5SW */
- RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
- break;
- default:
- break;
- }
-
- /* Set USARTSW bits according to RCC_USARTCLK value */
- RCC->CFGR3 |= RCC_USARTCLK;
-}
-
-/**
- * @brief Configures the USB clock (USBCLK).
- * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
- * derived from the PLL output.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
- * clock source
- * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
- * @retval None
- */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
-
- *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
-}
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the RTC
- * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
- * RTC clock source).
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the SPI2 and SPI3 clocks.
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOF
- * @arg RCC_AHBPeriph_TS
- * @arg RCC_AHBPeriph_CRC
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_SRAM
- * @arg RCC_AHBPeriph_DMA2
- * @arg RCC_AHBPeriph_DMA1
- * @arg RCC_AHBPeriph_ADC34
- * @arg RCC_AHBPeriph_ADC12
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @arg RCC_APB2Periph_TIM15
- * @arg RCC_APB2Periph_TIM16
- * @arg RCC_APB2Periph_TIM17
- * @arg RCC_APB2Periph_TIM1
- * @arg RCC_APB2Periph_TIM8
- * @arg RCC_APB2Periph_HRTIM1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_SPI3
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_UART4
- * @arg RCC_APB1Periph_UART5
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_CAN1
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC1
- * @arg RCC_APB1Periph_DAC2
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB peripheral reset.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOF
- * @arg RCC_AHBPeriph_TS
- * @arg RCC_AHBPeriph_ADC34
- * @arg RCC_AHBPeriph_ADC12
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBRSTR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBRSTR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @arg RCC_APB2Periph_TIM15
- * @arg RCC_APB2Periph_TIM16
- * @arg RCC_APB2Periph_TIM17
- * @arg RCC_APB2Periph_TIM1
- * @arg RCC_APB2Periph_TIM8
- * @arg RCC_APB2Periph_HRTIM1
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_SPI3
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_UART4
- * @arg RCC_APB1Periph_UART5
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_I2C3
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_CAN1
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
- * automatically generated. The NMI will be executed indefinitely, and
- * since NMI has higher priority than any other IRQ (and main program)
- * the application will be stacked in the NMI ISR unless the CSS interrupt
- * pending bit is cleared.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
- * @arg RCC_FLAG_MCOF: MCO Flag
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 0) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 1) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else if (tmp == 4) /* The flag to check is in CFGR register */
- {
- statusreg = RCC->CFGR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
-
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.h b/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.h
deleted file mode 100644
index 189214bd932..00000000000
--- a/lib/main/STM32F3/Drivers/CMSIS/Device/ST/STM32F30x/stm32f30x_rcc.h
+++ /dev/null
@@ -1,699 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_rcc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the RCC
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_RCC_H
-#define __STM32F30x_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SYSCLK_Frequency;
- uint32_t HCLK_Frequency;
- uint32_t PCLK1_Frequency;
- uint32_t PCLK2_Frequency;
- uint32_t ADC12CLK_Frequency;
- uint32_t ADC34CLK_Frequency;
- uint32_t I2C1CLK_Frequency;
- uint32_t I2C2CLK_Frequency;
- uint32_t I2C3CLK_Frequency;
- uint32_t TIM1CLK_Frequency;
- uint32_t HRTIM1CLK_Frequency;
- uint32_t TIM8CLK_Frequency;
- uint32_t USART1CLK_Frequency;
- uint32_t USART2CLK_Frequency;
- uint32_t USART3CLK_Frequency;
- uint32_t UART4CLK_Frequency;
- uint32_t UART5CLK_Frequency;
- uint32_t TIM15CLK_Frequency;
- uint32_t TIM16CLK_Frequency;
- uint32_t TIM17CLK_Frequency;
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-
-#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
-#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
-
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
- ((SOURCE) == RCC_PLLSource_PREDIV1))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_Factor
- * @{
- */
-
-#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
-#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
-#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
-#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
-#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
-#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
-#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
-#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
-#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
-#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
-#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
-#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
-#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
-#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
-#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
- ((MUL) == RCC_PLLMul_16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PREDIV1_division_factor
- * @{
- */
-#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
-#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
-
-#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
- ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
- ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
- ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
- ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
- ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
- ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
- ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_clock_source
- * @{
- */
-
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
-#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
-#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
-#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_ADC_clock_source
- * @{
- */
-
-/* ADC1 & ADC2 */
-#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
-#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
-#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
-#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
-#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
-#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
-#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
-#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
-#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
-#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
-#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
-#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
-#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
-
-/* ADC3 & ADC4 */
-#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
-#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
-#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
-#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
-#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
-#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
-#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
-#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
-#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
-#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
-#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
-#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
-#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
-
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_TIM_clock_source
- * @{
- */
-
-#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
-
-#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
-#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
-
-#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
-#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
-
-#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
-#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
-
-#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
-#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
-
-#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HRTIM_clock_source
- * @{
- */
-
-#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
-#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
-
-#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_I2C_clock_source
- * @{
- */
-
-#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
-#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
-
-#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
-#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
-
-#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
-#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
-
-#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
- ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
- ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USART_clock_source
- * @{
- */
-
-#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
-#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
-#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
-#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
-
-#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
-#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
-#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
-#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
-
-#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
-#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
-#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
-#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
-
-#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
-#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
-#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
-#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
-
-#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
-#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
-#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
-#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
-
-#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
- ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
- ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
- ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
- ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
- ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
- ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
-
-
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_configuration
- * @{
- */
-
-#define RCC_LSE_OFF ((uint32_t)0x00000000)
-#define RCC_LSE_ON RCC_BDCR_LSEON
-#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-
-#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
-
-/** @defgroup RCC_LSE_Drive_Configuration
- * @{
- */
-
-#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
-#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
-#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
-#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
- ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripherals
- * @{
- */
-
-#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
-#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
-#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
-#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
-#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
-#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
-#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
-#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
-#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
-#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
-#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
-#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
-#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
-#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
-#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
-
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Clock_Source
- * @{
- */
-
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)
-#define RCC_MCOSource_LSI ((uint8_t)0x02)
-#define RCC_MCOSource_LSE ((uint8_t)0x03)
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
-#define RCC_MCOSource_HSI ((uint8_t)0x05)
-#define RCC_MCOSource_HSE ((uint8_t)0x06)
-#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
- ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
- ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOPrescaler
- * @{
- */
-
-#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
-#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
-#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
-#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
-#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
-#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
-#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
-#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
-
-#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
- ((PRESCALER) == RCC_MCOPrescaler_2) || \
- ((PRESCALER) == RCC_MCOPrescaler_4) || \
- ((PRESCALER) == RCC_MCOPrescaler_8) || \
- ((PRESCALER) == RCC_MCOPrescaler_16) || \
- ((PRESCALER) == RCC_MCOPrescaler_32) || \
- ((PRESCALER) == RCC_MCOPrescaler_64) || \
- ((PRESCALER) == RCC_MCOPrescaler_128))
-/**
- * @}
- */
-
-/** @defgroup RCC_USB_Device_clock_source
- * @{
- */
-
-#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
-#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
-
-#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
- ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
-#define RCC_FLAG_HSERDY ((uint8_t)0x11)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
-#define RCC_FLAG_MCOF ((uint8_t)0x9C)
-#define RCC_FLAG_LSERDY ((uint8_t)0x21)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_MCOF))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-#ifdef STM32F303xC
- void RCC_MCOConfig(uint8_t RCC_MCOSource);
-#else
- void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
-#endif /* STM32F303xC */
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
-void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
-void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
-
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/Release_Notes.html b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/Release_Notes.html
deleted file mode 100644
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diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h
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-/**
- ******************************************************************************
- * @file stm32f30x_adc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- *
-
-
-
-
-
-
-
-
|
-
© COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_ADC_H
-#define __STM32F30x_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief ADC Init structure definition
- */
-typedef struct
-{
-
- uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
- Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
- This parameter can be a value of @ref ADC_resolution */
- uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
- to digital conversion of regular channels. This parameter
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
- uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
- This parameter can be a value of
- @ref ADC_external_trigger_edge_for_regular_channels_conversion */
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
- This parameter can be a value of @ref ADC_data_align */
- uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
- regular group conversion.
- This parameter can be set to ENABLE or DISABLE. */
- uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
- using the sequencer for regular channel group.
- This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-
-/**
- * @}
- */
-/**
- * @brief ADC Init structure definition
- */
-typedef struct
-{
-
- uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
- to digital conversion of injected channels. This parameter
- can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
- uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
- This parameter can be a value of
- @ref ADC_external_trigger_edge_for_Injected_channels_conversion */
- uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
- using the sequencer for injected channel group.
- This parameter must range from 1 to 4. */
- uint32_t ADC_InjecSequence1;
- uint32_t ADC_InjecSequence2;
- uint32_t ADC_InjecSequence3;
- uint32_t ADC_InjecSequence4;
-}ADC_InjectedInitTypeDef;
-
-/**
- * @}
- */
-typedef struct
-{
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in
- independent or multi mode.
- This parameter can be a value of @ref ADC_mode */
- uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
- and slave ADCs.
- This parameter can be a value of @ref ADC_Clock */
- uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
- This parameter can be a value of
- @ref ADC_Direct_memory_access_mode_for_multi_mode */
- uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
- This parameter can be a value of @ref ADC_DMA_Mode_definition */
- uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value between 0x0 and 0xF */
-
-}ADC_CommonInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC2) || \
- ((PERIPH) == ADC3) || \
- ((PERIPH) == ADC4))
-
-#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
- ((PERIPH) == ADC2) || \
- ((PERIPH) == ADC3) || \
- ((PERIPH) == ADC4))
-
-/** @defgroup ADC_ContinuousConvMode
- * @{
- */
-#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
-#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
-#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
- ((MODE) == ADC_ContinuousConvMode_Disable))
-/**
- * @}
- */
-/** @defgroup ADC_OverunMode
- * @{
- */
-#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
-#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
-#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
- ((MODE) == ADC_OverrunMode_Disable))
-/**
- * @}
- */
-/** @defgroup ADC_AutoInjecMode
- * @{
- */
-#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
-#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
-#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
- ((MODE) == ADC_AutoInjec_Disable))
-/**
- * @}
- */
-/** @defgroup ADC_resolution
- * @{
- */
-#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
-#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
-#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
-#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
- ((RESOLUTION) == ADC_Resolution_10b) || \
- ((RESOLUTION) == ADC_Resolution_8b) || \
- ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
-#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
-#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
-#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
-
-#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
- ((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
- ((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
- ((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
-#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
-#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
-#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
-
-#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
- ((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
- ((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
- ((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
-
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
- * @{
- */
-#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
-#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
-#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
-#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
-#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
-#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
-#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
-#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
-#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
-#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
-#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
-#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
-#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
-#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
-#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
-#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
-
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
- ((REGTRIG) == ADC_ExternalTrigConvEvent_15))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
- * @{
- */
-
-#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
-#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
-#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
-#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
-#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
-#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
-#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
-#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
-#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
-#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
-#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
-#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
-#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
-#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
-#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
-#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
-
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
- ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
-/**
- * @}
- */
-/** @defgroup ADC_data_align
- * @{
- */
-
-#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
-#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-/** @defgroup ADC_channels
- * @{
- */
-
-#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
-#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
-#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
-#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
-#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
-#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
-#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
-#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
-#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
-#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
-#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
-#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
-#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
-#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
-#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
-#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
-#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
-#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
-
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
-#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
- ((CHANNEL) == ADC_Channel_2) || \
- ((CHANNEL) == ADC_Channel_3) || \
- ((CHANNEL) == ADC_Channel_4) || \
- ((CHANNEL) == ADC_Channel_5) || \
- ((CHANNEL) == ADC_Channel_6) || \
- ((CHANNEL) == ADC_Channel_7) || \
- ((CHANNEL) == ADC_Channel_8) || \
- ((CHANNEL) == ADC_Channel_9) || \
- ((CHANNEL) == ADC_Channel_10) || \
- ((CHANNEL) == ADC_Channel_11) || \
- ((CHANNEL) == ADC_Channel_12) || \
- ((CHANNEL) == ADC_Channel_13) || \
- ((CHANNEL) == ADC_Channel_14) || \
- ((CHANNEL) == ADC_Channel_15) || \
- ((CHANNEL) == ADC_Channel_16) || \
- ((CHANNEL) == ADC_Channel_17) || \
- ((CHANNEL) == ADC_Channel_18))
-#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
- ((CHANNEL) == ADC_Channel_2) || \
- ((CHANNEL) == ADC_Channel_3) || \
- ((CHANNEL) == ADC_Channel_4) || \
- ((CHANNEL) == ADC_Channel_5) || \
- ((CHANNEL) == ADC_Channel_6) || \
- ((CHANNEL) == ADC_Channel_7) || \
- ((CHANNEL) == ADC_Channel_8) || \
- ((CHANNEL) == ADC_Channel_9) || \
- ((CHANNEL) == ADC_Channel_10) || \
- ((CHANNEL) == ADC_Channel_11) || \
- ((CHANNEL) == ADC_Channel_12) || \
- ((CHANNEL) == ADC_Channel_13) || \
- ((CHANNEL) == ADC_Channel_14))
-/**
- * @}
- */
-
-/** @defgroup ADC_mode
- * @{
- */
-#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
-#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
-#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
-#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
-#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
-#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
-#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
- ((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
- ((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
- ((MODE) == ADC_Mode_InjSimul) || \
- ((MODE) == ADC_Mode_RegSimul) || \
- ((MODE) == ADC_Mode_Interleave) || \
- ((MODE) == ADC_Mode_AltTrig))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Clock
- * @{
- */
-#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
-#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
-#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
-#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
-#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
- ((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
- ((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
- ((CLOCK) == ADC_Clock_SynClkModeDiv4))
-/**
- * @}
- */
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
- * @{
- */
-#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
-#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
-#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
- ((MODE) == ADC_DMAAccessMode_1) || \
- ((MODE) == ADC_DMAAccessMode_2))
-
-/**
- * @}
- */
-/** @defgroup ADC_sampling_time
- * @{
- */
-
-#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
-#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
-#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
-#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
-#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
-#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
-#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
-#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
- ((TIME) == ADC_SampleTime_2Cycles5) || \
- ((TIME) == ADC_SampleTime_4Cycles5) || \
- ((TIME) == ADC_SampleTime_7Cycles5) || \
- ((TIME) == ADC_SampleTime_19Cycles5) || \
- ((TIME) == ADC_SampleTime_61Cycles5) || \
- ((TIME) == ADC_SampleTime_181Cycles5) || \
- ((TIME) == ADC_SampleTime_601Cycles5))
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_Channel_selection
- * @{
- */
-
-#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
-#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
-#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
-#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
-#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
-#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
-#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
-#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
-#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
-#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
-#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
-#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
-#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
-#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
-#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
-#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
-#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
-#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
-
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
- ((CHANNEL) == ADC_InjectedChannel_2) || \
- ((CHANNEL) == ADC_InjectedChannel_3) || \
- ((CHANNEL) == ADC_InjectedChannel_4) ||\
- ((CHANNEL) == ADC_InjectedChannel_5) ||\
- ((CHANNEL) == ADC_InjectedChannel_6) ||\
- ((CHANNEL) == ADC_InjectedChannel_7) ||\
- ((CHANNEL) == ADC_InjectedChannel_8) ||\
- ((CHANNEL) == ADC_InjectedChannel_9) ||\
- ((CHANNEL) == ADC_InjectedChannel_10) ||\
- ((CHANNEL) == ADC_InjectedChannel_11) ||\
- ((CHANNEL) == ADC_InjectedChannel_12) ||\
- ((CHANNEL) == ADC_InjectedChannel_13) ||\
- ((CHANNEL) == ADC_InjectedChannel_14) ||\
- ((CHANNEL) == ADC_InjectedChannel_15) ||\
- ((CHANNEL) == ADC_InjectedChannel_16) ||\
- ((CHANNEL) == ADC_InjectedChannel_17) ||\
- ((CHANNEL) == ADC_InjectedChannel_18))
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_Sequence_selection
- * @{
- */
-
-#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
-#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
-#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
-#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
-#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
- ((SEQUENCE) == ADC_InjectedSequence_2) || \
- ((SEQUENCE) == ADC_InjectedSequence_3) || \
- ((SEQUENCE) == ADC_InjectedSequence_4))
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
-
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
- ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
- * @}
- */
-
-/** @defgroup ADC_Calibration_Mode_definition
- * @{
- */
-#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
-#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
-
-#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_DMA_Mode_definition
- * @{
- */
-#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
-#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
-
-#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-
-#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
-#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
-#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
-#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
-#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
-#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
-
-
-#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
- ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
- ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
- ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
- ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
- ((IT) == ADC_IT_JQOVF))
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-
-#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
-#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
-#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
-#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
-#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
-#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
-#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
-
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
- ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
- ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
- ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
- ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
- ((FLAG) == ADC_FLAG_JQOVF))
-/**
- * @}
- */
-
-/** @defgroup ADC_Common_flags_definition
- * @{
- */
-
-#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
-#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
-#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
-#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
-#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
-#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
-#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
-#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
-#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
-#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
-#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
-
-#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
-#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
-#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
-#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
-#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
-#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
-#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
-#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
-#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
-#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
-#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
-
-#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
-#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
- ((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
- ((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
- ((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
- ((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
- ((FLAG) == ADC_FLAG_MSTJQOVF) || \
- ((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
- ((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
- ((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
- ((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
- ((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
- ((FLAG) == ADC_FLAG_SLVJQOVF))
-/**
- * @}
- */
-
-/** @defgroup ADC_thresholds
- * @{
- */
-
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_offset
- * @{
- */
-
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_length
- * @{
- */
-
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_regular_length
- * @{
- */
-
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number
- * @{
- */
-
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_two_sampling_delay_number
- * @{
- */
-#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(ADC_TypeDef* ADCx);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
-void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
-void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_StartCalibration(ADC_TypeDef* ADCx);
-uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
-void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
-void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
-void ADC_DisableCmd(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
-void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
-void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
-void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
-void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
-void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and Vbat management function */
-void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
-void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
-
-void ADC_StartConversion(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
-void ADC_StopConversion(ADC_TypeDef* ADCx);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
-
-void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
-void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
-void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
-void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
-
-void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
-void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
-void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* ADC Dual Modes Configuration functions *************************************/
-FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_can.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_can.h
deleted file mode 100644
index 2303f9acd83..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_can.h
+++ /dev/null
@@ -1,643 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_can.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_CAN_H
-#define __STM32F30x_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
- It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter can be a value of
- @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be transmitted. This parameter can be a value
- of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will
- be transmitted. This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value between
- 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
- to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be received. This parameter can be a value of
- @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
- 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in
- the mailbox passes through. This parameter can be a
- value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_InitStatus
- * @{
- */
-
-#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED CAN_InitStatus_Failed
-#define CANINITOK CAN_InitStatus_Success
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
- ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || \
- ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-
- /**
- * @defgroup CAN_operating_mode
- * @{
- */
-#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
- ((MODE) == CAN_OperatingMode_Normal)|| \
- ((MODE) == CAN_OperatingMode_Sleep))
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_operating_mode_status
- * @{
- */
-
-#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_Filter_FIFO0
-#define CAN_FilterFIFO1 CAN_Filter_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
- ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD CAN_Id_Standard
-#define CAN_ID_EXT CAN_Id_Extended
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA CAN_RTR_Data
-#define CAN_RTR_REMOTE CAN_RTR_Remote
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
- an empty mailbox */
-/* Legacy defines */
-#define CANTXFAILED CAN_TxStatus_Failed
-#define CANTXOK CAN_TxStatus_Ok
-#define CANTXPENDING CAN_TxStatus_Pending
-#define CAN_NO_MB CAN_TxStatus_NoMailBox
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */
-#define CANSLEEPFAILED CAN_Sleep_Failed
-#define CANSLEEPOK CAN_Sleep_Ok
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED CAN_WakeUp_Failed
-#define CANWAKEUPOK CAN_WakeUp_Ok
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Code_constants
- * @{
- */
-#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
-#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CAN configuration to the default reset state *****/
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_CAN_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h
deleted file mode 100644
index ce41a21e11c..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_comp.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the COMP firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_COMP_H
-#define __STM32F30x_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup COMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief COMP Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
- This parameter can be a value of @ref COMP_InvertingInput */
-
- uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
- This parameter can be a value of @ref COMP_NonInvertingInput */
-
- uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
- This parameter can be a value of @ref COMP_Output */
-
- uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
- This parameter can be a value of @ref COMP_BlankingSrce */
-
- uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
- This parameter can be a value of @ref COMP_OutputPoloarity */
-
- uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
- This parameter can be a value of @ref COMP_Hysteresis */
-
- uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
- and allows to adjust the speed/consumption.
- This parameter can be a value of @ref COMP_Mode */
-}COMP_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Constants
- * @{
- */
-
-/** @defgroup COMP_Selection
- * @{
- */
-
-#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
-#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
-#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
-#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
-#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
-#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
-#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
-
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
- ((PERIPH) == COMP_Selection_COMP2) || \
- ((PERIPH) == COMP_Selection_COMP3) || \
- ((PERIPH) == COMP_Selection_COMP4) || \
- ((PERIPH) == COMP_Selection_COMP5) || \
- ((PERIPH) == COMP_Selection_COMP6) || \
- ((PERIPH) == COMP_Selection_COMP7))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_InvertingInput
- * @{
- */
-
-#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
-#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
-
-#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
- PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
- PC0 for COMP7) connected to comparator inverting input */
-
-#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
- PB15 for COMP6) connected to comparator inverting input */
-
-#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
-
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
- ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_VREFINT) || \
- ((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
- ((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
- ((INPUT) == COMP_InvertingInput_IO1) || \
- ((INPUT) == COMP_InvertingInput_IO2) || \
- ((INPUT) == COMP_InvertingInput_DAC2OUT1))
-/**
- * @}
- */
-
-/** @defgroup COMP_NonInvertingInput
- * @{
- */
-
-#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
- PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
- PA0 for COMP7) connected to comparator non inverting input */
-
-#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
- PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
-
-#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
- ((INPUT) == COMP_NonInvertingInput_IO2))
-/**
- * @}
- */
-
-/** @defgroup COMP_Output
- * @{
- */
-
-#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
-
-/* Output Redirection common for all comparators COMP1...COMP7 */
-#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
-#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
-#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
-#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
-#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
-
-/* Output Redirection common for COMP1 and COMP2 */
-#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
-#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
-#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
-#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
-#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
-#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
-
-/* Output Redirection specific to COMP2 */
-#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
-#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
-#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
-
-/* Output Redirection specific to COMP3 */
-#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
-#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
-#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
-#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
-
-/* Output Redirection specific to COMP4 */
-#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
-#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
-#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
-#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
-#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
-
-#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
-#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
-#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
-
-/* Output Redirection specific to COMP5 */
-#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
-#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
-#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
-#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
-
-/* Output Redirection specific to COMP6 */
-#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
-#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
-#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
-#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
-#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
-
-#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
-#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
-#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
-
-/* Output Redirection specific to COMP7 */
-#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
-#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
-#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
-#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
- ((OUTPUT) == COMP_Output_TIM1BKIN) || \
- ((OUTPUT) == COMP_Output_TIM1IC1) || \
- ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM2IC4) || \
- ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM3IC1) || \
- ((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM8BKIN) || \
- ((OUTPUT) == COMP_Output_TIM1BKIN2) || \
- ((OUTPUT) == COMP_Output_TIM8BKIN2) || \
- ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_Output_TIM3IC2) || \
- ((OUTPUT) == COMP_Output_TIM4IC1) || \
- ((OUTPUT) == COMP_Output_TIM15IC1) || \
- ((OUTPUT) == COMP_Output_TIM15BKIN) || \
- ((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM3IC3) || \
- ((OUTPUT) == COMP_Output_TIM4IC1) || \
- ((OUTPUT) == COMP_Output_TIM15IC1) || \
- ((OUTPUT) == COMP_Output_TIM2IC1) || \
- ((OUTPUT) == COMP_Output_TIM4IC3) || \
- ((OUTPUT) == COMP_Output_TIM16BKIN) || \
- ((OUTPUT) == COMP_Output_TIM17IC1) || \
- ((OUTPUT) == COMP_Output_TIM2IC2) || \
- ((OUTPUT) == COMP_Output_TIM16IC1) || \
- ((OUTPUT) == COMP_Output_TIM4IC4) || \
- ((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM2IC3) || \
- ((OUTPUT) == COMP_Output_TIM1IC2) || \
- ((OUTPUT) == COMP_Output_TIM17BKIN) || \
- ((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
- ((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
- ((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
- ((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
- ((OUTPUT) == COMP_Output_HRTIM1_EE8_2))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_BlankingSrce
- * @{
- */
-
-/* No blanking source can be selected for all comparators */
-#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
-
-/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
-
-/* Blanking source common for COMP1 and COMP2 */
-#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
-
-/* Blanking source common for COMP1, COMP2 and COMP5 */
-#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
-
-/* Blanking source common for COMP3 and COMP6 */
-#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
-
-/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
-
-/* Blanking source for COMP4 */
-#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
-#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
-
-/* Blanking source common for COMP6 and COMP7 */
-#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
-
-#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
- ((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
- ((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
- ((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
- ((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
- ((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
- ((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
- ((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
- ((SOURCE) == COMP_BlankingSrce_TIM15OC2))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputPoloarity
- * @{
- */
-#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
-#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
-
-#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
- ((POL) == COMP_OutputPol_Inverted))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Hysteresis
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the hysteresis level */
-#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
-#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
-#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
-#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
- ((HYSTERESIS) == COMP_Hysteresis_Low) || \
- ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
- ((HYSTERESIS) == COMP_Hysteresis_High))
-/**
- * @}
- */
-
-/** @defgroup COMP_Mode
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the power consumption values */
-#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
-#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
-#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
-#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
- ((MODE) == COMP_Mode_LowPower) || \
- ((MODE) == COMP_Mode_MediumSpeed) || \
- ((MODE) == COMP_Mode_HighSpeed))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputLevel
- * @{
- */
-/* When output polarity is not inverted, comparator output is high when
- the non-inverting input is at a higher voltage than the inverting input */
-#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
-/* When output polarity is not inverted, comparator output is low when
- the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup COMP_WindowMode
- * @{
- */
-#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
- ((WINDOW) == COMP_Selection_COMP4) || \
- ((WINDOW) == COMP_Selection_COMP6))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the COMP configuration to the default reset state ****/
-void COMP_DeInit(uint32_t COMP_Selection);
-
-/* Initialization and Configuration functions *********************************/
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
-void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
-
-/* Window mode control function ***********************************************/
-void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
-
-/* COMP configuration locking function ****************************************/
-void COMP_LockConfig(uint32_t COMP_Selection);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_COMP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h
deleted file mode 100644
index 1b4d4b692dd..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_crc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_CRC_H
-#define __STM32F30x_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_ReverseInputData
- * @{
- */
-#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
-#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
-#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
-#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
-
-#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
- ((DATA) == CRC_ReverseInputData_8bits) || \
- ((DATA) == CRC_ReverseInputData_16bits) || \
- ((DATA) == CRC_ReverseInputData_32bits))
-
-/**
- * @}
- */
-
-/** @defgroup CRC_PolynomialSize
- * @{
- */
-#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
-#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
-#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
-#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
-
-#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
- ((SIZE) == CRC_PolSize_8) || \
- ((SIZE) == CRC_PolSize_16) || \
- ((SIZE) == CRC_PolSize_32))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRC computation unit **********************************/
-void CRC_DeInit(void);
-void CRC_ResetDR(void);
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
-void CRC_ReverseOutputDataCmd(FunctionalState NewState);
-void CRC_SetInitRegister(uint32_t CRC_InitValue);
-void CRC_SetPolynomial(uint32_t CRC_Pol);
-
-/* CRC computation ************************************************************/
-uint32_t CRC_CalcCRC(uint32_t CRC_Data);
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-
-/* Independent register (IDR) access (write/read) *****************************/
-void CRC_SetIDRegister(uint8_t CRC_IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_CRC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h
deleted file mode 100644
index ce8ddefc59d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dac.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_DAC_H
-#define __STM32F30x_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
- uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
- the DAC channel output switch is enabled or disabled.
- This parameter can be a value of @ref DAC_buffer_switch */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
- ((PERIPH) == DAC2))
-
-#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
-
-/** @defgroup DAC_trigger_selection
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
-#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
- ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
- ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
- ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_buffer_switch
- * @{
- */
-
-#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
-#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
-
-#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
- ((STATE) == DAC_BufferSwitch_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignement
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(DAC_TypeDef* DACx);
-
-/* DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
-void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h
deleted file mode 100644
index f518236128d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dbgmcu.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_DBGMCU_H
-#define __STM32F30x_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)
-#define DBGMCU_STOP ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
-#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
-
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
-#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
-#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/* Device and Revision ID management functions ********************************/
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-
-/* Peripherals Configuration functions ****************************************/
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_DBGMCU_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dma.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dma.h
deleted file mode 100644
index b63d0ab43d8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dma.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dma.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_DMA_H
-#define __STM32F30x_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA Init structures definition
- */
-typedef struct
-{
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
-
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
-
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction. */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_circular_normal_mode
- @note: The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
- This parameter can be a value of @ref DMA_memory_to_memory */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
- ((PERIPH) == DMA1_Channel2) || \
- ((PERIPH) == DMA1_Channel3) || \
- ((PERIPH) == DMA1_Channel4) || \
- ((PERIPH) == DMA1_Channel5) || \
- ((PERIPH) == DMA1_Channel6) || \
- ((PERIPH) == DMA1_Channel7) || \
- ((PERIPH) == DMA2_Channel1) || \
- ((PERIPH) == DMA2_Channel2) || \
- ((PERIPH) == DMA2_Channel3) || \
- ((PERIPH) == DMA2_Channel4) || \
- ((PERIPH) == DMA2_Channel5))
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
-#define DMA_DIR_PeripheralDST DMA_CCR_DIR
-
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
- ((DIR) == DMA_DIR_PeripheralDST))
-/**
- * @}
- */
-
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-#define DMA_PeripheralInc_Enable DMA_CCR_PINC
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
- ((STATE) == DMA_PeripheralInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-#define DMA_MemoryInc_Enable DMA_CCR_MINC
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
- ((STATE) == DMA_MemoryInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
-#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
-#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define DMA_Mode_Circular DMA_CCR_CIRC
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
-/**
- * @}
- */
-
-/** @defgroup DMA_priority_level
- * @{
- */
-
-#define DMA_Priority_VeryHigh DMA_CCR_PL
-#define DMA_Priority_High DMA_CCR_PL_1
-#define DMA_Priority_Medium DMA_CCR_PL_0
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_Low))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_to_memory
- * @{
- */
-
-#define DMA_M2M_Disable ((uint32_t)0x00000000)
-#define DMA_M2M_Enable DMA_CCR_MEM2MEM
-
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupts_definition
- * @{
- */
-
-#define DMA_IT_TC ((uint32_t)0x00000002)
-#define DMA_IT_HT ((uint32_t)0x00000004)
-#define DMA_IT_TE ((uint32_t)0x00000008)
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)
-
-#define DMA2_IT_GL1 ((uint32_t)0x10000001)
-#define DMA2_IT_TC1 ((uint32_t)0x10000002)
-#define DMA2_IT_HT1 ((uint32_t)0x10000004)
-#define DMA2_IT_TE1 ((uint32_t)0x10000008)
-#define DMA2_IT_GL2 ((uint32_t)0x10000010)
-#define DMA2_IT_TC2 ((uint32_t)0x10000020)
-#define DMA2_IT_HT2 ((uint32_t)0x10000040)
-#define DMA2_IT_TE2 ((uint32_t)0x10000080)
-#define DMA2_IT_GL3 ((uint32_t)0x10000100)
-#define DMA2_IT_TC3 ((uint32_t)0x10000200)
-#define DMA2_IT_HT3 ((uint32_t)0x10000400)
-#define DMA2_IT_TE3 ((uint32_t)0x10000800)
-#define DMA2_IT_GL4 ((uint32_t)0x10001000)
-#define DMA2_IT_TC4 ((uint32_t)0x10002000)
-#define DMA2_IT_HT4 ((uint32_t)0x10004000)
-#define DMA2_IT_TE4 ((uint32_t)0x10008000)
-#define DMA2_IT_GL5 ((uint32_t)0x10010000)
-#define DMA2_IT_TC5 ((uint32_t)0x10020000)
-#define DMA2_IT_HT5 ((uint32_t)0x10040000)
-#define DMA2_IT_TE5 ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
- ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
- ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
- ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
- ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
- ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
- ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
- ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
- ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
- ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
- ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
-
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
- ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
- ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
- ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
- ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
- ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
- ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
- ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
- ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
- ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
- ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DMA configuration to the default reset state ******/
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-
-/* Data Counter functions******************************************************/
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Interrupts and flags management functions **********************************/
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
-void DMA_ClearFlag(uint32_t DMAy_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
-void DMA_ClearITPendingBit(uint32_t DMAy_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_DMA_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_exti.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_exti.h
deleted file mode 100644
index ed1f0c2fdd4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_exti.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_exti.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the EXTI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_EXTI_H
-#define __STM32F30x_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTITrigger_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
- Connected to the PVD Output */
-#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
- Connected to the RTC Alarm
- event */
-#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
- Connected to the USB Device
- Wakeup from suspend event */
-#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
- Connected to the RTC Tamper
- and Time Stamp events */
-#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
- Connected to the RTC wakeup
- event */
-#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
- Connected to the Comparator 1
- event */
-#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
- Connected to the Comparator 2
- event */
-#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
- Connected to the I2C1 wakeup
- event */
-#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
- Connected to the I2C2 wakeup
- event */
-#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
- Connected to the USART1 wakeup
- event */
-#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
- Connected to the USART2 wakeup
- event */
-#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
- reserved */
-#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
- Connected to the USART3 wakeup
- event */
-#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
- Connected to the Comparator 3
- event */
-#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
- Connected to the Comparator 4
- event */
-#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
- Connected to the Comparator 5
- event */
-#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
- Connected to the Comparator 6
- event */
-#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
- Connected to the Comparator 7
- event */
-#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
- Connected to the USART4 wakeup
- event */
-#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
- Connected to the USART5 wakeup
- event */
-
-#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
-#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
- ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
- ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
- ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
- ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_EXTI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_flash.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_flash.h
deleted file mode 100644
index af988f018e0..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_flash.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_flash.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_FLASH_H
-#define __STM32F30x_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup Flash_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
-#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1) || \
- ((LATENCY) == FLASH_Latency_2))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-
-#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
-#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-/**
- * @}
- */
-/** @defgroup FLASH_Address
- * @{
- */
-
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_DATA_ADDRESS
- * @{
- */
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Write_Protection
- * @{
- */
-
-#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
-#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
-#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
-#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
-#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
-#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
-#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
-#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
-#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
-#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
-#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
-#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
-#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
-#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
-#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
-#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
-#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
-
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Read_Protection
- * @{
- */
-
-/**
- * @brief Read Protection Level
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0xBB)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_IWatchdog
- * @{
- */
-
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STOP
- * @{
- */
-
-#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STDBY
- * @{
- */
-
-#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-/**
- * @}
- */
-/** @defgroup Option_Bytes_BOOT1
- * @{
- */
-
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-/**
- * @}
- */
-/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
- * @{
- */
-
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
- * @{
- */
-
-#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
-#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
-
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
-/**
- * @}
- */
-/** @defgroup Timeout_definition
- * @{
- */
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-/* Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_Launch(void);
-FLASH_Status FLASH_OB_Erase(void);
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-uint8_t FLASH_OB_GetUser(void);
-uint32_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-
-/* Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h
deleted file mode 100644
index 64e998defd9..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_gpio.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_GPIO_H
-#define __STM32F30x_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOD))
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
- GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
- GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
- ((SPEED) == GPIO_Speed_Level_3))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternate_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
- MCO, NJTRST, TRACED, TRACECK */
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
- USART1, USART2, USART3 */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
- COMP5_OUT, COMP6_OUT */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
- ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
- ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
- ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
- ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
- ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
- ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
- ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Speed_Legacy
- * @{
- */
-
-#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
-#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_hrtim.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_hrtim.h
deleted file mode 100644
index 39dea380b70..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_hrtim.h
+++ /dev/null
@@ -1,2746 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_hrtim.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the HRTIM firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_HRTIM_H
-#define __STM32F30x_HRTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HRTIM Configuration Structure definition - Time base related parameters
- */
-typedef struct
-{
- uint32_t Period; /*!< Specifies the timer period
- The period value must be above 3 periods of the fHRTIM clock.
- Maximum value is = 0xFFDF */
- uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
- uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
- This parameter can be any value of @ref HRTIM_PrescalerRatio */
- uint32_t Mode; /*!< Specifies the counter operating mode
- This parameter can be any value of @ref HRTIM_Mode */
-} HRTIM_BaseInitTypeDef;
-/**
- * @brief Waveform mode initialization parameters definition
- */
-typedef struct {
- uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
- This parameter can be a combination of @ref HRTIM_HalfModeEnable */
- uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
- This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
- uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
- This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
- uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
- This parameter can be any value of @ref HRTIM_DACSynchronization */
- uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
- This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
- uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
- update enable inputs (Slave timers only)
- This parameter can be any value of @ref HRTIM_UpdateGating */
- uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
- This parameter can be a combination of @ref HRTIM_TimerBurstMode */
- uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
- This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
-} HRTIM_TimerInitTypeDef;
-
-/**
- * @brief Basic output compare mode configuration definition
- */
-typedef struct {
- uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
- This parameter can be a combination of @ref HRTIM_BasicOCMode */
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_OutputIDLEState */
-} HRTIM_BasicOCChannelCfgTypeDef;
-
-/**
- * @brief Basic PWM output mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_OutputPolarity */
- uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_OutputIDLEState */
-} HRTIM_BasicPWMChannelCfgTypeDef;
-
-/**
- * @brief Basic capture mode configuration definition
- */
-typedef struct {
- uint32_t CaptureUnit; /*!< Specifies the external event Channel
- This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
- uint32_t Event; /*!< Specifies the external event triggering the capture
- This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
- This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
- This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
- This parameter can be a value of @ref HRTIM_ExternalEventFilter */
-} HRTIM_BasicCaptureChannelCfgTypeDef;
-
-/**
- * @brief Basic One Pulse mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t OutputPolarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_Output_IDLE_State */
- uint32_t Event; /*!< Specifies the external event triggering the pulse generation
- This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
- This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
- This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
- This parameter can be a value of @ref HRTIM_ExternalEventFilter */
-} HRTIM_BasicOnePulseChannelCfgTypeDef;
-
-/**
- * @brief Timer configuration definition
- */
-typedef struct {
- uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
- This parameter can be a value of @ref HRTIM_TimerPushPullMode */
- uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
- This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
- uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
- This parameter can be a value of @ref HRTIM_TimerFaultLock */
- uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
- This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
- uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
- This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
- uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
- This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
- uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
- This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
- uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
- This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
-} HRTIM_TimerCfgTypeDef;
-
-/**
- * @brief Compare unit configuration definition
- */
-typedef struct {
- uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
- the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
- the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
- uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
- This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
- uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
- CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
-} HRTIM_CompareCfgTypeDef;
-
-/**
- * @brief Capture unit configuration definition
- */
-typedef struct {
- uint32_t Trigger; /*!< Specifies source(s) triggering the capture
- This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
-} HRTIM_CaptureCfgTypeDef;
-
-/**
- * @brief Output configuration definition
- */
-typedef struct {
- uint32_t Polarity; /*!< Specifies the output polarity
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
- This parameter can be any value of @ref HRTIM_OutputSetSource */
- uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
- This parameter can be any value of @ref HRTIM_OutputResetSource */
- uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
- This parameter can be any value of @ref HRTIM_OutputIdleMode */
- uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
- This parameter can be any value of @ref HRTIM_OutputIDLEState */
- uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
- This parameter can be any value of @ref HRTIM_OutputFAULTState */
- uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
- This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
- uint32_t BurstModeEntryDelayed; /* !© COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_I2C_H
-#define __STM32F30x_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
- section in Reference manual*/
-
- uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_Analog_Filter */
-
- uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between 0x00 and 0x0F */
-
- uint32_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode */
-
- uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
- This parameter can be a 7-bit or 10-bit address */
-
- uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement */
-
- uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-
-/** @defgroup I2C_Analog_Filter
- * @{
- */
-
-#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
-#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
- ((FILTER) == I2C_AnalogFilter_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint32_t)0x00000000)
-#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
-#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
-
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint32_t)0x00000000)
-#define I2C_Ack_Disable I2C_CR2_NACK
-
-#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
- ((ACK) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
-#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
-
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint16_t)0x0000)
-#define I2C_Direction_Receiver ((uint16_t)0x0400)
-
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_DMA_transfer_requests
- * @{
- */
-
-#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
-#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
-
-#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_slave_address
- * @{
- */
-
-#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_own_address2
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address2_mask
- * @{
- */
-
-#define I2C_OA2_NoMask ((uint8_t)0x00)
-#define I2C_OA2_Mask01 ((uint8_t)0x01)
-#define I2C_OA2_Mask02 ((uint8_t)0x02)
-#define I2C_OA2_Mask03 ((uint8_t)0x03)
-#define I2C_OA2_Mask04 ((uint8_t)0x04)
-#define I2C_OA2_Mask05 ((uint8_t)0x05)
-#define I2C_OA2_Mask06 ((uint8_t)0x06)
-#define I2C_OA2_Mask07 ((uint8_t)0x07)
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
- ((MASK) == I2C_OA2_Mask01) || \
- ((MASK) == I2C_OA2_Mask02) || \
- ((MASK) == I2C_OA2_Mask03) || \
- ((MASK) == I2C_OA2_Mask04) || \
- ((MASK) == I2C_OA2_Mask05) || \
- ((MASK) == I2C_OA2_Mask06) || \
- ((MASK) == I2C_OA2_Mask07))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_timeout
- * @{
- */
-
-#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_TIMINGR ((uint8_t)0x10)
-#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
-#define I2C_Register_ISR ((uint8_t)0x18)
-#define I2C_Register_ICR ((uint8_t)0x1C)
-#define I2C_Register_PECR ((uint8_t)0x20)
-#define I2C_Register_RXDR ((uint8_t)0x24)
-#define I2C_Register_TXDR ((uint8_t)0x28)
-
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_TIMINGR) || \
- ((REGISTER) == I2C_Register_TIMEOUTR) || \
- ((REGISTER) == I2C_Register_ISR) || \
- ((REGISTER) == I2C_Register_ICR) || \
- ((REGISTER) == I2C_Register_PECR) || \
- ((REGISTER) == I2C_Register_RXDR) || \
- ((REGISTER) == I2C_Register_TXDR))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_NACKF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
- ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
- ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
- ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
- ((FLAG) == I2C_FLAG_BUSY))
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_TXIS I2C_ISR_TXIS
-#define I2C_IT_RXNE I2C_ISR_RXNE
-#define I2C_IT_ADDR I2C_ISR_ADDR
-#define I2C_IT_NACKF I2C_ISR_NACKF
-#define I2C_IT_STOPF I2C_ISR_STOPF
-#define I2C_IT_TC I2C_ISR_TC
-#define I2C_IT_TCR I2C_ISR_TCR
-#define I2C_IT_BERR I2C_ISR_BERR
-#define I2C_IT_ARLO I2C_ISR_ARLO
-#define I2C_IT_OVR I2C_ISR_OVR
-#define I2C_IT_PECERR I2C_ISR_PECERR
-#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_IT_ALERT I2C_ISR_ALERT
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
- ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
- ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
- ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_ALERT))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_ReloadEndMode_definition
- * @{
- */
-
-#define I2C_Reload_Mode I2C_CR2_RELOAD
-#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
-#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
-
-
-#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
- ((MODE) == I2C_AutoEnd_Mode) || \
- ((MODE) == I2C_SoftEnd_Mode))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_StartStopMode_definition
- * @{
- */
-
-#define I2C_No_StartStop ((uint32_t)0x00000000)
-#define I2C_Generate_Stop I2C_CR2_STOP
-#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_Generate_Start_Write I2C_CR2_START
-
-
-#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
- ((MODE) == I2C_Generate_Start_Read) || \
- ((MODE) == I2C_Generate_Start_Write) || \
- ((MODE) == I2C_No_StartStop))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/* SMBUS management functions ************************************************/
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* I2C registers management functions *****************************************/
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-
-/* Data transfers management functions ****************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h
deleted file mode 100644
index 6469db47523..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_iwdg.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_IWDG_H
-#define __STM32F30x_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)
-#define IWDG_FLAG_WVU ((uint16_t)0x0002)
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
- ((FLAG) == IWDG_FLAG_WVU))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Reload_Value
- * @{
- */
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_CounterWindow_Value
- * @{
- */
-#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-void IWDG_SetWindowValue(uint16_t WindowValue);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_IWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h
deleted file mode 100644
index f65b47863a6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_misc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_MISC_H
-#define __STM32F30x_MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be a value of @ref IRQn_Type (For
- the complete STM32 Devices IRQ Channels list, please
- refer to stm32f30x.h file) */
-
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
- specified in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15.
- A lower priority value indicates a higher priority */
-
-
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 15.
- A lower priority value indicates a higher priority */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/**
- *
-@verbatim
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
- ============================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ============================================================================================================================
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- ----------------------------------------------------------------------------------------------------------------------------
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ============================================================================================================================
-@endverbatim
-*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_Vector_Table_Base
- * @{
- */
-
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
- ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
- * @}
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
- ((GROUP) == NVIC_PriorityGroup_1) || \
- ((GROUP) == NVIC_PriorityGroup_2) || \
- ((GROUP) == NVIC_PriorityGroup_3) || \
- ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_opamp.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_opamp.h
deleted file mode 100644
index f1e170eb7e6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_opamp.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_opamp.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the operational
- * amplifiers (OPAMP) firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_OPAMP_H
-#define __STM32F30x_OPAMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup OPAMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief OPAMP Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
- This parameter can be a value of @ref OPAMP_InvertingInput */
-
- uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
- This parameter can be a value of @ref OPAMP_NonInvertingInput */
-
-}OPAMP_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Constants
- * @{
- */
-
-/** @defgroup OPAMP_Selection
- * @{
- */
-
-#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
-#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
-#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
-#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
-
-#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
- ((PERIPH) == OPAMP_Selection_OPAMP2) || \
- ((PERIPH) == OPAMP_Selection_OPAMP3) || \
- ((PERIPH) == OPAMP_Selection_OPAMP4))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_InvertingInput
- * @{
- */
-
-#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
- connected to OPAMPx inverting input */
-#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
- connected to OPAMPx inverting input */
-#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
-#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
-
-#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
- ((INPUT) == OPAMP_InvertingInput_IO2) || \
- ((INPUT) == OPAMP_InvertingInput_PGA) || \
- ((INPUT) == OPAMP_InvertingInput_Vout))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_NonInvertingInput
- * @{
- */
-
-#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
- connected to OPAMPx non inverting input */
-
-#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
- ((INPUT) == OPAMP_NonInvertingInput_IO2) || \
- ((INPUT) == OPAMP_NonInvertingInput_IO3) || \
- ((INPUT) == OPAMP_NonInvertingInput_IO4))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PGAGain_Config
- * @{
- */
-
-#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
-#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
-#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
-#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
-
-#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
- ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
- ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
- ((GAIN) == OPAMP_OPAMP_PGAGain_16))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PGAConnect_Config
- * @{
- */
-
-#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
-#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
-#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
-
-#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
- ((CONNECT) == OPAMP_PGAConnect_IO1) || \
- ((CONNECT) == OPAMP_PGAConnect_IO2))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_SecondaryInvertingInput
- * @{
- */
-
-#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
- ((INVINPUT) == OPAMP_InvertingInput_IO2))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Input
- * @{
- */
-
-#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
-#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
-
-#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
- ((INPUT) == OPAMP_Input_NonInverting))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Vref
- * @{
- */
-
-#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
-#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
-#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
-#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
-
-#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
- ((VREF) == OPAMP_Vref_10VDDA) || \
- ((VREF) == OPAMP_Vref_50VDDA) || \
- ((VREF) == OPAMP_Vref_90VDDA))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Trimming
- */
-
-#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
-#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
-
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
- ((TRIMMING) == OPAMP_Trimming_User))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_TrimValue
- * @{
- */
-
-#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_OutputLevel
- * @{
- */
-
-#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
-#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the OPAMP configuration to the default reset state ***/
-void OPAMP_DeInit(uint32_t OPAMP_Selection);
-
-/* Initialization and Configuration functions *********************************/
-void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
-void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
-void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
-void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
-void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
-void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
-void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
-void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
-uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
-
-/* Calibration functions ******************************************************/
-void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
-void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
-void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
-void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
-
-/* OPAMP configuration locking function ***************************************/
-void OPAMP_LockConfig(uint32_t OPAMP_Selection);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_OPAMP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_pwr.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_pwr.h
deleted file mode 100644
index caffbbd1db4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_pwr.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_pwr.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_PWR_H
-#define __STM32F30x_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level
- * @{
- */
-
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-/** @defgroup PWR_WakeUp_Pins
- * @{
- */
-
-#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
-#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
-#define PWR_WakeUpPin_3 PWR_CSR_EWUP3
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
- ((PIN) == PWR_WakeUpPin_2) || \
- ((PIN) == PWR_WakeUpPin_3))
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower PWR_CR_LPSDSR
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry
- * @{
- */
-
-#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
-#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_PVDCmd(FunctionalState NewState);
-
-/* WakeUp pins configuration functions ****************************************/
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rcc.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rcc.h
deleted file mode 100644
index 189214bd932..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rcc.h
+++ /dev/null
@@ -1,699 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_rcc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the RCC
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_RCC_H
-#define __STM32F30x_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SYSCLK_Frequency;
- uint32_t HCLK_Frequency;
- uint32_t PCLK1_Frequency;
- uint32_t PCLK2_Frequency;
- uint32_t ADC12CLK_Frequency;
- uint32_t ADC34CLK_Frequency;
- uint32_t I2C1CLK_Frequency;
- uint32_t I2C2CLK_Frequency;
- uint32_t I2C3CLK_Frequency;
- uint32_t TIM1CLK_Frequency;
- uint32_t HRTIM1CLK_Frequency;
- uint32_t TIM8CLK_Frequency;
- uint32_t USART1CLK_Frequency;
- uint32_t USART2CLK_Frequency;
- uint32_t USART3CLK_Frequency;
- uint32_t UART4CLK_Frequency;
- uint32_t UART5CLK_Frequency;
- uint32_t TIM15CLK_Frequency;
- uint32_t TIM16CLK_Frequency;
- uint32_t TIM17CLK_Frequency;
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-
-#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
-#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
-
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
- ((SOURCE) == RCC_PLLSource_PREDIV1))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_Factor
- * @{
- */
-
-#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
-#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
-#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
-#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
-#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
-#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
-#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
-#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
-#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
-#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
-#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
-#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
-#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
-#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
-#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
- ((MUL) == RCC_PLLMul_16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PREDIV1_division_factor
- * @{
- */
-#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
-#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
-
-#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
- ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
- ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
- ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
- ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
- ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
- ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
- ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_clock_source
- * @{
- */
-
-#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
-#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
-#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
-#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_ADC_clock_source
- * @{
- */
-
-/* ADC1 & ADC2 */
-#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
-#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
-#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
-#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
-#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
-#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
-#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
-#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
-#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
-#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
-#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
-#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
-#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
-
-/* ADC3 & ADC4 */
-#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
-#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
-#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
-#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
-#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
-#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
-#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
-#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
-#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
-#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
-#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
-#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
-#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
-
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_TIM_clock_source
- * @{
- */
-
-#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
-
-#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
-#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
-
-#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
-#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
-
-#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
-#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
-
-#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
-#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
-
-#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
- ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HRTIM_clock_source
- * @{
- */
-
-#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
-#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
-
-#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_I2C_clock_source
- * @{
- */
-
-#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
-#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
-
-#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
-#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
-
-#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
-#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
-
-#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
- ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
- ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USART_clock_source
- * @{
- */
-
-#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
-#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
-#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
-#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
-
-#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
-#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
-#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
-#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
-
-#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
-#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
-#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
-#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
-
-#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
-#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
-#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
-#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
-
-#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
-#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
-#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
-#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
-
-#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
- ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
- ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
- ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
- ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
- ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
- ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
-
-
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_configuration
- * @{
- */
-
-#define RCC_LSE_OFF ((uint32_t)0x00000000)
-#define RCC_LSE_ON RCC_BDCR_LSEON
-#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-
-#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S_Clock_Source
- * @{
- */
-#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
-#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
-
-#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
-
-/** @defgroup RCC_LSE_Drive_Configuration
- * @{
- */
-
-#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
-#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
-#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
-#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
- ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripherals
- * @{
- */
-
-#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
-#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
-#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
-#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
-#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
-#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
-#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
-#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
-#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
-#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
-#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
-#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
-#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
-#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
-#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
-
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Clock_Source
- * @{
- */
-
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)
-#define RCC_MCOSource_LSI ((uint8_t)0x02)
-#define RCC_MCOSource_LSE ((uint8_t)0x03)
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
-#define RCC_MCOSource_HSI ((uint8_t)0x05)
-#define RCC_MCOSource_HSE ((uint8_t)0x06)
-#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
- ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
- ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOPrescaler
- * @{
- */
-
-#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
-#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
-#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
-#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
-#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
-#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
-#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
-#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
-
-#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
- ((PRESCALER) == RCC_MCOPrescaler_2) || \
- ((PRESCALER) == RCC_MCOPrescaler_4) || \
- ((PRESCALER) == RCC_MCOPrescaler_8) || \
- ((PRESCALER) == RCC_MCOPrescaler_16) || \
- ((PRESCALER) == RCC_MCOPrescaler_32) || \
- ((PRESCALER) == RCC_MCOPrescaler_64) || \
- ((PRESCALER) == RCC_MCOPrescaler_128))
-/**
- * @}
- */
-
-/** @defgroup RCC_USB_Device_clock_source
- * @{
- */
-
-#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
-#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
-
-#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
- ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
-#define RCC_FLAG_HSERDY ((uint8_t)0x11)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
-#define RCC_FLAG_MCOF ((uint8_t)0x9C)
-#define RCC_FLAG_LSERDY ((uint8_t)0x21)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
- ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
- ((FLAG) == RCC_FLAG_MCOF))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-#ifdef STM32F303xC
- void RCC_MCOConfig(uint8_t RCC_MCOSource);
-#else
- void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
-#endif /* STM32F303xC */
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLK1Config(uint32_t RCC_HCLK);
-void RCC_PCLK2Config(uint32_t RCC_HCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
-void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
-void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
-
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h
deleted file mode 100644
index 85dad308778..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h
+++ /dev/null
@@ -1,852 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_rtc.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_RTC_H
-#define __STM32F30x_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x1FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter
- must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this
- parameter can be a value of @ref RTC_WeekDay_Definitions */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x06)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define RTC_Alarm_B ((uint32_t)0x00000200)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
- * @{
- */
-#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
- ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_AlarmB ((uint32_t)0x00400000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_AlarmB) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup RTC_Digital_Calibration_Definitions
- * @{
- */
-#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
-#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
- ((SIGN) == RTC_CalibSign_Negative))
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Calib_Output_selection_Definitions
- * @{
- */
-#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
-#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
- ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_period_Definitions
- * @{
- */
-#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
- * @{
- */
-#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0].
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
- ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
- ((SAVE) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
- ((TRIGGER) == RTC_TamperTrigger_HighLevel))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Filter_Definitions
- * @{
- */
-#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
- ((FILTER) == RTC_TamperFilter_2Sample) || \
- ((FILTER) == RTC_TamperFilter_4Sample) || \
- ((FILTER) == RTC_TamperFilter_8Sample))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
- * @{
- */
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
- * @{
- */
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
- input tamper 1 */
-#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
- input tamper 2 */
-#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
- input tamper 3 */
-
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
- * @{
- */
-#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
- ((SEL) == RTC_ShiftAdd1S_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
-#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
-#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
-#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS ((uint32_t)0x00000010)
-#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
-#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
- ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000)
-#define RTC_IT_ALRB ((uint32_t)0x00002000)
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
-
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
- ((IT) == RTC_IT_TAMP3))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A and Alarm B) configuration functions **********************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
-uint32_t RTC_GetWakeUpCounter(void);
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions ********************************/
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* Output Type Config configuration functions *********************************/
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h
deleted file mode 100644
index 4cd0c3e679c..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h
+++ /dev/null
@@ -1,606 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_spi.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_SPI_H
-#define __STM32F30x_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler.
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3))
-
-#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
- ((PERIPH) == SPI3) || \
- ((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
- ((PERIPH) == I2S3ext))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_4b ((uint16_t)0x0300)
-#define SPI_DataSize_5b ((uint16_t)0x0400)
-#define SPI_DataSize_6b ((uint16_t)0x0500)
-#define SPI_DataSize_7b ((uint16_t)0x0600)
-#define SPI_DataSize_8b ((uint16_t)0x0700)
-#define SPI_DataSize_9b ((uint16_t)0x0800)
-#define SPI_DataSize_10b ((uint16_t)0x0900)
-#define SPI_DataSize_11b ((uint16_t)0x0A00)
-#define SPI_DataSize_12b ((uint16_t)0x0B00)
-#define SPI_DataSize_13b ((uint16_t)0x0C00)
-#define SPI_DataSize_14b ((uint16_t)0x0D00)
-#define SPI_DataSize_15b ((uint16_t)0x0E00)
-#define SPI_DataSize_16b ((uint16_t)0x0F00)
-#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
- ((SIZE) == SPI_DataSize_5b) || \
- ((SIZE) == SPI_DataSize_6b) || \
- ((SIZE) == SPI_DataSize_7b) || \
- ((SIZE) == SPI_DataSize_8b) || \
- ((SIZE) == SPI_DataSize_9b) || \
- ((SIZE) == SPI_DataSize_10b) || \
- ((SIZE) == SPI_DataSize_11b) || \
- ((SIZE) == SPI_DataSize_12b) || \
- ((SIZE) == SPI_DataSize_13b) || \
- ((SIZE) == SPI_DataSize_14b) || \
- ((SIZE) == SPI_DataSize_15b) || \
- ((SIZE) == SPI_DataSize_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length
- * @{
- */
-
-#define SPI_CRCLength_8b ((uint16_t)0x0000)
-#define SPI_CRCLength_16b ((uint16_t)0x0800)
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
- ((LENGTH) == SPI_CRCLength_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High ((uint16_t)0x0008)
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_FIFO_reception_threshold
- * @{
- */
-
-#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
-#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
-#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
- ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_last_DMA_transfers
- * @{
- */
-
-#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
-#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
-#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
-#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
-#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
-/**
- * @}
- */
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_I2S_IT_FRE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_transmission_fifo_status_level
- * @{
- */
-
-#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
-#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
-#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level
- * @{
- */
-#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
-#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
-#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
-
-
-
-#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
- ((FLAG) == I2S_FLAG_UDR))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the SPI configuration to the default reset state*******/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-
-/* Initialization and Configuration functions *********************************/
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
-
-/* Data transfers functions ***************************************************/
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h
deleted file mode 100644
index d141386a79c..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_syscfg.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the SYSCFG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/*!< Define to prevent recursive inclusion -----------------------------------*/
-#ifndef __STM32F30x_SYSCFG_H
-#define __STM32F30x_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Exported_Constants
- * @{
- */
-
-/** @defgroup SYSCFG_EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
-#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOF))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_EXTI_Pin_sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-
-
-#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_DMA_Remap_Config
- * @{
- */
-#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
-#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
-#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */
-
-#define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */
-#define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */
-#define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */
-
-#define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */
-#define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */
-#define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */
-
-#define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */
-#define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */
-#define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */
-
-#define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */
-#define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */
-#define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */
-
-#define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */
-#define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */
-#define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */
-
-#define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */
-#define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */
-
-/* SYSCFG_DMA_Remap_Legacy */
-#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */
-#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */
-
-#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
- ((REMAP) == SYSCFG_DMARemap_TIM16) || \
- ((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \
- ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
- ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
- ((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \
- ((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \
- ((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \
- ((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \
- ((REMAP) == SYSCFG_DMARemapCh2_ADC2))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Trigger_Remap_Config
- * @{
- */
-#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */
-#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
-#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */
-#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */
-
-#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
- ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \
- ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \
- ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_EncoderRemap_Config
- * @{
- */
-#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
-#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
-#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
-#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
-
-#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
- ((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
- ((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
- ((REMAP) == SYSCFG_EncoderRemap_TIM4))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_I2C_FastModePlus_Config
- * @{
- */
-#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
-#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
-#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
-#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
-#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
-#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
-
-#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_FPU_Interrupt_Config
- * @{
- */
-#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
-#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
-#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
-#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
-#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
-#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
-
-#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Lock_Config
- * @{
- */
-#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
-#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
-
-#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
- ((CONFIG) == SYSCFG_Break_SRAMParity) || \
- ((CONFIG) == SYSCFG_Break_Lockup))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_SRAMWRP_Config
- * @{
- */
-#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
-#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
-#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
-#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
-#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
-#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
-#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
-#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
-
-#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_flags_definition
- * @{
- */
-
-#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
-
-#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the SYSCFG configuration to the default reset state **/
-void SYSCFG_DeInit(void);
-
-/* SYSCFG configuration functions *********************************************/
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
-void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
-void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
-void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
-void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
-void SYSCFG_BypassParityCheckDisable(void);
-void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_SYSCFG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h
deleted file mode 100644
index 64da3c6c5ce..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h
+++ /dev/null
@@ -1,1334 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_tim.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the TIM firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_TIM_H
-#define __STM32F30x_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup stm32f30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This structure is used with all TIMx except for TIM6 and TIM7.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_State */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief BDTR structure definition
- * @note This structure is used only with TIM1 and TIM8.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15) || \
- ((PERIPH) == TIM16) || \
- ((PERIPH) == TIM17))
-/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15) || \
- ((PERIPH) == TIM16) || \
- ((PERIPH) == TIM17))
-
-/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15))
-/* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM8))
-/* LIST4: TIM1 and TIM8 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
- ((PERIPH) == TIM8))
-/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8))
-/* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15) || \
- ((PERIPH) == TIM16) || \
- ((PERIPH) == TIM17))
-
-/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM4) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM8) || \
- ((PERIPH) == TIM15))
-/* LIST8: TIM16 (option register) */
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM1)||\
- ((PERIPH) == TIM8))
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint32_t)0x00000)
-#define TIM_OCMode_Active ((uint32_t)0x00010)
-#define TIM_OCMode_Inactive ((uint32_t)0x00020)
-#define TIM_OCMode_Toggle ((uint32_t)0x00030)
-#define TIM_OCMode_PWM1 ((uint32_t)0x00060)
-#define TIM_OCMode_PWM2 ((uint32_t)0x00070)
-
-#define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
-#define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
-#define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
-#define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
-#define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
-#define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
- ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
- ((MODE) == TIM_OCMode_Combined_PWM1) || \
- ((MODE) == TIM_OCMode_Combined_PWM2) || \
- ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
- ((MODE) == TIM_OCMode_Asymmetric_PWM2))
-
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive) || \
- ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
- ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
- ((MODE) == TIM_OCMode_Combined_PWM1) || \
- ((MODE) == TIM_OCMode_Combined_PWM2) || \
- ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
- ((MODE) == TIM_OCMode_Asymmetric_PWM2))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-#define TIM_Channel_5 ((uint16_t)0x0010)
-#define TIM_Channel_6 ((uint16_t)0x0014)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_State
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_State
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break1_Input_enable_disable
- * @{
- */
-
-#define TIM_Break1_Enable ((uint32_t)0x00001000)
-#define TIM_Break1_Disable ((uint32_t)0x00000000)
-#define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
- ((STATE) == TIM_Break1_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Input_enable_disable
- * @{
- */
-
-#define TIM_Break2_Enable ((uint32_t)0x01000000)
-#define TIM_Break2_Disable ((uint32_t)0x00000000)
-#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
- ((STATE) == TIM_Break2_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break1_Polarity
- * @{
- */
-
-#define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
-#define TIM_Break1Polarity_High ((uint32_t)0x00002000)
-#define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
- ((POLARITY) == TIM_Break1Polarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Polarity
- * @{
- */
-
-#define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
-#define TIM_Break2Polarity_High ((uint32_t)0x02000000)
-#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
- ((POLARITY) == TIM_Break2Polarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break1_Filter
- * @{
- */
-
-#define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Break2_Filter
- * @{
- */
-
-#define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define TIM_DMABase_OR ((uint16_t)0x0013)
-#define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
-#define TIM_DMABase_CCR5 ((uint16_t)0x0015)
-#define TIM_DMABase_CCR6 ((uint16_t)0x0016)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR) || \
- ((BASE) == TIM_DMABase_CCMR3) || \
- ((BASE) == TIM_DMABase_CCR5) || \
- ((BASE) == TIM_DMABase_CCR6))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define TIM_EventSource_Break2 ((uint16_t)0x0100)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-
-
-#define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
-#define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
-#define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
-#define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
-#define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
-#define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
-#define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
-#define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
-#define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
-#define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
-#define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
-#define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
-#define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
-#define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
-#define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
-#define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
-#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
- ((SOURCE) == TIM_TRGO2Source_Enable) || \
- ((SOURCE) == TIM_TRGO2Source_Update) || \
- ((SOURCE) == TIM_TRGO2Source_OC1) || \
- ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
- ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
- ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
- ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
- ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
- ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
- ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint32_t)0x00004)
-#define TIM_SlaveMode_Gated ((uint32_t)0x00005)
-#define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
-#define TIM_SlaveMode_External1 ((uint32_t)0x00007)
-#define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1) || \
- ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-/** @defgroup TIM_Remap
- * @{
- */
-#define TIM16_GPIO ((uint16_t)0x0000)
-#define TIM16_RTC_CLK ((uint16_t)0x0001)
-#define TIM16_HSEDiv32 ((uint16_t)0x0002)
-#define TIM16_MCO ((uint16_t)0x0003)
-
-#define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
-#define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
-#define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
-#define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
-#define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
-#define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
-
-#define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
-#define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
-#define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
-#define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
-#define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
-#define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \
- ((TIM_REMAP) == TIM16_RTC_CLK) || \
- ((TIM_REMAP) == TIM16_HSEDiv32) || \
- ((TIM_REMAP) == TIM16_MCO) ||\
- ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
- ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
- ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
- ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
- ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
- ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
- ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
- ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
- ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
- ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
- ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
- ((TIM_REMAP) == TIM8_ADC3_AWDG3))
-
-/**
- * @}
- */
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint32_t)0x00001)
-#define TIM_FLAG_CC1 ((uint32_t)0x00002)
-#define TIM_FLAG_CC2 ((uint32_t)0x00004)
-#define TIM_FLAG_CC3 ((uint32_t)0x00008)
-#define TIM_FLAG_CC4 ((uint32_t)0x00010)
-#define TIM_FLAG_COM ((uint32_t)0x00020)
-#define TIM_FLAG_Trigger ((uint32_t)0x00040)
-#define TIM_FLAG_Break ((uint32_t)0x00080)
-#define TIM_FLAG_Break2 ((uint32_t)0x00100)
-#define TIM_FLAG_CC1OF ((uint32_t)0x00200)
-#define TIM_FLAG_CC2OF ((uint32_t)0x00400)
-#define TIM_FLAG_CC3OF ((uint32_t)0x00800)
-#define TIM_FLAG_CC4OF ((uint32_t)0x01000)
-#define TIM_FLAG_CC5 ((uint32_t)0x10000)
-#define TIM_FLAG_CC6 ((uint32_t)0x20000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_Break2) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF) ||\
- ((FLAG) == TIM_FLAG_CC5) ||\
- ((FLAG) == TIM_FLAG_CC6))
-
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
- * @}
- */
-
-/** @defgroup TIM_OCReferenceClear
- * @{
- */
-#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
-#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
- ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Legacy
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
-void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
-void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
-void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_TIM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h
deleted file mode 100644
index 2d2690a783b..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h
+++ /dev/null
@@ -1,607 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_usart.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_USART_H
-#define __STM32F30x_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control*/
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4) || \
- ((PERIPH) == UART5))
-
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3))
-
-#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == UART4))
-
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint32_t)0x00000000)
-#define USART_WordLength_9b USART_CR1_M
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint32_t)0x00000000)
-#define USART_StopBits_2 USART_CR2_STOP_1
-#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint32_t)0x00000000)
-#define USART_Parity_Even USART_CR1_PCE
-#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx USART_CR1_RE
-#define USART_Mode_Tx USART_CR1_TE
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
- ((MODE) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-
-#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
-#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
-#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
-#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-
-#define USART_Clock_Disable ((uint32_t)0x00000000)
-#define USART_Clock_Enable USART_CR2_CLKEN
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint32_t)0x00000000)
-#define USART_CPOL_High USART_CR2_CPOL
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint32_t)0x00000000)
-#define USART_CPHA_2Edge USART_CR2_CPHA
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint32_t)0x00000000)
-#define USART_LastBit_Enable USART_CR2_LBCL
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx USART_CR3_DMAT
-#define USART_DMAReq_Rx USART_CR3_DMAR
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
- ((DMAREQ) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Recception_Error
- * @{
- */
-
-#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
-#define USART_DMAOnError_Disable USART_CR3_DDRE
-#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
- ((DMAERROR) == USART_DMAOnError_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_MuteMode_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
-#define USART_WakeUp_AddressMark USART_CR1_WAKE
-#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_Address_Detection
- * @{
- */
-
-#define USART_AddressLength_4b ((uint32_t)0x00000000)
-#define USART_AddressLength_7b USART_CR2_ADDM7
-#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
- ((ADDRESS) == USART_AddressLength_7b))
-/**
- * @}
- */
-
-/** @defgroup USART_StopMode_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
-#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
-#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
-#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
- ((SOURCE) == USART_WakeUpSource_StartBit) || \
- ((SOURCE) == USART_WakeUpSource_RXNE))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
-#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower USART_CR3_IRLP
-#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_DE_Polarity
- * @{
- */
-
-#define USART_DEPolarity_High ((uint32_t)0x00000000)
-#define USART_DEPolarity_Low USART_CR3_DEP
-#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
- ((POLARITY) == USART_DEPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup USART_Inversion_Pins
- * @{
- */
-
-#define USART_InvPin_Tx USART_CR2_TXINV
-#define USART_InvPin_Rx USART_CR2_RXINV
-#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
- ((PIN) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_AutoBaudRate_Mode
- * @{
- */
-
-#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
-#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
-#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
-#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
-#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
- ((MODE) == USART_AutoBaudRate_FallingEdge) || \
- ((MODE) == USART_AutoBaudRate_0x7FFrame) || \
- ((MODE) == USART_AutoBaudRate_0x55Frame))
-/**
- * @}
- */
-
-/** @defgroup USART_OVR_DETECTION
- * @{
- */
-
-#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
-#define USART_OVRDetection_Disable USART_CR3_OVRDIS
-#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
- ((OVR) == USART_OVRDetection_Disable))
-/**
- * @}
- */
-/** @defgroup USART_Request
- * @{
- */
-
-#define USART_Request_ABRRQ USART_RQR_ABRRQ
-#define USART_Request_SBKRQ USART_RQR_SBKRQ
-#define USART_Request_MMRQ USART_RQR_MMRQ
-#define USART_Request_RXFRQ USART_RQR_RXFRQ
-#define USART_Request_TXFRQ USART_RQR_TXFRQ
-
-#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
- ((REQUEST) == USART_Request_RXFRQ) || \
- ((REQUEST) == USART_Request_MMRQ) || \
- ((REQUEST) == USART_Request_SBKRQ) || \
- ((REQUEST) == USART_Request_ABRRQ))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-#define USART_FLAG_REACK USART_ISR_REACK
-#define USART_FLAG_TEACK USART_ISR_TEACK
-#define USART_FLAG_WU USART_ISR_WUF
-#define USART_FLAG_RWU USART_ISR_RWU
-#define USART_FLAG_SBK USART_ISR_SBKF
-#define USART_FLAG_CM USART_ISR_CMF
-#define USART_FLAG_BUSY USART_ISR_BUSY
-#define USART_FLAG_ABRF USART_ISR_ABRF
-#define USART_FLAG_ABRE USART_ISR_ABRE
-#define USART_FLAG_EOB USART_ISR_EOBF
-#define USART_FLAG_RTO USART_ISR_RTOF
-#define USART_FLAG_nCTSS USART_ISR_CTS
-#define USART_FLAG_CTS USART_ISR_CTSIF
-#define USART_FLAG_LBD USART_ISR_LBD
-#define USART_FLAG_TXE USART_ISR_TXE
-#define USART_FLAG_TC USART_ISR_TC
-#define USART_FLAG_RXNE USART_ISR_RXNE
-#define USART_FLAG_IDLE USART_ISR_IDLE
-#define USART_FLAG_ORE USART_ISR_ORE
-#define USART_FLAG_NE USART_ISR_NE
-#define USART_FLAG_FE USART_ISR_FE
-#define USART_FLAG_PE USART_ISR_PE
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
- ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
- ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
- ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
- ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
-
-#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
- ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @brief USART Interrupt definition
- * USART_IT possible values
- * Elements values convention: 0xZZZZYYXX
- * XX: Position of the corresponding Interrupt
- * YY: Register index
- * ZZZZ: Flag position
- * @{
- */
-
-#define USART_IT_WU ((uint32_t)0x00140316)
-#define USART_IT_CM ((uint32_t)0x0011010E)
-#define USART_IT_EOB ((uint32_t)0x000C011B)
-#define USART_IT_RTO ((uint32_t)0x000B011A)
-#define USART_IT_PE ((uint32_t)0x00000108)
-#define USART_IT_TXE ((uint32_t)0x00070107)
-#define USART_IT_TC ((uint32_t)0x00060106)
-#define USART_IT_RXNE ((uint32_t)0x00050105)
-#define USART_IT_IDLE ((uint32_t)0x00040104)
-#define USART_IT_LBD ((uint32_t)0x00080206)
-#define USART_IT_CTS ((uint32_t)0x0009030A)
-#define USART_IT_ERR ((uint32_t)0x00000300)
-#define USART_IT_ORE ((uint32_t)0x00030300)
-#define USART_IT_NE ((uint32_t)0x00020300)
-#define USART_IT_FE ((uint32_t)0x00010300)
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
- ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
- ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-/**
- * @}
- */
-
-/** @defgroup USART_Global_definition
- * @{
- */
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
-#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
-#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
-#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
-
-/* STOP Mode functions ********************************************************/
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
-
-/* AutoBaudRate functions *****************************************************/
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* RS485 mode functions *******************************************************/
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_USART_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h
deleted file mode 100644
index 4c694bf43fd..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_wwdg.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file contains all the functions prototypes for the WWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_WWDG_H
-#define __STM32F30x_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the WWDG configuration to the default reset state ****/
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation functions **************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c
deleted file mode 100644
index 1fb8cdefde2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c
+++ /dev/null
@@ -1,2404 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_adc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration
- * + Analog Watchdog configuration
- * + Temperature Sensor, Vbat & Vrefint (Internal Reference Voltage) management
- * + Regular Channels Configuration
- * + Regular Channels DMA Configuration
- * + Injected channels Configuration
- * + Interrupts and flags management
- * + Dual mode configuration
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) select the ADC clock using the function RCC_ADCCLKConfig()
- (#) Enable the ADC interface clock using RCC_AHBPeriphClockCmd();
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
- (#) Configure the ADC conversion resolution, data alignment, external
- trigger and edge, sequencer lenght and Enable/Disable the continuous mode
- using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** ADC channels group configuration ***
- ========================================
- [..]
- (+) To configure the ADC channels features, use ADC_Init(), ADC_InjectedInit()
- and/or ADC_RegularChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
- function.
- (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions.
- (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
- (+) To activate the calibration mode, use the ADC_StartCalibration() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** DMA for ADC channels features configuration ***
- ===================================================
- [..]
- (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
- (+) To configure the DMA transfer request, use ADC_DMAConfig() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_adc.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CFGR register Mask */
-#define CFGR_CLEAR_Mask ((uint32_t)0xFDFFC007)
-
-/* JSQR register Mask */
-#define JSQR_CLEAR_Mask ((uint32_t)0x00000000)
-
-/* ADC ADON mask */
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFC10E0)
-
-/* ADC JDRx registers offset */
-#define JDR_Offset ((uint8_t)0x80)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to:
- (#) Initialize and configure the ADC injected and/or regular channels and dual mode.
- (#) Management of the calibration process
- (#) ADC Power-on Power-off
- (#) Single ended or differential mode
- (#) Enabling the queue of context and the auto delay mode
- (#) The number of ADC conversions that will be done using the sequencer for regular
- channel group
- (#) Enable or disable the ADC peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the ADCx peripheral registers to their default reset values.
- * @param ADCx: where x can be 1, 2,3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- /* Enable ADC1/ADC2 reset state */
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, ENABLE);
- /* Release ADC1/ADC2 from reset state */
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, DISABLE);
- }
- else if((ADCx == ADC3) || (ADCx == ADC4))
- {
- /* Enable ADC3/ADC4 reset state */
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, ENABLE);
- /* Release ADC3/ADC4 from reset state */
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, DISABLE);
- }
-}
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CONVMODE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConvEvent));
- assert_param(IS_EXTERNALTRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigEventEdge));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_OVRUNMODE(ADC_InitStruct->ADC_OverrunMode));
- assert_param(IS_ADC_AUTOINJECMODE(ADC_InitStruct->ADC_AutoInjMode));
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfRegChannel));
-
- /*---------------------------- ADCx CFGR Configuration -----------------*/
- /* Get the ADCx CFGR value */
- tmpreg1 = ADCx->CFGR;
- /* Clear SCAN bit */
- tmpreg1 &= CFGR_CLEAR_Mask;
- /* Configure ADCx: scan conversion mode */
- /* Set SCAN bit according to ADC_ScanConvMode value */
- tmpreg1 |= (uint32_t)ADC_InitStruct->ADC_ContinuousConvMode |
- ADC_InitStruct->ADC_Resolution|
- ADC_InitStruct->ADC_ExternalTrigConvEvent|
- ADC_InitStruct->ADC_ExternalTrigEventEdge|
- ADC_InitStruct->ADC_DataAlign|
- ADC_InitStruct->ADC_OverrunMode|
- ADC_InitStruct->ADC_AutoInjMode;
-
- /* Write to ADCx CFGR */
- ADCx->CFGR = tmpreg1;
-
- /*---------------------------- ADCx SQR1 Configuration -----------------*/
- /* Get the ADCx SQR1 value */
- tmpreg1 = ADCx->SQR1;
- /* Clear L bits */
- tmpreg1 &= ~(uint32_t)(ADC_SQR1_L);
- /* Configure ADCx: regular channel sequence length */
- /* Set L bits according to ADC_NbrOfRegChannel value */
- tmpreg1 |= (uint32_t) (ADC_InitStruct->ADC_NbrOfRegChannel - 1);
- /* Write to ADCx SQR1 */
- ADCx->SQR1 = tmpreg1;
-
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Reset ADC init structure parameters values */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
- ADC_InitStruct->ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0;
- ADC_InitStruct->ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None;
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
- ADC_InitStruct->ADC_OverrunMode = DISABLE;
- ADC_InitStruct->ADC_AutoInjMode = DISABLE;
- ADC_InitStruct->ADC_NbrOfRegChannel = 1;
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_InjectInitStruct: pointer to an ADC_InjecInitTypeDef structure that contains
- * the configuration information for the specified ADC injected channel.
- * @retval None
- */
-void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent));
- assert_param(IS_EXTERNALTRIGINJ_EDGE(ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge));
- assert_param(IS_ADC_INJECTED_LENGTH(ADC_InjectedInitStruct->ADC_NbrOfInjecChannel));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence1));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence2));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence3));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence4));
-
- /*---------------------------- ADCx JSQR Configuration -----------------*/
- /* Get the ADCx JSQR value */
- tmpreg1 = ADCx->JSQR;
- /* Clear L bits */
- tmpreg1 &= JSQR_CLEAR_Mask;
- /* Configure ADCx: Injected channel sequence length, external trigger,
- external trigger edge and sequences
- */
- tmpreg1 = (uint32_t) ((ADC_InjectedInitStruct->ADC_NbrOfInjecChannel - (uint8_t)1) |
- ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent |
- ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge |
- (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence1) << 8) |
- (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence2) << 14) |
- (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence3) << 20) |
- (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence4) << 26));
- /* Write to ADCx SQR1 */
- ADCx->JSQR = tmpreg1;
-}
-
-/**
- * @brief Fills each ADC_InjectedInitStruct member with its default value.
- * @param ADC_InjectedInitStruct : pointer to an ADC_InjectedInitTypeDef structure which will be initialized.
- * @retval None
- */
-void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
-{
- ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent = ADC_ExternalTrigInjecConvEvent_0;
- ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge = ADC_ExternalTrigInjecEventEdge_None;
- ADC_InjectedInitStruct->ADC_NbrOfInjecChannel = 1;
- ADC_InjectedInitStruct->ADC_InjecSequence1 = ADC_InjectedChannel_1;
- ADC_InjectedInitStruct->ADC_InjecSequence2 = ADC_InjectedChannel_1;
- ADC_InjectedInitStruct->ADC_InjecSequence3 = ADC_InjectedChannel_1;
- ADC_InjectedInitStruct->ADC_InjecSequence4 = ADC_InjectedChannel_1;
-}
-
-/**
- * @brief Initializes the ADCs peripherals according to the specified parameters
- * in the ADC_CommonInitStruct.
- * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * that contains the configuration information for All ADCs peripherals.
- * @retval None
- */
-void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
- assert_param(IS_ADC_CLOCKMODE(ADC_CommonInitStruct->ADC_Clock));
- assert_param(IS_ADC_DMA_MODE(ADC_CommonInitStruct->ADC_DMAMode));
- assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
- assert_param(IS_ADC_TWOSAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- /* Get the ADC CCR value */
- tmpreg1 = ADC1_2->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CCR_CLEAR_MASK;
- }
- else
- {
- /* Get the ADC CCR value */
- tmpreg1 = ADC3_4->CCR;
-
- /* Clear MULTI, DELAY, DMA and ADCPRE bits */
- tmpreg1 &= CCR_CLEAR_MASK;
- }
- /*---------------------------- ADC CCR Configuration -----------------*/
- /* Configure ADCx: Multi mode, Delay between two sampling time, ADC clock, DMA mode
- and DMA access mode for dual mode */
- /* Set MULTI bits according to ADC_Mode value */
- /* Set CKMODE bits according to ADC_Clock value */
- /* Set MDMA bits according to ADC_DMAAccessMode value */
- /* Set DMACFG bits according to ADC_DMAMode value */
- /* Set DELAY bits according to ADC_TwoSamplingDelay value */
- tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
- ADC_CommonInitStruct->ADC_Clock |
- ADC_CommonInitStruct->ADC_DMAAccessMode |
- (uint32_t)(ADC_CommonInitStruct->ADC_DMAMode << 12) |
- (uint32_t)((uint32_t)ADC_CommonInitStruct->ADC_TwoSamplingDelay << 8));
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- /* Write to ADC CCR */
- ADC1_2->CCR = tmpreg1;
- }
- else
- {
- /* Write to ADC CCR */
- ADC3_4->CCR = tmpreg1;
- }
-}
-
-/**
- * @brief Fills each ADC_CommonInitStruct member with its default value.
- * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
-{
- /* Initialize the ADC_Mode member */
- ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
-
- /* initialize the ADC_Clock member */
- ADC_CommonInitStruct->ADC_Clock = ADC_Clock_AsynClkMode;
-
- /* Initialize the ADC_DMAAccessMode member */
- ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
-
- /* Initialize the ADC_DMAMode member */
- ADC_CommonInitStruct->ADC_DMAMode = ADC_DMAMode_OneShot;
-
- /* Initialize the ADC_TwoSamplingDelay member */
- ADC_CommonInitStruct->ADC_TwoSamplingDelay = 0;
-
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ADEN bit */
- ADCx->CR |= ADC_CR_ADEN;
- }
- else
- {
- /* Disable the selected ADC peripheral: Set the ADDIS bit */
- ADCx->CR |= ADC_CR_ADDIS;
- }
-}
-
-/**
- * @brief Starts the selected ADC calibration process.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_StartCalibration(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADCAL bit */
- ADCx->CR |= ADC_CR_ADCAL;
-}
-
-/**
- * @brief Returns the ADCx calibration value.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC calibration value */
- return (uint32_t)ADCx->CALFACT;
-}
-
-/**
- * @brief Sets the ADCx calibration register.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADC calibration register value */
- ADCx->CALFACT = ADC_Calibration;
-}
-
-/**
- * @brief Select the ADC calibration mode.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_CalibrationMode: the ADC calibration mode.
- * This parameter can be one of the following values:
- * @arg ADC_CalibrationMode_Single: to select the calibration for single channel
- * @arg ADC_CalibrationMode_Differential: to select the calibration for differential channel
- * @retval None
- */
-void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CALIBRATION_MODE(ADC_CalibrationMode));
- /* Set or Reset the ADCALDIF bit */
- ADCx->CR &= (~ADC_CR_ADCALDIF);
- ADCx->CR |= ADC_CalibrationMode;
-
-}
-
-/**
- * @brief Gets the selected ADC calibration status.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The new state of ADC calibration (SET or RESET).
- */
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of CAL bit */
- if ((ADCx->CR & ADC_CR_ADCAL) != (uint32_t)RESET)
- {
- /* CAL bit is set: calibration on going */
- bitstatus = SET;
- }
- else
- {
- /* CAL bit is reset: end of calibration */
- bitstatus = RESET;
- }
- /* Return the CAL bit status */
- return bitstatus;
-}
-
-/**
- * @brief ADC Disable Command.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_DisableCmd(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADDIS bit */
- ADCx->CR |= ADC_CR_ADDIS;
-}
-
-
-/**
- * @brief Gets the selected ADC disable command Status.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The new state of ADC ADC disable command (SET or RESET).
- */
-FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of ADDIS bit */
- if ((ADCx->CR & ADC_CR_ADDIS) != (uint32_t)RESET)
- {
- /* ADDIS bit is set */
- bitstatus = SET;
- }
- else
- {
- /* ADDIS bit is reset */
- bitstatus = RESET;
- }
- /* Return the ADDIS bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the specified ADC Voltage Regulator.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx Voltage Regulator.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* set the intermediate state before moving the ADC voltage regulator
- from enable state to disable state or from disable state to enable state */
- ADCx->CR &= ~(ADC_CR_ADVREGEN);
-
- if (NewState != DISABLE)
- {
- /* Set the ADVREGEN bit 0 */
- ADCx->CR |= ADC_CR_ADVREGEN_0;
- }
- else
- {
- /* Set the ADVREGEN bit 1 */
- ADCx->CR |=ADC_CR_ADVREGEN_1;
- }
-}
-
-/**
- * @brief Selectes the differential mode for a specific channel
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @note : Channel 15, 16 and 17 are fixed to single-ended inputs mode.
- * @retval None
- */
-void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_DIFFCHANNEL(ADC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the DIFSEL bit */
- ADCx->DIFSEL |= (uint32_t)(1 << ADC_Channel );
- }
- else
- {
- /* Reset the DIFSEL bit */
- ADCx->DIFSEL &= ~(uint32_t)(1 << ADC_Channel);
- }
-}
-
-/**
- * @brief Selects the Queue Of Context Mode for injected channels.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the Queue Of Context Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the JQM bit */
- ADCx->CFGR |= (uint32_t)(ADC_CFGR_JQM );
- }
- else
- {
- /* Reset the JQM bit */
- ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_JQM);
- }
-}
-
-/**
- * @brief Selects the ADC Delayed Conversion Mode.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADC Delayed Conversion Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the AUTDLY bit */
- ADCx->CFGR |= (uint32_t)(ADC_CFGR_AUTDLY );
- }
- else
- {
- /* Reset the AUTDLY bit */
- ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_AUTDLY);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the 3 Analog Watchdogs
- (AWDG1, AWDG2 and AWDG3) in the ADC.
-
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) The ADC guarded channel(s) is (are) selected using the functions:
- (++) ADC_AnalogWatchdog1SingleChannelConfig().
- (++) ADC_AnalogWatchdog2SingleChannelConfig().
- (++) ADC_AnalogWatchdog3SingleChannelConfig().
-
- (#) The Analog watchdog lower and higher threshold are configured using the functions:
- (++) ADC_AnalogWatchdog1ThresholdsConfig().
- (++) ADC_AnalogWatchdog2ThresholdsConfig().
- (++) ADC_AnalogWatchdog3ThresholdsConfig().
-
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the function:
- (++) ADC_AnalogWatchdogCmd().
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog on single/all regular
- * or injected channels
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
- /* Get the old register value */
- tmpreg = ADCx->CFGR;
- /* Clear AWDEN, AWDENJ and AWDSGL bits */
- tmpreg &= ~(uint32_t)(ADC_CFGR_AWD1SGL|ADC_CFGR_AWD1EN|ADC_CFGR_JAWD1EN);
- /* Set the analog watchdog enable mode */
- tmpreg |= ADC_AnalogWatchdog;
- /* Store the new register value */
- ADCx->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog1.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
- /* Set the ADCx high threshold */
- ADCx->TR1 &= ~(uint32_t)ADC_TR1_HT1;
- ADCx->TR1 |= (uint32_t)((uint32_t)HighThreshold << 16);
-
- /* Set the ADCx low threshold */
- ADCx->TR1 &= ~(uint32_t)ADC_TR1_LT1;
- ADCx->TR1 |= LowThreshold;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog2.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 8bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 8bit value.
- * @retval None
- */
-void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
- uint8_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADCx high threshold */
- ADCx->TR2 &= ~(uint32_t)ADC_TR2_HT2;
- ADCx->TR2 |= (uint32_t)((uint32_t)HighThreshold << 16);
-
- /* Set the ADCx low threshold */
- ADCx->TR2 &= ~(uint32_t)ADC_TR2_LT2;
- ADCx->TR2 |= LowThreshold;
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog3.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 8bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 8bit value.
- * @retval None
- */
-void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
- uint8_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADCx high threshold */
- ADCx->TR3 &= ~(uint32_t)ADC_TR3_HT3;
- ADCx->TR3 |= (uint32_t)((uint32_t)HighThreshold << 16);
-
- /* Set the ADCx low threshold */
- ADCx->TR3 &= ~(uint32_t)ADC_TR3_LT3;
- ADCx->TR3 |= LowThreshold;
-}
-
-/**
- * @brief Configures the analog watchdog 2 guarded single channel
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- /* Get the old register value */
- tmpreg = ADCx->CFGR;
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= ~(uint32_t)ADC_CFGR_AWD1CH;
- /* Set the Analog watchdog channel */
- tmpreg |= (uint32_t)((uint32_t)ADC_Channel << 26);
- /* Store the new register value */
- ADCx->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the analog watchdog 2 guarded single channel
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- /* Get the old register value */
- tmpreg = ADCx->AWD2CR;
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= ~(uint32_t)ADC_AWD2CR_AWD2CH;
- /* Set the Analog watchdog channel */
- tmpreg |= (uint32_t)1 << (ADC_Channel);
- /* Store the new register value */
- ADCx->AWD2CR |= tmpreg;
-}
-
-/**
- * @brief Configures the analog watchdog 3 guarded single channel
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @retval None
- */
-void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- /* Get the old register value */
- tmpreg = ADCx->AWD3CR;
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= ~(uint32_t)ADC_AWD3CR_AWD3CH;
- /* Set the Analog watchdog channel */
- tmpreg |= (uint32_t)1 << (ADC_Channel);
- /* Store the new register value */
- ADCx->AWD3CR |= tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions
- * @brief Vbat, Temperature Sensor & Vrefint (Internal Reference Voltage) management function
- *
-@verbatim
- ====================================================================================================
- ##### Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions #####
- ====================================================================================================
-
- [..] This section provides a function allowing to enable/ disable the internal
- connections between the ADC and the Vbat/2, Temperature Sensor and the Vrefint source.
-
- [..] A typical configuration to get the Temperature sensor and Vrefint channels
- voltages is done following these steps :
- (#) Enable the internal connection of Vbat/2, Temperature sensor and Vrefint sources
- with the ADC channels using:
- (++) ADC_TempSensorCmd()
- (++) ADC_VrefintCmd()
- (++) ADC_VbatCmd()
-
- (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint and/or ADC_Channel_Vbat using
- (++) ADC_RegularChannelConfig() or
- (++) ADC_InjectedInit() functions
-
- (#) Get the voltage values, using:
- (++) ADC_GetConversionValue() or
- (++) ADC_GetInjectedConversionValue().
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the temperature sensor channel.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param NewState: new state of the temperature sensor.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- (void)(ADCx);
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor channel*/
- ADC1_2->CCR |= ADC12_CCR_TSEN;
- }
- else
- {
- /* Disable the temperature sensor channel*/
- ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_TSEN;
- }
-}
-
-/**
- * @brief Enables or disables the Vrefint channel.
- * @param ADCx: where x can be 1 or 4 to select the ADC peripheral.
- * @param NewState: new state of the Vrefint.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- if (NewState != DISABLE)
- {
- /* Enable the Vrefint channel*/
- ADC1_2->CCR |= ADC12_CCR_VREFEN;
- }
- else
- {
- /* Disable the Vrefint channel*/
- ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VREFEN;
- }
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the Vrefint channel*/
- ADC3_4->CCR |= ADC34_CCR_VREFEN;
- }
- else
- {
- /* Disable the Vrefint channel*/
- ADC3_4->CCR &= ~(uint32_t)ADC34_CCR_VREFEN;
- }
- }
-}
-
-/**
- * @brief Enables or disables the Vbat channel.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param NewState: new state of the Vbat.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- (void)ADCx;
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Vbat channel*/
- ADC1_2->CCR |= ADC12_CCR_VBATEN;
- }
- else
- {
- /* Disable the Vbat channel*/
- ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VBATEN;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Regular Channels Configuration functions
- * @brief Regular Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Channels Configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to manage the ADC regular channels.
-
- [..] To configure a regular sequence of channels use:
- (#) ADC_RegularChannelConfig()
- this fuction allows:
- (++) Configure the rank in the regular group sequencer for each channel
- (++) Configure the sampling time for each channel
-
- (#) ADC_RegularChannelSequencerLengthConfig() to set the length of the regular sequencer
-
- [..] The regular trigger is configured using the following functions:
- (#) ADC_SelectExternalTrigger()
- (#) ADC_ExternalTriggerPolarityConfig()
-
- [..] The start and the stop conversion are controlled by:
- (#) ADC_StartConversion()
- (#) ADC_StopConversion()
-
- [..]
- (@)Please Note that the following features for regular channels are configurated
- using the ADC_Init() function :
- (++) continuous mode activation
- (++) Resolution
- (++) Data Alignement
- (++) Overrun Mode.
-
- [..] Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- regular channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
- [..] To configure the discontinous mode, the following functions should be used:
- (#) ADC_DiscModeChannelCountConfig() to configure the number of discontinuous channel to be converted.
- (#) ADC_DiscModeCmd() to enable the discontinuous mode.
-
- [..] To configure and enable/disable the Channel offset use the functions:
- (++) ADC_SetChannelOffset1()
- (++) ADC_SetChannelOffset2()
- (++) ADC_SetChannelOffset3()
- (++) ADC_SetChannelOffset4()
- (++) ADC_ChannelOffset1Cmd()
- (++) ADC_ChannelOffset2Cmd()
- (++) ADC_ChannelOffset3Cmd()
- (++) ADC_ChannelOffset4Cmd()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures for the selected ADC regular channel its corresponding
- * rank in the sequencer and its sample time.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
- * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
- * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
- * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
- * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
- * @retval None
- */
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* Regular sequence configuration */
- /* For Rank 1 to 4 */
- if (Rank < 5)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR1;
- /* Calculate the mask to clear */
- tmpreg2 = 0x1F << (6 * (Rank ));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR1 = tmpreg1;
- }
- /* For Rank 5 to 9 */
- else if (Rank < 10)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR2;
- /* Calculate the mask to clear */
- tmpreg2 = ADC_SQR2_SQ5 << (6 * (Rank - 5));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 5));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR2 = tmpreg1;
- }
- /* For Rank 10 to 14 */
- else if (Rank < 15)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR3;
- /* Calculate the mask to clear */
- tmpreg2 = ADC_SQR3_SQ10 << (6 * (Rank - 10));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 10));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR3 = tmpreg1;
- }
- else
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SQR4;
- /* Calculate the mask to clear */
- tmpreg2 = ADC_SQR3_SQ15 << (6 * (Rank - 15));
- /* Clear the old SQx bits for the selected rank */
- tmpreg1 &= ~tmpreg2;
- /* Calculate the mask to set */
- tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 15));
- /* Set the SQx bits for the selected rank */
- tmpreg1 |= tmpreg2;
- /* Store the new register value */
- ADCx->SQR4 = tmpreg1;
- }
-
- /* Channel sampling configuration */
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (ADC_Channel > ADC_Channel_9)
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR2;
- /* Calculate the mask to clear */
- tmpreg2 = ADC_SMPR2_SMP10 << (3 * (ADC_Channel - 10));
- /* Clear the old channel sample time */
- ADCx->SMPR2 &= ~tmpreg2;
- /* Calculate the mask to set */
- ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
-
- }
- else /* ADC_Channel include in ADC_Channel_[0..9] */
- {
- /* Get the old register value */
- tmpreg1 = ADCx->SMPR1;
- /* Calculate the mask to clear */
- tmpreg2 = ADC_SMPR1_SMP1 << (3 * (ADC_Channel - 1));
- /* Clear the old channel sample time */
- ADCx->SMPR1 &= ~tmpreg2;
- /* Calculate the mask to set */
- ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel));
- }
-}
-
-/**
- * @brief Sets the ADC regular channel sequence lenght.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param SequenceLength: The Regular sequence length. This parameter must be between 1 to 16.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Configure the ADC sequence lenght */
- ADCx->SQR1 &= ~(uint32_t)ADC_SQR1_L;
- ADCx->SQR1 |= (uint32_t)(SequencerLength - 1);
-}
-
-/**
- * @brief External Trigger Enable and Polarity Selection for regular channels.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_ExternalTrigConvEvent: ADC external Trigger source.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigger_Event0: External trigger event 0
- * @arg ADC_ExternalTrigger_Event1: External trigger event 1
- * @arg ADC_ExternalTrigger_Event2: External trigger event 2
- * @arg ADC_ExternalTrigger_Event3: External trigger event 3
- * @arg ADC_ExternalTrigger_Event4: External trigger event 4
- * @arg ADC_ExternalTrigger_Event5: External trigger event 5
- * @arg ADC_ExternalTrigger_Event6: External trigger event 6
- * @arg ADC_ExternalTrigger_Event7: External trigger event 7
- * @arg ADC_ExternalTrigger_Event8: External trigger event 8
- * @arg ADC_ExternalTrigger_Event9: External trigger event 9
- * @arg ADC_ExternalTrigger_Event10: External trigger event 10
- * @arg ADC_ExternalTrigger_Event11: External trigger event 11
- * @arg ADC_ExternalTrigger_Event12: External trigger event 12
- * @arg ADC_ExternalTrigger_Event13: External trigger event 13
- * @arg ADC_ExternalTrigger_Event14: External trigger event 14
- * @arg ADC_ExternalTrigger_Event15: External trigger event 15
- * @param ADC_ExternalTrigEventEdge: ADC external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg ADC_ExternalTrigEventEdge_OFF: Hardware trigger detection disabled
- * (conversions can be launched by software)
- * @arg ADC_ExternalTrigEventEdge_RisingEdge: Hardware trigger detection on the rising edge
- * @arg ADC_ExternalTrigEventEdge_FallingEdge: Hardware trigger detection on the falling edge
- * @arg ADC_ExternalTrigEventEdge_BothEdge: Hardware trigger detection on both the rising and falling edges
- * @retval None
- */
-void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_EXT_TRIG(ADC_ExternalTrigConvEvent));
- assert_param(IS_EXTERNALTRIG_EDGE(ADC_ExternalTrigEventEdge));
-
- /* Disable the selected ADC conversion on external event */
- ADCx->CFGR &= ~(ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
- ADCx->CFGR |= (uint32_t)(ADC_ExternalTrigEventEdge | ADC_ExternalTrigConvEvent);
-}
-
-/**
- * @brief Enables or disables the selected ADC start conversion .
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_StartConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADSTART bit */
- ADCx->CR |= ADC_CR_ADSTART;
-}
-
-/**
- * @brief Gets the selected ADC start conversion Status.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The new state of ADC start conversion (SET or RESET).
- */
-FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Check the status of ADSTART bit */
- if ((ADCx->CR & ADC_CR_ADSTART) != (uint32_t)RESET)
- {
- /* ADSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* ADSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the ADSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Stops the selected ADC ongoing conversion.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_StopConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADSTP bit */
- ADCx->CR |= ADC_CR_ADSTP;
-}
-
-
-/**
- * @brief Configures the discontinuous mode for the selected ADC regular
- * group channel.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param Number: specifies the discontinuous mode regular channel
- * count value. This number must be between 1 and 8.
- * @retval None
- */
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
-{
- uint32_t tmpreg1 = 0;
- uint32_t tmpreg2 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
- /* Get the old register value */
- tmpreg1 = ADCx->CFGR;
- /* Clear the old discontinuous mode channel count */
- tmpreg1 &= ~(uint32_t)(ADC_CFGR_DISCNUM);
- /* Set the discontinuous mode channel count */
- tmpreg2 = Number - 1;
- tmpreg1 |= tmpreg2 << 17;
- /* Store the new register value */
- ADCx->CFGR = tmpreg1;
-}
-
-/**
- * @brief Enables or disables the discontinuous mode on regular group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode
- * on regular group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- ADCx->CFGR |= ADC_CFGR_DISCEN;
- }
- else
- {
- /* Disable the selected ADC regular discontinuous mode */
- ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_DISCEN);
- }
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for regular channel.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @brief Returns the last ADC1, ADC2, ADC3 and ADC4 regular conversions results
- * data in the selected dual mode.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The Data conversion value.
- * @note In dual mode, the value returned by this function is as following
- * Data[15:0] : these bits contain the regular data of the Master ADC.
- * Data[31:16]: these bits contain the regular data of the Slave ADC.
- */
-uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx)
-{
- uint32_t tmpreg1 = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- if((ADCx == ADC1) || (ADCx== ADC2))
- {
- /* Get the dual mode conversion value */
- tmpreg1 = ADC1_2->CDR;
- }
- else
- {
- /* Get the dual mode conversion value */
- tmpreg1 = ADC3_4->CDR;
- }
- /* Return the dual mode conversion value */
- return (uint32_t) tmpreg1;
-}
-
-/**
- * @brief Set the ADC channels conversion value offset1
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Offset: the offset value for the selected ADC Channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- /* Select the Channel */
- ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1_CH;
- ADCx->OFR1 |= (uint32_t)((uint32_t)ADC_Channel << 26);
-
- /* Set the data offset */
- ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1;
- ADCx->OFR1 |= (uint32_t)Offset;
-}
-
-/**
- * @brief Set the ADC channels conversion value offset2
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Offset: the offset value for the selected ADC Channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- /* Select the Channel */
- ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2_CH;
- ADCx->OFR2 |= (uint32_t)((uint32_t)ADC_Channel << 26);
-
- /* Set the data offset */
- ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2;
- ADCx->OFR2 |= (uint32_t)Offset;
-}
-
-/**
- * @brief Set the ADC channels conversion value offset3
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Offset: the offset value for the selected ADC Channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- /* Select the Channel */
- ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3_CH;
- ADCx->OFR3 |= (uint32_t)((uint32_t)ADC_Channel << 26);
-
- /* Set the data offset */
- ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3;
- ADCx->OFR3 |= (uint32_t)Offset;
-}
-
-/**
- * @brief Set the ADC channels conversion value offset4
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected
- * @arg ADC_Channel_11: ADC Channel11 selected
- * @arg ADC_Channel_12: ADC Channel12 selected
- * @arg ADC_Channel_13: ADC Channel13 selected
- * @arg ADC_Channel_14: ADC Channel14 selected
- * @arg ADC_Channel_15: ADC Channel15 selected
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected
- * @param Offset: the offset value for the selected ADC Channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_OFFSET(Offset));
-
- /* Select the Channel */
- ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4_CH;
- ADCx->OFR4 |= (uint32_t)((uint32_t)ADC_Channel << 26);
-
- /* Set the data offset */
- ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4;
- ADCx->OFR4 |= (uint32_t)Offset;
-}
-
-/**
- * @brief Enables or disables the Offset1.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx offset1.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the OFFSET1_EN bit */
- ADCx->OFR1 |= ADC_OFR1_OFFSET1_EN;
- }
- else
- {
- /* Reset the OFFSET1_EN bit */
- ADCx->OFR1 &= ~(ADC_OFR1_OFFSET1_EN);
- }
-}
-
-/**
- * @brief Enables or disables the Offset2.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx offset2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the OFFSET1_EN bit */
- ADCx->OFR2 |= ADC_OFR2_OFFSET2_EN;
- }
- else
- {
- /* Reset the OFFSET1_EN bit */
- ADCx->OFR2 &= ~(ADC_OFR2_OFFSET2_EN);
- }
-}
-
-/**
- * @brief Enables or disables the Offset3.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx offset3.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the OFFSET1_EN bit */
- ADCx->OFR3 |= ADC_OFR3_OFFSET3_EN;
- }
- else
- {
- /* Reset the OFFSET1_EN bit */
- ADCx->OFR3 &= ~(ADC_OFR3_OFFSET3_EN);
- }
-}
-
-/**
- * @brief Enables or disables the Offset4.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the ADCx offset4.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the OFFSET1_EN bit */
- ADCx->OFR4 |= ADC_OFR4_OFFSET4_EN;
- }
- else
- {
- /* Reset the OFFSET1_EN bit */
- ADCx->OFR4 &= ~(ADC_OFR4_OFFSET4_EN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Regular Channels DMA Configuration functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the DMA for ADC regular
- channels. Since converted regular channel values are stored into a unique data register,
- it is useful to use DMA for conversion of more than one regular channel. This
- avoids the loss of the data already stored in the ADC Data register.
-
- (#) ADC_DMACmd() function is used to enable the ADC DMA mode, after each
- conversion of a regular channel, a DMA request is generated.
- (#) ADC_DMAConfig() function is used to select between the one shot DMA mode
- or the circular DMA mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_DMA_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CFGR |= ADC_CFGR_DMAEN;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMAEN;
- }
-}
-
-/**
- * @brief Configure ADC DMA mode.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_DMAMode: select the ADC DMA mode.
- * This parameter can be one of the following values:
- * @arg ADC_DMAMode_OneShot: ADC DMA Oneshot mode
- * @arg ADC_DMAMode_Circular: ADC DMA circular mode
- * @retval None
- */
-void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_DMA_PERIPH(ADCx));
- assert_param(IS_ADC_DMA_MODE(ADC_DMAMode));
-
- /* Set or reset the DMACFG bit */
- ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMACFG;
- ADCx->CFGR |= ADC_DMAMode;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 Injected channels Configuration functions
- * @brief Injected channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Injected channels Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to manage the ADC Injected channels,
- it is composed of :
-
- (#) Configuration functions for Injected channels sample time
- (#) Functions to start and stop the injected conversion
- (#) unction to select the discontinuous mode
- (#) Function to get the Specified Injected channel conversion data: This subsection
- provides an important function in the ADC peripheral since it returns the
- converted data of the specific injected channel.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures for the selected ADC injected channel its corresponding
- * sample time.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: ADC Channel1 selected
- * @arg ADC_InjectedChannel_2: ADC Channel2 selected
- * @arg ADC_InjectedChannel_3: ADC Channel3 selected
- * @arg ADC_InjectedChannel_4: ADC Channel4 selected
- * @arg ADC_InjectedChannel_5: ADC Channel5 selected
- * @arg ADC_InjectedChannel_6: ADC Channel6 selected
- * @arg ADC_InjectedChannel_7: ADC Channel7 selected
- * @arg ADC_InjectedChannel_8: ADC Channel8 selected
- * @arg ADC_InjectedChannel_9: ADC Channel9 selected
- * @arg ADC_InjectedChannel_10: ADC Channel10 selected
- * @arg ADC_InjectedChannel_11: ADC Channel11 selected
- * @arg ADC_InjectedChannel_12: ADC Channel12 selected
- * @arg ADC_InjectedChannel_13: ADC Channel13 selected
- * @arg ADC_InjectedChannel_14: ADC Channel14 selected
- * @arg ADC_InjectedChannel_15: ADC Channel15 selected
- * @arg ADC_InjectedChannel_16: ADC Channel16 selected
- * @arg ADC_InjectedChannel_17: ADC Channel17 selected
- * @arg ADC_InjectedChannel_18: ADC Channel18 selected
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles
- * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles
- * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles
- * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles
- * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles
- * @retval None
- */
-void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime)
-{
- uint32_t tmpreg1 = 0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* Channel sampling configuration */
- /* if ADC_InjectedChannel_10 ... ADC_InjectedChannel_18 is selected */
- if (ADC_InjectedChannel > ADC_InjectedChannel_9)
- {
- /* Calculate the mask to clear */
- tmpreg1 = ADC_SMPR2_SMP10 << (3 * (ADC_InjectedChannel - 10));
- /* Clear the old channel sample time */
- ADCx->SMPR2 &= ~tmpreg1;
- /* Calculate the mask to set */
- ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel - 10));
-
- }
- else /* ADC_InjectedChannel include in ADC_InjectedChannel_[0..9] */
- {
- /* Calculate the mask to clear */
- tmpreg1 = ADC_SMPR1_SMP1 << (3 * (ADC_InjectedChannel - 1));
- /* Clear the old channel sample time */
- ADCx->SMPR1 &= ~tmpreg1;
- /* Calculate the mask to set */
- ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel));
- }
-}
-
-/**
- * @brief Enables or disables the selected ADC start of the injected
- * channels conversion.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC software start injected conversion.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_StartInjectedConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Enable the selected ADC conversion for injected group on external event and start the selected
- ADC injected conversion */
- ADCx->CR |= ADC_CR_JADSTART;
-}
-
-/**
- * @brief Stops the selected ADC ongoing injected conversion.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval None
- */
-void ADC_StopInjectedConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the JADSTP bit */
- ADCx->CR |= ADC_CR_JADSTP;
-}
-
-/**
- * @brief Gets the selected ADC Software start injected conversion Status.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @retval The new state of ADC start injected conversion (SET or RESET).
- */
-FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Check the status of JADSTART bit */
- if ((ADCx->CR & ADC_CR_JADSTART) != (uint32_t)RESET)
- {
- /* JADSTART bit is set */
- bitstatus = SET;
- }
- else
- {
- /* JADSTART bit is reset */
- bitstatus = RESET;
- }
- /* Return the JADSTART bit status */
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the selected ADC automatic injected group
- * conversion after regular one.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC auto injected conversion
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC automatic injected group conversion */
- ADCx->CFGR |= ADC_CFGR_JAUTO;
- }
- else
- {
- /* Disable the selected ADC automatic injected group conversion */
- ADCx->CFGR &= ~ADC_CFGR_JAUTO;
- }
-}
-
-/**
- * @brief Enables or disables the discontinuous mode for injected group
- * channel for the specified ADC
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param NewState: new state of the selected ADC discontinuous mode
- * on injected group channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC injected discontinuous mode */
- ADCx->CFGR |= ADC_CFGR_JDISCEN;
- }
- else
- {
- /* Disable the selected ADC injected discontinuous mode */
- ADCx->CFGR &= ~ADC_CFGR_JDISCEN;
- }
-}
-
-/**
- * @brief Returns the ADC injected channel conversion result
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_InjectedSequence: the converted ADC injected sequence.
- * This parameter can be one of the following values:
- * @arg ADC_InjectedSequence_1: Injected Sequence1 selected
- * @arg ADC_InjectedSequence_2: Injected Sequence2 selected
- * @arg ADC_InjectedSequence_3: Injected Sequence3 selected
- * @arg ADC_InjectedSequence_4: Injected Sequence4 selected
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedSequence)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_INJECTED_SEQUENCE(ADC_InjectedSequence));
-
- tmp = (uint32_t)ADCx;
- tmp += ((ADC_InjectedSequence - 1 )<< 2) + JDR_Offset;
-
- /* Returns the selected injected channel conversion data value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure the ADC Interrupts, get
- the status and clear flags and Interrupts pending bits.
-
- [..] The ADC provide 11 Interrupts sources and 11 Flags which can be divided into 3 groups:
-
- (#) Flags and Interrupts for ADC regular channels
- (##)Flags
- (+) ADC_FLAG_RDY: ADC Ready flag
- (+) ADC_FLAG_EOSMP: ADC End of Sampling flag
- (+) ADC_FLAG_EOC: ADC End of Regular Conversion flag.
- (+) ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
- (+) ADC_FLAG_OVR: ADC overrun flag
-
- (##) Interrupts
- (+) ADC_IT_RDY: ADC Ready interrupt source
- (+) ADC_IT_EOSMP: ADC End of Sampling interrupt source
- (+) ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- (+) ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt
- (+) ADC_IT_OVR: ADC overrun interrupt source
-
-
- (#) Flags and Interrupts for ADC regular channels
- (##)Flags
- (+) ADC_FLAG_JEOC: ADC Ready flag
- (+) ADC_FLAG_JEOS: ADC End of Sampling flag
- (+) ADC_FLAG_JQOVF: ADC End of Regular Conversion flag.
-
- (##) Interrupts
- (+) ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- (+) ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- (+) ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
-
- (#) General Flags and Interrupts for the ADC
- (##)Flags
- (+) ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
- (+) ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
- (+) ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
-
- (##)Flags
- (+) ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
- (+) ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
- (+) ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
-
- (#) Flags for ADC dual mode
- (##)Flags for Master
- (+) ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
- (+) ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
- (+) ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
- (+) ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
- (+) ADC_FLAG_MSTOVR: ADC master overrun flag
- (+) ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
- (+) ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
- (+) ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
- (+) ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
- (+) ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
- (+) ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
-
- (##) Flags for Slave
- (+) ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
- (+) ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
- (+) ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
- (+) ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
- (+) ADC_FLAG_SLVOVR: ADC slave overrun flag
- (+) ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
- (+) ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
- (+) ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
- (+) ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
- (+) ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
- (+) ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
-
- The user should identify which mode will be used in his application to manage
- the ADC controller events: Polling mode or Interrupt mode.
-
- In the Polling Mode it is advised to use the following functions:
- - ADC_GetFlagStatus() : to check if flags events occur.
- - ADC_ClearFlag() : to clear the flags events.
-
- In the Interrupt Mode it is advised to use the following functions:
- - ADC_ITConfig() : to enable or disable the interrupt source.
- - ADC_GetITStatus() : to check if Interrupt occurs.
- - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_IT(ADC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->IER |= ADC_IT;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->IER &= (~(uint32_t)ADC_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
- * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR: ADC overrun flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
- * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
- * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
- * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- /* Check the status of the specified ADC flag */
- if ((ADCx->ISR & ADC_FLAG) != (uint32_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
- * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR: ADC overrun flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag
- * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag
- * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag
- * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
- /* Clear the selected ADC flags */
- ADCx->ISR = (uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the master or slave flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
- * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
- * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
- * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
- * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
- * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
- * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
- * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
- * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
- * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
- * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
- * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
- * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
- * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
- * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
- * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
- * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
- * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- uint32_t tmpreg1 = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_COMMONFLAG(ADC_FLAG));
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- tmpreg1 = ADC1_2->CSR;
- }
- else
- {
- tmpreg1 = ADC3_4->CSR;
- }
- /* Check the status of the specified ADC flag */
- if ((tmpreg1 & ADC_FLAG) != (uint32_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral.
- * @param ADC_FLAG: specifies the master or slave flag to clear.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag
- * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag
- * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag
- * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_MSTOVR: ADC master overrun flag
- * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag
- * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag
- * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag
- * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag
- * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag
- * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag
- * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag
- * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag
- * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag
- * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag
- * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag
- * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag
- * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag
- * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag
- * @retval None
- */
-void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_COMMONFLAG(ADC_FLAG));
-
- if((ADCx == ADC1) || (ADCx == ADC2))
- {
- /* Clear the selected ADC flags */
- ADC1_2->CSR |= (uint32_t)ADC_FLAG;
- }
- else
- {
- /* Clear the selected ADC flags */
- ADC3_4->CSR |= (uint32_t)ADC_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_IT(ADC_IT));
-
- itstatus = ADCx->ISR & ADC_IT;
-
- itenable = ADCx->IER & ADC_IT;
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_IT(ADC_IT));
- /* Clear the selected ADC interrupt pending bit */
- ADCx->ISR = (uint32_t)ADC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c
deleted file mode 100644
index 978d604ee8d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c
+++ /dev/null
@@ -1,1629 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_can.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral:
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
- (#) CAN pins configuration:
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF9 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
- (#) Initialise and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function.
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.
- (#) Receive a CAN frame using CAN_Recieve() function.
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
- (#) Return the number of pending received frames using CAN_MessagePending() function.
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at initialization
- phase and CAN_GetITStatus() function into interrupt routines to check
- if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should clear it
- using CAN_ClearITPendingBit() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_can.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CAN Master Control Register bits */
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-#define CAN_MODE_MASK ((uint32_t) 0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/** @defgroup CAN_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
- number of time quanta to perform resynchronization, the number of time
- quanta in Bit Segment 1 and 2 and many other modes.
- (+) Configure the CAN reception filter.
- (+) Select the start bank filter for slave CAN.
- (+) Enable or disable the Debug Freeze mode for CAN.
- (+) Enable or disable the CAN Time Trigger Operation communication mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Enable CAN1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
- /* Release CAN1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
- * the configuration information for the CAN peripheral.
- * @retval Constant indicates initialization succeed which will be
- * CAN_InitStatus_Failed or CAN_InitStatus_Success.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CAN_InitStatus_Failed;
- __IO uint32_t wait_ack = 0x00000000;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* Check acknowledge */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- InitStatus = CAN_InitStatus_Success ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN1->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN1->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
- * @retval None
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CAN1->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CAN1->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-/**
- * @brief Enables or disables the CAN Time TriggerOperation communication mode.
- * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
- * sent over the CAN bus.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
- * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
- * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
- * @retval None
- */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TTCM mode */
- CANx->MCR |= CAN_MCR_TTCM;
-
- /* Set TGT bits */
- CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
- }
- else
- {
- /* Disable the TTCM mode */
- CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
- /* Reset TGT bits */
- CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group2 CAN Frames Transmission functions
- * @brief CAN Frames Transmission functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Transmission functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
- (+) Check the transmission status of a CAN Frame.
- (+) Cancel a transmit request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
- * @retval The number of the mailbox that is used for transmission or
- * CAN_TxStatus_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_TxStatus_NoMailBox;
- }
-
- if (transmit_mailbox != CAN_TxStatus_NoMailBox)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_Id_Standard)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
- TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->IDE | \
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
- * CAN_TxStatus_Failed in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
- break;
- default:
- state = CAN_TxStatus_Failed;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CAN_TxStatus_Pending;
- break;
- /* transmit failed */
- case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
- break;
- /* transmit succeeded */
- case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
- break;
- default: state = CAN_TxStatus_Failed;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
- break;
- case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
- break;
- case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group3 CAN Frames Reception functions
- * @brief CAN Frames Reception functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Reception functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Receive a correct CAN frame.
- (+) Release a specified receive FIFO (2 FIFOs are available).
- (+) Return the number of the pending received CAN frames.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
- * CAN DLC, CAN data and FMI number.
- * @retval None
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_Id_Standard)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage : which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group4 CAN Operation modes functions
- * @brief CAN Operation modes functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Operation modes functions #####
- ===============================================================================
- [..] This section provides functions allowing to select the CAN Operation modes:
- (+) sleep mode.
- (+) normal mode.
- (+) initialization mode.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Selects the CAN Operation mode.
- * @param CAN_OperatingMode: CAN Operating Mode.
- * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
- * @retval status of the requested mode which can be:
- * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
- * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
- */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
- uint8_t status = CAN_ModeStatus_Failed;
-
- /* Timeout for INAK or also for SLAK bits*/
- uint32_t timeout = INAK_TIMEOUT;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
- if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
- {
- /* Request initialisation */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
- {
- /* Request leave initialisation and sleep mode and enter Normal mode */
- CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != 0)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
- {
- /* Request Sleep mode */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else
- {
- status = CAN_ModeStatus_Failed;
- }
-
- return (uint8_t) status;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CAN_Sleep_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CAN_Sleep_Ok;
- }
- /* return sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CAN_WakeUp_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* wake up done : Sleep mode exited */
- wakeupstatus = CAN_WakeUp_Ok;
- }
- /* return wakeup status */
- return (uint8_t)wakeupstatus;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group5 CAN Bus Error management functions
- * @brief CAN Bus Error management functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Bus Error management functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Return the CANx's last error code (LEC).
- (+) Return the CANx Receive Error Counter (REC).
- (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- [..]
- (@) If TEC is greater than 255, The CAN is in bus-off state.
- (@) If REC or TEC are greater than 96, an Error warning flag occurs.
- (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1 to select the CAN1 peripheral.
- * @retval Error code:
- * - CAN_ERRORCODE_NoErr: No Error
- * - CAN_ERRORCODE_StuffErr: Stuff Error
- * - CAN_ERRORCODE_FormErr: Form Error
- * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
- * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
- * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
- * - CAN_ERRORCODE_CRCErr: CRC Error
- * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
- */
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
- uint8_t errorcode=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the error code*/
- errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-
- /* Return the error code*/
- return errorcode;
-}
-
-/**
- * @brief Returns the CANx Receive Error Counter (REC).
- * @note In case of an error during reception, this counter is incremented
- * by 1 or by 8 depending on the error condition as defined by the CAN
- * standard. After every successful reception, the counter is
- * decremented by 1 or reset to 120 if its value was higher than 128.
- * When the counter value exceeds 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the Receive Error Counter*/
- counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-
- /* Return the Receive Error Counter*/
- return counter;
-}
-
-
-/**
- * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval LSB of the 9-bit CAN Transmit Error Counter.
- */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-
- /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- return counter;
-}
-/**
- * @}
- */
-
-/** @defgroup CAN_Group6 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CAN Interrupts
- and to get the status and clear flags and Interrupts pending bits.
- [..] The CAN provides 14 Interrupts sources and 15 Flags:
-
- *** Flags ***
- =============
- [..] The 15 flags can be divided on 4 groups:
- (+) Transmit Flags:
- (++) CAN_FLAG_RQCP0.
- (++) CAN_FLAG_RQCP1.
- (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags
- Set when when the last request (transmit or abort) has
- been performed.
- (+) Receive Flags:
- (++) CAN_FLAG_FMP0.
- (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags;
- Set to signal that messages are pending in the receive FIFO.
- These Flags are cleared only by hardware.
- (++) CAN_FLAG_FF0.
- (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags;
- Set when three messages are stored in the selected FIFO.
- (++) CAN_FLAG_FOV0.
- (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags;
- Set when a new message has been received and passed the filter
- while the FIFO was full.
- (+) Operating Mode Flags:
- (++) CAN_FLAG_WKU: Wake up Flag;
- Set to signal that a SOF bit has been detected while the CAN
- hardware was in Sleep mode.
- (++) CAN_FLAG_SLAK: Sleep acknowledge Flag;
- Set to signal that the CAN has entered Sleep Mode.
- (+) Error Flags:
- (++) CAN_FLAG_EWG: Error Warning Flag;
- Set when the warning limit has been reached (Receive Error Counter
- or Transmit Error Counter greater than 96).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_EPV: Error Passive Flag;
- Set when the Error Passive limit has been reached (Receive Error
- Counter or Transmit Error Counter greater than 127).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_BOF: Bus-Off Flag;
- Set when CAN enters the bus-off state. The bus-off state is
- entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_LEC: Last error code Flag;
- Set If a message has been transferred (reception or transmission)
- with error, and the error code is hold.
-
- *** Interrupts ***
- ==================
- [..] The 14 interrupts can be divided on 4 groups:
- (+) Transmit interrupt:
- (++) CAN_IT_TME: Transmit mailbox empty Interrupt;
- If enabled, this interrupt source is pending when no transmit
- request are pending for Tx mailboxes.
- (+) Receive Interrupts:
- (++) CAN_IT_FMP0.
- (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts;
- If enabled, these interrupt sources are pending when messages
- are pending in the receive FIFO.
- The corresponding interrupt pending bits are cleared only by hardware.
- (++) CAN_IT_FF0.
- (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts;
- If enabled, these interrupt sources are pending when three messages
- are stored in the selected FIFO.
- (++) CAN_IT_FOV0.
- (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts;
- If enabled, these interrupt sources are pending when a new message
- has been received and passed the filter while the FIFO was full.
- (+) Operating Mode Interrupts:
- (++) CAN_IT_WKU: Wake-up Interrupt;
- If enabled, this interrupt source is pending when a SOF bit has
- been detected while the CAN hardware was in Sleep mode.
- (++) CAN_IT_SLK: Sleep acknowledge Interrupt:
- If enabled, this interrupt source is pending when the CAN has
- entered Sleep Mode.
- (+) Error Interrupts:
- (++) CAN_IT_EWG: Error warning Interrupt;
- If enabled, this interrupt source is pending when the warning limit
- has been reached (Receive Error Counter or Transmit Error Counter=96).
- (++) CAN_IT_EPV: Error passive Interrupt;
- If enabled, this interrupt source is pending when the Error Passive
- limit has been reached (Receive Error Counter or Transmit Error Counter>127).
- (++) CAN_IT_BOF: Bus-off Interrupt;
- If enabled, this interrupt source is pending when CAN enters
- the bus-off state. The bus-off state is entered on TEC overflow,
- greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_IT_LEC: Last error code Interrupt;
- If enabled, this interrupt source is pending when a message has
- been transferred (reception or transmission) with error and the
- error code is hold.
- (++) CAN_IT_ERR: Error Interrupt;
- If enabled, this interrupt source is pending when an error condition
- is pending.
- [..] Managing the CAN controller events:
- The user should identify which mode will be used in his application to manage
- the CAN controller events: Polling mode or Interrupt mode.
- (+) In the Polling Mode it is advised to use the following functions:
- (++) CAN_GetFlagStatus() : to check if flags events occur.
- (++) CAN_ClearFlag() : to clear the flags events.
- (+) In the Interrupt Mode it is advised to use the following functions:
- (++) CAN_ITConfig() : to enable or disable the interrupt source.
- (++) CAN_GetITStatus() : to check if Interrupt occurs.
- (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
- pending bits since there are cleared only by hardware.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval None
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the interrupt enable bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default:
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval None
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
- break;
- default:
- break;
- }
-}
- /**
- * @}
- */
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c
deleted file mode 100644
index 588b2c403df..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_comp.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral:
- * + Comparators configuration
- * + Window mode control
- *
- @verbatim
-
- ==============================================================================
- ##### COMP Peripheral features #####
- ==============================================================================
- [..]
- The device integrates 7 analog comparators COMP1, COMP2...COMP7:
- (#) The non inverting input and inverting input can be set to GPIO pins
- as shown in table1. COMP Inputs below.
-
- (#) The COMP output is internally is available using COMP_GetOutputLevel()
- and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
-
- (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
- Refer to table 3. COMP Outputs redirection to embedded timers below.
-
- (#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
- mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
-
- (#) The seven comparators have interrupt capability with wake-up
- from Sleep and Stop modes (through the EXTI controller):
- (++) COMP1 is internally connected to EXTI Line 21
- (++) COMP2 is internally connected to EXTI Line 22
- (++) COMP3 is internally connected to EXTI Line 29
- (++) COMP4 is internally connected to EXTI Line 30
- (++) COMP5 is internally connected to EXTI Line 31
- (++) COMP6 is internally connected to EXTI Line 32
- (++) COMP7 is internally connected to EXTI Line 33
-
- [..] Table 1. COMP Inputs
- +------------------------------------------------------------------------------------------+
- | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |-----------------|----------------|---------------|---------------------------------------|
- | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | DAC1 OUT1(PA4) | OK | OK | OK | OK | OK | OK | OK |
- | | DAC1 OUT2(PA5) | OK | OK | OK | OK | OK | OK | OK |
- | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
- | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
- | | DAC2 OUT1(PA6) | --- | OK | --- | OK | --- | OK | --- |
- |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
- | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
- | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
- +------------------------------------------------------------------------------------------+
-
- [..] Table 2. COMP Outputs
- +-------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |-------|-------|-------|-------|-------|-------|-------|
- | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
- | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
- | PA6 | PA12 | --- | --- | --- | --- | --- |
- | PA11 | PB9 | --- | --- | --- | --- | --- |
- | PB8 | --- | --- | --- | --- | --- | --- |
- +-------------------------------------------------------+
-
- [..] Table 3. COMP Outputs redirection to embedded timers
- +----------------------------------------------------------------------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | | | | | | | |
- | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
- | | | | | | | |
- | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | + | + | + | + | + | + | + |
- | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
- | | | | | | | |
- | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
- | | | | | | | |
- | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
- | | | | | | | |
- | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
- | | | | | | | |
- | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
- | | | | | | | |
- | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
- | | | | | | | |
- | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
- +----------------------------------------------------------------------------------------------------------------------+
-
- [..] Table 4. COMP Outputs blanking sources
- +----------------------------------------------------------------------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
- | | | | | | | |
- | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
- | | | | | | | |
- | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
- | | | | | | | |
- +----------------------------------------------------------------------------------------------------------------------+
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions to configure and program the Comparators
- of all STM32F30x devices.
-
- To use the comparator, perform the following steps:
-
- (#) Enable the SYSCFG APB clock to get write access to comparator
- register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- (#) Configure the comparator input in analog mode using GPIO_Init()
-
- (#) Configure the comparator output in alternate function mode
- using GPIO_Init() and use GPIO_PinAFConfig() function to map the
- comparator output to the GPIO pin
-
- (#) Configure the comparator using COMP_Init() function:
- (++) Select the inverting input
- (++) Select the non-inverting input
- (++) Select the output polarity
- (++) Select the output redirection
- (++) Select the hysteresis level
- (++) Select the power mode
-
- (#) Enable the comparator using COMP_Cmd() function
-
- (#) If required enable the COMP interrupt by configuring and enabling
- EXTI line in Interrupt mode and selecting the desired sensitivity
- level using EXTI_Init() function. After that enable the comparator
- interrupt vector using NVIC_Init() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_comp.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup COMP
- * @brief COMP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CSR register Mask */
-#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Functions
- * @{
- */
-
-/** @defgroup COMP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes COMP peripheral registers to their default reset values.
- * @note Deinitialization can't be performed if the COMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
- * to select the COMP peripheral.
- * @param None
- * @retval None
- */
-void COMP_DeInit(uint32_t COMP_Selection)
-{
- /*!< Set COMP_CSR register to reset value */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
-}
-
-/**
- * @brief Initializes the COMP peripheral according to the specified parameters
- * in COMP_InitStruct
- * @note If the selected comparator is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @note By default, PA1 is selected as COMP1 non inverting input.
- * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
- * to select the COMP peripheral.
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
- * the configuration information for the specified COMP peripheral.
- * - COMP_InvertingInput specifies the inverting input of COMP
- * - COMP_NonInvertingInput specifies the non inverting input of COMP
- * - COMP_Output connect COMP output to selected timer
- * input (Input capture / Output Compare Reference Clear / Break Input)
- * - COMP_BlankingSrce specifies the blanking source of COMP
- * - COMP_OutputPol select output polarity
- * - COMP_Hysteresis configures COMP hysteresis value
- * - COMP_Mode configures COMP power mode
- * @retval None
- */
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
- assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
- assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
- assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
- assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
- assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
- assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
-
- /*!< Get the COMPx_CSR register value */
- tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
-
- /*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
- tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
-
- /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
- /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
- /*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
- /*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
- /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
- /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
- /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
- /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
- tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
- COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
- COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
-
- /*!< Write to COMPx_CSR register */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
-}
-
-/**
- * @brief Fills each COMP_InitStruct member with its default value.
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
-{
- COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
- COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
- COMP_InitStruct->COMP_Output = COMP_Output_None;
- COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
- COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
- COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
- COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
-}
-
-/**
- * @brief Enable or disable the COMP peripheral.
- * @note If the selected comparator is locked, enable/disable can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
- * to select the COMP peripheral.
- * @param NewState: new state of the COMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * When enabled, the comparator compares the non inverting input with
- * the inverting input and the comparison result is available
- * on comparator output.
- * When disabled, the comparator doesn't perform comparison and the
- * output level is low.
- * @retval None
- */
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected COMPx peripheral */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
- }
- else
- {
- /* Disable the selected COMP peripheral */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
- }
-}
-
-/**
- * @brief Close or Open the SW1 switch.
- * @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
- * To unlock the configuration, perform a system reset.
- * @note This switch is solely intended to redirect signals onto high
- * impedance input, such as COMP1 non-inverting input (highly resistive switch)
- * @param NewState: New state of the analog switch.
- * This parameter can be
- * ENABLE so the SW1 is closed; PA1 is connected to PA4
- * or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
- * @retval None
- */
-void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Close SW1 switch */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
- }
- else
- {
- /* Open SW1 switch */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
- }
-}
-
-/**
- * @brief Return the output level (high or low) of the selected comparator.
- * The output level depends on the selected polarity.
- * If the polarity is not inverted:
- * - Comparator output is low when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is high when the non-inverting input is at a higher
- * voltage than the inverting input
- * If the polarity is inverted:
- * - Comparator output is high when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is low when the non-inverting input is at a higher
- * voltage than the inverting input
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
- * to select the COMP peripheral.
- * @retval Returns the selected comparator output level: low or high.
- *
- */
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
-{
- uint32_t compout = 0x0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Check if selected comparator output is high */
- if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
- {
- compout = COMP_OutputLevel_High;
- }
- else
- {
- compout = COMP_OutputLevel_Low;
- }
-
- /* Return the comparator output level */
- return (uint32_t)(compout);
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group2 Window mode control function
- * @brief Window mode control function
- *
-@verbatim
- ===============================================================================
- ##### Window mode control function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the window mode.
- * Window mode for comparators makes use of two comparators:
- * COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
- * In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
- * non inverting inputs are connected together and only COMPx-1 non
- * inverting input can be used.
- * e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
- * is to be used.
- * @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
- * to select the COMP peripheral.
- * param NewState: new state of the window mode.
- * This parameter can be ENABLE or DISABLE.
- * When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
- * When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
- * @retval None
- */
-void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_COMP_WINDOW(COMP_Selection));
-
- if (NewState != DISABLE)
- {
- /* Enable the window mode */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
- }
- else
- {
- /* Disable the window mode */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group3 COMP configuration locking function
- * @brief COMP1, COMP2,...COMP7 configuration locking function
- * COMP1, COMP2,...COMP7 configuration can be locked each separately.
- * Unlocking is performed by system reset.
- *
-@verbatim
- ===============================================================================
- ##### Configuration Lock function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected comparator (COMP1/COMP2) configuration.
- * @note Locking the configuration means that all control bits are read-only.
- * To unlock the comparator configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be COMP_Selection_COMPx where x can be 1 to 7
- * to select the COMP peripheral.
- * @retval None
- */
-void COMP_LockConfig(uint32_t COMP_Selection)
-{
- /* Check the parameter */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Set the lock bit corresponding to selected comparator */
- *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c
deleted file mode 100644
index 94a02fe3300..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_crc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of CRC computation unit peripheral:
- * + Configuration of the CRC computation unit
- * + CRC computation of one/many 32-bit data
- * + CRC Independent register (IDR) access
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
- function.
- (#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
- (#) Set the polynomial coefficients using CRC_SetPolynomial();
- (#) If required, select the reverse operation on input data
- using CRC_ReverseInputDataSelect();
- (#) If required, enable the reverse operation on output data
- using CRC_ReverseOutputDataCmd(Enable);
- (#) If required, set the initialization remainder value using
- CRC_SetInitRegister();
- (#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
- or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
- data buffer.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_crc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
- * @brief Configuration of the CRC computation unit functions
- *
-@verbatim
- ===============================================================================
- ##### CRC configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes CRC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CRC_DeInit(void)
-{
- /* Set DR register to reset value */
- CRC->DR = 0xFFFFFFFF;
- /* Set the POL register to the reset value: 0x04C11DB7 */
- CRC->POL = 0x04C11DB7;
- /* Reset IDR register */
- CRC->IDR = 0x00;
- /* Set INIT register to reset value */
- CRC->INIT = 0xFFFFFFFF;
- /* Reset the CRC calculation unit */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Resets the CRC calculation unit and sets INIT register content in DR register.
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR |= CRC_CR_RESET;
-}
-
-/**
- * @brief Selects the polynomial size.
- * @param CRC_PolSize: Specifies the polynomial size.
- * This parameter can be:
- * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
- * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
- * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
- * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
- * @retval None
- */
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset POL_SIZE bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
- /* Set the polynomial size */
- tmpcr |= (uint32_t)CRC_PolSize;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Selects the reverse operation to be performed on input data.
- * @param CRC_ReverseInputData: Specifies the reverse operation on input data.
- * This parameter can be:
- * @arg CRC_ReverseInputData_No: No reverse operation is performed
- * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
- * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
- * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
- * @retval None
- */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset REV_IN bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
- /* Set the reverse operation */
- tmpcr |= (uint32_t)CRC_ReverseInputData;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Enables or disable the reverse operation on output data.
- * The reverse operation on output data is performed on 32-bit.
- * @param NewState: new state of the reverse operation on output data.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRC_ReverseOutputDataCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable reverse operation on output data */
- CRC->CR |= CRC_CR_REV_OUT;
- }
- else
- {
- /* Disable reverse operation on output data */
- CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
- }
-}
-
-/**
- * @brief Initializes the INIT register.
- * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
- * @param CRC_InitValue: Programmable initial CRC value
- * @retval None
- */
-void CRC_SetInitRegister(uint32_t CRC_InitValue)
-{
- CRC->INIT = CRC_InitValue;
-}
-
-/**
- * @brief Initializes the polynomail coefficients.
- * @param CRC_Pol: Polynomial to be used for CRC calculation.
- * @retval None
- */
-void CRC_SetPolynomial(uint32_t CRC_Pol)
-{
- CRC->POL = CRC_Pol;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
- * @brief CRC computation of one/many 32-bit data functions
- *
-@verbatim
- ===============================================================================
- ##### CRC computation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param CRC_Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t CRC_Data)
-{
- CRC->DR = CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 16-bit CRC of a given 16-bit data.
- * @param CRC_Data: data half-word(16-bit) to compute its CRC
- * @retval 16-bit CRC
- */
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
-{
- *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 8-bit CRC of a given 8-bit data.
- * @param CRC_Data: 8-bit data to compute its CRC
- * @retval 8-bit CRC
- */
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
-{
- *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
- * @brief CRC Independent Register (IDR) access (write/read) functions
- *
-@verbatim
- ===============================================================================
- ##### CRC Independent Register (IDR) access functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Stores an 8-bit data in the Independent Data(ID) register.
- * @param CRC_IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t CRC_IDValue)
-{
- CRC->IDR = CRC_IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c
deleted file mode 100644
index 3c350ba2da7..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dac.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral:
- * + DAC channels configuration: trigger, output buffer, data format
- * + DMA management
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### DAC Peripheral features #####
- ===============================================================================
- [..] The device integrates two 12-bit Digital Analog Converters that can
- be used independently or simultaneously (dual mode):
- (#) DAC1 integrates two DAC channels:
- (++) DAC1 channel 1 with DAC1_OUT1 as output
- (++) DAC1 channel 2 with DAC1_OUT2 as output
- (++) The two channels can be used independently or simultaneously (dual mode)
-
- (#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output
-
- [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
- and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
- DAC_SetChannel1Data()/DAC_SetChannel2Data.
-
- [..] Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
- The used pin (GPIOx_Pin9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
- The timer TRGO event should be selected using TIM_SelectOutputTrigger()
- (++) To trigger DAC conversions by TIM3 instead of TIM8 follow
- this sequence:
- (+++) Enable SYSCFG APB clock by calling
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- (+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init()
- (+++) Remap the DAC trigger from TIM8 to TIM3 by calling
- SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE)
- (#) Software using DAC_Trigger_Software
-
- [..] Each DAC channel integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable, the output buffer use
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-
- [..] Refer to the device datasheet for more details about output impedance
- value with and without output buffer.
-
- [..] Both DAC channels can be used to generate:
- (+) Noise wave using DAC_WaveGeneration_Noise
- (+) Triangle wave using DAC_WaveGeneration_Triangle
-
- [..] Wave generation can be disabled using DAC_WaveGeneration_None
-
- [..] The DAC data format can be:
- (+) 8-bit right alignment using DAC_Align_8b_R
- (+) 12-bit left alignment using DAC_Align_12b_L
- (+) 12-bit right alignment using DAC_Align_12b_R
-
- [..] The analog output voltage on each DAC channel pin is determined
- by the following equation:
- (+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register.
- VREF+ is the input voltage reference (refer to the device datasheet)
- e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868);
- Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- [..] A DMA1 request can be generated when an external trigger (but not
- a software trigger) occurs if DMA1 requests are enabled using
- DAC_DMACmd()
- DMA1 requests are mapped as following:
- (+) DAC channel1 is mapped on DMA1 channel3 which must be already
- configured
- (+) DAC channel2 is mapped on DMA1 channel4 which must be already
- configured
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable DAC APB1 clock to get write access to DAC registers
- using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
-
- (+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
- in analog mode.
-
- (+) Configure the DAC channel using DAC_Init()
-
- (+) Enable the DAC channel using DAC_Cmd()
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_dac.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)
-
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/** @defgroup DAC_Group1 DAC channels configuration
- * @brief DAC channels configuration: trigger, output buffer, data format
- *
-@verbatim
- ===============================================================================
- ##### DAC channels configuration: trigger, output buffer, data format #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @retval None
- */
-void DAC_DeInit(DAC_TypeDef* DACx)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
-
- if (DACx == DAC1)
- {
- /* Enable DAC1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
- /* Release DAC1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
- }
- else
- {
- /* Enable DAC2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
- /* Release DAC2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the DAC peripheral according to the specified
- * parameters in the DAC_InitStruct.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
- * contains the configuration information for the specified DAC channel.
- * @retval None
- */
-void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DACx->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
- mask/amplitude for wave generation */
-
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch);
-
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DACx->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
- /* Initialize the DAC_Buffer_Switch member */
- DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the DAC channel is enabled the trigger source can no more
- * be modified.
- * @retval None
- */
-void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software
- * triggers.
- * @param DACx: where x can be 1 to select the DAC1 peripheral.
- * @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_LIST1_PERIPH(DACx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DACx->SWTRIGR |= DUAL_SWTRIG_SET;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param DACx: where x can be 1 to select the DAC1 peripheral.
- * @note Wave generation is not available in DAC2.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: Specifies the wave type to enable or disable.
- * This parameter can be one of the following values:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * @retval None
- */
-void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_LIST1_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DACx->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DACx->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Align: Specifies the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DACx;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel2.
- * @param DACx: where x can be 1 to select the DAC peripheral.
- * @note This function is available only for DAC1.
- * @param DAC_Align: Specifies the data alignment for DAC channel2.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data : Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_LIST1_PERIPH(DACx));
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DACx;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for dual channel DAC.
- * @param DACx: where x can be 1 to select the DAC peripheral.
- * @note This function isn't applicable for DAC2.
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data
- * holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data
- * holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval None
- */
-void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_LIST1_PERIPH(DACx));
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DACx;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DACx;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group2 DMA management functions
- * @brief DMA management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * When enabled DMA1 is generated when an external trigger (EXTI Line9,
- * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
- * must be already configured.
- * @retval None
- */
-void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before
- * the acknowledgement for the first external trigger is received (first request).
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DACx->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: thee selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before
- * the acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's pending flags.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @retval None
- */
-void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DACx->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before
- * the acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's interrupt pending bits.
- * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @retval None
- */
-void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_PERIPH(DACx));
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DACx->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c
deleted file mode 100644
index ced108ab773..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dbgmcu.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Debug MCU (DBGMCU) peripheral:
- * + Device and Revision ID management
- * + Peripherals Configuration
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_dbgmcu.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
- * @brief Device and Revision ID management functions
- *
-@verbatim
- ==============================================================================
- ##### Device and Revision ID management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
- * @brief Peripherals Configuration
- *
-@verbatim
- ==============================================================================
- ##### Peripherals Configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
- * Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
- * Core is halted.
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
- * Core is halted.
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
- * @param NewState: new state of the specified APB1 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
- * @param NewState: new state of the specified APB2 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c
deleted file mode 100644
index 0c33b67b0ba..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c
+++ /dev/null
@@ -1,866 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_dma.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable The DMA controller clock using
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
- using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
- (#) Enable and configure the peripheral to be connected to the DMA channel
- (except for internal SRAM / FLASH memories: no initialization is necessary).
- (#) For a given Channel, program the Source and Destination addresses,
- the transfer Direction, the Buffer Size, the Peripheral and Memory
- Incrementation mode and Data Size, the Circular or Normal mode,
- the channel transfer Priority and the Memory-to-Memory transfer
- mode (if needed) using the DMA_Init() function.
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
- (#) Enable the DMA channel using the DMA_Cmd() function.
- (#) Activate the needed channel Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- (#) Optionally, you can configure the number of data to be transferred
- when the channel is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
- enabled and running).
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_dma.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
-#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
-
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to initialize the DMA channel
- source and destination addresses, incrementation and data sizes, transfer
- direction, buffer size, circular/normal mode selection, memory-to-memory
- mode selection and channel priority value.
- [..] The DMA_Init() function follows the DMA configuration procedures as described
- in reference manual (RM00316).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DMAy Channelx registers to their default reset
- * values.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @retval None
- */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CCR = 0;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->CNDTR = 0;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->CPAR = 0;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->CMAR = 0;
-
- if (DMAy_Channelx == DMA1_Channel1)
- {
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel2)
- {
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel3)
- {
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel4)
- {
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel5)
- {
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel6)
- {
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel7)
- {
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
- }
- else if (DMAy_Channelx == DMA2_Channel1)
- {
- /* Reset interrupt pending bits for DMA2 Channel1 */
- DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
- }
- else if (DMAy_Channelx == DMA2_Channel2)
- {
- /* Reset interrupt pending bits for DMA2 Channel2 */
- DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
- }
- else if (DMAy_Channelx == DMA2_Channel3)
- {
- /* Reset interrupt pending bits for DMA2 Channel3 */
- DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
- }
- else if (DMAy_Channelx == DMA2_Channel4)
- {
- /* Reset interrupt pending bits for DMA2 Channel4 */
- DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
- }
- else
- {
- if (DMAy_Channelx == DMA2_Channel5)
- {
- /* Reset interrupt pending bits for DMA2 Channel5 */
- DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Channelx according to the specified parameters
- * in the DMA_InitStruct.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
- /* Get the DMAy_Channelx CCR value */
- tmpreg = DMAy_Channelx->CCR;
-
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= CCR_CLEAR_MASK;
-
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set DIR bit according to DMA_DIR value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set PL bits according to DMA_Priority value */
- /* Set the MEM2MEM bit according to DMA_M2M value */
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
- /* Write to DMAy Channelx CCR */
- DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
- /* Write to DMAy Channelx CPAR */
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
- /* Write to DMAy Channelx CMAR */
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
- /* Initialize the DMA_MemoryBaseAddr member */
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
- /* Initialize the DMA_M2M member */
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Channelx.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param NewState: new state of the DMAy Channelx.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Channelx */
- DMAy_Channelx->CCR |= DMA_CCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..] This subsection provides function allowing to configure and read the buffer
- size (number of data to be transferred).The DMA data counter can be written
- only when the DMA channel is disabled (ie. after transfer complete event).
- [..] The following function can be used to write the Channel data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
- [..]
- (@) It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- [..] The DMA data counter can be read to indicate the number of remaining transfers
- for the relative DMA channel. This counter is decremented at the end of each
- data transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial
- value(configured before enabling the DMA channel).
- [..] The following function can be used to read the Channel data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the number of data units in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DataNumber: The number of data units in the current DMAy Channelx
- * transfer.
- * @note This function can only be used when the DMAy_Channelx is disabled.
- * @retval None.
- */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DataNumber;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current
- * DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @retval The number of remaining data units in the current DMAy Channelx
- * transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- /* Return the number of remaining data units for DMAy Channelx */
- return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to configure the DMA Interrupt
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the DMA controller events: Polling mode or Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller
- number, x : DMA channel number):
- (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
- (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
- (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
- above occurred.
- [..]
- (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] Each DMA channel can be managed through 4 Interrupts:
- (+) Interrupt Source
- (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
- event.
- (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete
- event.
- (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
- (##) DMA_IT_GL: to indicate that at least one of the interrupts described
- above occurred.
- -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
- the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
- [..] In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DMAy Channelx interrupts.
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled
- * or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA interrupts */
- DMAy_Channelx->CCR |= DMA_IT;
- }
- else
- {
- /* Disable the selected DMA interrupts */
- DMAy_Channelx->CCR &= ~DMA_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx flag is set or not.
- * @param DMAy_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- *
- * @note
- * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
- * relative to the same channel is set (Transfer Complete, Half-transfer
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
- * DMAy_FLAG_TEx).
- *
- * @retval The new state of DMAy_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
-
- /* Calculate the used DMAy */
- if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR ;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR ;
- }
-
- /* Check the status of the specified DMAy flag */
- if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
- {
- /* DMAy_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMAy_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMAy_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's pending flags.
- * @param DMAy_FLAG: specifies the flag to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- *
- * @note
- * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
- * relative to the same channel (Transfer Complete, Half-transfer Complete and
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- *
- * @retval None
- */
-void DMA_ClearFlag(uint32_t DMAy_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
-
-/* Calculate the used DMAy */
- if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Clear the selected DMAy flags */
- DMA2->IFCR = DMAy_FLAG;
- }
- else
- {
- /* Clear the selected DMAy flags */
- DMA1->IFCR = DMAy_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
- * @param DMAy_IT: specifies the DMAy interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
- *
- * @note
- * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
- * interrupts relative to the same channel is set (Transfer Complete,
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
- * DMAy_IT_HTx or DMAy_IT_TEx).
- *
- * @retval The new state of DMAy_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMAy_IT));
-
- /* Calculate the used DMA */
- if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Get DMA2 ISR register value */
- tmpreg = DMA2->ISR;
- }
- else
- {
- /* Get DMA1 ISR register value */
- tmpreg = DMA1->ISR;
- }
-
- /* Check the status of the specified DMAy interrupt */
- if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
- {
- /* DMAy_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMAy_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DMAy_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's interrupt pending bits.
- * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
- *
- * @note
- * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
- * interrupts relative to the same channel (Transfer Complete, Half-transfer
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
- * DMAy_IT_TEx).
- *
- * @retval None
- */
-void DMA_ClearITPendingBit(uint32_t DMAy_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
-
- /* Calculate the used DMAy */
- if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
- {
- /* Clear the selected DMAy interrupt pending bits */
- DMA2->IFCR = DMAy_IT;
- }
- else
- {
- /* Clear the selected DMAy interrupt pending bits */
- DMA1->IFCR = DMAy_IT;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c
deleted file mode 100644
index 6f8a9d014f8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_exti.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### EXTI features #####
- ===============================================================================
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD output
- (#) EXTI line 17 is connected to the RTC Alarm event
- (#) EXTI line 18 is connected to USB Device wakeup event
- (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
- (#) EXTI line 20 is connected to the RTC wakeup event
- (#) EXTI line 21 is connected to the Comparator 1 wakeup event
- (#) EXTI line 22 is connected to the Comparator 2 wakeup event
- (#) EXTI line 23 is connected to the I2C1 wakeup event
- (#) EXTI line 24 is connected to the I2C2 wakeup event
- (#) EXTI line 25 is connected to the USART1 wakeup event
- (#) EXTI line 26 is connected to the USART2 wakeup event
- (#) EXTI line 27 is reserved
- (#) EXTI line 28 is connected to the USART3 wakeup event
- (#) EXTI line 29 is connected to the Comparator 3 event
- (#) EXTI line 30 is connected to the Comparator 4 event
- (#) EXTI line 31 is connected to the Comparator 5 event
- (#) EXTI line 32 is connected to the Comparator 6 event
- (#) EXTI line 33 is connected to the Comparator 7 event
- (#) EXTI line 34 is connected for thr UART4 wakeup event
- (#) EXTI line 35 is connected for the UART5 wakeup event
-
- ##### How to use this driver #####
- ===============================================================================
- [..] In order to use an I/O pin as an external interrupt source,
- follow steps below:
- (#) Configure the I/O in input mode using GPIO_Init().
- (#) Select the input source pin for the EXTI line using
- SYSCFG_EXTILineConfig().
- (#) Select the mode(interrupt, event) and configure the trigger
- selection (Rising, falling or both) using EXTI_Init(). For the
- internal interrupt, the trigger selection is not needed
- (the active edge is always the rising one).
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
- (#) Optionally, you can generate a software interrupt using the function
- EXTI_GenerateSWInterrupt().
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_exti.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x1F800000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->SWIER = 0x00000000;
- EXTI->PR = 0xE07FFFFF;
- EXTI->IMR2 = 0x0000000C;
- EXTI->EMR2 = 0x00000000;
- EXTI->RTSR2 = 0x00000000;
- EXTI->FTSR2 = 0x00000000;
- EXTI->SWIER2 = 0x00000000;
- EXTI->PR2 = 0x00000003;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
- * EXTI_Mode specifies which EXTI line is used as interrupt or an event.
- * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
- * pending bit will be set.
- * EXTI_LineCmd controls (Enable/Disable) the EXTI line.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
- * contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-
-
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
-
- tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
-
- *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
-
- tmp = (uint32_t)EXTI_BASE;
-
- /* Clear Rising Falling edge configuration */
- *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
-
- /* Select the trigger for the selected interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
-
- *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- }
- }
-
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
- }
-
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt
- * will be generated.
- * This parameter can be any combination of EXTI_Linex where x can be (0..20).
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
-
- *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- * @brief EXTI Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the EXTI Interrupts
- sources and check or clear the flags or pending bits status.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be any combination of EXTI_Linex where x can be (0..20).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..20).
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
-
- *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be any combination of EXTI_Linex where x can be (0..20).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-
-}
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..20).
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
-
- *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c
deleted file mode 100644
index 20b9782557e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c
+++ /dev/null
@@ -1,1170 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_flash.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * + FLASH Interface configuration
- * + FLASH Memory Programming
- * + Option Bytes Programming
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions to configure and program the FLASH
- memory of all STM32F30x devices. These functions are split in 4 groups:
- (#) FLASH Interface configuration functions: this group includes the
- management of following features:
- (++) Set the latency.
- (++) Enable/Disable the Half Cycle Access.
- (++) Enable/Disable the prefetch buffer.
- (#) FLASH Memory Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the FLASH interface.
- (++) Erase function: Erase page, erase all pages.
- (++) Program functions: Half Word and Word write.
- (#) FLASH Option Bytes Programming functions: this group includes all
- needed functions to manage the Option Bytes:
- (++) Lock and Unlock the Flash Option bytes.
- (++) Launch the Option Bytes loader
- (++) Erase the Option Bytes
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user option Bytes
- (++) Set/Reset the BOOT1 bit
- (++) Enable/Disable the VDDA Analog Monitoring
- (++) Enable/Disable the SRAM parity
- (++) Get the user option bytes
- (++) Get the Write protection
- (++) Get the read protection status
- (#) FLASH Interrupts and flags management functions: this group includes
- all needed functions to:
- (++) Enable/Disable the FLASH interrupt sources.
- (++) Get flags status.
- (++) Clear flags.
- (++) Get FLASH operation status.
- (++) Wait for last FLASH operation.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_flash.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* FLASH Mask */
-#define RDPRT_MASK ((uint32_t)0x00000002)
-#define WRP01_MASK ((uint32_t)0x0000FFFF)
-#define WRP23_MASK ((uint32_t)0xFFFF0000)
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
- [..] This group includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency);
- (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
- [..] The unlock sequence is not needed for these functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @arg FLASH_Latency_2: FLASH Two Latency cycles
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Read the ACR register */
- tmpreg = FLASH->ACR;
-
- /* Sets the Latency value */
- tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
- tmpreg |= FLASH_Latency;
-
- /* Write the ACR register */
- FLASH->ACR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Half cycle flash access.
- * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
- * This parameter can be one of the following values:
- * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
- * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
- * @retval None
- */
-void FLASH_HalfCycleAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_HLFCYA;
- }
- else
- {
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_HLFCYA));
- }
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the Prefetch Buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- }
- else
- {
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
- [..] This group includes the following functions:
- (+) void FLASH_Unlock(void);
- (+) void FLASH_Lock(void);
- (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
- (+) FLASH_Status FLASH_EraseAllPages(void);
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
- [..] Any operation of erase or program should follow these steps:
- (#) Call the FLASH_Unlock() function to enable the FLASH control register
- program memory access.
- (#) Call the desired function to erase page or program data.
- (#) Call the FLASH_Lock() function to disable the FLASH control register
- access (recommended to protect the FLASH memory against possible
- unwanted operation).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
- }
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified page in program memory.
- * @note To correctly run this function, the FLASH_Unlock() function
- * must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Page_Address: The page address in program memory to be erased.
- * @note A Page is erased in the Program memory only if the address to load
- * is the start address of a page (multiple of 1024 bytes).
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the page */
- FLASH->CR |= FLASH_CR_PER;
- FLASH->AR = Page_Address;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PER Bit */
- FLASH->CR &= ~FLASH_CR_PER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH pages.
- * @note To correctly run this function, the FLASH_Unlock() function
- * must be called before.
- * all the FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the MER Bit */
- FLASH->CR &= ~FLASH_CR_MER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function
- * must be called before.
- * Call the FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function
- * must be called before.
- * Call the FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new data */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
- [..] This group includes the following functions:
- (+) void FLASH_OB_Unlock(void);
- (+) void FLASH_OB_Lock(void);
- (+) void FLASH_OB_Erase(void);
- (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
- (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
- (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
- (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
- (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
- (+) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
- (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
- (+) FLASH_Status FLASH_OB_Launch(void);
- (+) uint32_t FLASH_OB_GetUser(void);
- (+) uint8_t FLASH_OB_GetWRP(void);
- (+) uint8_t FLASH_OB_GetRDP(void);
- [..] Any operation of erase or program should follow these steps:
- (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
- register access.
- (#) Call one or several functions to program the desired Option Bytes:
- (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
- => to Enable/Disable the desired sector write protection.
- (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the
- desired read Protection Level.
- (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
- => to configure the user Option Bytes.
- (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
- => to set the boot1 mode
- (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
- => to Enable/Disable the VDDA monotoring.
- (++) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
- => to Enable/Disable the SRAM Parity check.
- (++) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
- => to write all user option bytes: OB_IWDG, OB_STOP, OB_STDBY,
- OB_BOOT1, OB_VDDA_ANALOG and OB_VDD_SD12.
- (#) Once all needed Option Bytes to be programmed are correctly written,
- call the FLASH_OB_Launch() function to launch the Option Bytes
- programming process.
- (#@) When changing the IWDG mode from HW to SW or from SW to HW, a system
- reset is needed to make the change effective.
- (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
- register access (recommended to protect the Option Bytes against
- possible unwanted operations).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
- {
- /* Unlocking the option bytes block access */
- FLASH->OPTKEYR = FLASH_OPTKEY1;
- FLASH->OPTKEYR = FLASH_OPTKEY2;
- }
-}
-
-/**
- * @brief Locks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTWREN Bit to lock the option bytes block access */
- FLASH->CR &= ~FLASH_CR_OPTWRE;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval None
- */
-void FLASH_OB_Launch(void)
-{
- /* Set the OBL_Launch bit to launch the option byte loading */
- FLASH->CR |= FLASH_CR_OBL_LAUNCH;
-}
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_Erase(void)
-{
- uint16_t rdptmp = OB_RDP_Level_0;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Get the actual read protection Option Byte value */
- if(FLASH_OB_GetRDP() != RESET)
- {
- rdptmp = 0x00;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- /* Restore the last read protection Option Byte value */
- OB->RDP = (uint16_t)rdptmp;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if (status != FLASH_TIMEOUT)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Write protects the desired pages
- * @note To correctly run this function, the FLASH_OB_Unlock() function
- * must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_WRP: specifies the address of the pages to be write protected.
- * This parameter can be:
- * @arg value between OB_WRP_Pages0to35 and OB_WRP_Pages60to63
- * @arg OB_WRP_AllPages
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
-{
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
-
- OB_WRP = (uint32_t)(~OB_WRP);
- WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
- WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTPG;
-
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/**
- * @brief Enables or disables the read out protection.
- * @note To correctly run this function, the FLASH_OB_Unlock() function
- * must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param FLASH_ReadProtection_Level: specifies the read protection level.
- * This parameter can be:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Chip protection
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->RDP = OB_RDP;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if(status != FLASH_TIMEOUT)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param OB_IWDG: Selects the IWDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software IWDG selected
- * @arg OB_IWDG_HW: Hardware IWDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = (uint8_t)((uint8_t)(OB_IWDG | OB_STOP) | (uint8_t)(OB_STDBY |0xF8));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT1.
- * @param OB_BOOT1: Set or Reset the BOOT1.
- * This parameter can be one of the following values:
- * @arg OB_BOOT1_RESET: BOOT1 Reset
- * @arg OB_BOOT1_SET: BOOT1 Set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT1(OB_BOOT1));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT1|0xEF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the analogue monitoring on VDDA Power source.
- * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
- * This parameter can be one of the following values:
- * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
- * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
- * @retval None
- */
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_VDDA_ANALOG |0xDF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the SRAM partiy.
- * @param OB_SRAM_Parity: Set or Reset the SRAM partiy enable bit.
- * This parameter can be one of the following values:
- * @arg OB_SRAM_PARITY_SET: Set SRAM partiy.
- * @arg OB_SRAM_PARITY_RESET: Reset SRAM partiy.
- * @retval None
- */
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_SRAM_Parity | 0xBF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY/ BOOT1 and OB_VDDA_ANALOG.
- * @note To correctly run this function, the FLASH_OB_Unlock() function
- * must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_USER: Selects all user option bytes
- * This parameter is a combination of the following values:
- * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
- * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
- * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
- * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
- * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Authorize the small information block programming */
- FLASH->OPTKEYR = FLASH_KEY1;
- FLASH->OPTKEYR = FLASH_KEY2;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_USER | 0x88;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note To correctly run this function, the FLASH_OB_Unlock() function
- * must be called before.
- * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes .
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OBR >> 8);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(FLASH->WRPR);
-}
-
-/**
- * @brief Checks whether the FLASH Read out Protection Status is set or not.
- * @param None
- * @retval FLASH ReadOut Protection Status(SET or RESET)
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or
- * disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be:
- * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status FLASHstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- FLASHstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- FLASHstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the FLASH Status */
- return FLASHstatus;
-}
-
-/**
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_BUSY,
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- status = FLASH_GetStatus();
- Timeout--;
- }
-
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c
deleted file mode 100644
index 006b9c77cc0..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c
+++ /dev/null
@@ -1,535 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_gpio.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * + Initialization and Configuration functions
- * + GPIO Read and Write functions
- * + GPIO Alternate functions configuration functions
- *
- * @verbatim
-
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
- (#) Configure the GPIO pin(s) using GPIO_Init()
- Four possible configuration are available for each pin:
- (++) Input: Floating, Pull-up, Pull-down.
- (++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
- Open Drain (Pull-up, Pull-down or no Pull).
- In output mode, the speed is configurable: Low, Medium, Fast or High.
- (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
- Open Drain (Pull-up, Pull-down or no Pull).
- (++) Analog: required mode when a pin is to be used as ADC channel,
- DAC output or comparator input.
- (#) Peripherals alternate function:
- (++) For ADC, DAC and comparators, configure the desired pin in
- analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
- (++) For other peripherals (TIM, USART...):
- (+++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (+++) Configure the desired pin in alternate function mode using
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (+++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (+++) Call GPIO_Init() function.
- (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
- (#) To set/reset the level of a pin configured in output mode use
- GPIO_SetBits()/GPIO_ResetBits()
- (#) During and just after reset, the alternate functions are not active
- and the GPIO pins are configured in input floating mode (except JTAG pins).
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
- general-purpose (PC14 and PC15, respectively) when the LSE
- oscillator is off. The LSE has priority over the GPIO function.
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
- (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
- the priority over the GPIO function.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_gpio.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if(GPIOx == GPIOA)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
- }
- else if(GPIOx == GPIOB)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
- }
- else if(GPIOx == GPIOC)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
- }
- else if(GPIOx == GPIOD)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
- }
- else if(GPIOx == GPIOE)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
- }
- else
- {
- if(GPIOx == GPIOF)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
- * contains the configuration information for the specified GPIO
- * peripheral.
- * @note GPIO_Pin: selects the pin to be configured:
- * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
- * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
- * and GPIO_Pin_10 for GPIOF.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
- uint32_t tmpreg = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /*-------------------------- Configure the port pins -----------------------*/
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration */
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- /* Use temporary variable to update PUPDR register configuration, to avoid
- unexpected transition in the GPIO pin configuration. */
- tmpreg = GPIOx->PUPDR;
- tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- GPIOx->PUPDR = tmpreg;
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval The input port pin value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: Specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BRR = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * @note This parameter can be GPIO_Pin_x where x can be :
- * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
- * (0..2, 4, 6, 9..10) for GPIOF.
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enumeration values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port output data
- * register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
- * @brief GPIO Alternate functions configuration functions
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15).
- * @param GPIO_AF: selects the pin to be used as Alternate function.
- * This parameter can be one of the following value:
- * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
- * TRACED, TRACECK.
- * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
- * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
- * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
- * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
- * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
- * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
- * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
- * USART2, USART3.
- * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
- * COMP6_OUT.
- * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
- * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
- * @arg GPIO_AF_11: TIM1, TIM8.
- * @arg GPIO_AF_12: TIM1, HRTIM.
- * @arg GPIO_AF_13: HRTIM, AOP2_OUT.
- * @arg GPIO_AF_14: USBDM, USBDP.
- * @arg GPIO_AF_15: OUT.
- * @note The pin should already been configured in Alternate Function mode(AF)
- * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * @note Refer to the Alternate function mapping table in the device datasheet
- * for the detailed mapping of the system and peripherals alternate
- * function I/O pins.
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_hrtim.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_hrtim.c
deleted file mode 100644
index 06c2d33080a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_hrtim.c
+++ /dev/null
@@ -1,4109 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_hrtim.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief HRTIMx module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the HRTIMx peripheral:
- * + Initialization/de-initialization methods
- * + I/O operation methods
- * + Peripheral Control methods
- *
- @verbatim
-================================================================================
- ##### © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_hrtim.h"
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup HRTIM
- * @brief HRTIM driver module
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
- HRTIM_FLTR_FLT2EN |\
- HRTIM_FLTR_FLT3EN |\
- HRTIM_FLTR_FLT4EN | \
- HRTIM_FLTR_FLT5EN)
-
-#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
- HRTIM_TIMUPDATETRIGGER_TIMER_A |\
- HRTIM_TIMUPDATETRIGGER_TIMER_B |\
- HRTIM_TIMUPDATETRIGGER_TIMER_C |\
- HRTIM_TIMUPDATETRIGGER_TIMER_D |\
- HRTIM_TIMUPDATETRIGGER_TIMER_E)
-
-#define HRTIM_TIM_OFFSET (uint32_t)0x00000080
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static uint32_t TimerIdxToTimerId[] =
-{
- HRTIM_TIMERID_TIMER_A,
- HRTIM_TIMERID_TIMER_B,
- HRTIM_TIMERID_TIMER_C,
- HRTIM_TIMERID_TIMER_D,
- HRTIM_TIMERID_TIMER_E,
- HRTIM_TIMERID_MASTER,
-};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
-static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
-static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
-static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_TimerInitTypeDef * TimerInit);
-static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * CompareCfg);
-static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event);
-static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * OutputCfg);
-static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t Event,
- HRTIM_EventCfgTypeDef * EventCfg);
-static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Event);
- /** @defgroup HRTIM_Private_Functions
- * @{
- */
-
-/** @defgroup HRTIM_Group1 Initialization/de-initialization methods
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization/de-initialization methods #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+)Initializes timer in basic time base mode
- (+)Initializes timer in basic OC mode
- (+)Initializes timer in basic PWM mode
- (+)Initializes timer in basic Capture mode
- (+)Initializes timer in One Pulse mode
- (+)Initializes a timer operating in waveform mode
- (+)De-initializes the HRTIMx timer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HRTIMx timer in basic time base mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 for master timer
- * @arg 0x1 to 0x5 for timers A to E
- * @note The time-base unit initialization parameters specify:
- * The timer counter operating mode (continuous, one shot)
- * The timer clock prescaler
- * The timer period
- * The timer repetition counter.
- * @retval None
- */
-void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure master timer */
- HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
- }
- else
- {
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
- }
-}
-
-/**
- * @brief De-initializes a timer operating in all mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @retval None
- */
-void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
-{
- (void)HRTIMx;
- /* Check the parameters */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE);
- }
-
-/**
- * @brief Initializes the HRTIMx timer in basic output compare mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x1 to 0x5 for timers A to E
- * @note Initializes the time-base unit of the timer and prepare it to
- * operate in output compare mode
- * @retval None
- */
-void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
-
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
-}
-
-/**
- * @brief Initializes the HRTIMx timer in basic PWM mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x1 to 0x5 for timers A to E
- * @note Initializes the time-base unit of the timer and prepare it to
- * operate in capture mode
- * @retval None
- */
-void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
-
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
-}
-
-/**
- * @brief Initializes a timer operating in basic capture mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x1 to 0x5 for timers A to E
- * @retval None
- */
-void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
-
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
-}
-
-/**
- * @brief Initializes the HRTIMx timer in basic one pulse mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x1 to 0x5 for timers A to E
- * @note Initializes the time-base unit of the timer and prepare it to
- * operate in one pulse mode. In this mode the counter operates
- * in single shot mode (retriggerable or not)
- * @retval None
- */
-void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
-
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
-}
-
-/**
- * @brief Initializes a timer operating in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 for master timer
- * @arg 0x1 to 0x5 for timers A to E
- * @param pTimerInit: pointer to the timer initialization data structure
- * @retval None
- */
-void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
- HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
- assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
- assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
- assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
- assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
- assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
- assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate));
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
-
- /* Configure master timer */
- HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
- HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
- }
- else
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
-
- /* Configure timing unit */
- HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
- HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Group2 I/O operation methods
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation methods #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the HRTIMx data
- transfers.
- (+) Starts the DLL calibration.
- (+) Starts / stops the counter of a timer operating in basic time base mode
- (+) Starts / stops the output compare signal generation on the designed timer output
- (+) Starts / stops the PWM output signal generation on the designed timer output
- (+) Enables / disables a basic capture on the designed capture unit
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the DLL calibration
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param CalibrationRate: DLL calibration period
- * This parameter can be one of the following values:
- * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
- * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms
- * @arg HRTIM_CALIBRATIONRATE_910: 910 us
- * @arg HRTIM_CALIBRATIONRATE_114: 114 us
- * @arg HRTIM_CALIBRATIONRATE_14: 14 us
- * @retval None
- */
-void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
-{
- uint32_t HRTIM_dllcr;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
-
- /* Configure DLL Calibration */
- HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
-
- if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
- {
- /* One shot DLL calibration */
- HRTIM_dllcr &= ~(HRTIM_DLLCR_CALEN);
- HRTIM_dllcr |= HRTIM_DLLCR_CAL;
- }
- else
- {
- /* Periodic DLL calibration */
- HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
- HRTIM_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
- }
-
- /* Update HRTIMx register */
- HRTIMx->HRTIM_COMMON.DLLCR = HRTIM_dllcr;
-
-}
-/**
- * @brief Starts the counter of a timer operating in basic time base mode
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval None
- */
-void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Enable the timer counter */
- __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Stops the counter of a timer operating in basic time base mode
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval None
- */
-void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Disable the timer counter */
- __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Enable the timer output */
- (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
-
- /* Enable the timer counter */
- __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Disable the timer output */
- HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
-
- /* Disable the timer counter */
- __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Enable the timer output */
- HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
-
- /* Enable the timer counter */
- __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Disable the timer output */
- HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
-
- /* Disable the timer counter */
- __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Enables a basic capture on the designed capture unit
- * @param HRTIMx: pointer to HRTIM peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval None
- * @note The external event triggering the capture is available for all timing
- * units. It can be used directly and is active as soon as the timing
- * unit counter is enabled.
- */
-void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- (void)CaptureChannel;
- /* Enable the timer counter */
- __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-
-}
-
-/**
- * @brief Disables a basic capture on the designed capture unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval None
- */
-void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
- }
-
-}
-
-/**
- * @brief Enables the basic one pulse signal generation on the designed output
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Enable the timer output */
- HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
-
- /* Enable the timer counter */
- __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Disables the basic one pulse signal generation on the designed output
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Disable the timer output */
- HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
-
- /* Disable the timer counter */
- __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimersToStart: Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_TIMER_A
- * @arg HRTIM_TIMERID_TIMER_B
- * @arg HRTIM_TIMERID_TIMER_C
- * @arg HRTIM_TIMERID_TIMER_D
- * @arg HRTIM_TIMERID_TIMER_E
- * @retval None
- */
-void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
- uint32_t TimersToStart)
-{
- /* Enable timer(s) counter */
- HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
-}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimersToStop: Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_TIMER_A
- * @arg HRTIM_TIMERID_TIMER_B
- * @arg HRTIM_TIMERID_TIMER_C
- * @arg HRTIM_TIMERID_TIMER_D
- * @arg HRTIM_TIMERID_TIMER_E
- * @retval None
- */
-void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
- uint32_t TimersToStop)
-{
- /* Disable timer(s) counter */
- HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
-}
-
-/**
- * @brief Enables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output enabling
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param OutputsToStart: Timer output(s) to enable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
- uint32_t OutputsToStart)
-{
- /* Enable the HRTIM outputs */
- HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
-}
-
-/**
- * @brief Disables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output disabling
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param OutputsToStop: Timer output(s) to disable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval None
- */
-void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
- uint32_t OutputsToStop)
-{
- /* Disable the HRTIM outputs */
- HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
-}
-
-/**
- * @brief Enables or disables the Master and slaves interrupt request
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
- * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
- * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
- * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
- * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
- * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
-{
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- if(NewState != DISABLE)
- {
- HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
- }
- else
- {
- HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
- }
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- if(NewState != DISABLE)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
- }
- else
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
- }
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Enables or disables the common interrupt request
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
- * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
- * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
- * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
- * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
- * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
-{
- if(NewState != DISABLE)
- {
- HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
- }
- else
- {
- HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
- }
-}
-
-/**
- * @brief Clears the Master and slaves interrupt flags
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
- * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
- * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
- * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
- * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
- * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag
- * @retval None
- */
-void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
-{
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Clears the common interrupt flags
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
- * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
- * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
- * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
- * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
- * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
- * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
- * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
- * @retval None
- */
-void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
-{
- HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
-}
-
-/**
- * @brief Clears the Master and slaves interrupt request pending bits
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
- * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
- * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
- * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
- * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source
- * @retval None
- */
-void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
-{
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Clears the common interrupt pending bits
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
- * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
- * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
- * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
- * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
- * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
- * @retval None
- */
-void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
-{
- HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
-}
-
-
-/**
- * @brief Checks whether the specified HRTIM flag is set or not.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_FLAG: specifies the HRTIM flags to check.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
- * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
- * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
- * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
- * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
- * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
- * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
- * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
- * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag
- * @retval The new state of HRTIM_FLAG (SET or RESET).
- */
-FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
-{
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- FlagStatus bitstatus = RESET;
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- break;
-
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- break;
-
- default:
- break;
- }
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified HRTIM common flag is set or not.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param HRTIM_FLAG: specifies the HRTIM flags to check.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
- * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
- * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
- * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
- * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
- * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
- * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
- * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
- * @retval The new state of HRTIM_FLAG (SET or RESET).
- */
-FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
-{
- FlagStatus bitstatus = RESET;
-
- if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified HRTIM interrupt has occurred or not.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt
- * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt
- * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt
- * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt
- * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt
- * @retval The new state of the HRTIM_IT(SET or RESET).
- */
-ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
-
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
-
- itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- break;
-
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
-
- itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- }
- break;
-
- default:
- break;
- }
- return bitstatus;
-}
-
-/**
- * @brief Checks whether the specified HRTIM common interrupt has occurred or not.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param HRTIM_IT: specifies the HRTIM interrupt source to check.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt
- * @arg HRTIM_IT_FLT4: Fault 4 Interrupt
- * @arg HRTIM_IT_FLT5: Fault 5 Interrupt
- * @arg HRTIM_IT_SYSFLT: System Fault Interrupt
- * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag
- * @arg HRTIM_IT_BMPER: Burst mode period Interrupt
- * @retval The new state of HRTIM_FLAG (SET or RESET).
- */
-ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
-
- itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
- itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
-
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Enables or disables the HRTIMx's DMA Requests.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param HRTIM_DMA: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source
- * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source
- * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source
- * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source
- * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source
- * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source
- * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source
- * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source
- * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source
- * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source
- * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source
- * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source
- * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source
- * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source
- * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source
- * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source
- * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source
- * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source
- * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source
- * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source
- * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
-{
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- switch(TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- if(NewState != DISABLE)
- {
- HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
- }
- else
- {
- HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
- }
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- case HRTIM_TIMERINDEX_TIMER_B:
- case HRTIM_TIMERINDEX_TIMER_C:
- case HRTIM_TIMERINDEX_TIMER_D:
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- if(NewState != DISABLE)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
- }
- else
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
- }
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Group3 Peripheral Control methods
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control methods #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the HRTIMx data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output in basic output compare mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OCChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure
- * @note When the timer operates in basic output compare mode:
- * Output 1 is implicitely controled by the compare unit 1
- * Output 2 is implicitely controled by the compare unit 2
- * Output Set/Reset crossbar is set according to the selected output compare mode:
- * Toggle: SETxyR = RSTxyR = CMPy
- * Active: SETxyR = CMPy, RSTxyR = 0
- * Inactive: SETxy =0, RSTxy = CMPy
- * @retval None
- */
-void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
-{
- uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
- assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
-
- /* Configure timer compare unit */
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(HRTIMx,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
- OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
- OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- switch (pBasicOCChannelCfg->Mode)
- {
- case HRTIM_BASICOCMODE_TOGGLE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = OutputCfg.SetSource;
- }
- break;
- case HRTIM_BASICOCMODE_ACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
- }
- break;
- case HRTIM_BASICOCMODE_INACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
- }
- else
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
- }
- OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
- }
- break;
- default:
- break;
- }
-
- HRTIM_OutputConfig(HRTIMx, TimerIdx, OCChannel, &OutputCfg);
-}
-
-/**
- * @brief Configures an output in basic PWM mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param PWMChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure
- * @note When the timer operates in basic PWM output mode:
- * Output 1 is implicitly controled by the compare unit 1
- * Output 2 is implicitly controled by the compare unit 2
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * @retval None
- */
-void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
-{
- uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
-
- /* Configure timer compare unit */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(HRTIMx,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
- OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
- OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(HRTIMx, TimerIdx, PWMChannel, &OutputCfg);
-}
-
-/**
- * @brief Configures a basic capture
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureChannel: Capture unit
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure
- * @note When the timer operates in basic capture mode the capture is triggered
- * by the designated external event and GPIO input is implicitly used as event source.
- * The cature can be triggered by a rising edge, a falling edge or both
- * edges on event channel.
- * @retval None
- */
-void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
-{
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
- assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
- EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_ExternalEventConfig(HRTIMx,
- pBasicCaptureChannelCfg->Event,
- &EventCfg);
-
- /* Memorize capture trigger (will be configured when the capture is started */
- HRTIM_CaptureUnitConfig(HRTIMx,
- TimerIdx,
- CaptureChannel,
- pBasicCaptureChannelCfg->Event);
-}
-
-/**
- * @brief Configures an output basic one pulse mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param OnePulseChannel: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
- * @note When the timer operates in basic one pulse mode:
- * the timer counter is implicitly started by the reset event,
- * the reset of the timer counter is triggered by the designated external event
- * GPIO input is implicitly used as event source,
- * Output 1 is implicitly controled by the compare unit 1,
- * Output 2 is implicitly controled by the compare unit 2.
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
- * @retval None
- */
-void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel,
- HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
-{
- uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
- assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
- assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
-
- /* Configure timer compare unit */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
-
- HRTIM_CompareUnitConfig(HRTIMx,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
- OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
- OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(HRTIMx,
- TimerIdx,
- OnePulseChannel,
- &OutputCfg);
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
- EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_ExternalEventConfig(HRTIMx,
- pBasicOnePulseChannelCfg->Event,
- &EventCfg);
-
- /* Configure the timer reset register */
- HRTIM_TIM_ResetConfig(HRTIMx,
- TimerIdx,
- pBasicOnePulseChannelCfg->Event);
-}
-
-/**
- * @brief Configures the general behavior of a timer operating in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param pTimerCfg: pointer to the timer configuration structure
- * @note When the timer operates in waveform mode, all the features supported by
- * the HRTIMx are available without any limitation.
- * @retval None
- */
-void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- uint32_t HRTIM_timcr;
- uint32_t HRTIM_timfltr;
- uint32_t HRTIM_timoutr;
- uint32_t HRTIM_timrstr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
- assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
- assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
- assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion));
- assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode));
- assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
- assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
- assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
-
- /* Configure timing unit (Timer A to Timer E) */
- HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
- HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
- HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
- HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
-
- /* Set the push-pull mode */
- HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
- HRTIM_timcr |= pTimerCfg->PushPull;
-
- /* Enable/Disable registers update on timer counter reset */
- HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
- HRTIM_timcr |= pTimerCfg->ResetUpdate;
-
- /* Set the timer update trigger */
- HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
- HRTIM_timcr |= pTimerCfg->UpdateTrigger;
-
- /* Enable/Disable the fault channel at timer level */
- HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
- HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
-
- /* Lock/Unlock fault sources at timer level */
- HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
- HRTIM_timfltr |= pTimerCfg->FaultLock;
-
- /* Enable/Disable dead time insertion at timer level */
- HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
- HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
-
- /* Enable/Disable delayed protection at timer level */
- HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
- HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
-
- /* Set the timer counter reset trigger */
- HRTIM_timrstr = pTimerCfg->ResetTrigger;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
- HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
- HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
- }
-
-/**
- * @brief Configures the compare unit of a timer operating in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * 0xFF for master timer
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CompareUnit: Compare unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param pCompareCfg: pointer to the compare unit configuration structure
- * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
- * application has to configure separately the capture unit. Capture unit
- * to configure in that case depends on the compare unit auto delayed mode
- * is applied to (see below):
- * Auto delayed on output compare 2: capture unit 1 must be configured
- * Auto delayed on output compare 4: capture unit 2 must be configured
- * @retval None
- */
- void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef* pCompareCfg)
-{
- uint32_t HRTIM_timcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
-
- /* Configure the compare unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
- HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
- HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
- HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
- HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Sets the HRTIMx Master Comparex Register value
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param CompareUnit: Compare unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param Compare: specifies the Comparex register new value
- * @retval None
- */
-void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
- uint32_t CompareUnit,
- uint32_t Compare)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
-
- /* Configure the compare unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Sets the HRTIMx Slave Comparex Register value
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param CompareUnit: Compare unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param Compare: specifies the Comparex register new value
- * @retval None
- */
-void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- uint32_t Compare)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
-
- /* Configure the compare unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = Compare;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- /* Set the compare value */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = Compare;
- }
- break;
- default:
- break;
- }
-}
-/**
- * @brief Configures the capture unit of a timer operating in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureChannel: Capture unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pCaptureCfg: pointer to the compare unit configuration structure
- * @retval None
- */
-void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- HRTIM_CaptureCfgTypeDef* pCaptureCfg)
-{
- /* Configure the capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the output of a timer operating in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pOutputCfg: pointer to the timer output configuration structure
- * @retval None
- */
-void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState));
- assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
- assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState));
- assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
- assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
-
- /* Configure the timer output */
- HRTIM_OutputConfig(HRTIMx, TimerIdx, Output, pOutputCfg);
-}
-
-/**
- * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Event: external event for which timer event filtering must be configured
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
- * @retval None
- */
-void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Event,
- HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
-{
- uint32_t HRTIM_eefr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_EVENT(Event));
- assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
- assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
-
- /* Configure timer event filtering capabilities */
- switch (Event)
- {
- case HRTIM_TIMEVENTFILTER_NONE:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
- }
- break;
- case HRTIM_EVENT_1:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
- HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
- HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_2:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
- HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_3:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
- HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_4:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
- HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_5:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
- HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_6:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
- HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
- HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_7:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
- HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_8:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
- HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_9:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
- HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
- }
- break;
- case HRTIM_EVENT_10:
- {
- HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
- HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
- HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
- HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the dead time insertion feature for a timer
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure
- * @retval None
- */
-void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
-{
- uint32_t HRTIM_dtr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
-
- HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
-
- /* Clear timer dead times configuration */
- HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
- HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
- HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
-
- /* Set timer dead times configuration */
- HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
- HRTIM_dtr |= pDeadTimeCfg->RisingValue;
- HRTIM_dtr |= pDeadTimeCfg->RisingSign;
- HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
- HRTIM_dtr |= pDeadTimeCfg->RisingLock;
- HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
- HRTIM_dtr |= pDeadTimeCfg->FallingSign;
- HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
- HRTIM_dtr |= pDeadTimeCfg->FallingLock;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
-}
-
-/**
- * @brief Configures the chopper mode feature for a timer
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param pChopperModeCfg: pointer to the chopper mode configuration structure
- * @retval None
- */
-void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
-{
- uint32_t HRTIM_chpr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
-
- /* Clear timer chopper mode configuration */
- HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
-
- /* Set timer chopper mode configuration */
- HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
- HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
- HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
-}
-
-/**
- * @brief Configures the burst DMA controller for a timer
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param RegistersToUpdate: registers to be written by DMA
- * This parameter can be any combination of the following values:
- * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
- * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
- * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
- * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
- * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
- * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
- * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
- * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
- * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
- * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
- * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
- * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
- * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
- * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
- * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
- * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
- * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
- * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
- * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
- * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
- * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
- * @retval None
- */
-void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t RegistersToUpdate)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
-
- /* Set the burst DMA timer update register */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_MASTER:
- {
- HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the external input/output synchronization of the HRTIMx
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param pSynchroCfg: pointer to the input/output synchronization configuration structure
- * @retval None
- */
-void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
-{
- uint32_t HRTIM_mcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource));
- assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource));
- assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity));
-
- HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
-
- /* Set the synchronization input source */
- HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
- HRTIM_mcr |= pSynchroCfg->SyncInputSource;
-
- /* Set the event to be sent on the synchronization output */
- HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
- HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
-
- /* Set the polarity of the synchronization output */
- HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
- HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
-}
-
-/**
- * @brief Configures the burst mode feature of the HRTIMx
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param pBurstModeCfg: pointer to the burst mode configuration structure
- * @retval None
- */
-void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
- HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
-{
- uint32_t HRTIM_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
- assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
- assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
- assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
-
- HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
-
- /* Set the burst mode operating mode */
- HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
- HRTIM_bmcr |= pBurstModeCfg->Mode;
-
- /* Set the burst mode clock source */
- HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
- HRTIM_bmcr |= pBurstModeCfg->ClockSource;
-
- /* Set the burst mode prescaler */
- HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
- HRTIM_bmcr |= pBurstModeCfg->Prescaler;
-
- /* Enable/disable burst mode registers preload */
- HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
- HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
-
- /* Set the burst mode trigger */
- HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
-
- /* Set the burst mode compare value */
- HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
-
- /* Set the burst mode period */
- HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
-}
-
-/**
- * @brief Configures the conditioning of an external event
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Event: external event to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pEventCfg: pointer to the event conditioning configuration structure
- * @retval None
- */
-void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t Event,
- HRTIM_EventCfgTypeDef* pEventCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
- assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
- assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode));
- assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter));
-
- /* Configure the event channel */
- HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
-
-}
-
-/**
- * @brief Configures the external event conditioning block prescaler
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Prescaler: Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx
- * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2
- * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4
- * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8
- * @retval None
- */
-void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t Prescaler)
-{
- uint32_t HRTIM_eecr3;
-
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
-
- /* Set the external event prescaler */
- HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
- HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
- HRTIM_eecr3 |= Prescaler;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
-}
-
-/**
- * @brief Configures the conditioning of fault input
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Fault: fault input to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param pFaultCfg: pointer to the fault conditioning configuration structure
- * @retval None
- */
-void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
- HRTIM_FaultCfgTypeDef* pFaultCfg,
- uint32_t Fault)
-{
- uint32_t HRTIM_fltinr1;
- uint32_t HRTIM_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Fault));
- assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
- assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
- assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
- assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
-
- /* Configure fault channel */
- HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
- HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
-
- switch (Fault)
- {
- case HRTIM_FAULT_1:
- {
- HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
- HRTIM_fltinr1 |= pFaultCfg->Polarity;
- HRTIM_fltinr1 |= pFaultCfg->Source;
- HRTIM_fltinr1 |= pFaultCfg->Filter;
- HRTIM_fltinr1 |= pFaultCfg->Lock;
- }
- break;
- case HRTIM_FAULT_2:
- {
- HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
- HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
- HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
- HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
- HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
- }
- break;
- case HRTIM_FAULT_3:
- {
- HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
- HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
- HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
- HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
- HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
- }
- break;
- case HRTIM_FAULT_4:
- {
- HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
- HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
- HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
- HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
- HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
- }
- break;
- case HRTIM_FAULT_5:
- {
- HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
- HRTIM_fltinr2 |= pFaultCfg->Polarity;
- HRTIM_fltinr2 |= pFaultCfg->Source;
- HRTIM_fltinr2 |= pFaultCfg->Filter;
- HRTIM_fltinr2 |= pFaultCfg->Lock;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
- HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
-}
-
-/**
- * @brief Configures the fault conditioning block prescaler
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Prescaler: Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx
- * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2
- * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4
- * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8
- * @retval None
- */
-void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t Prescaler)
-{
- uint32_t HRTIM_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
-
- /* Set the external event prescaler */
- HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
- HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
- HRTIM_fltinr2 |= Prescaler;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
-}
-
-/**
- * @brief Enables or disables the HRTIMx Fault mode.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Fault: fault input to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param Enable: Fault mode controller enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULT_ENABLED: Fault mode enabled
- * @arg HRTIM_FAULT_DISABLED: Fault mode disabled
- * @retval None
- */
-void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
-{
- uint32_t HRTIM_fltinr1;
- uint32_t HRTIM_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Fault));
- assert_param(IS_HRTIM_FAULTCTL(Enable));
-
- /* Configure fault channel */
- HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
- HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
-
- switch (Fault)
- {
- case HRTIM_FAULT_1:
- {
- HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
- HRTIM_fltinr1 |= Enable;
- }
- break;
- case HRTIM_FAULT_2:
- {
- HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
- HRTIM_fltinr1 |= (Enable<< 8);
- }
- break;
- case HRTIM_FAULT_3:
- {
- HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
- HRTIM_fltinr1 |= (Enable << 16);
- }
- break;
- case HRTIM_FAULT_4:
- {
- HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
- HRTIM_fltinr1 |= (Enable << 24);
- }
- break;
- case HRTIM_FAULT_5:
- {
- HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
- HRTIM_fltinr2 |= Enable;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
- HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
-}
-
-/**
- * @brief Configures both the ADC trigger register update source and the ADC
- * trigger source.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param ADC trigger: ADC trigger to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
- * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
- * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
- * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
- * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
- * @retval None
- */
-void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t ADCTrigger,
- HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
-{
- uint32_t HRTIM_cr1;
-
- /* Check parameters */
- assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
- assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
-
- /* Set the ADC trigger update source */
- HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
-
- switch (ADCTrigger)
- {
- case HRTIM_ADCTRIGGER_1:
- {
- HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
- HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
-
- /* Set the ADC trigger 1 source */
- HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_2:
- {
- HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
- HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
-
- /* Set the ADC trigger 2 source */
- HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_3:
- {
- HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
- HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
-
- /* Set the ADC trigger 3 source */
- HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
- }
- case HRTIM_ADCTRIGGER_4:
- {
- HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
- HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
-
- /* Set the ADC trigger 4 source */
- HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
-}
-
-
-/**
- * @brief Enables or disables the HRTIMx burst mode controller.
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Enable: Burst mode controller enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
- * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
- * @retval None
- */
-void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
-{
- uint32_t HRTIM_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODECTL(Enable));
-
- /* Enable/Disable the burst mode controller */
- HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
- HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
- HRTIM_bmcr |= Enable;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
-}
-
-/**
- * @brief Triggers a software capture on the designed capture unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureUnit: Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval None
- * @note The 'software capture' bit in the capure configuration register is
- * automatically reset by hardware
- */
-void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- /* Force a software capture on concerned capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Triggers the update of the registers of one or several timers
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimersToUpdate: timers concerned with the software register update
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval None
- * @note The 'software update' bits in the HRTIMx control register 2 register are
- * automatically reset by hardware
- */
-void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
- uint32_t TimersToUpdate)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
-
- /* Force timer(s) registers update */
- HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
-
-}
-
-/**
- * @brief Triggers the reset of one or several timers
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimersToUpdate: timers concerned with the software counter reset
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
- * @retval None
- * @note The 'software reset' bits in the HRTIMx control register 2 are
- * automatically reset by hardware
- */
-void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
- uint32_t TimersToReset)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
-
- /* Force timer(s) registers update */
- HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
-
-}
-
-/**
- * @brief Forces the timer output to its active or inactive state
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param OutputLevel: indicates whether the output is forced to its active or inactive state
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state
- * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state
- * @retval None
- * @note The 'software set/reset trigger' bit in the output set/reset registers
- * is automatically reset by hardware
- */
-void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output,
- uint32_t OutputLevel)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
-
- /* Force timer output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
- }
- }
- break;
- default:
- break;
- }
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Group4 Peripheral State methods
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State methods #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns actual value of the capture register of the designated capture unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param CaptureUnit: Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval Captured value
- */
-uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- uint32_t captured_value = 0;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- /* Read captured value */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
- }
- break;
- default:
- break;
- }
-
- return captured_value;
-}
-
-/**
- * @brief Returns actual level (active or inactive) of the designated output
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output level
- * @note Returned output level is taken before the output stage (chopper,
- * polarity).
- */
-uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- default:
- break;
- }
-
- return output_level;
-}
-
-/**
- * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output state
- */
-uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- (void)(TimerIdx);
- uint32_t output_bit = 0;
- uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Set output state according to output control status and output disable status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- {
- output_bit = HRTIM_OENR_TA1OEN;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- {
- output_bit = HRTIM_OENR_TA2OEN;
- }
- break;
- case HRTIM_OUTPUT_TB1:
- {
- output_bit = HRTIM_OENR_TB1OEN;
- }
- break;
- case HRTIM_OUTPUT_TB2:
- {
- output_bit = HRTIM_OENR_TB2OEN;
- }
- break;
- case HRTIM_OUTPUT_TC1:
- {
- output_bit = HRTIM_OENR_TC1OEN;
- }
- break;
- case HRTIM_OUTPUT_TC2:
- {
- output_bit = HRTIM_OENR_TC2OEN;
- }
- break;
- case HRTIM_OUTPUT_TD1:
- {
- output_bit = HRTIM_OENR_TD1OEN;
- }
- break;
- case HRTIM_OUTPUT_TD2:
- {
- output_bit = HRTIM_OENR_TD2OEN;
- }
- break;
- case HRTIM_OUTPUT_TE1:
- {
- output_bit = HRTIM_OENR_TE1OEN;
- }
- break;
- case HRTIM_OUTPUT_TE2:
- {
- output_bit = HRTIM_OENR_TE2OEN;
- }
- break;
- default:
- break;
- }
-
- if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
- {
- /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
- output_state = HRTIM_OUTPUTSTATE_RUN;
- }
- else
- {
- if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
- {
- /* Output is disabled: output in FAULT state */
- output_state = HRTIM_OUTPUTSTATE_FAULT;
- }
- else
- {
- /* Output is disabled: output in IDLE state */
- output_state = HRTIM_OUTPUTSTATE_IDLE;
- }
- }
-
- return(output_state);
-}
-
-/**
- * @brief Returns the level (active or inactive) of the designated output
- * when the delayed protection was triggered
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param Output: Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
- * @retval Delayed protection status
- */
-uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the delayed protection status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
- {
- /* Output 1 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 1 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
- {
- /* Output 2 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 2 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- default:
- break;
- }
-
- return delayed_protection_status;
-}
-
-/**
- * @brief Returns the actual status (active or inactive) of the burst mode controller
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @retval Burst mode controller status
- */
-uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
-{
- uint32_t burst_mode_status;
-
- /* Read burst mode status */
- burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
-
- return burst_mode_status;
-}
-
-/**
- * @brief Indicates on which output the signal is currently active (when the
- * push pull mode is enabled)
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @retval Burst mode controller status
- */
-uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx)
-{
- uint32_t current_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
-
- return current_pushpull_status;
-}
-
-
-/**
- * @brief Indicates on which output the signal was applied, in push-pull mode
- balanced fault mode or delayed idle mode, when the protection was triggered
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @retval Idle Push Pull Status
- */
-uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx)
-{
- uint32_t idle_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
-
- return idle_pushpull_status;
-}
-
-/**
- * @brief Configures the master timer time base
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @retval None
- */
-void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Set the prescaler ratio */
- HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
- HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
-
- /* Set the operating mode */
- HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
- HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
- HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) time base
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @retval None
- */
-void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
-{
- /* Set the prescaler ratio */
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
-
- /* Set the operating mode */
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
- HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
-}
-
-/**
- * @brief Configures the master timer in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param pTimerInit: pointer to the timer initialization data structure
- * @retval None
- */
-void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
- HRTIM_TimerInitTypeDef * pTimerInit)
-{
- uint32_t HRTIM_mcr;
- uint32_t HRTIM_bmcr;
-
- /* Configure master timer */
- HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
- HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
-
- /* Enable/Disable the half mode */
- HRTIM_mcr &= ~(HRTIM_MCR_HALF);
- HRTIM_mcr |= pTimerInit->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
- HRTIM_mcr |= pTimerInit->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
- HRTIM_mcr |= pTimerInit->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
- HRTIM_mcr |= pTimerInit->DACSynchro;
-
- /* Enable/Disable preload mechanism for timer registers */
- HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
- HRTIM_mcr |= pTimerInit->PreloadEnable;
-
- /* Master timer registers update handling */
- HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
- HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
-
- /* Enable/Disable registers update on repetition */
- HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
- HRTIM_mcr |= pTimerInit->RepetitionUpdate;
-
- /* Set the timer burst mode */
- HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
- HRTIM_bmcr |= pTimerInit->BurstMode;
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
- HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
-
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) in waveform mode
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param pTimerInit: pointer to the timer initialization data structure
- * @retval None
- */
-void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- HRTIM_TimerInitTypeDef * pTimerInit)
-{
- uint32_t HRTIM_timcr;
- uint32_t HRTIM_bmcr;
-
- /* Configure timing unit */
- HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
- HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
-
- /* Enable/Disable the half mode */
- HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
- HRTIM_timcr |= pTimerInit->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
- HRTIM_timcr |= pTimerInit->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
- HRTIM_timcr |= pTimerInit->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
- HRTIM_timcr |= pTimerInit->DACSynchro;
-
- /* Enable/Disable preload mechanism for timer registers */
- HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
- HRTIM_timcr |= pTimerInit->PreloadEnable;
-
- /* Timing unit registers update handling */
- HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
- HRTIM_timcr |= pTimerInit->UpdateGating;
-
- /* Enable/Disable registers update on repetition */
- HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
- if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
- {
- HRTIM_timcr |= HRTIM_TIMCR_TREPU;
- }
-
- /* Set the timer burst mode */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
- HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
- HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
- HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
- HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
- HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIMx registers */
- HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
- HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
-}
-
-/**
- * @brief Configures a compare unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param CompareUnit: Compare unit identifier
- * @param pCompareCfg: pointer to the compare unit configuration data structure
- * @retval None
- */
-void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * pCompareCfg)
-{
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure the compare unit of the master timer */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
- }
- break;
- default:
- break;
- }
- }
- else
- {
- /* Configure the compare unit of the timing unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
- }
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * @brief Configures a capture unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param CaptureUnit: Capture unit identifier
- * @param pCaptureCfg: pointer to the compare unit configuration data structure
- * @retval None
- */
-void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event)
-{
- uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
- }
- break;
- default:
- break;
-
- }
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the output of a timing unit
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param Output: timing unit output identifier
- * @param pOutputCfg: pointer to the output configuration data structure
- * @retval None
- */
-void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- uint32_t HRTIM_outr;
- uint32_t shift = 0;
-
- HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
-
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Set the output set/reset crossbar */
- HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
-
- shift = 0;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Set the output set/reset crossbar */
- HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
-
- shift = 16;
- }
- break;
- default:
- break;
- }
-
- /* Clear output config */
- HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
- HRTIM_OUTR_IDLM1 |
- HRTIM_OUTR_IDLES1|
- HRTIM_OUTR_FAULT1|
- HRTIM_OUTR_CHP1 |
- HRTIM_OUTR_DIDL1) << shift);
-
- /* Set the polarity */
- HRTIM_outr |= (pOutputCfg->Polarity << shift);
-
- /* Set the IDLE mode */
- HRTIM_outr |= (pOutputCfg->IdleMode << shift);
-
- /* Set the IDLE state */
- HRTIM_outr |= (pOutputCfg->IdleState << shift);
-
- /* Set the FAULT state */
- HRTIM_outr |= (pOutputCfg->FaultState << shift);
-
- /* Set the chopper mode */
- HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
-
- /* Set the burst mode entry mode */
- HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
-
- /* Update HRTIMx register */
- HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
-}
-
-/**
- * @brief Configures an external event channel
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param Event: Event channel identifier
- * @param pEventCfg: pointer to the event channel configuration data structure
- * @retval None
- */
-static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t Event,
- HRTIM_EventCfgTypeDef *pEventCfg)
-{
- uint32_t hrtim_eecr1;
- uint32_t hrtim_eecr2;
- uint32_t hrtim_eecr3;
-
- /* Configure external event channel */
- hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
- hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
- hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
- hrtim_eecr1 |= pEventCfg->Source;
- hrtim_eecr1 |= pEventCfg->Polarity;
- hrtim_eecr1 |= pEventCfg->Sensitivity;
- /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE1FAST bit) */
- hrtim_eecr1 |= pEventCfg->FastMode;
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 6);
- hrtim_eecr1 |= (pEventCfg->Polarity << 6);
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
- /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE2FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 6);
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 12);
- hrtim_eecr1 |= (pEventCfg->Polarity << 12);
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
- /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE3FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 12);
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 18);
- hrtim_eecr1 |= (pEventCfg->Polarity << 18);
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
- /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE4FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 18);
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 24);
- hrtim_eecr1 |= (pEventCfg->Polarity << 24);
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
- /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE5FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 24);
- HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
- hrtim_eecr2 |= pEventCfg->Source;
- hrtim_eecr2 |= pEventCfg->Polarity;
- hrtim_eecr2 |= pEventCfg->Sensitivity;
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
- hrtim_eecr3 |= pEventCfg->Filter;
- /* Update the HRTIM registers */
- HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
- HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 6);
- hrtim_eecr2 |= (pEventCfg->Polarity << 6);
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
- hrtim_eecr3 |= (pEventCfg->Filter << 6);
- /* Update the HRTIM registers */
- HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
- HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 12);
- hrtim_eecr2 |= (pEventCfg->Polarity << 12);
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
- hrtim_eecr3 |= (pEventCfg->Filter << 12);
- /* Update the HRTIM registers */
- HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
- HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 18);
- hrtim_eecr2 |= (pEventCfg->Polarity << 18);
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
- hrtim_eecr3 |= (pEventCfg->Filter << 18);
- /* Update the HRTIM registers */
- HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
- HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 24);
- hrtim_eecr2 |= (pEventCfg->Polarity << 24);
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
- hrtim_eecr3 |= (pEventCfg->Filter << 24);
- /* Update the HRTIM registers */
- HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
- HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the timer counter reset
- * @param HRTIMx: pointer to HRTIMx peripheral
- * @param TimerIdx: Timer index
- * @param Event: Event channel identifier
- * @retval None
- */
-void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
- uint32_t TimerIdx,
- uint32_t Event)
-{
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
- }
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
-#pragma GCC diagnostic pop
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c
deleted file mode 100644
index e50ccf283b8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c
+++ /dev/null
@@ -1,1585 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_i2c.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Inter-Integrated circuit (I2C):
- * + Initialization and Configuration
- * + Communications handling
- * + SMBUS management
- * + I2C registers management
- * + Data transfers management
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ============================================================================
- ##### How to use this driver #####
- ============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
- function for I2C1 or I2C2.
- (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, OpenDrain and speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function.
- (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
- using the I2C_Init() function.
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
- (++) Enable the general call using the I2C_GeneralCallCmd() function.
- (++) Enable the clock stretching using I2C_StretchClockCmd() function.
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
- (++) For SMBus Mode:
- (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using I2C_DMACmd() function.
- (#) Enable the I2C using the I2C_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
- [..]
- (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
- must be enabled by setting the driving capability control bit in SYSCFG.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_i2c.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
- /* Disable I2Cx Peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /*---------------------------- I2Cx FILTERS Configuration ------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear I2Cx CR1 register */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: analog and digital filter */
- /* Set ANFOFF bit according to I2C_AnalogFilter value */
- /* Set DFN bits according to I2C_DigitalFilter value */
- tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
-
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
- /*---------------------------- I2Cx TIMING Configuration -------------------*/
- /* Configure I2Cx: Timing */
- /* Set TIMINGR bits according to I2C_Timing */
- /* Write to I2Cx TIMING */
- I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
-
- /* Enable I2Cx Peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Clear tmpreg local variable */
- tmpreg = 0;
- /* Clear OAR1 register */
- I2Cx->OAR1 = (uint32_t)tmpreg;
- /* Clear OAR2 register */
- I2Cx->OAR2 = (uint32_t)tmpreg;
- /* Configure I2Cx: Own Address1 and acknowledged address */
- /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
- /* Set OA1 bits according to I2C_OwnAddress1 value */
- tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
- (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
- /* Write to I2Cx OAR1 */
- I2Cx->OAR1 = tmpreg;
- /* Enable Own Address1 acknowledgement */
- I2Cx->OAR1 |= I2C_OAR1_OA1EN;
-
- /*---------------------------- I2Cx MODE Configuration ---------------------*/
- /* Configure I2Cx: mode */
- /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
- tmpreg = I2C_InitStruct->I2C_Mode;
- /* Write to I2Cx CR1 */
- I2Cx->CR1 |= tmpreg;
-
- /*---------------------------- I2Cx ACK Configuration ----------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear I2Cx CR2 register */
- tmpreg &= CR2_CLEAR_MASK;
- /* Configure I2Cx: acknowledgement */
- /* Set NACK bit according to I2C_Ack value */
- tmpreg |= I2C_InitStruct->I2C_Ack;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
- /*---------------- Reset I2C init structure parameters values --------------*/
- /* Initialize the I2C_Timing member */
- I2C_InitStruct->I2C_Timing = 0;
- /* Initialize the I2C_AnalogFilter member */
- I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
- /* Initialize the I2C_DigitalFilter member */
- I2C_InitStruct->I2C_DigitalFilter = 0;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
- }
-}
-
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Disable peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /* Perform a dummy read to delay the disable of peripheral for minimum
- 3 APB clock cycles to perform the software reset functionality */
- *(__IO uint32_t *)(uint32_t)I2Cx;
-
- /* Enable peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ERRI: Error interrupt mask
- * @arg I2C_IT_TCI: Transfer Complete interrupt mask
- * @arg I2C_IT_STOPI: Stop Detection interrupt mask
- * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
- * @arg I2C_IT_ADDRI: Address Match interrupt mask
- * @arg I2C_IT_RXI: RX interrupt mask
- * @arg I2C_IT_TXI: TX interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR1 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
- }
-}
-
-/**
- * @brief Enables or disables the I2C Clock stretching.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable clock stretching */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
- }
- else
- {
- /* Disable clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
-}
-
-/**
- * @brief Enables or disables I2C wakeup from stop mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable wakeup from stop mode */
- I2Cx->CR1 |= I2C_CR1_WUPEN;
- }
- else
- {
- /* Disable wakeup from stop mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C own address 2.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C own address 2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable own address 2 */
- I2Cx->OAR2 |= I2C_OAR2_OA2EN;
- }
- else
- {
- /* Disable own address 2 */
- I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
- }
-}
-
-/**
- * @brief Configures the I2C slave own address 2 and mask.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Mask: specifies own address 2 mask to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_OA2_NoMask: no mask.
- * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
- * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
- * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
- * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
- * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
- * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
- * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
- * @retval None
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_OWN_ADDRESS2(Address));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
- (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C general call mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C general call mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable general call mode */
- I2Cx->CR1 |= I2C_CR1_GCEN;
- }
- else
- {
- /* Disable general call mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C slave byte control.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C slave byte control.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable slave byte control */
- I2Cx->CR1 |= I2C_CR1_SBC;
- }
- else
- {
- /* Disable slave byte control */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
- }
-}
-
-/**
- * @brief Configures the slave address to be transmitted after start generation.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx SADD bit [9:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit addressing mode for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit addressing mode */
- I2Cx->CR2 |= I2C_CR2_ADD10;
- }
- else
- {
- /* Disable 10-bit addressing mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group2 Communications handling functions
- * @brief Communications handling functions
- *
-@verbatim
- ===============================================================================
- ##### Communications handling functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles I2C communication.
-
- [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
- mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
-
- [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
- this configuration should be done before generating start condition in master
- mode.
-
- [..] When switching from master write operation to read operation in 10Bit addressing
- mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
- Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
-
- [..] In master mode, when transferring more than 255 bytes Reload mode should be used
- to handle communication. In the first phase of transfer, Nbytes should be set to
- 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
- function should be called to handle remaining communication.
-
- [..] In master mode, when software end mode is selected when all data is transferred
- TC flag is set I2C_TransferHandling() function should be called to generate STOP
- or generate ReStart.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C automatic end mode (stop condition is
- * automatically sent when nbytes data are transferred).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C automatic end mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has effect if Reload mode is disabled.
- * @retval None
- */
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto end mode */
- I2Cx->CR2 |= I2C_CR2_AUTOEND;
- }
- else
- {
- /* Disable Auto end mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
- }
-}
-
-/**
- * @brief Enables or disables the I2C nbytes reload mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the nbytes reload mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto Reload mode */
- I2Cx->CR2 |= I2C_CR2_RELOAD;
- }
- else
- {
- /* Disable Auto Reload mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
- }
-}
-
-/**
- * @brief Configures the number of bytes to be transmitted/received.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * @retval None
- */
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx Nbytes bit [7:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
-
- /* Set I2Cx Nbytes */
- tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the type of transfer request for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Direction: specifies the transfer request direction to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_Direction_Transmitter: Master request a write transfer
- * @arg I2C_Direction_Receiver: Master request a read transfer
- * @retval None
- */
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
-{
-/* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
-
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction == I2C_Direction_Transmitter)
- {
- /* Request a write Transfer */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
- }
- else
- {
- /* Request a read Transfer */
- I2Cx->CR2 |= I2C_CR2_RD_WRN;
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR2 |= I2C_CR2_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
- }
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit header only mode with read direction.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit header only mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This mode can be used only when switching from master transmitter mode
- * to master receiver mode.
- * @retval None
- */
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit header only mode */
- I2Cx->CR2 |= I2C_CR2_HEAD10R;
- }
- else
- {
- /* Disable 10-bit header only mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
- }
-}
-
-/**
- * @brief Generates I2C communication Acknowledge.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the Acknowledge.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable ACK generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
- }
- else
- {
- /* Enable NACK generation */
- I2Cx->CR2 |= I2C_CR2_NACK;
- }
-}
-
-/**
- * @brief Returns the I2C slave matched address .
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the slave matched address .
- */
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
-}
-
-/**
- * @brief Returns the I2C slave received request.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received request.
- */
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
-{
- uint32_t tmpreg = 0;
- uint16_t direction = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
-
- /* If write transfer is requested */
- if (tmpreg == 0)
- {
- /* write transfer is requested */
- direction = I2C_Direction_Transmitter;
- }
- else
- {
- /* Read transfer is requested */
- direction = I2C_Direction_Receiver;
- }
- return direction;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param ReloadEndMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_Reload_Mode: Enable Reload mode .
- * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
- * @arg I2C_SoftEnd_Mode: Enable Software end mode.
- * @param StartStopMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_No_StartStop: Don't Generate stop and start condition.
- * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
- * @arg I2C_Generate_Start_Read: Generate Restart for read request.
- * @arg I2C_Generate_Start_Write: Generate Restart for write request.
- * @retval None
- */
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
- assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
- assert_param(IS_START_STOP_MODE(StartStopMode));
-
- /* Get the CR2 register value */
- tmpreg = I2Cx->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
- (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
-
- /* update CR2 register */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group3 SMBUS management functions
- * @brief SMBUS management functions
- *
-@verbatim
- ===============================================================================
- ##### SMBUS management functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles SMBus communication
- and timeouts detection.
-
- [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusDevice.
-
- [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusHost.
-
- [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
- function.
-
- [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
- configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
- function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
- the detection.
-
- [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
- function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
- procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
- (both SCL and SDA high) is detected also.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables I2C SMBus alert.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx SMBus alert.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable SMBus alert */
- I2Cx->CR1 |= I2C_CR1_ALERTEN;
- }
- else
- {
- /* Disable SMBus alert */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Extended clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
- * high detection).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Idle clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
- }
-}
-
-/**
- * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
- * idle SCL and SDA high when TIDLE = 1).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutA to be programmed.
- * @retval None
- */
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTA bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
-
- /* Set I2Cx TIMEOUTA */
- tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutB to be programmed.
- * @retval None
- */
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTB bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
-
- /* Set I2Cx TIMEOUTB */
- tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Enables or disables I2C PEC calculation.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC calculation */
- I2Cx->CR1 |= I2C_CR1_PECEN;
- }
- else
- {
- /* Disable PEC calculation */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C PEC transmission/reception request.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC transmission/reception request */
- I2Cx->CR1 |= I2C_CR2_PECBYTE;
- }
- else
- {
- /* Disable PEC transmission/reception request */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
- }
-}
-
-/**
- * @brief Returns the I2C PEC.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the PEC .
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group4 I2C registers management functions
- * @brief I2C registers management functions
- *
-@verbatim
- ===============================================================================
- ##### I2C registers management functions #####
- ===============================================================================
- [..] This section provides a functions that allow user the management of
- I2C registers.
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_TIMINGR: TIMING register.
- * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
- * @arg I2C_Register_ISR: ISR register.
- * @arg I2C_Register_ICR: ICR register.
- * @arg I2C_Register_PECR: PECR register.
- * @arg I2C_Register_RXDR: RXDR register.
- * @arg I2C_Register_TXDR: TXDR register.
- * @retval The value of the read register.
- */
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t)I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Data transfers management functions
- * @brief Data transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the I2C data transfers.
-
- [..] The read access of the I2C_RXDR register can be done using
- the I2C_ReceiveData() function and returns the received value.
- Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
- function and stores the written data into TXDR.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Write in the DR register the data to be sent */
- I2Cx->TXDR = (uint8_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->RXDR;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
- requests:
- (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C DMA interface.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_DMAReq_Tx: Tx DMA transfer request
- * @arg I2C_DMAReq_Rx: Rx DMA transfer request
- * @param NewState: new state of the selected I2C DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR1 |= I2C_DMAReq;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) .
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the I2C communication can be managed by 15 flags:
- (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
- (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
- (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
- (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
- (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
- (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
- (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
- (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
- [..]
- (@)Do not use the BUSY flag to handle each data transmission or reception.It is
- better to use the TXIS and RXNE flags instead.
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
- and 15 pending bits:
- [..] Interrupt Source:
- (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
- (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
- (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
- (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
- (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
- (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
- (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
-
- [..] Pending Bits:
- (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
- (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
- (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
- (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_IT_BERR: to indicate the status of Bus error flag.
- (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
- (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_TXE: Transmit data register empty
- * @arg I2C_FLAG_TXIS: Transmit interrupt status
- * @arg I2C_FLAG_RXNE: Receive data register not empty
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_TC: Transfer complete (master mode)
- * @arg I2C_FLAG_TCR: Transfer complete reload
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @arg I2C_FLAG_BUSY: Bus busy
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t tmpreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_FLAG;
-
- if(tmpreg != 0)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_FLAG;
- }
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_TXIS: Transmit interrupt status
- * @arg I2C_IT_RXNE: Receive data register not empty
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_TC: Transfer complete (master mode)
- * @arg I2C_IT_TCR: Transfer complete reload
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t tmpreg = 0;
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- /* If Error interrupt */
- if((uint32_t)(I2C_IT & ERROR_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
- }
- /* If TC interrupt */
- else if((uint32_t)(I2C_IT & TC_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
- }
- else
- {
- enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
- }
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_IT;
-
- /* Check the status of the specified I2C flag */
- if((tmpreg != RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c
deleted file mode 100644
index c82e3e8b029..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_iwdg.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- @verbatim
-
- ===============================================================================
- ##### IWDG features #####
- ===============================================================================
- [..] The IWDG can be started by either software or hardware (configurable
- through option byte).
- [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
- [..] The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
- [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
- For more information, please refer to the STM32F30x Reference manual.
-
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver allows to use IWDG peripheral with either window option enabled
- or disabled. To do so follow one of the two procedures below.
- (#) Window option is enabled:
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
-
- (#) Window option is disabled:
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) reload the IWDG counter at regular intervals during normal operation
- to prevent an MCU reset, using IWDG_ReloadCounter() function.
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_iwdg.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- * @brief Prescaler and Counter configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Prescaler and Counter configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_RELOAD;
-}
-
-
-/**
- * @brief Sets the IWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * @retval None
- */
-void IWDG_SetWindowValue(uint16_t WindowValue)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
- IWDG->WINR = WindowValue;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- * @brief IWDG activation function
- *
-@verbatim
- ===============================================================================
- ##### IWDG activation function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group3 Flag management function
- * @brief Flag management function
- *
-@verbatim
- ===============================================================================
- ##### Flag management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c
deleted file mode 100644
index b4a2978710a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_misc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- *
- @verbatim
-
- ===============================================================================
- ##### How to configure Interrupts using driver #####
- ===============================================================================
- [..] This section provide functions allowing to configure the NVIC interrupts
- (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
- (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
- function according to the following table.
- The table below gives the allowed values of the pre-emption priority
- and subpriority according to the Priority Grouping configuration
- performed by NVIC_PriorityGroupConfig function.
-
- (#) Enable and Configure the priority of the selected IRQ Channels.
- [..]
- (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
- the IRQ priority will be managed only by subpriority.
- The sub-priority is only used to sort pending exception priorities,
- and does not affect active exceptions.
- (@) Lower priority values gives higher priority.
- (@) Priority Order:
- (#@) Lowest Preemption priority.
- (#@) Lowest Subpriority.
- (#@) Lowest hardware priority (IRQn position).
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_misc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures the priority grouping: pre-emption priority and subpriority.
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
- * 4 bits for subpriority.
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
- * 3 bits for subpriority.
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
- * 2 bits for subpriority.
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
- * 1 bits for subpriority.
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
- * 0 bits for subpriority.
- * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
- * interrupt. This interrupts priority is managed only with subpriority.
- * @retval None
- */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
- tmppre = (0x4 - tmppriority);
- tmpsub = tmpsub >> tmppriority;
-
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
- tmppriority = tmppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Sets the vector table location and Offset.
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
- * This parameter can be one of the following values:
- * @arg NVIC_VectTab_RAM
- * @arg NVIC_VectTab_FLASH
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
- * @retval None
- */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
- assert_param(IS_NVIC_OFFSET(Offset));
-
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND
- * @arg NVIC_LP_SLEEPDEEP
- * @arg NVIC_LP_SLEEPONEXIT
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c
deleted file mode 100644
index aae41873b19..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_opamp.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral:
- * + OPAMP Configuration
- * + OPAMP calibration
- *
- @verbatim
-
- ==============================================================================
- ##### OPAMP Peripheral Features #####
- ==============================================================================
-
- [..]
- The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
-
- (+) The OPAMPs non inverting input can be selected among the list shown by
- table below.
-
- (+) The OPAMPs inverting input can be selected among the list shown by
- table below.
-
- (+) The OPAMPs outputs can be internally connected to the inverting input
- (follower mode)
- (+) The OPAMPs outputs can be internally connected to resistor feedback
- output (Programmable Gain Amplifier mode)
-
- (+) The OPAMPs outputs can be internally connected to ADC
-
- (+) The OPAMPs can be calibrated to compensate the offset compensation
-
- (+) Timer-controlled Mux for automatic switch of inverting and
- non-inverting input
-
- OPAMPs inverting/non-inverting inputs:
- +--------------------------------------------------------------+
- | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
- |-----------------|--------|--------|--------|--------|--------|
- | | PGA | OK | OK | OK | OK |
- | Inverting Input | Vout | OK | OK | OK | OK |
- | | IO1 | PC5 | PC5 | PB10 | PB10 |
- | | IO2 | PA3 | PA5 | PB2 | PD8 |
- |-----------------|--------|--------|--------|--------|--------|
- | | IO1 | PA7 | PD14 | PB13 | PD11 |
- | Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 |
- | Input | IO3 | PA3 | PB0 | PA1 | PA4 |
- | | IO4 | PA1 | PA7 | PB0 | PB13 |
- +--------------------------------------------------------------+
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions to configure and program the OPAMP
- of all STM32F30x devices.
-
- To use the OPAMP, perform the following steps:
-
- (#) Enable the SYSCFG APB clock to get write access to OPAMP
- register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- (#) Configure the OPAMP input in analog mode using GPIO_Init()
-
- (#) Configure the OPAMP using OPAMP_Init() function:
- (++) Select the inverting input
- (++) Select the non-inverting inverting input
-
- (#) Enable the OPAMP using OPAMP_Cmd() function
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_opamp.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup OPAMP
- * @brief OPAMP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93)
-#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF)
-#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Functions
- * @{
- */
-
-/** @defgroup OPAMP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes OPAMP peripheral registers to their default reset values.
- * @note Deinitialization can't be performed if the OPAMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param None
- * @retval None
- */
-void OPAMP_DeInit(uint32_t OPAMP_Selection)
-{
- /*!< Set OPAMP_CSR register to reset value */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
-}
-
-/**
- * @brief Initializes the OPAMP peripheral according to the specified parameters
- * in OPAMP_InitStruct
- * @note If the selected OPAMP is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
- * the configuration information for the specified OPAMP peripheral.
- * - OPAMP_InvertingInput specifies the inverting input of OPAMP
- * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
- * @retval None
- */
-void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
- assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
-
- /*!< Get the OPAMPx_CSR register value */
- tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
-
- /*!< Clear the inverting and non inverting bits selection bits */
- tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
-
- /*!< Configure OPAMP: inverting and non inverting inputs */
- tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
-
- /*!< Write to OPAMPx_CSR register */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
-}
-
-/**
- * @brief Fills each OPAMP_InitStruct member with its default value.
- * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
-{
- OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
- OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
-}
-
-/**
- * @brief Configure the feedback resistor gain.
- * @note If the selected OPAMP is locked, gain configuration can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param NewState: new state of the OPAMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
- assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
-
- /* Reset the configuration bits */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
-
- /* Set the new configuration */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
-}
-
-/**
- * @brief Configure the OPAMP's internal reference.
- * @note This feature is used when calibration enabled or OPAMP's reference
- * connected to the non inverting input.
- * @note If the selected OPAMP is locked, Vref configuration can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param OPAMP_Vref: This parameter can be:
- * OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
- * OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
- * OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
- * OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
- * @retval None
- */
-void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_VREF(OPAMP_Vref));
-
- /*!< Get the OPAMPx_CSR register value */
- tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
-
- /*!< Clear the CALSEL bits */
- tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
-
- /*!< Configure OPAMP reference */
- tmpreg |= (uint32_t)(OPAMP_Vref);
-
- /*!< Write to OPAMPx_CSR register */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
-}
-
-/**
- * @brief Connnect the internal reference to the OPAMP's non inverting input.
- * @note If the selected OPAMP is locked, Vref configuration can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param NewState: new state of the OPAMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Connnect the internal reference to the OPAMP's non inverting input */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
- }
- else
- {
- /* Disconnnect the internal reference to the OPAMP's non inverting input */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
- }
-}
-
-/**
- * @brief Enables or disables connecting the OPAMP's internal reference to ADC.
- * @note If the selected OPAMP is locked, Vref connection can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param NewState: new state of the Vrefint output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable output internal reference */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
- }
- else
- {
- /* Disable output internal reference */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
- }
-}
-
-/**
- * @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled
- * mux mode according to the specified parameters in OPAMP_InitStruct.
- * @note If the selected OPAMP is locked, timer-controlled mux configuration
- * can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
- * the configuration information for the specified OPAMP peripheral.
- * - OPAMP_InvertingInput specifies the inverting input of OPAMP
- * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
- * @note PGA and Vout can't be selected as seconadry inverting input.
- * @retval None
- */
-void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
- assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
-
- /*!< Get the OPAMPx_CSR register value */
- tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
-
- /*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
- tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
-
- /*!< Configure OPAMP: secondary inverting and non inverting inputs */
- tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
-
- /*!< Write to OPAMPx_CSR register */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
-}
-
-/**
- * @brief Enable or disable the timer-controlled mux mode.
- * @note If the selected OPAMP is locked, enable/disable can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param NewState: new state of the OPAMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the timer-controlled Mux mode */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
- }
- else
- {
- /* Disable the timer-controlled Mux mode */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
- }
-}
-
-/**
- * @brief Enable or disable the OPAMP peripheral.
- * @note If the selected OPAMP is locked, enable/disable can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param NewState: new state of the OPAMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected OPAMPx peripheral */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
- }
- else
- {
- /* Disable the selected OPAMPx peripheral */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
- }
-}
-
-/**
- * @brief Return the output level (high or low) during calibration of the selected OPAMP.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * - OPAMP output is low when the non-inverting input is at a lower
- * voltage than the inverting input
- * - OPAMP output is high when the non-inverting input is at a higher
- * voltage than the inverting input
- * @note OPAMP ouput level is provided only during calibration phase.
- * @retval Returns the selected OPAMP output level: low or high.
- *
- */
-uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
-{
- uint32_t opampout = 0x0;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
-
- /* Check if selected OPAMP output is high */
- if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
- {
- opampout = OPAMP_OutputLevel_High;
- }
- else
- {
- opampout = OPAMP_OutputLevel_Low;
- }
-
- /* Return the OPAMP output level */
- return (uint32_t)(opampout);
-}
-
-/**
- * @brief Select the trimming mode.
- * @param OffsetTrimming: the selected offset trimming mode.
- * This parameter can be one of the following values:
- * @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
- * calibration
- * @arg OPAMP_Trimming_User: user trimming values are used for offset
- * calibration
- * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
- * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
- * trimming value.
- * @retval None
- */
-void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
-{
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
-
- /* Reset USERTRIM bit */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
-
- /* Select trimming mode */
- *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
-}
-
-/**
- * @brief Configure the trimming value of the OPAMP.
- * @param OPAMP_Selection: the selected OPAMP.
- * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
- * to select the OPAMP peripheral.
- * @param OPAMP_Input: the selected OPAMP input.
- * This parameter can be one of the following values:
- * @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
- * @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
- * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
- * or equal to 0x0000001F.
- * @retval None
- */
-void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
- assert_param(IS_OPAMP_INPUT(OPAMP_Input));
- assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
-
- /*!< Get the OPAMPx_CSR register value */
- tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
-
- /*!< Clear the trimming bits */
- tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<© COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-
-/* --- CR Register ---*/
-
-/* Alias word address of HSION bit */
-#define CR_OFFSET (RCC_OFFSET + 0x00)
-#define HSION_BitNumber 0x00
-#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
-
-/* Alias word address of PLLON bit */
-#define PLLON_BitNumber 0x18
-#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
-
-/* Alias word address of CSSON bit */
-#define CSSON_BitNumber 0x13
-#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
-
-/* --- CFGR Register ---*/
-/* Alias word address of USBPRE bit */
-#define CFGR_OFFSET (RCC_OFFSET + 0x04)
-#define USBPRE_BitNumber 0x16
-#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
-/* Alias word address of I2SSRC bit */
-#define I2SSRC_BitNumber 0x17
-#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
-
-/* --- BDCR Register ---*/
-
-/* Alias word address of RTCEN bit */
-#define BDCR_OFFSET (RCC_OFFSET + 0x20)
-#define RTCEN_BitNumber 0x0F
-#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
-
-/* Alias word address of BDRST bit */
-#define BDRST_BitNumber 0x10
-#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
-
-/* --- CSR Register ---*/
-
-/* Alias word address of LSION bit */
-#define CSR_OFFSET (RCC_OFFSET + 0x24)
-#define LSION_BitNumber 0x00
-#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
-
-/* ---------------------- RCC registers bit mask ------------------------ */
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CFGR register byte 3 (Bits[31:23]) base address */
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the internal/external
- clocks, PLL, CSS and MCO.
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
- or through the PLL as System clock source.
- The HSI clock can be used also to clock the USART and I2C peripherals.
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- LSE can be used also to clock the USART peripherals.
- (#) PLL (clocked by HSI or HSE), for System clock.
- (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
- exception vector.
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
- PLL clock on PA8 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * @note HSI ON and used as system clock source
- * @note HSE and PLL OFF
- * @note AHB, APB1 and APB2 prescalers set to 1.
- * @note CSS and MCO OFF
- * @note All interrupts disabled
- * @note However, this function doesn't modify the configuration of the
- * @note Peripheral clocks
- * @note LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFC000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
- /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFC000;
-
- /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
- RCC->CFGR3 &= (uint32_t)0xF00ECCC;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function resets the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
-
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This function waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if timeout is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN3300 for more details on how to
- * calibrate the HSI.
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the PLL and/or system clock.
- * @note HSI can not be stopped if it is used directly or through the PLL
- * as system clock. In this case, you have to select another source
- * of the system clock then stop the HSI.
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to this
- * domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEON);
-
- /* Reset LSEBYP bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
-
- /* Configure LSE */
- RCC->BDCR |= RCC_LSE;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE) drive capability.
- * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
- * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
- * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
- * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
- * @retval None
- */
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
-
- /* Clear LSEDRV[1:0] bits */
- RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
-
- /* Set the LSE Drive */
- RCC->BDCR |= RCC_LSEDrive;
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PLL clock source and multiplication factor.
- * @note This function must be used only when the PLL is disabled.
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
- * PLL source).
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
- * PLL clock entry
- * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
- * This parameter can be RCC_PLLMul_x where x:[2,16]
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
- /* Clear PLL Source [16] and Multiplier [21:18] bits */
- RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
-
- /* Set the PLL Source and Multiplier */
- RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
-}
-
-/**
- * @brief Enables or disables the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the PREDIV1 division factor.
- * @note This function must be used only when the PLL is disabled.
- * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
- * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
- * @retval None
- */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
- tmpreg = RCC->CFGR2;
- /* Clear PREDIV1[3:0] bits */
- tmpreg &= ~(RCC_CFGR2_PREDIV1);
-
- /* Set the PREDIV1 division factor */
- tmpreg |= RCC_PREDIV1_Div;
-
- /* Store the new value */
- RCC->CFGR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
-}
-
-#ifdef STM32F303xC
-/**
- * @brief Selects the clock source to output on MCO pin (PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCO[3:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource */
- tmpreg |= RCC_MCOSource<<24;
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#else
-
-/**
- * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
- * prescsaler.
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
- * This parameter can be one of the following values:
- * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
- * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
- * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
- * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
- * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
- * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
- * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
- * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
- assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCOPRE[2:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource and RCC_MCOPrescaler */
- tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#endif /* STM32F303xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the System, AHB, APB1 and
- APB2 busses clocks.
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
- APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
- Depending on the maximum frequency, the FLASH wait states (WS) should be
- adapted accordingly:
- +---------------------------------+
- | Wait states | HCLK clock |
- | (Latency) | frequency (MHz) |
- |-------------- |-----------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|-----------------|
- |1WS(2CPU cycle)|24 < HCLK <=48 |
- |---------------|-----------------|
- |2WS(3CPU cycle)|48 < HCLK <= 72 |
- +---------------------------------+
-
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
- [..]
- (@) All the peripheral clocks are derived from the System clock (SYSCLK)
- except:
- (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
- (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
- (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
- (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
- (+@) The ADC clock which is derived from PLL output.
- (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
- (HSE divided by a programmable prescaler). The System clock (SYSCLK)
- frequency must be higher or equal to the RTC clock frequency.
- (+@) IWDG clock which is always the LSI clock.
- [..] It is recommended to use the following software sequences to tune the number
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).
- (+) Increasing the CPU frequency
- (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
- function
- (++) Check that Flash Prefetch buffer activation is taken into account by
- reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
- (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (+) Decreasing the CPU frequency
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (++) Program the new number of WS, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
- function
- (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
- using the FLASH_GetPrefetchBufferStatus() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following values:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @note Depending on the device voltage range, the software has to set correctly
- * these bits to ensure that the system frequency does not exceed the
- * maximum allowed frequency (for more details refer to section above
- * "CPU, AHB and APB busses clocks configuration functions").
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the Low Speed APB clock (PCLK1).
- * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB1 clock = HCLK
- * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK1Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
- /* Clear PPRE1[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE1;
-
- /* Set PPRE1[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the High Speed APB clock (PCLK2).
- * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB2 clock = HCLK
- * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
- * @retval None
- */
-void RCC_PCLK2Config(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
- /* Clear PPRE2[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE2;
- /* Set PPRE2[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK << 3;
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
- *
- * @note This function returns the frequencies of :
- * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
- * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
- *
- * @note The frequency returned by this function is not the real frequency
- * in the chip. It is calculated based on the predefined constant and
- * the source selected by RCC_SYSCLKConfig().
- *
- * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
- *
- * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
- *
- * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
- *
- * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * return wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
- uint32_t apb2presc = 0, ahbpresc = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- pllclk = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- pllclk = (HSE_VALUE / prediv1factor) * pllmull;
- }
- RCC_Clocks->SYSCLK_Frequency = pllclk;
- break;
- default: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- ahbpresc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
-
- /* Get PCLK1 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE1;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* Get PCLK2 prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE2;
- tmp = tmp >> 11;
- apb2presc = APBAHBPrescTable[tmp];
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
-
- /* Get ADC12CLK prescaler */
- tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
- tmp = tmp >> 4;
- presc = ADCPrescTable[tmp & 0x0F];
- if (((tmp & 0x10) != 0) && (presc != 0))
- {
- /* ADC12CLK clock frequency is derived from PLL clock */
- RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
- }
- else
- {
- /* ADC12CLK clock frequency is AHB clock */
- RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* Get ADC34CLK prescaler */
- tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
- tmp = tmp >> 9;
- presc = ADCPrescTable[tmp & 0x0F];
- if (((tmp & 0x10) != 0) && (presc != 0))
- {
- /* ADC34CLK clock frequency is derived from PLL clock */
- RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
- }
- else
- {
- /* ADC34CLK clock frequency is AHB clock */
- RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
- {
- /* I2C1 Clock is HSI Osc. */
- RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C1 Clock is System Clock */
- RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
- {
- /* I2C2 Clock is HSI Osc. */
- RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C2 Clock is System Clock */
- RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* I2C3CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
- {
- /* I2C3 Clock is HSI Osc. */
- RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C3 Clock is System Clock */
- RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* TIM1CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM1 Clock is 2 * pllclk */
- RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM1 Clock is APB2 clock. */
- RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM1CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* HRTIM1 Clock is 2 * pllclk */
- RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* HRTIM1 Clock is APB2 clock. */
- RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM8CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM8 Clock is 2 * pllclk */
- RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM8 Clock is APB2 clock. */
- RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM15CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM15 Clock is 2 * pllclk */
- RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM15 Clock is APB2 clock. */
- RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM16CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM16 Clock is 2 * pllclk */
- RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM16 Clock is APB2 clock. */
- RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* TIM17CLK clock frequency */
- if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
- && (apb2presc == ahbpresc))
- {
- /* TIM17 Clock is 2 * pllclk */
- RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
- }
- else
- {
- /* TIM17 Clock is APB2 clock. */
- RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
- }
-
- /* USART1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
- {
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
- /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
- STM32F302/01/34 x4/x6/x8 respective erratasheets) */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
-#else
- /* USART Clock is PCLK2 */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
-#endif
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
- }
-
- /* USART2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
- }
-
- /* USART3CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
- }
-
- /* UART4CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
- }
-
- /* UART5CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral clocks configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the Peripheral clocks.
- (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
- (HSE divided by 32).
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are
- off except internal SRAM, Flash and SWD. Before to start using
- a peripheral you have to enable its interface clock. You can do this
- using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
- and RCC_APB1PeriphClockCmd() functions.
- (#) To reset the peripherals configuration (to the default state after
- device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
- and RCC_APB1PeriphResetCmd() functions.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the ADC clock (ADCCLK).
- * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
- * the PLL Clock.
- * This parameter can be one of the following values:
- * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
- * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
- * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
- * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
- * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
- * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
- * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
- * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
- * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
- * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
- * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
- * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
- * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
- * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
- * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
- * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
- * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
- * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
- * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
- * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
- * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
- * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
- * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
- * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
- * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
- * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
- * @retval None
- */
-void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
-
- tmp = (RCC_PLLCLK >> 28);
-
- /* Clears ADCPRE34 bits */
- if (tmp != 0)
- {
- RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
- }
- /* Clears ADCPRE12 bits */
- else
- {
- RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
- }
- /* Set ADCPRE bits according to RCC_PLLCLK value */
- RCC->CFGR2 |= RCC_PLLCLK;
-}
-
-/**
- * @brief Configures the I2C clock (I2CCLK).
- * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
- * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
- * (x can be 1 or 2 or 3).
- * @retval None
- */
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
-
- tmp = (RCC_I2CCLK >> 28);
-
- /* Clear I2CSW bit */
- switch (tmp)
- {
- case 0x00:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
- break;
- case 0x01:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
- break;
- case 0x02:
- RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
- break;
- default:
- break;
- }
-
- /* Set I2CSW bits according to RCC_I2CCLK value */
- RCC->CFGR3 |= RCC_I2CCLK;
-}
-
-/**
- * @brief Configures the TIMx clock sources(TIMCLK).
- * @note The configuration of the TIMx clock source is only possible when the
- * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
- * @note If one of the previous conditions is missed, the TIM clock source
- * configuration is lost and calling again this function becomes mandatory.
- * @param RCC_TIMCLK: defines the TIMx clock source.
- * This parameter can be one of the following values:
- * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
- * when prescaled)
- * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
- * (x can be 1, 8, 15, 16, 17).
- * @retval None
- */
-void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
-
- tmp = (RCC_TIMCLK >> 28);
-
- /* Clear TIMSW bit */
-
- switch (tmp)
- {
- case 0x00:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
- break;
- case 0x01:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
- break;
- case 0x02:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
- break;
- case 0x03:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
- break;
- case 0x04:
- RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
- break;
- default:
- break;
- }
-
- /* Set I2CSW bits according to RCC_TIMCLK value */
- RCC->CFGR3 |= RCC_TIMCLK;
-}
-
-/**
- * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
- * @note The configuration of the HRTIM1 clock source is only possible when the
- * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
- * @note If one of the previous conditions is missed, the TIM clock source
- * configuration is lost and calling again this function becomes mandatory.
- * @param RCC_HRTIMCLK: defines the TIMx clock source.
- * This parameter can be one of the following values:
- * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
- * when prescaled)
- * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
- * (x can be 1 or 8).
- * @retval None
- */
-void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
-
- /* Clear HRTIMSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
-
- /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
- RCC->CFGR3 |= RCC_HRTIMCLK;
-}
-
-/**
- * @brief Configures the USART clock (USARTCLK).
- * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
- * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
- * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
- * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
- * (x can be 1, 2, 3, 4 or 5).
- * @retval None
- */
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
-
- tmp = (RCC_USARTCLK >> 28);
-
- /* Clear USARTSW[1:0] bit */
- switch (tmp)
- {
- case 0x01: /* clear USART1SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
- break;
- case 0x02: /* clear USART2SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
- break;
- case 0x03: /* clear USART3SW */
- RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
- break;
- case 0x04: /* clear UART4SW */
- RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
- break;
- case 0x05: /* clear UART5SW */
- RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
- break;
- default:
- break;
- }
-
- /* Set USARTSW bits according to RCC_USARTCLK value */
- RCC->CFGR3 |= RCC_USARTCLK;
-}
-
-/**
- * @brief Configures the USB clock (USBCLK).
- * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
- * derived from the PLL output.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
- * clock source
- * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
- * @retval None
- */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
-
- *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
-}
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the RTC
- * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
- * RTC clock source).
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
- * @brief Configures the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the SPI2 and SPI3 clocks.
- * @param RCC_I2SCLKSource: specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
- * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- * @retval None
- */
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
-
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOF
- * @arg RCC_AHBPeriph_TS
- * @arg RCC_AHBPeriph_CRC
- * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_SRAM
- * @arg RCC_AHBPeriph_DMA2
- * @arg RCC_AHBPeriph_DMA1
- * @arg RCC_AHBPeriph_ADC34
- * @arg RCC_AHBPeriph_ADC12
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @arg RCC_APB2Periph_TIM15
- * @arg RCC_APB2Periph_TIM16
- * @arg RCC_APB2Periph_TIM17
- * @arg RCC_APB2Periph_TIM1
- * @arg RCC_APB2Periph_TIM8
- * @arg RCC_APB2Periph_HRTIM1
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_SPI3
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_UART4
- * @arg RCC_APB1Periph_UART5
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_CAN1
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC1
- * @arg RCC_APB1Periph_DAC2
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB peripheral reset.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA
- * @arg RCC_AHBPeriph_GPIOB
- * @arg RCC_AHBPeriph_GPIOC
- * @arg RCC_AHBPeriph_GPIOD
- * @arg RCC_AHBPeriph_GPIOE
- * @arg RCC_AHBPeriph_GPIOF
- * @arg RCC_AHBPeriph_TS
- * @arg RCC_AHBPeriph_ADC34
- * @arg RCC_AHBPeriph_ADC12
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBRSTR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBRSTR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG
- * @arg RCC_APB2Periph_SPI1
- * @arg RCC_APB2Periph_USART1
- * @arg RCC_APB2Periph_TIM15
- * @arg RCC_APB2Periph_TIM16
- * @arg RCC_APB2Periph_TIM17
- * @arg RCC_APB2Periph_TIM1
- * @arg RCC_APB2Periph_TIM8
- * @arg RCC_APB2Periph_HRTIM1
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2
- * @arg RCC_APB1Periph_TIM3
- * @arg RCC_APB1Periph_TIM4
- * @arg RCC_APB1Periph_TIM6
- * @arg RCC_APB1Periph_TIM7
- * @arg RCC_APB1Periph_WWDG
- * @arg RCC_APB1Periph_SPI2
- * @arg RCC_APB1Periph_SPI3
- * @arg RCC_APB1Periph_USART2
- * @arg RCC_APB1Periph_USART3
- * @arg RCC_APB1Periph_UART4
- * @arg RCC_APB1Periph_UART5
- * @arg RCC_APB1Periph_I2C1
- * @arg RCC_APB1Periph_I2C2
- * @arg RCC_APB1Periph_I2C3
- * @arg RCC_APB1Periph_USB
- * @arg RCC_APB1Periph_CAN1
- * @arg RCC_APB1Periph_PWR
- * @arg RCC_APB1Periph_DAC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
- * automatically generated. The NMI will be executed indefinitely, and
- * since NMI has higher priority than any other IRQ (and main program)
- * the application will be stacked in the NMI ISR unless the CSS interrupt
- * pending bit is cleared.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
- * @arg RCC_FLAG_MCOF: MCO Flag
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 0) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 1) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else if (tmp == 4) /* The flag to check is in CFGR register */
- {
- statusreg = RCC->CFGR;
- }
- else /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
-
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c
deleted file mode 100644
index 798d7558dc4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c
+++ /dev/null
@@ -1,2598 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_rtc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Smooth digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Output Type Config configuration
- * + Shift control synchronisation
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### RTC Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
-
- ##### Backup Domain Access #####
- ===============================================================================
- [..] After reset, the backup domain (RTC registers and RTC backup data
- registers) is protected against possible unwanted write accesses.
- [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
- (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable the backup domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
- RTC hour format using the RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
- functions.
- (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function.
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
- function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals.
- To output the selected RTC signal on RTC_AF pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
- To output the RTC Clock on RTC_AF pin, use the RTC_CalibOutputCmd()
- function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF trigger and enables the RTC TimeStamp
- using the RTC_TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the
- RTC_GetTimeStamp() function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- RTC_TSOnTamperDetecCmd() function.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
- ##### RTC and low power modes #####
- ===============================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop
- and Standby lowpower modes.
- The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC
- clock source is LSE or LSI.
-
- ##### Selection of RTC_AF alternate functions #####
- ===============================================================================
- [..] The RTC_AF pin (PC13) can be used for the following purposes:
- (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- +------------------------------------------------------------------------------------------+
- | Pin |RTC ALARM |RTC CALIB |RTC TAMPER |RTC TIMESTAMP |PC13MODE| PC13VALUE |
- | configuration | OUTPUT | OUTPUT | INPUT | INPUT | bit | bit |
- | and function | ENABLED | ENABLED | ENABLED | ENABLED | | |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output OD | 1 |Don't care|Don't care | Don't care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output PP | 1 |Don't care|Don't care | Don't care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Calibration out | | | | | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TAMPER input | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP and | | | | | Don't | |
- | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |
- | floating | | | | | | |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP input | | | | | Don't | |
- | floating | 0 | 0 | 0 | 1 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Output PP | 0 | 0 | 0 | 0 | 1 | PC13 output |
- | Forced | | | | | | |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Wakeup Pin or | 0 | 0 | 0 | 0 | 0 | Don't care |
- | Standard GPIO | | | | | | |
- +------------------------------------------------------------------------------------------+
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_rtc.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
- RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
- RTC_FLAG_SHPF))
-
-#define INITMODE_TIMEOUT ((uint32_t) 0x00002000)
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
-#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)
-#define SHPF_TIMEOUT ((uint32_t) 0x00002000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to initialize and configure the RTC
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
- Write protection, enter and exit the RTC initialization mode, RTC registers
- synchronization check and reference clock detection enable.
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
- split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter initialization
- mode. In this mode, the calendar counter is stopped and its value
- can be updated. When the initialization sequence is complete, the
- calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the RTC_TR
- and RTC_DR shadow registers. The RTC_WaitForSynchro() function
- implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are deinitialized
- * - ERROR: RTC registers are not deinitialized
- */
-ErrorStatus RTC_DeInit(void)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- RTC->TR = (uint32_t)0x00000000;
- RTC->DR = (uint32_t)0x00002101;
-
- /* Reset All CR bits except CR[2:0] */
- RTC->CR &= (uint32_t)0x00000007;
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- /* Reset all RTC CR register bits */
- RTC->CR &= (uint32_t)0x00000000;
- RTC->WUTR = (uint32_t)0x0000FFFF;
- RTC->PRER = (uint32_t)0x007F00FF;
- RTC->ALRMAR = (uint32_t)0x00000000;
- RTC->ALRMBR = (uint32_t)0x00000000;
- RTC->SHIFTR = (uint32_t)0x00000000;
- RTC->CALR = (uint32_t)0x00000000;
- RTC->ALRMASSR = (uint32_t)0x00000000;
- RTC->ALRMBSSR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- RTC->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper and alternate functions configuration register */
- RTC->TAFCR = 0x00000000;
-
- /* Wait till the RTC RSF flag is set */
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Clear RTC CR FMT Bit */
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
- /* Set RTC_CR register */
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-
- /* Configure the RTC PRER */
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_InitStruct member with its default value.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
- /* Initialize the RTC_HourFormat member */
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
- /* Initialize the RTC_AsynchPrediv member */
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
- /* Initialize the RTC_SynchPrediv member */
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
-}
-
-/**
- * @brief Enables or disables the RTC registers write protection.
- * @note All the RTC registers are write protected except for RTC_ISR[13:8],
- * RTC_TAFCR and RTC_BKPxR.
- * @note Writing a wrong key reactivates the write protection.
- * @note The protection mechanism is not affected by system reset.
- * @param NewState: new state of the write protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
- }
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus RTC_EnterInitMode(void)
-{
- __IO uint32_t initcounter = 0x00;
- ErrorStatus status = ERROR;
- uint32_t initstatus = 0x00;
-
- /* Check if the Initialization mode is set */
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- RTC->ISR = (uint32_t)RTC_INIT_MASK;
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- do
- {
- initstatus = RTC->ISR & RTC_ISR_INITF;
- initcounter++;
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- return (status);
-}
-
-/**
- * @brief Exits the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval None
- */
-void RTC_ExitInitMode(void)
-{
- /* Exit Initialization mode */
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus RTC_WaitForSynchro(void)
-{
- __IO uint32_t synchrocounter = 0;
- ErrorStatus status = ERROR;
- uint32_t synchrostatus = 0x00;
-
- if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
- {
- /* Bypass shadow mode */
- status = SUCCESS;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear RSF flag */
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Wait the registers to be synchronised */
- do
- {
- synchrostatus = RTC->ISR & RTC_ISR_RSF;
- synchrocounter++;
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
-
- return (status);
-}
-
-/**
- * @brief Enables or disables the RTC reference clock detection.
- * @param NewState: new state of the RTC reference clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC reference clock detection is enabled
- * - ERROR: RTC reference clock detection is disabled
- */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the RTC reference clock detection */
- RTC->CR |= RTC_CR_REFCKON;
- }
- else
- {
- /* Disable the RTC reference clock detection */
- RTC->CR &= ~RTC_CR_REFCKON;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or Disables the Bypass Shadow feature.
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @param NewState: new state of the Bypass Shadow feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Set the BYPSHAD bit */
- RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
- }
- else
- {
- /* Reset the BYPSHAD bit */
- RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- * @brief Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Time and Date configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC Calendar
- (Time and Date).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the RTC current time.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
- }
- else
- {
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_TimeStruct member with its default value
- * (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
- RTC_TimeStruct->RTC_Hours = 0;
- RTC_TimeStruct->RTC_Minutes = 0;
- RTC_TimeStruct->RTC_Seconds = 0;
-}
-
-/**
- * @brief Get the RTC current Time.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contain the returned current time configuration.
- * @retval None
- */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
- }
-}
-
-/**
- * @brief Gets the RTC current Calendar Subseconds value.
- * @note This function freeze the Time and Date registers after reading the
- * SSR register.
- * @param None
- * @retval RTC current Calendar Subseconds value.
- */
-uint32_t RTC_GetSubSecond(void)
-{
- uint32_t tmpreg = 0;
-
- /* Get subseconds values from the correspondent registers*/
- tmpreg = (uint32_t)(RTC->SSR);
-
- /* Read DR register to unfroze calendar registers */
- (void) (RTC->DR);
-
- return (tmpreg);
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Date register is configured
- * - ERROR: RTC Date register is not configured
- */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
- {
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
- }
- if (RTC_Format == RTC_Format_BIN)
- {
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- assert_param(IS_RTC_MONTH(tmpreg));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- assert_param(IS_RTC_DATE(tmpreg));
- }
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_DateStruct->RTC_Date) | \
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_DateStruct member with its default value
- * (Monday, January 01 xx00).
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
- RTC_DateStruct->RTC_Date = 1;
- RTC_DateStruct->RTC_Month = RTC_Month_January;
- RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
- * @brief Get the RTC current date.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
- * contain the returned current date configuration.
- * @retval None
- */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- * @brief Alarms (Alarm A and Alarm B) configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Alarms (Alarm A and Alarm B) configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to program and read the RTC Alarms.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified RTC Alarm.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the RTC_AlarmCmd(DISABLE)).
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- RTC->ALRMAR = (uint32_t)tmpreg;
- }
- else
- {
- RTC->ALRMBR = (uint32_t)tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Fills each RTC_AlarmStruct member with its default value
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
- * all fields are masked).
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
- /* Alarm Date Settings : Date = 1st day of the month */
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
- * contains the output alarm configuration values.
- * @retval None
- */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)(RTC->ALRMAR);
- }
- else
- {
- tmpreg = (uint32_t)(RTC->ALRMBR);
- }
-
- /* Fill the structure with the read parameters */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
- RTC_ALRMAR_HU)) >> 16);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
- RTC_ALRMAR_MNU)) >> 8);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
- RTC_ALRMAR_SU));
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
- if (RTC_Format == RTC_Format_BIN)
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Hours);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Minutes);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Seconds);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- }
-}
-
-/**
- * @brief Enables or disables the specified RTC Alarm.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be any combination of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param NewState: new state of the specified alarm.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Alarm is enabled/disabled
- * - ERROR: RTC Alarm is not enabled/disabled
- */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
- __IO uint32_t alarmcounter = 0x00;
- uint32_t alarmstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm state */
- if (NewState != DISABLE)
- {
- RTC->CR |= (uint32_t)RTC_Alarm;
-
- status = SUCCESS;
- }
- else
- {
- /* Disable the Alarm in RTC_CR register */
- RTC->CR &= (uint32_t)~RTC_Alarm;
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- do
- {
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
- alarmcounter++;
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Configures the RTC AlarmA/B Subseconds value and mask.
- * @note This function is performed only when the Alarm is disabled.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.
- * This parameter can be a value from 0 to 0x00007FFF.
- * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.
- * This parameter can be any combination of the following values:
- * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.
- * There is no comparison on sub seconds for Alarm.
- * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
- * Only SS[0] is compared
- * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
- * Only SS[1:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
- * Only SS[2:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
- * Only SS[3:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
- * Only SS[4:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
- * Only SS[5:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
- * Only SS[6:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
- * Only SS[7:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
- * Only SS[8:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
- * Only SS[9:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
- * Only SS[10:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
- * Only SS[11:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
- * Only SS[12:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison.
- * Only SS[13:0] are compared
- * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match
- * to activate alarm
- * @retval None
- */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm A or Alarm B SubSecond registers */
- tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
-
- if (RTC_Alarm == RTC_Alarm_A)
- {
- /* Configure the AlarmA SubSecond register */
- RTC->ALRMASSR = tmpreg;
- }
- else
- {
- /* Configure the Alarm B SubSecond register */
- RTC->ALRMBSSR = tmpreg;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
-}
-
-/**
- * @brief Gets the RTC Alarm Subseconds value.
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @arg RTC_Alarm_B: to select Alarm B
- * @param None
- * @retval RTC Alarm Subseconds value.
- */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
- uint32_t tmpreg = 0;
-
- /* Get the RTC_ALRMxR register */
- if (RTC_Alarm == RTC_Alarm_A)
- {
- tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
- }
- else
- {
- tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- return (tmpreg);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions
- * @brief WakeUp Timer configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Wakeup clock source.
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpClock: Wakeup Clock source.
- * This parameter can be one of the following values:
- * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
- * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
- * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
- * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
- * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
- * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
- * @retval None
- */
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- RTC->CR |= (uint32_t)RTC_WakeUpClock;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the RTC Wakeup counter.
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.
- * This parameter can be a value from 0x0000 to 0xFFFF.
- * @retval None
- */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Wakeup Timer counter */
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC WakeUp timer counter value.
- * @param None
- * @retval The RTC WakeUp Counter value.
- */
-uint32_t RTC_GetWakeUpCounter(void)
-{
- /* Get the counter value */
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Enables or Disables the RTC WakeUp timer.
- * @param NewState: new state of the WakeUp timer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the Wakeup Timer */
- RTC->CR |= (uint32_t)RTC_CR_WUTE;
- status = SUCCESS;
- }
- else
- {
- /* Disable the Wakeup Timer */
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group5 Daylight Saving configuration functions
- * @brief Daylight Saving configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Daylight Saving configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Adds or substract one hour from the current time.
- * @param RTC_DayLightSaveOperation: the value of hour adjustment.
- * This parameter can be one of the following values:
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
- * in CR register to store the operation.
- * This parameter can be one of the following values:
- * @arg RTC_StoreOperation_Reset: BCK Bit Reset
- * @arg RTC_StoreOperation_Set: BCK Bit Set
- * @retval None
- */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
- /* Check the parameters */
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC Day Light Saving stored operation.
- * @param None
- * @retval RTC Day Light Saving stored operation.
- * - RTC_StoreOperation_Reset
- * - RTC_StoreOperation_Set
- */
-uint32_t RTC_GetStoreOperation(void)
-{
- return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group6 Output pin Configuration function
- * @brief Output pin Configuration function
- *
-@verbatim
- ===============================================================================
- ##### Output pin Configuration function #####
- ===============================================================================
- [..] This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC output source (AFO_ALARM).
- * @param RTC_Output: Specifies which signal will be routed to the RTC output.
- * This parameter can be one of the following values:
- * @arg RTC_Output_Disable: No output selected
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
- * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
- * This parameter can be one of the following:
- * @arg RTC_OutputPolarity_High: The output pin is high when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @arg RTC_OutputPolarity_Low: The output pin is low when the
- * ALRAF/ALRBF/WUTF is high (depending on OSEL)
- * @retval None
- */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT(RTC_Output));
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
- /* Configure the output selection and polarity */
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- * @brief Digital Calibration configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Digital Calibration configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RTC clock to be output through the relative
- * pin.
- * @param NewState: new state of the digital calibration Output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the RTC clock output */
- RTC->CR |= (uint32_t)RTC_CR_COE;
- }
- else
- {
- /* Disable the RTC clock output */
- RTC->CR &= (uint32_t)~RTC_CR_COE;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param RTC_CalibOutput : Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
- * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
- * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /*clear flags before config*/
- RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)RTC_CalibOutput;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Smooth Calibration Settings.
- * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values:
- * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
- * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s.
- * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
- * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
- * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Calib registers are configured
- * - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
- ErrorStatus status = ERROR;
- uint32_t recalpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* check if a calibration is pending*/
- if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
- {
- /* wait until the Calibration is completed*/
- while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
- {
- recalpfcount++;
- }
- }
-
- /* check if the calibration pending is completed or if there is no calibration operation at all*/
- if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
- {
- /* Configure the Smooth calibration settings */
- RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Group8 TimeStamp configuration functions
- * @brief TimeStamp configuration functions
- *
-@verbatim
- ===============================================================================
- ##### TimeStamp configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or Disables the RTC TimeStamp functionality with the
- * specified time stamp pin stimulating edge.
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following:
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
- * edge of the related pin.
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param NewState: new state of the TimeStamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Get the new configuration */
- if (NewState != DISABLE)
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
- }
- else
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- RTC->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Gets the RTC TimeStamp value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contains the TimeStamp time values.
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
- * contains the TimeStamp date values.
- * @retval None
- */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-
- /* Fill the Date structure fields with the read parameters */
- RTC_StampDateStruct->RTC_Year = 0;
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the Time structure parameters to Binary format */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
- /* Convert the Date structure parameters to Binary format */
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @brief Gets the RTC timestamp Subseconds value.
- * @param None
- * @retval RTC current timestamp Subseconds value.
- */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
- /* Get timestamp subseconds values from the correspondent registers */
- return (uint32_t)(RTC->TSSSR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group9 Tampers configuration functions
- * @brief Tampers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Tampers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the select Tamper pin edge.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @arg RTC_Tamper_3: Select Tamper 3.
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
- * stimulates tamper event.
- * This parameter can be one of the following values:
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
- * @retval None
- */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
-
- /* Check if the active level for Tamper is rising edge (Low level)*/
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
- }
- else
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
- }
-}
-
-/**
- * @brief Enables or Disables the Tamper detection.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @arg RTC_Tamper_3: Select Tamper 3.
- * @param NewState: new state of the tamper pin.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_Tamper;
- }
- else
- {
- /* Disable the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_Tamper;
- }
-}
-
-/**
- * @brief Configures the Tampers Filter.
- * @param RTC_TamperFilter: Specifies the tampers filter.
- * This parameter can be one of the following values:
- * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
- * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
- * samples at the active level
- * @retval None
- */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-
- /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
- * @brief Configures the Tampers Sampling Frequency.
- * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
- * This parameter can be one of the following values:
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 32768
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 16384
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 8192
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 4096
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 2048
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 1024
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 512
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 256
- * @retval None
- */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
-
- /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
- * @brief Configures the Tampers Pins input Precharge Duration.
- * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
- * Precharge Duration.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
- * @retval None
- */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-
- /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
- * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
- * @note The timestamp is valid even the TSE bit in tamper control register
- * is reset.
- * @param NewState: new state of the timestamp on tamper event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Save timestamp on tamper detection event */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
- }
- else
- {
- /* Tamper detection does not cause a timestamp to be saved */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
- }
-}
-
-/**
- * @brief Enables or Disables the Precharge of Tamper pin.
- * @param NewState: new state of tamper pull up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable precharge of the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
- }
- else
- {
- /* Disable precharge of the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions
- * @brief Backup Data Registers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Backup Data Registers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to
- * specify the register.
- * @retval None
- */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group11 Output Type Config configuration functions
- * @brief Output Type Config configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Output Type Config configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Output Pin mode.
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
- * This parameter can be one of the following values:
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
- * Open Drain mode.
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
- * Push Pull mode.
- * @retval None
- */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
- RTC->TAFCR |= (uint32_t)(RTC_OutputType);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group12 Shift control synchronisation functions
- * @brief Shift control synchronisation functions
- *
-@verbatim
- ===============================================================================
- ##### Shift control synchronisation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register
- * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
- * This parameter can be one of the following values :
- * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
- * @arg RTC_ShiftAdd1S_Reset: No effect.
- * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Shift registers are configured
- * - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
- ErrorStatus status = ERROR;
- uint32_t shpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Check if a Shift is pending*/
- if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
- {
- /* Wait until the shift is completed*/
- while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
- {
- shpfcount++;
- }
- }
-
- /* Check if the Shift pending is completed or if there is no Shift operation at all*/
- if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
- {
- /* check if the reference clock detection is disabled */
- if((RTC->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group13 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] All RTC interrupts are connected to the EXTI controller.
- (+) To enable the RTC Alarm interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 17 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
- the NVIC_Init() function.
- (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
- using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
- (+) To enable the RTC Wakeup interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 20 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using
- the NVIC_Init() function.
- (++) Configure the RTC to generate the RTC wakeup timer event using the
- RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
- functions.
- (+) To enable the RTC Tamper interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
- the NVIC_Init() function.
- (++) Configure the RTC to detect the RTC tamper event using the
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
- (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select
- the rising edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
- the NVIC_Init() function.
- (++) Configure the RTC to detect the RTC time-stamp event using the
- RTC_TimeStampCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt mask
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask
- * @arg RTC_IT_ALRB: Alarm B interrupt mask
- * @arg RTC_IT_ALRA: Alarm A interrupt mask
- * @arg RTC_IT_TAMP: Tamper event interrupt mask
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- else
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RTC_FLAG_RECALPF: RECALPF event flag
- * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_INITF: Initialization mode flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_INITS: Registers Configured flag
- * @argRTC_FLAG_SHPF : Shift operation pending flag.
- * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
- * @arg RTC_FLAG_ALRBWF: Alarm B Write flag
- * @arg RTC_FLAG_ALRAWF: Alarm A write flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- /* Get all the flags */
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-
- /* Return the status of the flag */
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's pending flags.
- * @param RTC_FLAG: specifies the RTC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag
- * @arg RTC_FLAG_ALRBF: Alarm B flag
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @retval None
- */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the Flags in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occurred or not.
- * @param RTC_IT: specifies the RTC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @arg RTC_IT_TAMP3: Tamper3 event interrupt
- * @retval The new state of RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- /* Get the TAMPER Interrupt enable bit and pending bit */
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
-
- /* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
-
- /* Get the Interrupt pending bit */
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-
- /* Get the status of the Interrupt */
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's interrupt pending bits.
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @arg RTC_IT_TAMP3: Tamper3 event interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
- /* Get the RTC_ISR Interrupt pending bits mask */
- tmpreg = (uint32_t)(RTC_IT >> 4);
-
- /* Clear the interrupt pending bits in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted.
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint8_t bcdhigh = 0;
-
- while (Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted.
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint8_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c
deleted file mode 100644
index f6a5ca5cde8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c
+++ /dev/null
@@ -1,1410 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_spi.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
-
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
- function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
- function for SPI2.
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()
- function.
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function in SPI mode. In I2S mode, program the Mode, Standard, Data Format,
- MCLK Output, Audio frequency and Polarity using I2S_Init() function.
- (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
- at which threshold the RXNE event is generated.
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_I2S_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init() function
- it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
- using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
- [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
- peripheral is able to manage sending and receiving data simultaneously
- using two data lines. Each SPI peripheral has an extended block called I2Sxext
- (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- The extension block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The extension block uses the same clock sources
- as its master.
- To configure I2S full duplex you have to:
- (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
- (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
- I2S_Init() function.
- (#) Call I2S_Cmd() for SPIx then for its extended block.
- (#) Configure interrupts or DMA requests and to get/clear flag status,
- use I2Sxext instance for the extension block.
- [..] Functions that can be called with I2Sxext instances are:
- I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(),
- SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
- SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
- [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
- [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
- I2S_StructInit(&I2SInitStruct);
- I2SInitStruct.Mode = I2S_Mode_MasterTx;
- I2S_Init(SPI3, &I2SInitStruct);
- I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
- I2S_Cmd(SPI3, ENABLE);
- I2S_Cmd(SPI3ext, ENABLE);
- ...
- while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
- {}
- SPI_I2S_SendData16(SPI3, txdata[i]);
- ...
- while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
- {}
- rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext);
- ...
- [..]
- (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
- just after calling the function SPI_Init().
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_spi.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define CR2_LDMA_MASK ((uint16_t)0x9FFF)
-
-#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI Direction,
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
- [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
- and Slave mode (details for these procedures are available in reference manual).
- [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
- use the following function to manage the NSS bit:
- void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
- [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
- is selected, use the follwoing function to enable the NSS output feature.
- void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
- [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the
- following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
- And it can be managed by software in the SPI Motorola mode using this function:
- void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
- [..] This section provides also functions to initialize the I2S Mode, Standard,
- Data Format, MCLK Output, Audio frequency and Polarity.
- [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
- and Slave mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SPIx peripheral registers to their default
- * reset values.
- * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3
- * in SPI mode.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- else
- {
- if (SPIx == SPI3)
- {
- /* Enable SPI3 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
- /* Release SPI3 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
- }
- }
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* Initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* Initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
- /* Configuring the SPI in master mode */
- if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
- {
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/slave mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
- (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
- (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
- SPI_InitStruct->SPI_FirstBit)));
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
- /*-------------------------Data Size Configuration -----------------------*/
- /* Get the SPIx CR2 value */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &= (uint16_t)~SPI_CR2_DS;
- /* Configure SPIx: Data Size */
- tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
- /* Write to SPIx CR2 */
- SPIx->CR2 = tmpreg;
- }
- /* Configuring the SPI in slave mode */
- else
- {
-/*---------------------------- Data size Configuration -----------------------*/
- /* Get the SPIx CR2 value */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &= (uint16_t)~SPI_CR2_DS;
- /* Configure SPIx: Data Size */
- tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
- /* Write to SPIx CR2 */
- SPIx->CR2 = tmpreg;
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/salve mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
- (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
- (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
- SPI_InitStruct->SPI_FirstBit)));
-
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
- }
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3
- * in I2S mode.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- * @note
- * The function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0;
- RCC_ClocksTypeDef RCC_Clocks;
- uint32_t sourceclock = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_23_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) */
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* I2S Clock source is System clock: Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = RCC_Clocks.SYSCLK_Frequency;
-
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
- (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
- I2S_InitStruct->I2S_CPOL)));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the TI Mode.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in
- * I2S mode or I2Sxext for I2S full duplex mode.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_DataSize: specifies the SPI data size.
- * For the SPIx peripheral this parameter can be one of the following values:
- * @arg SPI_DataSize_4b: Set data size to 4 bits
- * @arg SPI_DataSize_5b: Set data size to 5 bits
- * @arg SPI_DataSize_6b: Set data size to 6 bits
- * @arg SPI_DataSize_7b: Set data size to 7 bits
- * @arg SPI_DataSize_8b: Set data size to 8 bits
- * @arg SPI_DataSize_9b: Set data size to 9 bits
- * @arg SPI_DataSize_10b: Set data size to 10 bits
- * @arg SPI_DataSize_11b: Set data size to 11 bits
- * @arg SPI_DataSize_12b: Set data size to 12 bits
- * @arg SPI_DataSize_13b: Set data size to 13 bits
- * @arg SPI_DataSize_14b: Set data size to 14 bits
- * @arg SPI_DataSize_15b: Set data size to 15 bits
- * @arg SPI_DataSize_16b: Set data size to 16 bits
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
- /* Read the CR2 register */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &= (uint16_t)~SPI_CR2_DS;
- /* Set new DS[3:0] bits value */
- tmpreg |= SPI_DataSize;
- SPIx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the FIFO reception threshold for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
- * This parameter can be one of the following values:
- * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/2.
- * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4.
- * @retval None
- */
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
-
- /* Clear FRXTH bit */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
-
- /* Set new FRXTH bit value */
- SPIx->CR2 |= SPI_RxFIFOThreshold;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its
- * extension I2Sxext according to the specified parameters in the
- * I2S_InitStruct.
- * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified I2S peripheral
- * extension.
- *
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
- *
- * @note The I2S full duplex extension can be configured in slave mode only.
- *
- * @retval None
- */
-void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, tmp = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
- I2Sxext->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2Sxext->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
- {
- tmp = I2S_Mode_SlaveRx;
- }
- else
- {
- if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
- {
- tmp = I2S_Mode_SlaveTx;
- }
- }
-
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2Sxext->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called and the NSS hardware management mode is selected.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the NSS pulse management mode.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits NSSP is not taken into
- * consideration and are configured by hardware respectively to the
- * TI mode requirements.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the NSS pulse management mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the NSS pulse management mode */
- SPIx->CR2 |= SPI_CR2_NSSP;
- }
- else
- {
- /* Disable the NSS pulse management mode */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI or I2S
- data transfers.
- [..] In reception, data are received and then stored into an internal Rx buffer while
- In transmission, data are first stored into an internal Tx buffer before being
- transmitted.
- [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
- function and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_I2S_SendData() function and stores the written data into
- Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits a Data through the SPIx peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
-{
- uint32_t spixbase = 0x00;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- *(__IO uint8_t *) spixbase = Data;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- SPIx->DR = (uint16_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx peripheral.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The value of the received data.
- */
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
-{
- uint32_t spixbase = 0x00;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- return *(__IO uint8_t *) spixbase;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx peripheral.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
-
- return SPIx->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation.
- [..] SPI communication using CRC is possible through the following procedure:
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
- [..]
- (@)
- (+@) It is advised to don't read the calculate CRC values during the communication.
- (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
- (+@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
- (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
- (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
- (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multislave environment where the
- communication master addresses slaves alternately.
- (+@) Between a slave deselection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
- [..]
- (@) To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function.
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the CRC calculation length for the selected SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_CRCLength: specifies the SPI CRC calculation length.
- * This parameter can be one of the following values:
- * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
- * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
- * @retval None
- */
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
-
- /* Clear CRCL bit */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
-
- /* Set new CRCL bit value */
- SPIx->CR1 |= SPI_CRCLength;
-}
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmits the SPIx CRC value.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
-
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
- * last transfers and for the selected SPI.
- * @note This function have a meaning only if DMA mode is selected and if
- * the packing mode is used (data length <= 8 and DMA transfer size halfword)
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
- * This parameter can be one of the following values:
- * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
- * and number of data for reception Odd.
- * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd
- * and number of data for reception Odd.
- * @retval None
- */
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
-
- /* Clear LDMA_TX and LDMA_RX bits */
- SPIx->CR2 &= CR2_LDMA_MASK;
-
- /* Set new LDMA_TX and LDMA_RX bits value */
- SPIx->CR2 |= SPI_LastDMATransfer;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to configure the SPI/I2S
- Interrupts sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register.
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register.
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
- (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
- [..]
- (@) Do not use the BSY flag to handle each data transmission or reception.
- It is better to use the TXE and RXNE flags instead.
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
- and 5 pending bits:
- [..] Pending Bits:
- (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
- (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
- (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
- (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
- (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
- [..] Interrupt Source:
- (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** FIFO Status ***
- ===================
- [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
- following function:
- (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Returns the current SPIx Transmission FIFO filled level.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The Transmission FIFO filling state.
- * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
- * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Transmission FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
-}
-
-/**
- * @brief Returns the current SPIx Reception FIFO filled level.
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
- * @retval The Reception FIFO filling state.
- * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
- * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Reception FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
-}
-
-/**
- * @brief Checks whether the specified SPI flag is set or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
- * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
- * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
- * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_FRE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c
deleted file mode 100644
index 67a17f34c65..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_syscfg.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the SYSCFG peripheral:
- * + Remapping the memory mapped at 0x00000000
- * + Remapping the DMA channels
- * + Enabling I2C fast mode plus driving capability for I2C plus
- * + Remapping USB interrupt line
- * + Configuring the EXTI lines connection to the GPIO port
- * + Configuring the CLASSB requirements
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] The SYSCFG registers can be accessed only when the SYSCFG
- interface APB clock is enabled.
- [..] To enable SYSCFG APB clock use:
- RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_syscfg.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Reset value od SYSCFG_CFGR1 register */
-#define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
-
-/* ------------ SYSCFG registers bit address in the alias region -------------*/
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-
-/* --- CFGR1 Register ---*/
-/* Alias word address of USB_IT_RMP bit */
-#define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
-#define USBITRMP_BitNumber 0x05
-#define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
-
-/* --- CFGR2 Register ---*/
-/* Alias word address of BYP_ADDR_PAR bit */
-#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
-#define BYPADDRPAR_BitNumber 0x04
-#define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
- * @brief SYSCFG Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### SYSCFG Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SYSCFG registers to their default reset values.
- * @param None
- * @retval None
- * @note MEM_MODE bits are not affected by APB reset.
- * MEM_MODE bits took the value from the user option bytes.
- */
-void SYSCFG_DeInit(void)
-{
- /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
- SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
- /* Set FPU Interrupt Enable bits to default value */
- SYSCFG->CFGR1 |= 0x7C000000;
- /* Reset RAM Write protection bits to default value */
- SYSCFG->RCR = 0x00000000;
- /* Set EXTICRx registers to reset value */
- SYSCFG->EXTICR[0] = 0;
- SYSCFG->EXTICR[1] = 0;
- SYSCFG->EXTICR[2] = 0;
- SYSCFG->EXTICR[3] = 0;
- /* Set CFGR2 register to reset value */
- SYSCFG->CFGR2 = 0;
- /* Set CFGR3 register to reset value */
- SYSCFG->CFGR3 = 0;
-}
-
-/**
- * @brief Configures the memory mapping at address 0x00000000.
- * @param SYSCFG_MemoryRemap: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
-{
- uint32_t tmpcfgr1 = 0;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
-
- /* Get CFGR1 register value */
- tmpcfgr1 = SYSCFG->CFGR1;
-
- /* Clear MEM_MODE bits */
- tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
-
- /* Set the new MEM_MODE bits value */
- tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
-
- /* Set CFGR1 register with the new memory remap configuration */
- SYSCFG->CFGR1 = tmpcfgr1;
-}
-
-/**
- * @brief Configures the DMA channels remapping.
- * @param SYSCFG_DMARemap: selects the DMA channels remap.
- * This parameter can be one of the following values:
- * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
- * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
- * @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
- * @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
- * @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
- * @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
- * @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
- * @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
- * @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
- * @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
- * @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
- * @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
- * @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
- * @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
- * @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
- * @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
- * @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
- * @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
- * @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
- * @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be: Enable or Disable.
- * @note When enabled, DMA channel of the selected peripheral is remapped
- * @note When disabled, Default DMA channel is mapped to the selected peripheral
- * @note
- * By default TIM17 DMA requests is mapped to channel 1
- * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
- * to remap TIM17 DMA requests to DMA1 channel 2
- * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
- * to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
- * @retval None
- */
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
- {
- if (NewState != DISABLE)
- {
- /* Remap the DMA channel */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
- }
- else
- {
- /* use the default DMA channel mapping */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
- }
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Remap the DMA channel */
- SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
- }
- else
- {
- /* use the default DMA channel mapping */
- SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
- }
- }
-}
-
-/**
- * @brief Configures the remapping capabilities of DAC/TIM triggers.
- * @param SYSCFG_TriggerRemap: selects the trigger to be remapped.
- * This parameter can be one of the following values:
- * @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
- * @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
- * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
- * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
- * @param NewState: new state of the trigger mapping.
- * This parameter can be: ENABLE or DISABLE.
- * @note ENABLE: Enable fast mode plus driving capability for selected pin
- * @note DISABLE: Disable fast mode plus driving capability for selected pin
- * @retval None
- */
-void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
- {
- if (NewState != DISABLE)
- {
- /* Remap the trigger */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
- }
- else
- {
- /* Use the default trigger mapping */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
- }
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Remap the trigger */
- SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
- }
- else
- {
- /* Use the default trigger mapping */
- SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
- }
- }
-}
-
-/**
- * @brief Configures the remapping capabilities of encoder mode.
- * @ note This feature implement the so-called M/T method for measuring speed
- * and position using quadrature encoders.
- * @param SYSCFG_EncoderRemap: selects the remap option for encoder mode.
- * This parameter can be one of the following values:
- * @arg SYSCFG_EncoderRemap_No: No remap
- * @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
- * @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
- * @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
- * @retval None
- */
-void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
-
- /* Reset the encoder mode remapping bits */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
-
- /* Set the selected configuration */
- SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
-}
-
-/**
- * @brief Remaps the USB interrupt lines.
- * @param NewState: new state of the mapping of USB interrupt lines.
- * This parameter can be:
- * @param ENABLE: Remap the USB interrupt line as following:
- * @arg USB Device High Priority (USB_HP) interrupt mapped to line 74.
- * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75.
- * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
- * @param DISABLE: Use the default USB interrupt line:
- * @arg USB Device High Priority (USB_HP) interrupt mapped to line 19.
- * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20.
- * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
- * @retval None
- */
-void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Remap the USB interupt lines */
- *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
-}
-
-/**
- * @brief Configures the I2C fast mode plus driving capability.
- * @param SYSCFG_I2CFastModePlus: selects the pin.
- * This parameter can be one of the following values:
- * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
- * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
- * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
- * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
- * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
- * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be:
- * @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
- * @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
- * @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
- * @retval None
- */
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable fast mode plus driving capability for selected I2C pin */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
- }
- else
- {
- /* Disable fast mode plus driving capability for selected I2C pin */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
- }
-}
-
-/**
- * @brief Enables or disables the selected SYSCFG interrupts.
- * @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SYSCFG_IT_IXC: Inexact Interrupt
- * @arg SYSCFG_IT_IDC: Input denormal Interrupt
- * @arg SYSCFG_IT_OFC: Overflow Interrupt
- * @arg SYSCFG_IT_UFC: Underflow Interrupt
- * @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
- * @arg SYSCFG_IT_IOC: Invalid operation Interrupt
- * @param NewState: new state of the specified SYSCFG interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SYSCFG_IT(SYSCFG_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SYSCFG interrupts */
- SYSCFG->CFGR1 |= SYSCFG_IT;
- }
- else
- {
- /* Disable the selected SYSCFG interrupts */
- SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
- }
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
- * for EXTI lines where x can be (A, B, C, D, E or F).
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * This parameter can be EXTI_PinSourcex where x can be (0..15)
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Connects the selected parameter to the break input of TIM1.
- * @note The selected configuration is locked and can be unlocked by system reset
- * @param SYSCFG_Break: selects the configuration to be connected to break
- * input of TIM1
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
- * @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
- * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
- * @retval None
- */
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
-}
-
-/**
- * @brief Disables the parity check on RAM.
- * @note Disabling the parity check on RAM locks the configuration bit.
- * To re-enable the parity check on RAM perform a system reset.
- * @param None
- * @retval None
- */
-void SYSCFG_BypassParityCheckDisable(void)
-{
- /* Disable the adddress parity check on RAM */
- *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
-}
-
-/**
- * @brief Enables the ICODE SRAM write protection.
- * @note Enabling the ICODE SRAM write protection locks the configuration bit.
- * To disable the ICODE SRAM write protection perform a system reset.
- * @param None
- * @retval None
- */
-void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
-
- /* Enable the write-protection on the selected ICODE SRAM page */
- SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
-}
-
-/**
- * @brief Checks whether the specified SYSCFG flag is set or not.
- * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
- * This parameter can be one of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval The new state of SYSCFG_Flag (SET or RESET).
- */
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
-{
- (void)SYSCFG_Flag;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- /* Check the status of the specified SPI flag */
- if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
- {
- /* SYSCFG_Flag is set */
- bitstatus = SET;
- }
- else
- {
- /* SYSCFG_Flag is reset */
- bitstatus = RESET;
- }
- /* Return the SYSCFG_Flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the selected SYSCFG flag.
- * @param SYSCFG_Flag: selects the flag to be cleared.
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval None
- */
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c
deleted file mode 100644
index 60a52596aa2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c
+++ /dev/null
@@ -1,3995 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_tim.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Advanced-control timers (TIM1 and TIM8) specific features
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- @verbatim
-
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the TIM
- of all stm32f30x devices.
- These functions are split in 9 groups:
-
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler
- (++) Set/Get Autoreload
- (++) Counter modes configuration
- (++) Set Clock division
- (++) Select the One Pulse mode
- (++) Update Request Configuration
- (++) Update Disable Configuration
- (++) Auto-Preload Configuration
- (++) Enable/Disable the counter
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode
- (++) Select the output compare modes
- (++) Select the Polarities of each channel
- (++) Set/Get the Capture/Compare register values
- (++) Select the Output Compare Fast mode
- (++) Select the Output Compare Forced mode
- (++) Output Compare-Preload Configuration
- (++) Clear Output Compare Reference
- (++) Select the OCREF Clear signal
- (++) Enable/Disable the Capture/Compare Channels
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode
- (++) Configure Channel1/2 in PWM Input mode
- (++) Set the Input Capture Prescaler
- (++) Get the Capture/Compare values
-
- (#) Advanced-control timers (TIM1 and TIM8) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management
- (++) Enable/Disable interrupt sources
- (++) Get flags status
- (++) Clear flags/ Pending bits
- (++) Enable/Disable DMA requests
- (++) Configure DMA burst mode
- (++) Select CaptureCompare DMA request
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
-
- (#) TIM synchronization management: this group includes all needed
- functions to configure the Synchronization unit:
- (++) Select Input Trigger
- (++) Select Output Trigger
- (++) Select Master Slave Mode
- (++) ETR Configuration when used as external trigger
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration
- (++) Select Hall Sensor
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_tim.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-#define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F)
-#define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
-
- *** TIM Driver: how to use it in Timing(Time base) Mode ***
- ============================================================
- [..]
- To use the Timer in Timing(Time base) mode, the following steps are mandatory:
-
- (#) Enable TIM clock using
- RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
- the Time Base unit
- with the corresponding configuration
- (#) Enable the NVIC if you need to generate the update interrupt.
- (#) Enable the corresponding interrupt using the function
- TIM_ITConfig(TIMx, TIM_IT_Update)
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @retval None
-
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM8)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
- }
- else if (TIMx == TIM15)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
- }
- else if (TIMx == TIM16)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
- }
- else
- {
- if (TIMx == TIM17)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * that contains the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) ||
- (TIMx == TIM3)|| (TIMx == TIM4))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if((TIMx != TIM6) && (TIMx != TIM7))
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) ||
- (TIMx == TIM16) || (TIMx == TIM17))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
-
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
-
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
-
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @retval Counter Register value
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
- }
-}
-
-/**
- * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping.
- * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param NewState: new state of the UIFREMAP bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_UIFREMAP;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
-
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select
- * the TIMx peripheral.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Output Compare Mode ***
- ========================================================
- [..]
- To use the Timer in Output Compare mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode
- (++) TIM Output State: TIM_OutputState
- (++) TIM Pulse value: TIM_Pulse
- (++) TIM Output Compare Polarity : TIM_OCPolarity
-
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
- corresponding configuration
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
- (@) In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
-
- (@) If the corresponding interrupt or DMA request are needed, the user should:
- (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (#@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified parameters in
- * the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
- tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
-
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
- tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
- /* Reset the Output N State */
- tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
-
- /* Set the Output N State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
- tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
-
- /* Set the Output N State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
- tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
- tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel5 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 5: Reset the CC5E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR3 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
-
- /* Set the Output State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel6 according to the specified parameters
- * in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
-
- /* Disable the Channel 5: Reset the CC5E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR3 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
-
- /* Set the Output State */
- tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
-
- if((TIMx == TIM1) || (TIMx == TIM8))
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Output Compare IDLE State */
- tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Selects the TIM Group Channel 5 and Channel 1,
- OC1REFC is the logical AND of OC1REFC and OC5REF.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the GC5C1 Bit */
- TIMx->CCR5 |= TIM_CCR5_GC5C1;
- }
- else
- {
- /* Reset the GC5C1 Bit */
- TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
- }
-}
-
-/**
- * @brief Selects the TIM Group Channel 5 and Channel 2,
- OC2REFC is the logical AND of OC2REFC and OC5REF.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the GC5C2 Bit */
- TIMx->CCR5 |= TIM_CCR5_GC5C2;
- }
- else
- {
- /* Reset the GC5C2 Bit */
- TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
- }
-}
-
-
-/**
- * @brief Selects the TIM Group Channel 5 and Channel 3,
- OC3REFC is the logical AND of OC3REFC and OC5REF.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the GC5C3 Bit */
- TIMx->CCR5 |= TIM_CCR5_GC5C3;
- }
- else
- {
- /* Reset the GC5C3 Bit */
- TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
- }
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x00000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode. If needed, user has to enable this channel using
- * TIM_CCxCmd() and TIM_CCxNCmd() functions.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @arg TIM_OCMode_Retrigerrable_OPM1
- * @arg TIM_OCMode_Retrigerrable_OPM2
- * @arg TIM_OCMode_Combined_PWM1
- * @arg TIM_OCMode_Combined_PWM2
- * @arg TIM_OCMode_Asymmetric_PWM1
- * @arg TIM_OCMode_Asymmetric_PWM2
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare5 Register value
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param Compare5: specifies the Capture Compare5 register new value.
- * @retval None
- */
-void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Set the Capture Compare5 Register value */
- TIMx->CCR5 = Compare5;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare6 Register value
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param Compare6: specifies the Capture Compare5 register new value.
- * @retval None
- */
-void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Set the Capture Compare6 Register value */
- TIMx->CCR6 = Compare6;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
-
- /* Configure The Forced output Mode */
- tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
-
- /* Configure The Forced output Mode */
- tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 5 waveform to active or inactive level.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC5REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
- * @retval None
- */
-void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC5M Bits */
- tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
-
- /* Configure The Forced output Mode */
- tmpccmr3 |= (uint32_t)(TIM_ForcedAction);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Forces the TIMx output 6 waveform to active or inactive level.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC5REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
- * @retval None
- */
-void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC6M Bits */
- tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
-
- /* Configure The Forced output Mode */
- tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR5.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC5PE Bit */
- tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr3 |= (uint32_t)(TIM_OCPreload);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR6.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC5PE Bit */
- tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
-
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= ((uint32_t)TIM_OCFast << 8);
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= ((uint32_t)TIM_OCFast << 8);
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
-
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= ((uint32_t)TIM_OCClear << 8);
-
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
-
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= ((uint32_t)TIM_OCClear << 8);
-
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF5 signal on an external event
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC5CE Bit */
- tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr3 |= (uint32_t)(TIM_OCClear);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Clears or safeguards the OCREF6 signal on an external event
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint32_t tmpccmr3 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr3 = TIMx->CCMR3;
-
- /* Reset the OC5CE Bit */
- tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr3 |= ((uint32_t)TIM_OCClear << 8);
-
- /* Write to TIMx CCMR3 register */
- TIMx->CCMR3 = tmpccmr3;
-}
-
-/**
- * @brief Selects the OCReference Clear source.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
- * This parameter can be one of the following values:
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
- * @retval None
- */
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
-
- /* Set the TIM_OCReferenceClear source */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
- TIMx->SMCR |= TIM_OCReferenceClear;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint32_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
- tmpccer |= TIM_OCNPolarity;
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
- tmpccer |= ((uint32_t)TIM_OCPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
- tmpccer |= ((uint32_t)TIM_OCNPolarity << 4);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC3P;
- tmpccer |= ((uint32_t)TIM_OCPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
- tmpccer |= ((uint32_t)TIM_OCNPolarity << 8);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC4P;
- tmpccer |= ((uint32_t)TIM_OCPolarity << 12);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 5 polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC5 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC5P Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC5P;
- tmpccer |= ((uint32_t)TIM_OCPolarity << 16);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 6 polarity.
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- * @param TIM_OCPolarity: specifies the OC6 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint32_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
-
- /* Set or Reset the CC6P Bit */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- tmpccer |= ((uint32_t)TIM_OCPolarity << 20);
-
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @arg TIM_Channel_5: TIM Channel 5
- * @arg TIM_Channel_6: TIM Channel 6
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint32_t)(~tmp);
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint32_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Input Capture Mode ***
- =======================================================
- [..]
- To use the Timer in Input Capture mode, the following steps are mandatory:
-
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
-
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
-
- (#) Configure the Time base unit as described in the first part of this driver,
- if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF
- (++) Prescaler value = 0x0000
- (++) Counter mode = Up counting
- (++) Clock Division = TIM_CKD_DIV1
-
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel
- (++) TIM Input Capture polarity: TIM_ICPolarity
- (++) TIM Input Capture selection: TIM_ICSelection
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler
- (++) TIM Input CApture filter value: TIM_ICFilter
-
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
- corresponding configuration and to measure only frequency or duty cycle of the input signal,
- or,
- Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
- corresponding configuration and to measure the frequency and the duty cycle of the input signal
-
- (#) Enable the NVIC or the DMA to read the measured frequency.
-
- (#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
- using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
-
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified parameters
- * in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
- * the configuration information for the specified TIM peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
- * @brief Advanced-control timers (TIM1 and TIM8) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1 and TIM8) specific features #####
- ===============================================================================
-
- *** TIM Driver: how to use the Break feature ***
- ================================================
- [..]
- After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Configures the Break1 feature.
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_Break1Polarity: specifies the Break1 polarity.
- * This parameter can be one of the following values:
- * @arg TIM_Break1Polarity_Low: Break1 input is active low
- * @arg TIM_Break1Polarity_High: Break1 input is active high
- * @param TIM_Break1Filter: specifies the Break1 filter value.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
-{ /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
-
- /* Reset the BKP and BKF Bits */
- TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF);
- /* Configure the Break1 polarity and filter */
- TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16);
-}
-
-/**
- * @brief Configures the Break2 feature.
- * @param TIMx: where x can be 1 or 8 to select the TIM
- * @param TIM_Break2Polarity: specifies the Break2 polarity.
- * This parameter can be one of the following values:
- * @arg TIM_Break2Polarity_Low: Break2 input is active low
- * @arg TIM_Break2Polarity_High: Break2 input is active high
- * @param TIM_Break2Filter: specifies the Break2 filter value.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
-
- /* Reset the BKP and BKF Bits */
- TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F);
-
- /* Configure the Break1 polarity and filter */
- TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20);
-}
-
-/**
- * @brief Enables or disables the TIM Break1 input.
- * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM Break1 input.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Break1 */
- TIMx->BDTR |= TIM_BDTR_BKE;
- }
- else
- {
- /* Disable the Break1 */
- TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
- }
-}
-
-/**
- * @brief Enables or disables the TIM Break2 input.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
- * @param NewState: new state of the TIM Break2 input.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Break1 */
- TIMx->BDTR |= TIM_BDTR_BK2E;
- }
- else
- {
- /* Disable the Break1 */
- TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
- }
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
- }
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
- }
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
- * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
- * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
- * be used: TIM_IT_Update or TIM_IT_CC1
- * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
-
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
- * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
-
- if ((TIMx->SR & TIM_FLAG) != RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
- * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM1_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param TIM_InputTriggerSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
- * to select the TIM peripheral.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
-
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
- tmpsmcr |= TIM_TS_ETRF;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in synchronization Mode ***
- =========================================================
- [..] Case of two/several Timers
-
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
- [..] Case of Timers and external trigger(ETR pin)
-
- (#) Configure the External trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15
- * to select the TIM peripheral.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
-
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
- *
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST7_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode2 (TRGO2).
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
- *
- * @param TIM_TRGO2Source: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs(TRGO2)
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
- * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGO2Source;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
- * the counter and triggers an update of the registers
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
- * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
- * reinitializes the counter, generates an update
- * of the registers and starts the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
-
- /* Select the Slave Mode */
- TIMx->SMCR |= (uint32_t)TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO)
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM
- * peripheral.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
- tmpsmcr |= TIM_EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM
- * peripheral.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIM16 Remapping input Capabilities.
- * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input reampping source.
- * This parameter can be one of the following values:
- * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
- * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
- * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.
- * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock.
- * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
- * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
- * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.
- * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
- * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
- * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3.
- * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
- * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
- * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
- * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
- * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
- * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.
- * @retval : None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
- * to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0, tmpccer = 0;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
- tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
- * peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
-
- /* Select the Input and set the filter */
- tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
- tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12);
- tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
-
- /* Select the Input and set the filter */
- tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c
deleted file mode 100644
index 1b69b833ec3..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c
+++ /dev/null
@@ -1,2084 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_usart.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + STOP Mode
- * + AutoBaudRate
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + RS485 mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
- function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
- function for USART2, USART3, UART4 and UART5.
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or and SCLK).
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the SPI_Init()
- function.
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode:
- (++) Configure the DMA using DMA_Init() function.
- (++) Activate the needed channel Request using USART_DMACmd() function.
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
- [..]
- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_usart.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
-#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
-#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint32_t)0x000000FF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate.
- (++) Word Length.
- (++) Stop Bit.
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- [..]
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- [..]
- (++) Hardware flow control.
- (++) Receiver/transmitter modes.
- [..] The USART_Init() function follows the USART asynchronous configuration
- procedure(details for the procedure are available in reference manual.
- (+) For the synchronous mode in addition to the asynchronous mode parameters
- these parameters should be also configured:
- (++) USART Clock Enabled.
- (++) USART polarity.
- (++) USART phase.
- (++) USART LastBit.
- [..] These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else if (USARTx == UART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
- }
- else
- {
- if (USARTx == UART5)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t divider = 0, apbclock = 0, tmpreg = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* Disable USART */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
-
- /*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-
- /*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = tmpreg;
-
- /*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = tmpreg;
-
- /*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if (USARTx == USART1)
- {
- apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
- }
- else if (USARTx == USART2)
- {
- apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
- }
- else if (USARTx == USART3)
- {
- apbclock = RCC_ClocksStatus.USART3CLK_Frequency;
- }
- else if (USARTx == UART4)
- {
- apbclock = RCC_ClocksStatus.UART4CLK_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.UART5CLK_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* (divider * 10) computing in case Oversampling mode is 8 Samples */
- divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* (divider * 10) computing in case Oversampling mode is 16 Samples */
- divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
- }
-
- /* round the divider : if fractional part i greater than 0.5 increment divider */
- if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2)
- {
- divider++;
- }
-
- /* Implement the divider in case Oversampling mode is 8 Samples */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* get the LSB of divider and shift it to the right by 1 bit */
- tmpreg = (divider & (uint16_t)0x000F) >> 1;
-
- /* update the divider value */
- divider = (divider & (uint16_t)0xFFF0) | tmpreg;
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)divider;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Enables or disables the USART's transmitter or receiver.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_Direction: specifies the USART direction.
- * This parameter can be any combination of the following values:
- * @arg USART_Mode_Tx: USART Transmitter
- * @arg USART_Mode_Rx: USART Receiver
- * @param NewState: new state of the USART transfer direction.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MODE(USART_DirectionMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART's transfer interface by setting the TE and/or RE bits
- in the USART CR1 register */
- USARTx->CR1 |= USART_DirectionMode;
- }
- else
- {
- /* Disable the USART's transfer interface by clearing the TE and/or RE bits
- in the USART CR3 register */
- USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
- }
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called before calling USART_Init()
- * function in order to have correct baudrate Divider value.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBIT bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBIT bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @brief Enables or disables the USART's most significant bit first
- * transmitted/received following the start bit.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART most significant bit first
- * transmitted/received following the start bit.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the most significant bit first transmitted/received following the
- start bit by setting the MSBFIRST bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_MSBFIRST;
- }
- else
- {
- /* Disable the most significant bit first transmitted/received following the
- start bit by clearing the MSBFIRST bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
- }
-}
-
-/**
- * @brief Enables or disables the binary data inversion.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new defined levels for the USART data.
- * This parameter can be: ENABLE or DISABLE.
- * @arg ENABLE: Logical data from the data register are send/received in negative
- * logic. (1=L, 0=H). The parity bit is also inverted.
- * @arg DISABLE: Logical data from the data register are send/received in positive
- * logic. (1=H, 0=L)
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the binary data inversion feature by setting the DATAINV bit in
- the CR2 register */
- USARTx->CR2 |= USART_CR2_DATAINV;
- }
- else
- {
- /* Disable the binary data inversion feature by clearing the DATAINV bit in
- the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
- }
-}
-
-/**
- * @brief Enables or disables the Pin(s) active level inversion.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_InvPin: specifies the USART pin(s) to invert.
- * This parameter can be any combination of the following values:
- * @arg USART_InvPin_Tx: USART Tx pin active level inversion.
- * @arg USART_InvPin_Rx: USART Rx pin active level inversion.
- * @param NewState: new active level status for the USART pin(s).
- * This parameter can be: ENABLE or DISABLE.
- * - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
- * - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the active level inversion for selected pins by setting the TXINV
- and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 |= USART_InvPin;
- }
- else
- {
- /* Disable the active level inversion for selected requests by clearing the
- TXINV and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 &= (uint32_t)~USART_InvPin;
- }
-}
-
-/**
- * @brief Enables or disables the swap Tx/Rx pins.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USARTx TX/RX pins pinout.
- * This parameter can be: ENABLE or DISABLE.
- * @arg ENABLE: The TX and RX pins functions are swapped.
- * @arg DISABLE: TX/RX pins are used as defined in standard pinout
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_SWAP;
- }
- else
- {
- /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
- }
-}
-
-/**
- * @brief Enables or disables the receiver Time Out feature.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USARTx receiver Time Out.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the receiver time out feature by setting the RTOEN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_RTOEN;
- }
- else
- {
- /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
- }
-}
-
-/**
- * @brief Sets the receiver Time Out value.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value.
- * @retval None
- */
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
-
- /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
- /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR |= USART_ReceiverTimeOut;
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group2 STOP Mode functions
- * @brief STOP Mode functions
- *
-@verbatim
- ===============================================================================
- ##### STOP Mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- WakeUp from STOP mode.
-
- [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
- or LSI.
-
- [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
- function.
-
- [..] After configuring the source of WakeUp and before entering in Stop Mode
- USART_STOPModeCmd() function should be called to allow USART WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART peripheral in STOP Mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USARTx peripheral state in stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note
- * This function has to be called when USART clock is set to HSI or LSE.
- * @retval None
- */
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
- register */
- USARTx->CR1 |= USART_CR1_UESM;
- }
- else
- {
- /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
- register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method form stop mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_WakeUp: specifies the selected USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
- * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
- * @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
- USARTx->CR3 |= USART_WakeUpSource;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group3 AutoBaudRate functions
- * @brief AutoBaudRate functions
- *
-@verbatim
- ===============================================================================
- ##### AutoBaudRate functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the AutoBaudRate detections.
-
- [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
- The character patterns used to calculate baudrate must be chosen by calling
- USART_AutoBaudRateConfig() function. These function take as parameter :
- (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
- (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern.
-
- [..] At any later time, another request for AutoBaudRate detection can be performed
- using USART_RequestCmd() function.
-
- [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
- that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
- indicate that this procedure is completed without success. USART_GetFlagStatus ()
- function should be used to monitor the status of these flags.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Auto Baud Rate.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USARTx auto baud rate.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto baud rate feature by setting the ABREN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_ABREN;
- }
- else
- {
- /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
- }
-}
-
-/**
- * @brief Selects the USART auto baud rate method.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method.
- * This parameter can be one of the following values:
- * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
- * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
- * @arg USART_AutoBaudRate_0x7FFrame: 0x7F frame.
- * @arg USART_AutoBaudRate_0x55Frame: 0x55 frame.
- * @note
- * This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
- USARTx->CR2 |= USART_AutoBaudRate;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group4 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the USART data transfers.
- [..] During an USART reception, data shifts in least significant bit first
- through the RX pin. When a transmission is taking place, a write instruction to
- the USART_TDR register stores the data in the shift register.
- [..] The read access of the USART_RDR register can be done using
- the USART_ReceiveData() function and returns the RDR value.
- Whereas a write access to the USART_TDR can be done using USART_SendData()
- function and stores the written data into TDR.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->TDR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..] For instance one of the USARTs can be the master, its TX output is
- connected to the RX input of the other USART. The others are slaves,
- their respective TX outputs are logically ANDed together and connected
- to the RX input of the master. USART multiprocessor communication is
- possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up methode (USART_WakeUp_IdleLine or
- USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
- for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
- function.
- [..] The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
-}
-
-/**
- * @brief Enables or disables the USART's mute mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the MME bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_MME;
- }
- else
- {
- /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method from mute mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Configure the the USART Address detection length.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_AddressLength: specifies the USART address length detection.
- * This parameter can be one of the following values:
- * @arg USART_AddressLength_4b: 4-bit address length detection
- * @arg USART_AddressLength_7b: 7-bit address length detection
- * @retval None
- */
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
- USARTx->CR2 |= USART_AddressLength;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group6 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- LIN Mode communication.
- [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
- with the LIN standard.
- [..] Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break
- detection capability : 13-bit break generation and 10/11 bit break
- detection.
- [..] USART LIN Master transmitter communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..] USART LIN Master receiver communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the break detection length
- using the USART_LINBreakDetectLengthConfig() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register.
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..] The USART can be configured to follow a single-wire half-duplex protocol
- where the TX and RX lines are internally connected.
- [..] USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) The RX pin is no longer used.
- (@) In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group8 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..] The Smartcard interface is designed to support asynchronous protocol
- Smartcards as defined in the ISO 7816-3 standard. The USART can provide
- a clock to the smartcard through the SCLK output. In smartcard mode,
- SCLK is not associated to the communication but is simply derived from
- the internal peripheral input clock through a 5-bit prescaler.
- [..] Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
- function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
- function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled.
- (++) USART CPOL Low.
- (++) USART CPHA on first edge.
- (++) USART Last Bit Clock Enabled.
- (#) Program the Smartcard interface using the USART_Init() function as
- following:
- (++) Word Length = 9 Bits.
- (++) 1.5 Stop Bit.
- (++) Even parity.
- (++) BaudRate = 12096 baud.
- (++) Hardware flow control disabled (RTS and CTS signals).
- (++) Tx and Rx enabled
- (#) Optionally you can enable the parity error interrupt using
- the USART_ITConfig() function.
- (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- Please refer to the ISO 7816-3 specification for more details.
- [..]
- (@) It is also possible to choose 0.5 stop bit for receiving but it is
- recommended to use 1.5 stop bits for both transmitting and receiving
- to avoid switching between the two configurations.
- (@) In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @brief Sets the Smart Card number of retries in transmit and receive.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param USART_AutoCount: specifies the Smart Card auto retry count.
- * @retval None
- */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
- assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
- /* Clear the USART auto retry count */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
- /* Set the USART auto retry count*/
- USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
-}
-
-/**
- * @brief Sets the Smart Card Block length.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3.
- * @param USART_BlockLength: specifies the Smart Card block length.
- * @retval None
- */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_123_PERIPH(USARTx));
-
- /* Clear the Smart card block length */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
- /* Set the Smart Card block length */
- USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
- any data on the IrDA receive line will be ignored by the IrDA decoder
- and if the Receiver is busy, data on the TX from the USART to IrDA will
- not be encoded by IrDA. While receiving data, transmission should be
- avoided as the data to be transmitted could be corrupted.
- [..] IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal
- mode using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) A pulse of width less than two and greater than one PSC period(s) may or
- may not be rejected.
- (@) The receiver set up time should be managed by software. The IrDA physical
- layer specification specifies a minimum of 10 ms delay between
- transmission and reception (IrDA is a half duplex protocol).
- (@) In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup USART_Group10 RS485 mode function
- * @brief RS485 mode function
- *
-@verbatim
- ===============================================================================
- ##### RS485 mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- RS485 flow control.
- [..] RS485 flow control (Driver enable feature) handling is possible through
- the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Enable the Driver Enable using the USART_DECmd() function.
- (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
- function.
- (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime()
- function and deassertion time using the USART_SetDEDeassertionTime()
- function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) The assertion and dessertion times are expressed in sample time units (1/8 or
- 1/16 bit time, depending on the oversampling rate).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DE functionality.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param NewState: new state of the driver enable mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the DE functionality by setting the DEM bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_DEM;
- }
- else
- {
- /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
- }
-}
-
-/**
- * @brief Configures the USART's DE polarity
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_DEPolarity: specifies the DE polarity.
- * This parameter can be one of the following values:
- * @arg USART_DEPolarity_Low
- * @arg USART_DEPolarity_High
- * @retval None
- */
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
- USARTx->CR3 |= USART_DEPolarity;
-}
-
-/**
- * @brief Sets the specified RS485 DE assertion time
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_AssertionTime: specifies the time between the activation of the DE
- * signal and the beginning of the start bit
- * @retval None
- */
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime));
-
- /* Clear the DE assertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
- /* Set the new value for the DE assertion time */
- USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
-}
-
-/**
- * @brief Sets the specified RS485 DE deassertion time
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_DeassertionTime: specifies the time between the middle of the last
- * stop bit in a transmitted message and the de-activation of the DE signal
- * @retval None
- */
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime));
-
- /* Clear the DE deassertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
- /* Set the new value for the DE deassertion time */
- USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group11 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
- requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
- FunctionalState NewState).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_1234_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint32_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Enables or disables the USART's DMA interface when reception error occurs.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4.
- * @param USART_DMAOnError: specifies the DMA status in case of reception error.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA
- * reception error is asserted.
- * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA
- * reception error is asserted.
- * @retval None
- */
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
-{
- /* Check the parameters */
- assert_param(IS_USART_1234_PERIPH(USARTx));
- assert_param(IS_USART_DMAONERROR(USART_DMAOnError));
-
- /* Clear the DMA Reception error detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
- /* Set the new value for the DMA Reception error detection bit */
- USARTx->CR3 |= USART_DMAOnError;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group12 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to configure the
- USART Interrupts sources, Requests and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to
- manage the communication: Polling mode, Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI communication can be managed by these flags:
- (#) USART_FLAG_REACK: to indicate the status of the Receive Enable
- acknowledge flag
- (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable
- acknowledge flag.
- (#) USART_FLAG_WUF: to indicate the status of the Wake up flag.
- (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
- (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
- (#) USART_FLAG_CMF: to indicate the status of the Character match flag.
- (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
- (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
- (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
- (#) USART_FLAG_EOBF: to indicate the status of the End of block flag.
- (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.
- (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input
- bit status.
- (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
- (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
- (#) USART_FLAG_TC: to indicate the status of the transmit operation.
- (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
- (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
- (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
- (#) USART_FLAG_NE: to indicate if a noise error occur.
- (#) USART_FLAG_FE: to indicate if a frame error occur.
- (#) USART_FLAG_PE: to indicate if a parity error occur.
- (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
- sources and 10 pending bits:
- (+) Pending Bits:
- (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
- (##) USART_IT_CM: to indicate the status of Character match interrupt.
- (##) USART_IT_EOB: to indicate the status of End of block interrupt.
- (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
- (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
- (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
- (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
- (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
- (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
- (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
- (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
- (##) USART_IT_PE: to indicate the status of Parity Error interrupt.
-
- (+) Interrupt Source:
- (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
- (##) USART_IT_CM: specifies the interrupt source for Character match
- interrupt.
- (##) USART_IT_EOB: specifies the interrupt source for End of block
- interrupt.
- (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
- interrupt.
- (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
- (##) USART_IT_LBD: specifies the interrupt source for LIN Break
- detection interrupt.
- (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data
- Register empty interrupt.
- (##) USART_IT_TC: specifies the interrupt source for Transmission
- complete interrupt.
- (##) USART_IT_RXNE: specifies the interrupt source for Receive Data
- register not empty interrupt.
- (##) USART_IT_IDLE: specifies the interrupt source for Idle line
- detection interrupt.
- (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
- (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
- (Frame error, noise error, overrun error)
- -@@- Some parameters are coded in order to use them as interrupt
- source or as pending bits.
- [..] In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0, itpos = 0, itmask = 0;
- uint32_t usartxbase = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x04;
- }
- else if (usartreg == 0x03) /* The IT is in CR3 register */
- {
- usartxbase += 0x08;
- }
- else /* The IT is in CR1 register */
- {
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables the specified USART's Request.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_Request: specifies the USART request.
- * This parameter can be any combination of the following values:
- * @arg USART_Request_TXFRQ: Transmit data flush ReQuest
- * @arg USART_Request_RXFRQ: Receive data flush ReQuest
- * @arg USART_Request_MMRQ: Mute Mode ReQuest
- * @arg USART_Request_SBKRQ: Send Break ReQuest
- * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
- * @param NewState: new state of the DMA interface when reception error occurs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_REQUEST(USART_Request));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
- register.*/
- USARTx->RQR |= USART_Request;
- }
- else
- {
- /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
- register.*/
- USARTx->RQR &= (uint32_t)~USART_Request;
- }
-}
-
-/**
- * @brief Enables or disables the USART's Overrun detection.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.
- * This parameter can be any combination of the following values:
- * @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error
- * is asserted.
- * @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error
- * is asserted.
- * @retval None
- */
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
-
- /* Clear the OVR detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
- /* Set the new value for the OVR detection bit */
- USARTx->CR3 |= USART_OVRDetection;
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive Enable acknowledge flag.
- * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.
- * @arg USART_FLAG_WUF: Wake up flag.
- * @arg USART_FLAG_RWU: Receive Wake up flag.
- * @arg USART_FLAG_SBK: Send Break flag.
- * @arg USART_FLAG_CMF: Character match flag.
- * @arg USART_FLAG_BUSY: Busy flag.
- * @arg USART_FLAG_ABRF: Auto baud rate flag.
- * @arg USART_FLAG_ABRE: Auto baud rate error flag.
- * @arg USART_FLAG_EOBF: End of block flag.
- * @arg USART_FLAG_RTOF: Receive time out flag.
- * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TXE: Transmit data register empty flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- * @arg USART_FLAG_IDLE: Idle Line detection flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Error flag.
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_WUF: Wake up flag.
- * @arg USART_FLAG_CMF: Character match flag.
- * @arg USART_FLAG_EOBF: End of block flag.
- * @arg USART_FLAG_RTOF: Receive time out flag.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_IDLE: IDLE line detected flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Errorflag.
- *
- * @note
- * - RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * - TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation
- * to USART_TDR register (USART_SendData()).
- * - TXE flag is cleared by a write to the USART_TDR register
- * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * - SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- USARTx->ICR = USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0, usartreg = 0;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x10;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->ISR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: Select the USART peripheral. This parameter can be one of the
- * following values: USART1 or USART2 or USART3 or UART4 or UART5.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_IDLE: IDLE line detected interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @note
- * - RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * - TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by a write
- * operation to USART_TDR register (USART_SendData()).
- * - TXE pending bit is cleared by a write to the USART_TDR register
- * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- bitpos = USART_IT >> 0x10;
- itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
- USARTx->ICR = (uint32_t)itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c b/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c
deleted file mode 100644
index 13e23e7c7f6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_wwdg.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 04-April-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ==============================================================================
- ##### WWDG features #####
- ==============================================================================
-
- [..] Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- [..] An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- [..] Once enabled the WWDG cannot be disabled except by a system reset.
-
- [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- [..] The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- [..] WWDG counter clock = PCLK1 / Prescaler.
- [..] WWDG timeout = (WWDG counter clock) * (counter value).
-
- [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
- function.
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x_wwdg.h"
-#include "stm32f30x_rcc.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------------------- WWDG registers bit mask ---------------------------- */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- * @brief Prescaler, Refresh window and Counter configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Prescaler, Refresh window and Counter configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_MASK;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- WWDG->CFR |= WWDG_CFR_EWI;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset).
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_MASK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- * @brief WWDG activation functions
- *
-@verbatim
- ==============================================================================
- ##### WWDG activation function #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent generating
- * an immediate reset).
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Interrupts and flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((WWDG->SR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index 06ff562c49b..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3173 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @brief This file contains aliases definition for the STM32Cube HAL constants
- * macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-/**
- * @}
- */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
- /**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
- /**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32_assert_template.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32_assert_template.h
deleted file mode 100644
index d71e0c30bf3..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32_assert_template.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_assert.h
- * @author MCD Application Team
- * @brief STM32 assert template file.
- * This file should be copied to the application folder and renamed
- * to stm32_assert.h.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(char* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h
deleted file mode 100644
index 98a534ee7d6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h
+++ /dev/null
@@ -1,916 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_H
-#define __STM32F3xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_conf.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL
- * @{
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup HAL_Private_Macros
- * @{
- */
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
- * @brief SYSCFG registers bit address in the alias region
- * @{
- */
-/* ------------ SYSCFG registers bit address in the alias region -------------*/
-#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
-/* --- CFGR2 Register ---*/
-/* Alias word address of BYP_ADDR_PAR bit */
-#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
-#define BYPADDRPAR_BitNumber 0x04U
-#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
-/**
- * @}
- */
-
-#if defined(SYSCFG_CFGR1_DMA_RMP)
-/** @defgroup HAL_DMA_Remapping HAL DMA Remapping
- * Elements values convention: 0xXXYYYYYY
- * - YYYYYY : Position in the register
- * - XX : Register index
- * - 00: CFGR1 register in SYSCFG
- * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
- * @{
- */
-#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
-#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
- 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
-#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
- 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
-#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
-#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
-#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
- 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
-#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
- 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
-#if defined(SYSCFG_CFGR3_DMA_RMP)
-#if !defined(HAL_REMAP_CFGR3_MASK)
-#define HAL_REMAP_CFGR3_MASK (0x01000000U)
-#endif
-
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 4 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 4 */
-#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
- x0: No remap (ADC2 on DMA2)
- 10: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
- 11: Map on DMA1 channel 4 */
-#endif /* SYSCFG_CFGR3_DMA_RMP */
-
-#if defined(SYSCFG_CFGR3_DMA_RMP)
-#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
- (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
- (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
- (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
- (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
- (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
- (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
- (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
- (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
- (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
- (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
- (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
- (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
- (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
- (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
- (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
- (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
- (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
- (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
- (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
- (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
-#else
-#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
- (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
- (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
- (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
- (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
- (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
- (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
-#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR1_DMA_RMP */
-
-/** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
- * Elements values convention: 0xXXYYYYYY
- * - YYYYYY : Position in the register
- * - XX : Register index
- * - 00: CFGR1 register in SYSCFG
- * - 01: CFGR3 register in SYSCFG
- * @{
- */
-#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
- 0: No remap (DAC trigger is TIM8_TRGO)
- 1: Remap (DAC trigger is TIM3_TRGO) */
-#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
- 0: No remap
- 1: Remap (TIM1_TRG3 = TIM17_OC) */
-#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
-#if !defined(HAL_REMAP_CFGR3_MASK)
-#define HAL_REMAP_CFGR3_MASK (0x01000000U)
-#endif
-#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
- 0: Remap (DAC trigger is TIM15_TRGO)
- 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
-#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
- 0: No remap
- 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
-#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
- (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
- (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
- (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
-#else
-#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
- (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
-#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
-/**
- * @}
- */
-
-#if defined (STM32F302xE)
-/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
- * @{
- */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
- 0: No remap (TIM1_CC3)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
- 0: No remap (TIM2_CC2)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
- 0: No remap (TIM4_CC4)
- 1: Remap (TIM20_CC1) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
- 0: No remap (TIM6_TRGO)
- 1: Remap (TIM20_CC2) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
- 0: No remap (TIM3_CC4)
- 1: Remap (TIM20_CC3) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
- 0: No remap (TIM2_CC1)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
- 0: No remap (EXTI line 15)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
- 0: No remap (TIM3_CC1)
- 1: Remap (TIM20_CC4) */
-
-#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
-/**
- * @}
- */
-#endif /* STM32F302xE */
-
-#if defined (STM32F303xE) || defined (STM32F398xx)
-/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
- * @{
- */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
- 0: No remap (TIM1_CC3)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
- 0: No remap (TIM2_CC2)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
- 0: No remap (TIM4_CC4)
- 1: Remap (TIM20_CC1) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
- 0: No remap (TIM6_TRGO)
- 1: Remap (TIM20_CC2) */
-#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
- 0: No remap (TIM3_CC4)
- 1: Remap (TIM20_CC3) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
- 0: No remap (TIM2_CC1)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
- 0: No remap (EXTI line 15)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
- 0: No remap (TIM3_CC1)
- 1: Remap (TIM20_CC4) */
-#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
- 0: No remap (EXTI line 2)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
- 0: No remap (TIM4_CC1)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
- 0: No remap (TIM2_CC1)
- 1: Remap (TIM20_CC1) */
-#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
- 0: No remap (TIM4_CC3)
- 1: Remap (TIM20_TRGO) */
-#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
- 0: No remap (TIM1_CC3)
- 1: Remap (TIM20_TRGO2) */
-#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
- 0: No remap (TIM7_TRGO)
- 1: Remap (TIM20_CC2) */
-
-#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
-/**
- * @}
- */
-#endif /* STM32F303xE || STM32F398xx */
-
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
- * @{
- */
-
-/** @brief Fast-mode Plus driving capability on a specific GPIO
- */
-#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
-#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
-#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
-#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
-#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
-#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
-/**
- * @}
- */
-
-#if defined(SYSCFG_RCR_PAGE0)
-/* CCM-SRAM defined */
-/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
- * @{
- */
-#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
-#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
-#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
-#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
-#if defined(SYSCFG_RCR_PAGE4)
-/* More than 4KB CCM-SRAM defined */
-#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
-#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
-#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
-#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
-#endif /* SYSCFG_RCR_PAGE4 */
-#if defined(SYSCFG_RCR_PAGE8)
-#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
-#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
-#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
-#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
-#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
-#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
-#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
-#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
-#endif /* SYSCFG_RCR_PAGE8 */
-
-#if defined(SYSCFG_RCR_PAGE8)
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
-#elif defined(SYSCFG_RCR_PAGE4)
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
-#else
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
-#endif /* SYSCFG_RCR_PAGE8 */
-/**
- * @}
- */
-#endif /* SYSCFG_RCR_PAGE0 */
-
-/** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
- * @{
- */
-#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
-#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
-#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
-#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
-#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
-#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
-
-#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
- (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
- (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
- (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
- (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
- (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
- * @{
- */
-
-/** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
- * @{
- */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
-#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
-#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
-
-#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
-
-#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
-
-#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
-
-#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
-#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
-#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
-#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
-/**
- * @}
- */
-
-/** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
- * @{
- */
-#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
-#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
-#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
-#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
-#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
-
-#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
-#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
-#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
-#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
-/**
- * @}
- */
-
-/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
- * @{
- */
-#if defined(SYSCFG_CFGR1_MEM_MODE)
-/** @brief Main Flash memory mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
-#endif /* SYSCFG_CFGR1_MEM_MODE */
-
-#if defined(SYSCFG_CFGR1_MEM_MODE_0)
-/** @brief System Flash memory mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
- SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
- }while(0U)
-#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
-
-#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
-/** @brief Embedded SRAM mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
- SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
- }while(0U)
-#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
-
-#if defined(SYSCFG_CFGR1_MEM_MODE_2)
-#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
- SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
- }while(0U)
-#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
-/**
- * @}
- */
-
-/** @defgroup Encoder_Mode Encoder Mode
- * @{
- */
-#if defined(SYSCFG_CFGR1_ENCODER_MODE)
-/** @brief No Encoder mode
- */
-#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
-#endif /* SYSCFG_CFGR1_ENCODER_MODE */
-
-#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
-/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- */
-#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
- SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
- }while(0U)
-#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
-
-#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
-/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
- */
-#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
- SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
- }while(0U)
-#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
-
-#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
-/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
- */
-#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
- SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
- }while(0U)
-#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
-/**
- * @}
- */
-
-/** @defgroup DMA_Remap_Enable DMA Remap Enable
- * @{
- */
-#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
-/** @brief DMA remapping enable/disable macros
- * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
- */
-#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
- (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
- (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
- (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
- }while(0U)
-#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
- (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
- (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
- (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
- }while(0U)
-#elif defined(SYSCFG_CFGR1_DMA_RMP)
-/** @brief DMA remapping enable/disable macros
- * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
- */
-#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
- SYSCFG->CFGR1 |= (__DMA_REMAP__); \
- }while(0U)
-#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
- SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
- }while(0U)
-#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
-/**
- * @}
- */
-
-/** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
- * @{
- */
-/** @brief Fast-mode Plus driving capability enable/disable macros
- * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
- * That you can find above these macros.
- */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
- SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0U)
-
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
- CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0U)
-/**
- * @}
- */
-
-/** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
- * @{
- */
-/** @brief SYSCFG interrupt enable/disable macros
- * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
- */
-#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
- SYSCFG->CFGR1 |= (__INTERRUPT__); \
- }while(0U)
-
-#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
- SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
- }while(0U)
-/**
- * @}
- */
-
-#if defined(SYSCFG_CFGR1_USB_IT_RMP)
-/** @defgroup USB_Interrupt_Remap USB Interrupt Remap
- * @{
- */
-/** @brief USB interrupt remapping enable/disable macros
- */
-#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
-#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR1_USB_IT_RMP */
-
-#if defined(SYSCFG_CFGR1_VBAT)
-/** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
- * @{
- */
-/** @brief SYSCFG interrupt enable/disable macros
- */
-#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
-#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR1_VBAT */
-
-#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
-/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
- * @{
- */
-/** @brief SYSCFG Break Lockup lock
- * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
- * @note The selected configuration is locked and can be unlocked by system reset
- */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
- SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
- }while(0U)
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
-
-#if defined(SYSCFG_CFGR2_PVD_LOCK)
-/** @defgroup PVD_Lock_Enable PVD Lock
- * @{
- */
-/** @brief SYSCFG Break PVD lock
- * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
- * @note The selected configuration is locked and can be unlocked by system reset
- */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
- SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
- }while(0U)
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR2_PVD_LOCK */
-
-#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
-/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
- * @{
- */
-/** @brief SYSCFG Break SRAM PARITY lock
- * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
- * @note The selected configuration is locked and can be unlocked by system reset
- */
-#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
- SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
- }while(0U)
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
-
-/** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
- * @{
- */
-#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
-/** @brief Trigger remapping enable/disable macros
- * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
- */
-#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
- (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
- (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
- (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
- }while(0U)
-#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
- (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
- (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
- (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
- }while(0U)
-#else
-/** @brief Trigger remapping enable/disable macros
- * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
- */
-#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
- (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
- }while(0U)
-#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
- (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
- }while(0U)
-#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
-/**
- * @}
- */
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-/** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
- * @{
- */
-/** @brief ADC trigger remapping enable/disable macros
- * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
- */
-#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
- (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
- }while(0U)
-#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
- (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
- }while(0U)
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
-/** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
- * @{
- */
-/**
- * @brief Parity check on RAM disable macro
- * @note Disabling the parity check on RAM locks the configuration bit.
- * To re-enable the parity check on RAM perform a system reset.
- */
-#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
-
-#if defined(SYSCFG_RCR_PAGE0)
-/** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
- * @{
- */
-/** @brief CCM RAM page write protection enable macro
- * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
- * @note write protection can only be disabled by a system reset
- */
-#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
- SYSCFG->RCR |= (__PAGE_WP__); \
- }while(0U)
-/**
- * @}
- */
-#endif /* SYSCFG_RCR_PAGE0 */
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h
deleted file mode 100644
index 16eca9a7bbf..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_adc.h
- * @author MCD Application Team
- * @brief Header file containing functions prototypes of ADC HAL library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_ADC_H
-#define __STM32F3xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/* Include ADC HAL Extended module */
-/* (include on top of file since ADC structures are defined in extended file) */
-#include "stm32f3xx_hal_adc_ex.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
- * @{
- */
-/**
- * @brief HAL ADC state machine: ADC states definition (bitfields)
- * @note ADC state machine is managed by bitfields, state must be compared
- * with bit by bit.
- * For example:
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
- */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/**
- * @brief ADC handle Structure definition
- */
-typedef struct __ADC_HandleTypeDef
-{
- ADC_TypeDef *Instance; /*!< Register base address */
-
- ADC_InitTypeDef Init; /*!< ADC required parameters */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
-
- HAL_LockTypeDef Lock; /*!< ADC locking object */
-
- __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
-
- __IO uint32_t ErrorCode; /*!< ADC Error code */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
- ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-}ADC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macro ADC Exported Macros
- * @{
- */
-/** @brief Reset ADC handle state
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- * @brief ADC Peripheral State functions
- * @{
- */
-/* Peripheral State functions *************************************************/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F3xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h
deleted file mode 100644
index 1d26d6ddff8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h
+++ /dev/null
@@ -1,3988 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_adc_ex.h
- * @author MCD Application Team
- * @brief Header file containing functions prototypes of ADC HAL library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_ADC_EX_H
-#define __STM32F3xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADCEx ADCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
- * @{
- */
-struct __ADC_HandleTypeDef;
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Structure definition of ADC initialization and regular group
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
- * ScanConvMode, EOCSelection, LowPowerAutoWait.
- * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
- * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled
- * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
- * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
- The clock is common for all the ADCs.
- This parameter can be a value of @ref ADCEx_ClockPrescaler
- Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
- AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
- Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
- Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
- uint32_t Resolution; /*!< Configures the ADC resolution.
- This parameter can be a value of @ref ADCEx_Resolution */
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting)
- or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U).
- See reference manual for alignments with other resolutions.
- This parameter can be a value of @ref ADCEx_Data_align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be a value of @ref ADCEx_Scan_mode */
- uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
- This parameter can be a value of @ref ADCEx_EOCSelection. */
- uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
- New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
- This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
- This parameter can be set to ENABLE or DISABLE.
- Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
- Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
- and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16.
- Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
- Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */
- uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
- If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
- This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
- uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
- or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
- This parameter can be set to ENABLE or DISABLE.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
- uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
- This parameter is for regular group only.
- This parameter can be a value of @ref ADCEx_Overrun
- Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
- Note: Error reporting in function of conversion mode:
- - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
- - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
-}ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
- * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
- * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADCEx_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
- This parameter can be a value of @ref ADCEx_regular_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- This parameter can be a value of @ref ADCEx_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
- uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
- In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
- Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
- This parameter must be a value of @ref ADCEx_SingleDifferential
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
- Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
- uint32_t OffsetNumber; /*!< Selects the offset number
- This parameter can be a value of @ref ADCEx_OffsetNumber
- Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
- uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
- Offset value must be a positive number.
- Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
-}ADC_ChannelConfTypeDef;
-
-/**
- * @brief Structure definition of ADC injected group and ADC channel for injected group
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
- * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
- * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
- * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
- * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
- * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
- * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t InjectedChannel; /*!< Configure the ADC injected channel
- This parameter can be a value of @ref ADCEx_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t InjectedRank; /*!< The rank in the regular group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- This parameter can be a value of @ref ADCEx_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
- uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
- In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
- Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
- This parameter must be a value of @ref ADCEx_SingleDifferential
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
- Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
- uint32_t InjectedOffsetNumber; /*!< Selects the offset number
- This parameter can be a value of @ref ADCEx_OffsetNumber
- Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
- Offset value must be a positive number.
- Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
- This parameter can be set to ENABLE or DISABLE.
- If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
- new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
- Caution: This feature request that the sequence is fully configured before injected conversion start.
- Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set.
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
- This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
- If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-
-/**
- * @brief ADC Injection Configuration
- */
-typedef struct
-{
- uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
- HAL_ADCEx_InjectedConfigChannel() call to finally initialize
- JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
-
- uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
-}ADC_InjectionConfigTypeDef;
-
-/**
- * @brief Structure definition of ADC analog watchdog
- * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
- * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
- */
-typedef struct
-{
- uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel.
- For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
- For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
- This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
- uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
- For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
- This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
- uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
- For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
- For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
- Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
- This parameter can be a value of @ref ADCEx_channels. */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
- uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
-}ADC_AnalogWDGConfTypeDef;
-
-/**
- * @brief Structure definition of ADC multimode
- * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode')
- * - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
- This parameter can be a value of @ref ADCEx_Common_mode */
- uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode:
- selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
- This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
- Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
- Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel.
- Refer to device errata sheet for more details. */
- uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
- Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
- from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */
-}ADC_MultiModeTypeDef;
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Structure definition of ADC and regular group initialization
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
- * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
- * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
- * ADC can be either disabled or enabled without conversion on going on regular group.
- */
-typedef struct
-{
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U).
- This parameter can be a value of @ref ADCEx_Data_align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be a value of @ref ADCEx_Scan_mode
- Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U)
- or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
- the last conversion of the sequence. All previous conversions would be overwritten by the last one.
- Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
-}ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
- * ADC can be either disabled or enabled without conversion on going on regular group.
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADCEx_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
- This parameter can be a value of @ref ADCEx_regular_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
- This parameter can be a value of @ref ADCEx_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
-}ADC_ChannelConfTypeDef;
-
-/**
- * @brief ADC Configuration injected Channel structure definition
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
- * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
- * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
- * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
- * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
- */
-typedef struct
-{
- uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
- This parameter can be a value of @ref ADCEx_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t InjectedRank; /*!< Rank in the injected group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
- This parameter can be a value of @ref ADCEx_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
- Offset value must be a positive number.
- Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-
-/**
- * @brief ADC Configuration analog watchdog definition
- * @note The setting of these parameters with function is conditioned to ADC state.
- * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
- */
-typedef struct
-{
- uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
- This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
- uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
- This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
- This parameter can be a value of @ref ADCEx_channels. */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */
-}ADC_AnalogWDGConfTypeDef;
-#endif /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
- * @{
- */
-
-/** @defgroup ADCEx_Error_Code ADC Extended Error Code
- * @{
- */
-#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
- enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
-#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
-/**
- * @}
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
- * @{
- */
-#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
-#endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Resolution ADC Extended Resolution
- * @{
- */
-#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
-#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
-#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
-#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
- * @{
- */
-#define ADC_DATAALIGN_RIGHT (0x00000000U)
-#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
- * @{
- */
-#define ADC_SCAN_DISABLE (0x00000000U)
-#define ADC_SCAN_ENABLE (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
- * @{
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/*!< External triggers of regular group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-
-/*!< External triggers of regular group for ADC3&ADC4 only */
-#define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1
-#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3
-#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1
-#define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1
-#define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO
-#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1
-#define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2
-
-/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */
-/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
-/* ADC3_4 by driver when needed. */
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
-#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
-#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-
-#define ADC_SOFTWARE_START (0x00000001U)
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/* ADC external triggers specific to device STM303xE: mask to differentiate */
-/* standard triggers from specific timer 20U, needed for reallocation of */
-/* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */
-/* triggers without remap. */
-#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
-
-/*!< List of external triggers specific to device STM303xE: using Timer20 */
-/* with ADC trigger input remap. */
-/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
-/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
-
-/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
-#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
-
-/*!< External triggers of regular group for ADC3&ADC4 only, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-/* None */
-
-/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
-/* ADC3_4 by driver when needed. */
-#define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */
-#define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
-#define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */
-#endif /* STM32F303xE || STM32F398xx */
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/*!< External triggers of regular group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START (0x00000001U)
-
-#if defined(STM32F302xE)
-/* ADC external triggers specific to device STM302xE: mask to differentiate */
-/* standard triggers from specific timer 20U, needed for reallocation of */
-/* triggers common to ADC1&2 and to avoind mixing with standard */
-/* triggers without remap. */
-#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
-
-/*!< List of external triggers specific to device STM302xE: using Timer20 */
-/* with ADC trigger input remap. */
-/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
-/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
-
-/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
-/* device STM302xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
-#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
-#endif /* STM32F302xE */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/*!< External triggers of regular group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
-#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
-#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START (0x00000001U)
-
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/*!< External triggers of regular group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-#define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
-#define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START (0x00000001U)
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* List of external triggers with generic trigger name, sorted by trigger */
-/* name: */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
-#define ADC_SOFTWARE_START (0x00000001U)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
- * @{
- */
-#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
-#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Overrun ADC Extended overrun
- * @{
- */
-#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */
-#define ADC_OVR_DATA_PRESERVED (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_channels ADC Extended Channels
- * @{
- */
-/* Note: Depending on devices, some channels may not be available on package */
-/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
-#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
-#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
-#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
-#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
-#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
-#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
-
-/* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
-#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15
-#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
-#define ADC_CHANNEL_VBAT ADC_CHANNEL_17
-
-/* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */
-#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
-#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
-#define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
-
-/* Note: VrefInt internal channels available on all ADCs, but only */
-/* one ADC is allowed to be connected to VrefInt at the same time. */
-#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
- * @{
- */
-#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
-#define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */
-#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */
-#define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */
-#define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */
-#define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
- * @{
- */
-#define ADC_SINGLE_ENDED (0x00000000U)
-#define ADC_DIFFERENTIAL_ENDED (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
- * @{
- */
-#define ADC_OFFSET_NONE (0x00U)
-#define ADC_OFFSET_1 (0x01U)
-#define ADC_OFFSET_2 (0x02U)
-#define ADC_OFFSET_3 (0x03U)
-#define ADC_OFFSET_4 (0x04U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
- * @{
- */
-#define ADC_REGULAR_RANK_1 (0x00000001U)
-#define ADC_REGULAR_RANK_2 (0x00000002U)
-#define ADC_REGULAR_RANK_3 (0x00000003U)
-#define ADC_REGULAR_RANK_4 (0x00000004U)
-#define ADC_REGULAR_RANK_5 (0x00000005U)
-#define ADC_REGULAR_RANK_6 (0x00000006U)
-#define ADC_REGULAR_RANK_7 (0x00000007U)
-#define ADC_REGULAR_RANK_8 (0x00000008U)
-#define ADC_REGULAR_RANK_9 (0x00000009U)
-#define ADC_REGULAR_RANK_10 (0x0000000AU)
-#define ADC_REGULAR_RANK_11 (0x0000000BU)
-#define ADC_REGULAR_RANK_12 (0x0000000CU)
-#define ADC_REGULAR_RANK_13 (0x0000000DU)
-#define ADC_REGULAR_RANK_14 (0x0000000EU)
-#define ADC_REGULAR_RANK_15 (0x0000000FU)
-#define ADC_REGULAR_RANK_16 (0x00000010U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
- * @{
- */
-#define ADC_INJECTED_RANK_1 (0x00000001U)
-#define ADC_INJECTED_RANK_2 (0x00000002U)
-#define ADC_INJECTED_RANK_3 (0x00000003U)
-#define ADC_INJECTED_RANK_4 (0x00000004U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
- * @{
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/* List of external triggers with generic trigger name, independently of ADC */
-/* target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/* External triggers of injected group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-/* External triggers of injected group for ADC3&ADC4 only */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2
-
-/* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
-/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
-/* ADC3_4 by driver when needed. */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
-
-#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/*!< List of external triggers specific to device STM303xE: using Timer20 */
-/* with ADC trigger input remap. */
-/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
-/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
-
-/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
-
-/*!< External triggers of injected group for ADC3&ADC4 only, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */
-
-/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
-/* device STM303xE: : using Timer20 with ADC trigger input remap */
-/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
-/* ADC3_4 by driver when needed. */
-#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
-#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */
-#endif /* STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
- \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F303xE || STM32F398xx */
-
-#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/* External triggers of injected group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
-
-#if defined(STM32F302xE)
-/*!< List of external triggers specific to device STM302xE: using Timer20 */
-/* with ADC trigger input remap. */
-/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
-/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
-
-/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
-/* device STM302xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
-#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
-#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
-#endif /* STM32F302xE */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/* External triggers of injected group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target (caution: applies to other ADCs sharing the same common group), */
-/* sorted by trigger name: */
-
-/* External triggers of injected group for ADC1&ADC2 */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
-#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* List of external triggers with generic trigger name, sorted by trigger */
-/* name: */
-
-/* External triggers of injected group for ADC1 */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
-
-#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U))
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
-#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
-#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0))
-#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1))
-#define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
-#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0))
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
- * @{
- */
-#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
-#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
-#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
- * @{
- */
-#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U))
-#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2))
-#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3))
-#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
- * @{
- */
-#define ADC_ANALOGWATCHDOG_1 (0x00000001U)
-#define ADC_ANALOGWATCHDOG_2 (0x00000002U)
-#define ADC_ANALOGWATCHDOG_3 (0x00000003U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
- * @{
- */
-#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
-/**
- * @}
- */
-
-/** @defgroup ADC_conversion_group ADC Conversion Group
- * @{
- */
-#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
-#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
-#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Event_type ADC Extended Event Type
- * @{
- */
-#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */
-#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */
-#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */
-#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
-#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
-
-#define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
- * @{
- */
-#define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */
-#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */
-#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */
-#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
-#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */
-#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */
-#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
-#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
-#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
-
-#define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
- * @{
- */
-#define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */
-#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
-#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
-#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
-#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */
-#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */
-#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */
-#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
-
-#define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
- * @{
- */
-#define ADC_DATAALIGN_RIGHT (0x00000000U)
-#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
- * @{
- */
-#define ADC_SCAN_DISABLE (0x00000000U)
-#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
- * @{
- */
-/* List of external triggers with generic trigger name, sorted by trigger */
-/* name: */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
-#define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
-#define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START ADC_SWSTART
-/**
- * @}
- */
-
-/** @defgroup ADCEx_channels ADC Extended Channels
- * @{
- */
-/* Note: Depending on devices, some channels may not be available on package */
-/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_0 (0x00000000U)
-#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
-#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
-#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
-#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
-#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
-#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
-#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
-#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
-#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
-
-#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
-#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
-#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
-/**
- * @}
- */
-
-/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
- * @{
- */
-#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
-#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
-#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
-#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
-#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
-#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
- * @{
- */
-#define ADC_REGULAR_RANK_1 (0x00000001U)
-#define ADC_REGULAR_RANK_2 (0x00000002U)
-#define ADC_REGULAR_RANK_3 (0x00000003U)
-#define ADC_REGULAR_RANK_4 (0x00000004U)
-#define ADC_REGULAR_RANK_5 (0x00000005U)
-#define ADC_REGULAR_RANK_6 (0x00000006U)
-#define ADC_REGULAR_RANK_7 (0x00000007U)
-#define ADC_REGULAR_RANK_8 (0x00000008U)
-#define ADC_REGULAR_RANK_9 (0x00000009U)
-#define ADC_REGULAR_RANK_10 (0x0000000AU)
-#define ADC_REGULAR_RANK_11 (0x0000000BU)
-#define ADC_REGULAR_RANK_12 (0x0000000CU)
-#define ADC_REGULAR_RANK_13 (0x0000000DU)
-#define ADC_REGULAR_RANK_14 (0x0000000EU)
-#define ADC_REGULAR_RANK_15 (0x0000000FU)
-#define ADC_REGULAR_RANK_16 (0x00000010U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
- * @{
- */
-#define ADC_INJECTED_RANK_1 (0x00000001U)
-#define ADC_INJECTED_RANK_2 (0x00000002U)
-#define ADC_INJECTED_RANK_3 (0x00000003U)
-#define ADC_INJECTED_RANK_4 (0x00000004U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
- * @{
- */
-/* External triggers for injected groups of ADC1 */
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
- * @{
- */
-#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-/**
- * @}
- */
-
-/** @defgroup ADC_conversion_group ADC Conversion Group
- * @{
- */
-#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
-#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
-#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Event_type ADC Extended Event Type
- * @{
- */
-#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
- * @{
- */
-#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
- * @{
- */
-#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
-#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
-#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
-#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
-#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
-
-/**
- * @}
- */
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
- * @{
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers of regular group for ADC1 & ADC2 */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
-#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
-#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
-#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
-
-/* External triggers of regular group for ADC3 & ADC4 */
-#define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U)
-#define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3)
-#define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
-#define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-/* List of external triggers of common group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
-#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
-#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-/* List of external triggers of common group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
-#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
-#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
-#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-/* List of external triggers of common group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
-#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
-#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3)
-#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* List of external triggers of regular group for ADC1: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U)
-#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
-#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
-#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
-#define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
-#define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
-#define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
-#define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC_SOFTWARE_START (0x00000001U)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
- * @{
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers for injected groups of ADC1 & ADC2 */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
-#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-
-/* External triggers for injected groups of ADC3 & ADC4 */
-/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */
-/* JEXT2 is the main trigger, JEXT5 could be redirected to another */
-/* in future devices. */
-/* However, this channel is implemented with a SW offset of 0x10000 for */
-/* differentiation between similar triggers of common groups ADC1&ADC2, */
-/* ADC3&ADC4 (Differentiation processed into macro */
-/* ADC_JSQR_JEXTSEL_SET) */
-#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U)
-#define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#endif /* STM32F303xE || STM32F398xx */
-
-#define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
-#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
-#define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
-#define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-/* List of external triggers of group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
-#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-/* List of external triggers of group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
-#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-/* List of external triggers of group ADC1&ADC2: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* List of external triggers of injected group for ADC1: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
-#define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
-#define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
-#define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
-#define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
-#define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
- ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
- ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
- ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
- ADC_FLAG_JQOVF)
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
- * @{
- */
-/* List of external triggers of regular group for ADC1: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)
-#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
-#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
-#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
- * @{
- */
-/* List of external triggers of injected group for ADC1: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers of injected group for ADC1 */
-#define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)
-#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
-#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
- * @{
- */
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
- (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
- ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
- ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
- (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
- ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
- (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
- ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
- ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
- (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
- ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
- (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
- ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
- ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
- (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
- ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)
-#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)
-#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
-/**
- * @}
- */
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
- * @{
- */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user. */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/**
- * @brief Enable the ADC peripheral
- * @param __HANDLE__ ADC handle
- * @note ADC enable requires a delay for ADC stabilization time
- * (refer to device datasheet, parameter tSTAB)
- * @note On STM32F3 devices, some hardware constraints must be strictly
- * respected before using this macro:
- * - ADC internal voltage regulator must be preliminarily enabled.
- * This is performed by function HAL_ADC_Init().
- * - ADC state requirements: ADC must be disabled, no conversion on
- * going, no calibration on going.
- * These checks are performed by functions HAL_ADC_start_xxx().
- * @retval None
- */
-#define __HAL_ADC_ENABLE(__HANDLE__) \
- (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN))
-
-/**
- * @brief Disable the ADC peripheral
- * @param __HANDLE__ ADC handle
- * @note On STM32F3 devices, some hardware constraints must be strictly
- * respected before using this macro:
- * - ADC state requirements: ADC must be enabled, no conversion on
- * going.
- * These checks are performed by functions HAL_ADC_start_xxx().
- * @retval None
- */
-#define __HAL_ADC_DISABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \
- __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
- } while(0U)
-
-/**
- * @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
-
-/**
- * @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
- * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
- * @arg ADC_IT_OVR: ADC overrun interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
- * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
- * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Get the selected ADC's flag status.
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
- * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR: ADC overrun flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
- * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
- * @retval None
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the ADC's pending flags
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
- * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
- * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
- * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
- * @arg ADC_FLAG_OVR: ADC overrun flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
- * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
- * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
- * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
- * @retval None
- */
-/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */
-/* register ISR). */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
-
-/** @brief Reset ADC handle state
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/**
- * @brief Enable the ADC peripheral
- * @note ADC enable requires a delay for ADC stabilization time
- * (refer to device datasheet, parameter tSTAB)
- * @note On STM32F37x devices, if ADC is already enabled this macro trigs
- * a conversion SW start on regular group.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_ENABLE(__HANDLE__) \
- (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-
-/**
- * @brief Disable the ADC peripheral
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_DISABLE(__HANDLE__) \
- (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-
-/** @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected ADC's flag status.
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_STRT: ADC Regular group start flag
- * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
- * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
- * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
- * @retval None
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the ADC's pending flags
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_STRT: ADC Regular group start flag
- * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
- * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
- * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
- * @retval None
- */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
-
-/** @brief Reset ADC handle state
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @addtogroup ADCEx_Private_Macro ADCEx Private Macros
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/**
- * @brief Verification of hardware constraints before ADC can be enabled
- * @param __HANDLE__ ADC handle
- * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
- */
-#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
- (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \
- (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | \
- ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS | \
- ADC_CR_ADEN ) ) \
- ) ? SET : RESET)
-
-/**
- * @brief Verification of ADC state: enabled or disabled
- * @param __HANDLE__ ADC handle
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_IS_ENABLE(__HANDLE__) \
- (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
- ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
- ) ? SET : RESET)
-
-/**
- * @brief Test if conversion trigger of regular group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
-
-/**
- * @brief Check if no conversion on going on regular and/or injected groups
- * @param __HANDLE__ ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Check if no conversion on going on regular group
- * @param __HANDLE__ ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Check if no conversion on going on injected group
- * @param __HANDLE__ ADC handle
- * @retval SET (conversion is on going) or RESET (no conversion is on going)
- */
-#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
- ) ? RESET : SET)
-
-/**
- * @brief Returns resolution bits in CFGR1 register: RES[1:0].
- * Returned value is among parameters to @ref ADCEx_Resolution.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
-
-/**
- * @brief Simultaneously clears and sets specific bits of the handle State
- * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
- * the first parameter is the ADC handle State, the second parameter is the
- * bit field to clear, the third and last parameter is the bit field to set.
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Clear ADC error code (set it to error code: "no error")
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
- * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
-
-/**
- * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 1 and 4.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 5 and 9.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 10 and 14.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
-
-/**
- * @brief Set the selected regular Channel rank for rank between 15 and 16.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
-
-/**
- * @brief Set the selected injected Channel rank.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
-
-
-/**
- * @brief Set the Analog Watchdog 1 channel.
- * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
- * @retval None
- */
-#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U)
-
-/**
- * @brief Configure the channel number into Analog Watchdog 2 or 3.
- * @param _CHANNEL_ ADC Channel
- * @retval None
- */
-#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
-
-/**
- * @brief Enable automatic conversion of injected group
- * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion.
- * @retval None
- */
-#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U)
-
-/**
- * @brief Enable ADC injected context queue
- * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U)
-
-/**
- * @brief Enable ADC discontinuous conversion mode for injected group
- * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U)
-
-/**
- * @brief Enable ADC discontinuous conversion mode for regular group
- * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
- * @retval None
- */
-#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
-
-/**
- * @brief Configures the number of discontinuous conversions for regular group.
- * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
-
-/**
- * @brief Enable the ADC auto delay mode.
- * @param _AUTOWAIT_ Auto delay bit enable or disable.
- * @retval None
- */
-#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param _CONTINUOUS_MODE_ Continuous mode.
- * @retval None
- */
-#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
-
-/**
- * @brief Enable ADC overrun mode.
- * @param _OVERRUN_MODE_ Overrun mode.
- * @retval Overrun bit setting to be programmed into CFGR register
- */
-/* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
-/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */
-/* as the default case to be compliant with other STM32 devices. */
-#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
- ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
- )? (ADC_CFGR_OVRMOD) : (0x00000000U) \
- )
-
-/**
- * @brief Enable the ADC DMA continuous request.
- * @param _DMACONTREQ_MODE_ DMA continuous request mode.
- * @retval None
- */
-#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
-
-/**
- * @brief For devices with 3 ADCs or more: Defines the external trigger source
- * for regular group according to ADC into common group ADC1&ADC2 or
- * ADC3&ADC4 (some triggers with same source have different value to
- * be programmed into ADC EXTSEL bits of CFGR register).
- * Note: No risk of trigger bits value of common group ADC1&ADC2
- * misleading to another trigger at same bits value, because the 3
- * exceptions below are circular and do not point to any other trigger
- * with direct treatment.
- * For devices with 2 ADCs or less: this macro makes no change.
- * @param __HANDLE__ ADC handle
- * @param __EXT_TRIG_CONV__ External trigger selected for regular group.
- * @retval External trigger to be programmed into EXTSEL bits of CFGR register
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
- (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
- )? \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T2_TRGO) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T3_TRGO) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T8_TRGO) \
- : \
- (__EXT_TRIG_CONV__) \
- ) \
- ) \
- ) \
- : \
- (__EXT_TRIG_CONV__) \
- )
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/* Note: Macro including external triggers specific to device STM303xE: using */
-/* Timer20 with ADC trigger input remap. */
-#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
- (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
- )? \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T2_TRGO) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T3_TRGO) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_T8_TRGO) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \
- )? \
- (ADC3_4_EXTERNALTRIG_T2_CC1) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIG_EXT_IT2) \
- : \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \
- )? \
- (ADC3_4_EXTERNALTRIG_T4_CC1) \
- : \
- (__EXT_TRIG_CONV__) \
- ) \
- ) \
- ) \
- ) \
- ) \
- ) \
- : \
- (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
- )
-#endif /* STM32F303xE || STM32F398xx */
-#else
-#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
- (__EXT_TRIG_CONV__)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-/**
- * @brief For devices with 3 ADCs or more: Defines the external trigger source
- * for injected group according to ADC into common group ADC1&ADC2 or
- * ADC3&ADC4 (some triggers with same source have different value to
- * be programmed into ADC JEXTSEL bits of JSQR register).
- * Note: No risk of trigger bits value of common group ADC1&ADC2
- * misleading to another trigger at same bits value, because the 3
- * exceptions below are circular and do not point to any other trigger
- * with direct treatment, except trigger
- * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
- * For devices with 2 ADCs or less: this macro makes no change.
- * @param __HANDLE__ ADC handle
- * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group
- * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
- */
-#if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
-#if defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
- )? \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
- : \
- (__EXT_TRIG_INJECTCONV__) \
- ) \
- ) \
- ) \
- ) \
- : \
- (__EXT_TRIG_INJECTCONV__) \
- )
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/* Note: Macro including external triggers specific to device STM303xE: using */
-/* Timer20 with ADC trigger input remap. */
-#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
- )? \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) \
- == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \
- : \
- ( ( (__EXT_TRIG_INJECTCONV__) \
- == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \
- )? \
- (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \
- : \
- (__EXT_TRIG_INJECTCONV__) \
- ) \
- ) \
- ) \
- ) \
- ) \
- ) \
- : \
- (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
- )
-#endif /* STM32F303xE || STM32F398xx */
-#else
-#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (__EXT_TRIG_INJECTCONV__)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-/**
- * @brief Configure the channel number into offset OFRx register
- * @param _CHANNEL_ ADC Channel
- * @retval None
- */
-#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U)
-
-/**
- * @brief Configure the channel number into differential mode selection register
- * @param _CHANNEL_ ADC Channel
- * @retval None
- */
-#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
-
-/**
- * @brief Calibration factor in differential mode to be set into calibration register
- * @param _Calibration_Factor_ Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
-
-/**
- * @brief Calibration factor in differential mode to be retrieved from calibration register
- * @param _Calibration_Factor_ Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
-
-/**
- * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
- * @param _Threshold_ Threshold value
- * @retval None
- */
-#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
-
-/**
- * @brief Enable the ADC DMA continuous request for ADC multimode.
- * @param _DMAContReq_MODE_ DMA continuous request mode.
- * @retval None
- */
-#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
-
-/**
- * @brief Verification of hardware constraints before ADC can be disabled
- * @param __HANDLE__ ADC handle
- * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
- */
-#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
- (( ( ((__HANDLE__)->Instance->CR) & \
- (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
- ) ? SET : RESET)
-
-
-/**
- * @brief Shift the offset in function of the selected ADC resolution.
- * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
- * If resolution 12 bits, no shift.
- * If resolution 10 bits, shift of 2 ranks on the left.
- * If resolution 8 bits, shift of 4 ranks on the left.
- * If resolution 6 bits, shift of 6 ranks on the left.
- * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
- * @param __HANDLE__ ADC handle
- * @param _Offset_ Value to be shifted
- * @retval None
- */
-#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
- ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
-
-/**
- * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
- * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
- * If resolution 12 bits, no shift.
- * If resolution 10 bits, shift of 2 ranks on the left.
- * If resolution 8 bits, shift of 4 ranks on the left.
- * If resolution 6 bits, shift of 6 ranks on the left.
- * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
- * @param __HANDLE__ ADC handle
- * @param _Threshold_ Value to be shifted
- * @retval None
- */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
- ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
-
-/**
- * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
- * Thresholds have to be left-aligned on bit 7.
- * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
- * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
- * If resolution 8 bits, no shift.
- * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
- * @param __HANDLE__ ADC handle
- * @param _Threshold_ Value to be shifted
- * @retval None
- */
-#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
- ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
- ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \
- (_Threshold_) << 2U )
-
-/**
- * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
- * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
- * @param __HANDLE__ ADC handle
- * @retval Common control register ADC1_2 or ADC3_4
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_MASTER_INSTANCE(__HANDLE__) \
- ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
- )? (ADC1) : (ADC3) \
- )
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_MASTER_INSTANCE(__HANDLE__) \
- (ADC1)
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_MASTER_INSTANCE(__HANDLE__) \
- (ADC1)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
- * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
- * @param __HANDLE__ ADC handle
- * @retval Common control register ADC1_2 or ADC3_4
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_COMMON_REGISTER(__HANDLE__) \
- ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
- )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \
- )
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_COMMON_REGISTER(__HANDLE__) \
- (ADC1_2_COMMON)
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_COMMON_REGISTER(__HANDLE__) \
- (ADC1_COMMON)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
- ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
- )? \
- (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \
- : \
- (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \
- )
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
- (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
- (RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
- (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- (!RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
- * @param __HANDLE__ ADC handle.
- * @retval None
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
- ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
- (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) || \
- (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) || \
- (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
- (!RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
- * @param __HANDLE__ ADC handle.
- * @retval None
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
- ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
- (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) || \
- (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) || \
- (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
- (!RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
- )? \
- (ADC1->CFGR & ADC_CFGR_JAUTO) \
- : \
- (ADC3->CFGR & ADC_CFGR_JAUTO) \
- )
-#elif defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
- )? \
- (ADC1->CFGR & ADC_CFGR_JAUTO) \
- : \
- (RESET) \
- )
-#else
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
- (RESET)
-#endif
-
-/**
- * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
- * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
- * @param __HANDLE__ ADC handle
- * @param __HANDLE_OTHER_ADC__ other ADC handle
- * @retval None
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
- ( ( ((__HANDLE__)->Instance == ADC1) \
- )? \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
- : \
- ( ( ((__HANDLE__)->Instance == ADC2) \
- )? \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
- : \
- ( ( ((__HANDLE__)->Instance == ADC3) \
- )? \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \
- : \
- ( ( ((__HANDLE__)->Instance == ADC4) \
- )? \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \
- : \
- ((__HANDLE_OTHER_ADC__)->Instance = NULL) \
- ) \
- ) \
- ) \
- )
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
- ( ( ((__HANDLE__)->Instance == ADC1) \
- )? \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
- : \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
- )
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
- ((__HANDLE_OTHER_ADC__)->Instance = NULL)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Set handle of the ADC slave associated to the ADC master
- * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
- * @param __HANDLE_MASTER__ ADC master handle
- * @param __HANDLE_SLAVE__ ADC slave handle
- * @retval None
- */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
- )? \
- ((__HANDLE_SLAVE__)->Instance = ADC2) \
- : \
- ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \
- )? \
- ((__HANDLE_SLAVE__)->Instance = ADC4) \
- : \
- ((__HANDLE_SLAVE__)->Instance = NULL) \
- ) \
- )
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
- )? \
- ((__HANDLE_SLAVE__)->Instance = ADC2) \
- : \
- ( NULL ) \
- )
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
- ((RESOLUTION) == ADC_RESOLUTION_10B) || \
- ((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B) )
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B) )
-
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT) )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
- ((SCAN_MODE) == ADC_SCAN_ENABLE) )
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
-
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
- ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
- ((CHANNEL) == ADC_CHANNEL_VBAT) || \
- ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
- ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \
- ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \
- ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \
- ((CHANNEL) == ADC_CHANNEL_VOPAMP4) )
-
-#define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) )
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
- ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_601CYCLES_5) )
-
-#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \
- ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
-
-#define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_1) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_2) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_3) || \
- ((OFFSET_NUMBER) == ADC_OFFSET_4) )
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_10) || \
- ((CHANNEL) == ADC_REGULAR_RANK_11) || \
- ((CHANNEL) == ADC_REGULAR_RANK_12) || \
- ((CHANNEL) == ADC_REGULAR_RANK_13) || \
- ((CHANNEL) == ADC_REGULAR_RANK_14) || \
- ((CHANNEL) == ADC_REGULAR_RANK_15) || \
- ((CHANNEL) == ADC_REGULAR_RANK_16) )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F303xE || STM32F398xx */
-
-#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-
-#if defined(STM32F302xE)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F302xE */
-
-#if defined(STM32F302xC)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F302xC */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
-
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
- \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F303xE || STM32F398xx */
-
-#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-
-#if defined(STM32F302xE)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F302xE */
-
-#if defined(STM32F302xC)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F302xC */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F303x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F334x8 */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
- ((CHANNEL) == ADC_INJECTED_RANK_2) || \
- ((CHANNEL) == ADC_INJECTED_RANK_3) || \
- ((CHANNEL) == ADC_INJECTED_RANK_4) )
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERL) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) )
-
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
- ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \
- ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) )
-
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
-
-#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
- ((CONVERSION) == ADC_INJECTED_GROUP) || \
- ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
- ((EVENT) == ADC_AWD2_EVENT) || \
- ((EVENT) == ADC_AWD3_EVENT) || \
- ((EVENT) == ADC_OVR_EVENT) || \
- ((EVENT) == ADC_JQOVF_EVENT) )
-
-/** @defgroup ADCEx_range_verification ADC Extended Range Verification
- * in function of ADC resolution selected (12, 10, 8 or 6 bits)
- * @{
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \
- (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) )
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
- * @{
- */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
- * @{
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
- * @{
- */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
-/**
- * @}
- */
-
-/** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
- * @{
- */
-/**
- * @brief Calibration factor length verification (7 bits maximum)
- * @param _Calibration_Factor_ Calibration factor value
- * @retval None
- */
-#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/**
- * @brief Verification of ADC state: enabled or disabled
- * @param __HANDLE__ ADC handle
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_IS_ENABLE(__HANDLE__) \
- ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
- ) ? SET : RESET)
-
-/**
- * @brief Test if conversion trigger of regular group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
-
-/**
- * @brief Simultaneously clears and sets specific bits of the handle State
- * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
- * the first parameter is the ADC handle State, the second parameter is the
- * bit field to clear, the third and last parameter is the bit field to set.
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Clear ADC error code (set it to error code: "no error")
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
- ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
- * @brief Set ADC number of conversions into regular channel sequence length.
- * @param _NbrOfConversion_ Regular channel sequence length
- * @retval None
- */
-#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
- (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 10 and 18.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 0 and 9.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 1 and 6.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 7 and 12.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 13 and 16.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
-
-/**
- * @brief Set the injected sequence length.
- * @param _JSQR_JL_ Sequence length.
- * @retval None
- */
-#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
- (((_JSQR_JL_) -1U) << 20U)
-
-/**
- * @brief Set the selected injected channel rank
- * Note: on STM32F37x devices, channel rank position in JSQR register
- * is depending on total number of ranks selected into
- * injected sequencer (ranks sequence starting from 4-JL)
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @param _JSQR_JL_ Sequence length.
- * @retval None
- */
-#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
- ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param _CONTINUOUS_MODE_ Continuous mode.
- * @retval None
- */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
- ((_CONTINUOUS_MODE_) << 1U)
-
-/**
- * @brief Configures the number of discontinuous conversions for the regular group channels.
- * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
- (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
-
-/**
- * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
- * @param _SCAN_MODE_ Scan conversion mode.
- * @retval None
- */
-/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
-/* is equivalent to ADC_SCAN_ENABLE. */
-#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
- (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
- )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
- )
-
-/**
- * @brief Calibration factor in differential mode to be set into calibration register
- * @param _Calibration_Factor_ Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \
- ((_Calibration_Factor_) << 16U)
-
-/**
- * @brief Calibration factor in differential mode to be retrieved from calibration register
- * @param _Calibration_Factor_ Calibration factor value
- * @retval None
- */
-#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \
- ((_Calibration_Factor_) >> 16U)
-
-
-/**
- * @brief Get the maximum ADC conversion cycles on all channels.
- * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
- * Approximation of sampling time within 4 ranges, returns the highest value:
- * below 7.5 cycles {1.5 cycle; 7.5 cycles},
- * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
- * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
- * equal to 239.5 cycles
- * Unit: ADC clock cycles
- * @param __HANDLE__ ADC handle
- * @retval ADC conversion cycles on all channels
- */
-#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
- (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
- \
- (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
- ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
- : \
- ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
- ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
- ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
- )
-
-/**
- * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
- * from system clock configuration register.
- * Approximation within 3 ranges, returns the higher value:
- * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
- * total prescaler 32 (ADC presc 0 and APB2 presc all, or
- * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
- * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
- * Unit: none (prescaler factor)
- * @retval ADC and APB2 prescaler factor
- */
-#define ADC_CLOCK_PRESCALER_RANGE() \
- (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \
- (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \
- : \
- (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \
- )
-
-/**
- * @brief Get the ADC clock prescaler from system clock configuration register.
- * @retval None
- */
-#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT) )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
- ((SCAN_MODE) == ADC_SCAN_ENABLE) )
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
- ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
- ((CHANNEL) == ADC_CHANNEL_VBAT) )
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_10) || \
- ((CHANNEL) == ADC_REGULAR_RANK_11) || \
- ((CHANNEL) == ADC_REGULAR_RANK_12) || \
- ((CHANNEL) == ADC_REGULAR_RANK_13) || \
- ((CHANNEL) == ADC_REGULAR_RANK_14) || \
- ((CHANNEL) == ADC_REGULAR_RANK_15) || \
- ((CHANNEL) == ADC_REGULAR_RANK_16) )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
-
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
-
-#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
- ((CHANNEL) == ADC_INJECTED_RANK_2) || \
- ((CHANNEL) == ADC_INJECTED_RANK_3) || \
- ((CHANNEL) == ADC_INJECTED_RANK_4) )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
- ((CONVERSION) == ADC_INJECTED_GROUP) || \
- ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
-
-#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
-
-/** @defgroup ADCEx_range_verification ADC Extended Range Verification
- * For a unique ADC resolution: 12 bits
- * @{
- */
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))
-/**
- * @}
- */
-
-/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
- * @{
- */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
- * @{
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
- * @{
- */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
-/**
- * @}
- */
-
-#endif /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions *********************************/
-
-/** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-
-/* ADC calibration */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
-uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
-#endif /* STM32F373xC || STM32F378xx */
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* ADC multimode */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/* ADC group regular stop conversion without impacting group injected */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc);
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc);
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc);
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* ADC multimode */
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F3xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
deleted file mode 100644
index bcc92b9d7d5..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
+++ /dev/null
@@ -1,819 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_can.h
- * @author MCD Application Team
- * @brief Header file of CAN HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_CAN_H
-#define __STM32F3xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
- * @{
- */
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
-
-}HAL_CAN_StateTypeDef;
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE. */
-}CAN_InitTypeDef;
-
-/**
- * @brief CAN filter configuration structure definition
- */
-typedef struct
-{
- uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-
- uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint32_t FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t BankNumber; /*!< Select the start slave bank filter
- F3 devices don't support CAN2 interface (Slave). Therefore this parameter
- is meaningless but it has been kept for compatibility accross STM32 families */
-
-}CAN_FilterConfTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
-}CanTxMsgTypeDef;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
- * @brief CAN handle Structure definition
- */
-typedef struct
-{
- CAN_TypeDef *Instance; /*!< Register base address */
-
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
-
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
-
- HAL_LockTypeDef Lock; /*!< CAN locking object */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
- __IO uint32_t ErrorCode; /*!< CAN Error code
- This parameter can be a value of @ref CAN_Error_Code */
-
-}CAN_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
- * @{
- */
-
-/** @defgroup CAN_Error_Code CAN Error Code
- * @{
- */
-#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
-#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
-#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
-#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
-#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
-/**
- * @}
- */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
- * @{
- */
-#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
- * @{
- */
-#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
-#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
-#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
-#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-/**
- * @}
- */
-
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
- * @{
- */
-#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
-#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
-#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
- * @{
- */
-#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
-#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
-#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
-#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
-#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
-#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
-#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
-#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
-#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
-#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
-#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
-#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
-#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
-#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
-#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
- * @{
- */
-#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
-#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
-#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
-#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
-#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
-#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
-#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
- * @{
- */
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
- * @{
- */
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
- * @{
- */
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type CAN Identifier Type
- * @{
- */
-#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
-#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
- * @{
- */
-#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
-#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags CAN Flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
-#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
-#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
-#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
-#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
-#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
-
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts CAN Interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Mailboxes CAN Mailboxes
-* @{
-*/
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
- * @{
- */
-
-/** @brief Reset CAN handle state
- * @param __HANDLE__ CAN handle.
- * @retval None
- */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
- * @brief Enable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle.
- * @param __INTERRUPT__ CAN Interrupt
- * @retval None
- */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle.
- * @param __INTERRUPT__ CAN Interrupt
- * @retval None
- */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__ CAN handle.
- * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
- */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
-
-/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __INTERRUPT__ specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
- * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__ CAN handle.
- * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
-
- /**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__ CAN handle.
- * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
- * @retval None
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disables the DBG Freeze for CAN.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __NEWSTATE__ new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions CAN Exported Functions
- * @{
- */
-
-/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK (0x000000FFU)
-/**
- * @}
- */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
-#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
-
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F302x8 || */
- /* STM32F373xC || STM32F378xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h
deleted file mode 100644
index 0d394813cd6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h
+++ /dev/null
@@ -1,749 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_cec.h
- * @author MCD Application Team
- * @brief Header file of CEC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CEC_H
-#define __STM32F3xx_HAL_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CEC_Exported_Types CEC Exported Types
- * @{
- */
-
-/**
- * @brief CEC Init Structure definition
- */
-typedef struct
-{
- uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
- It can be one of @ref CEC_Signal_Free_Time
- and belongs to the set {0U,...,7} where
- 0x0 is the default configuration
- else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
-
- uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
- or CEC_EXTENDED_TOLERANCE */
-
- uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
- CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
- CEC_RX_STOP_ON_BRE: reception is stopped. */
-
- uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
- CEC line upon Bit Rising Error detection.
- CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
- CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
-
- uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
- CEC line upon Long Bit Period Error detection.
- CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
- CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
-
- uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
- upon an error detected on a broadcast message.
-
- It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
-
- 1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
- and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
- b) LBPE detection: error-bit generation on the CEC line
- if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
-
- 2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
- no error-bit generation in case neither a) nor b) are satisfied. Additionally,
- there is no error-bit generation in case of Short Bit Period Error detection in
- a broadcast message while LSTN bit is set. */
-
- uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
- CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
-
- uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
-
- CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
- own address (OAR). Messages addressed to different destination are ignored.
- Broadcast messages are always received.
-
- CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
- address (OAR) with positive acknowledge. Messages addressed to different destination
- are received, but without interfering with the CEC bus: no acknowledge sent. */
-
- uint16_t OwnAddress; /*!< Own addresses configuration
- This parameter can be a value of @ref CEC_OWN_ADDRESS */
-
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
-
-
-}CEC_InitTypeDef;
-
-/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
- * - gState contains CEC state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6 Error information
- * 0 : No Error
- * 1 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL CEC Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
- Value is allowed for gState only */
-HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
-
-/**
- * @brief CEC handle Structure definition
- */
-typedef struct
-{
- CEC_TypeDef *Instance; /*!< CEC registers base address */
-
- CEC_InitTypeDef Init; /*!< CEC communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
-
- uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
-
- uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
-}CEC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CEC_Exported_Constants CEC Exported Constants
- * @{
- */
-
-/** @defgroup CEC_Error_Code CEC Error Code
- * @{
- */
-#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
-#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
-#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
-#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
-#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
-#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
-#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
-#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
-#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
-#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
-/**
- * @}
- */
-
-/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
- * @{
- */
-#define CEC_DEFAULT_SFT (0x00000000U)
-#define CEC_0_5_BITPERIOD_SFT (0x00000001U)
-#define CEC_1_5_BITPERIOD_SFT (0x00000002U)
-#define CEC_2_5_BITPERIOD_SFT (0x00000003U)
-#define CEC_3_5_BITPERIOD_SFT (0x00000004U)
-#define CEC_4_5_BITPERIOD_SFT (0x00000005U)
-#define CEC_5_5_BITPERIOD_SFT (0x00000006U)
-#define CEC_6_5_BITPERIOD_SFT (0x00000007U)
-/**
- * @}
- */
-
-/** @defgroup CEC_Tolerance CEC Receiver Tolerance
- * @{
- */
-#define CEC_STANDARD_TOLERANCE (0x00000000U)
-#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
-/**
- * @}
- */
-
-/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
- * @{
- */
-#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
-#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
-/**
- * @}
- */
-
-/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
- * @{
- */
-#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
-#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
- * @{
- */
-#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
-#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
- * @{
- */
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
-#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
-/**
- * @}
- */
-
-/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
- * @{
- */
-#define CEC_SFT_START_ON_TXSOM (0x00000000U)
-#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
-/**
- * @}
- */
-
-/** @defgroup CEC_Listening_Mode CEC Listening mode option
- * @{
- */
-#define CEC_REDUCED_LISTENING_MODE (0x00000000U)
-#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
-/**
- * @}
- */
-
-/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
- * @{
- */
-#define CEC_CFGR_OAR_LSB_POS (16U)
-/**
- * @}
- */
-
-/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
- * @{
- */
-#define CEC_INITIATOR_LSB_POS (4U)
-/**
- * @}
- */
-
-/** @defgroup CEC_OWN_ADDRESS CEC Own Address
- * @{
- */
-#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
-#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
-#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
-#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
-#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
-#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
-#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
-#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
-#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
-#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
-#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
-#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
-#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
-#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
-#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE
-#define CEC_IT_TXERR CEC_IER_TXERRIE
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE
-#define CEC_IT_TXEND CEC_IER_TXENDIE
-#define CEC_IT_TXBR CEC_IER_TXBRIE
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE
-#define CEC_IT_LBPE CEC_IER_LBPEIE
-#define CEC_IT_SBPE CEC_IER_SBPEIE
-#define CEC_IT_BRE CEC_IER_BREIE
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE
-#define CEC_IT_RXEND CEC_IER_RXENDIE
-#define CEC_IT_RXBR CEC_IER_RXBRIE
-/**
- * @}
- */
-
-/** @defgroup CEC_Flags_Definitions CEC Flags definition
- * @{
- */
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND CEC_ISR_TXEND
-#define CEC_FLAG_TXBR CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE CEC_ISR_LBPE
-#define CEC_FLAG_SBPE CEC_ISR_SBPE
-#define CEC_FLAG_BRE CEC_ISR_BRE
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND CEC_ISR_RXEND
-#define CEC_FLAG_RXBR CEC_ISR_RXBR
-/**
- * @}
- */
-
-/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
- * @{
- */
-#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
-/**
- * @}
- */
-
-/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
- * @{
- */
-#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
-/**
- * @}
- */
-
-/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
- * @{
- */
-#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CEC_Exported_Macros CEC Exported Macros
- * @{
- */
-
-/** @brief Reset CEC handle gstate & RxState
- * @param __HANDLE__ CEC handle.
- * @retval None
- */
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
- } while(0U)
-
-/** @brief Checks whether or not the specified CEC interrupt flag is set.
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __FLAG__ specifies the flag to check.
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval ITStatus
- */
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-
-/** @brief Clears the interrupt or status flag when raised (write at 1U)
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __FLAG__ specifies the interrupt/status flag to clear.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval none
- */
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
-
-/** @brief Enables the specified CEC interrupt.
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __INTERRUPT__ specifies the CEC interrupt to enable.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval none
- */
-#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/** @brief Disables the specified CEC interrupt.
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __INTERRUPT__ specifies the CEC interrupt to disable.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval none
- */
-#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-
-/** @brief Checks whether or not the specified CEC interrupt is enabled.
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __INTERRUPT__ specifies the CEC interrupt to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
-
-/** @brief Enables the CEC device
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
-
-/** @brief Disables the CEC device
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
-
-/** @brief Set Transmission Start flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
-
-/** @brief Set Transmission End flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
- */
-#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
-
-/** @brief Get Transmission Start flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
-
-/** @brief Get Transmission End flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
-
-/** @brief Clear OAR register
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
-
-/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
- * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
- * @retval none
- */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions
- * @{
- */
-
-/** @addtogroup CEC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
-void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @addtogroup CEC_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
-void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
-void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @addtogroup CEC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CEC_Private_Types CEC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Variables CEC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Macros CEC Private Macros
- * @{
- */
-
-#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
-
-#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
- ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
-
-#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
- ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
-
-#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
-
-#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
-
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
-
-#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
- ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
-
-#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
- ((__MODE__) == CEC_FULL_LISTENING_MODE))
-
-/** @brief Check CEC message size.
- * The message size is the payload size: without counting the header,
- * it varies from 0 byte (ping operation, one header only, no payload) to
- * 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__ CEC message size.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
-
-/** @brief Check CEC device Own Address Register (OAR) setting.
- * OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__ CEC own address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
-
-/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__ CEC initiator or logical address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h
deleted file mode 100644
index 0510e0f047b..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_comp.h
- * @author MCD Application Team
- * @brief Header file of COMP HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_COMP_H
-#define __STM32F3xx_HAL_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup COMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup COMP_Exported_Types COMP Exported Types
- * @{
- */
-/**
- * @brief COMP Init structure definition
- */
-typedef struct
-{
-
- uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
- This parameter can be a value of @ref COMPEx_InvertingInput */
-
- uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
- This parameter can be a value of @ref COMPEx_NonInvertingInput
- Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
-
- uint32_t Output; /*!< Selects the output redirection of the comparator.
- This parameter can be a value of @ref COMPEx_Output */
-
- uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
- This parameter can be a value of @ref COMP_OutputPolarity */
-
- uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
- This parameter can be a value of @ref COMPEx_Hysteresis
- Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
-
- uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
- This parameter can be a value of @ref COMPEx_BlankingSrce
- Note: Not available on STM32F373xB/C and STM32F378xx devices */
-
- uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
- to adjust the speed/consumption.
- This parameter can be a value of @ref COMPEx_Mode
- Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
-
- uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
- This parameter can be a value of @ref COMPEx_WindowMode */
-
- uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
- This parameter can be a value of @ref COMP_TriggerMode */
-
-}COMP_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */
- HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
- HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */
- HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
- HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
-}HAL_COMP_StateTypeDef;
-
-/**
- * @brief COMP Handle Structure definition
- */
-typedef struct
-{
- COMP_TypeDef *Instance; /*!< Register base address */
- COMP_InitTypeDef Init; /*!< COMP required parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
-}COMP_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
- * @{
- */
-
-/** @defgroup COMP_OutputPolarity COMP Output Polarity
- * @{
- */
-#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
-#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputLevel COMP Output Level
- * @{
- */
-/* When output polarity is not inverted, comparator output is low when
- the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
-/* When output polarity is not inverted, comparator output is high when
- the non-inverting input is at a higher voltage than the inverting input */
-#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
-/**
- * @}
- */
-
-/** @defgroup COMP_TriggerMode COMP Trigger Mode
- * @{
- */
-#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup COMP_State_Lock COMP State Lock
- * @{
- */
-#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup COMP_Exported_Macros COMP Exported Macros
- * @{
- */
-
-/** @brief Reset COMP handle state.
- * @param __HANDLE__ COMP handle.
- * @retval None
- */
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-/**
- * @}
- */
-
-/* Include COMP HAL Extended module */
-#include "stm32f3xx_hal_comp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
- * @{
- */
-/** @addtogroup COMP_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-/* Callback in Interrupt mode */
-void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/* Peripheral State functions **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
- * @{
- */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMP_Private_Macros COMP Private Macros
- * @{
- */
-
-/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
- * @{
- */
-
-#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
- ((__POL__) == COMP_OUTPUTPOL_INVERTED))
-
-#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
- ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h
deleted file mode 100644
index 039bce25003..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h
+++ /dev/null
@@ -1,2795 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_comp_ex.h
- * @author MCD Application Team
- * @brief Header file of COMP HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_COMP_EX_H
-#define __STM32F3xx_HAL_COMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup COMPEx COMPEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Constants COMP Extended Exported Constants
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices)
- * @{
- */
-#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
- PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
- PC0 for COMP7) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
- PB15 for COMP6) connected to comparator inverting input */
-/* Aliases for compatibility */
-#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
-/**
- * @}
- */
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
- * @{
- */
-#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6)
- connected to comparator inverting input */
-/* Aliases for compatibility */
-#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
-/**
- * @}
- */
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
- * @{
- */
-/* Note: On these STM32 devices, there is only 1 comparator inverting input */
-/* connected to a GPIO. */
-/* It must be chosen among the 2 literals COMP_INVERTINGINPUT_IOx */
-/* depending on comparator instance COMPx. */
-#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2),
- connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< IO2 (PB2 for COMP4, PB15 for COMP6)
- connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC2_CH1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_CH1_OUT connected to comparator inverting input */
-
-/* Aliases for compatibility */
-#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
-/**
- * @}
- */
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
- * @{
- */
-#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1U/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3U/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2) /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1)) /*!< IO1 (PA0 for COMP1, PA2 for COMP2) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL) /*!< DAC2_CH1_OUT connected to comparator inverting input */
-
-/* Aliases for compatibility */
-#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
- * @{
- */
-#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
- PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
- PA0 for COMP7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
- PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
-/**
- * @}
- */
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
- * @{
- */
-#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
- connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */
-/**
- * @}
- */
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
- * @{
- */
-#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
- connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
-/**
- * @}
- */
-#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
- * @{
- */
-#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
- PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
- PA0 for COMP7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
-/**
- * @}
- */
-#else
-/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
- * @{
- */
-#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
- connected to comparator non inverting input */
-/**
- * @}
- */
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
- * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
- * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
- * - XXXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
-#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
-#define COMP_OUTPUT_TIM1BKIN2 (0x0000142AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
-/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
-#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
-/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
-#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
-/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
-/**
- * @}
- */
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
- * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
- * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
- * - XXXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
-#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
-/* Output Redirection common to COMP2 and COMP4 */
-#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0AU) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
-/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
-#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC1 (0x00002802U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
-/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
-#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
-#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
-/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
-/**
- * @}
- */
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F302xC/STM32F302xE Product devices)
- * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
- * - YYYYYY : Applicable comparator instance number (bitmap format: 000001 for COMP1, 100000 for COMP6)
- * - XXXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */
-#define COMP_OUTPUT_NONE (0x0000002BU) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN (0x0000042BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
-#define COMP_OUTPUT_TIM1BKIN2 (0x0000142BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
-/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR (0x00001803U) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
-#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x00002403U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
-/* Output Redirection common to COMP1,COMP2 and COMP4 */
-#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0BU) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
-/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
-#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
-#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
-#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
-/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
-#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
-/**
- * @}
- */
-#elif defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xC/STM32F358xx Product devices)
- * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
- * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
- * - XXXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP1...COMP7 */
-#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
-/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
-/* Output Redirection common to COMP1, COMP2 and COMP3 */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
-/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
-#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
-/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
-/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
-#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
-/* Output Redirection specific to COMP3 */
-#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
-#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
-#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
-#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
-/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
-#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
-#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
-#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
-/* Output Redirection specific to COMP5 */
-#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
-#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
-#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
-#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
-/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
-#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
-/* Output Redirection specific to COMP7 */
-#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
-#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
-#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
-#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
-/**
- * @}
- */
-#elif defined(STM32F303xE) || defined(STM32F398xx)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xE/STM32F398xx Product devices)
- * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
- * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
- * - XXXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP1...COMP7 */
-#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
-#define COMP_OUTPUT_TIM20BKIN (0x0000307FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM20BKIN2 (0x0000347FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 (0x0000387FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2U, TIM8 Break Input 2 and TIM20 Break Input 2 */
-/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
-/* Output Redirection common to COMP1, COMP2 and COMP3 */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
-/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
-#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
-/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
-/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
-#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
-/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM20OCREFCLR (0x00003C04U) /*!< COMP2 output connected to TIM20 OCREF Clear */
-/* Output Redirection specific to COMP3 */
-#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
-#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
-#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
-#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
-/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
-#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
-#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
-#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
-/* Output Redirection specific to COMP5 */
-#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
-#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
-#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
-#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
-/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
-#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
-/* Output Redirection specific to COMP7 */
-#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
-#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
-#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
-#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
-/**
- * @}
- */
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup COMPEx_Output COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
- * Elements value convention: 00000XXX000000YYb
- * - YY : Applicable comparator instance number (bitmap format: 01 for COMP1, 10 for COMP2)
- * - XXX : COMPxOUTSEL value
- * @{
- */
-/* Output Redirection values common to all comparators COMP1 and COMP2 */
-#define COMP_OUTPUT_NONE (0x0003U) /*!< COMP1 or COMP2 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM2IC4 (0x0403U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
-#define COMP_OUTPUT_TIM2OCREFCLR (0x0503U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
-/* Output Redirection specific to COMP1 */
-#define COMP_OUTPUT_TIM15BKIN (0x0101U) /*!< COMP1 output connected to TIM15 Break Input */
-#define COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U) /*!< COMP1 output connected to TIM3 Input Capture 1U */
-#define COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U) /*!< COMP1 output connected to TIM3 OCREF Clear */
-#define COMP_OUTPUT_TIM5IC4 (0x0601U) /*!< COMP1 output connected to TIM5 Input Capture 4U */
-#define COMP_OUTPUT_TIM5OCREFCLR (0x0701U) /*!< COMP1 output connected to TIM5 OCREF Clear */
-/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM16BKIN (0x0102U) /*!< COMP2 output connected to TIM16 Break Input */
-#define COMP_OUTPUT_TIM4IC1 (0x0202U) /*!< COMP2 output connected to TIM4 Input Capture 1U */
-#define COMP_OUTPUT_TIM4OCREFCLR (0x0302U) /*!< COMP2 output connected to TIM4 OCREF Clear */
-#define COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
-#define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U) /*!< COMP2 output connected to TIM3 OCREF Clear */
-/**
- * @}
- */
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
- * @{
- */
-#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
- is connected to the non inverting input of comparator X-1U */
-/**
- * @}
- */
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
- * @{
- */
-#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2
- is connected to the non inverting input of comparator 1 (PA1) */
-/**
- * @}
- */
-#else
-/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices)
- * @{
- */
-#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled (not available) */
-/**
- * @}
- */
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-/** @defgroup COMPEx_Mode COMP Extended Mode
- * @{
- */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Please refer to the electrical characteristics in the device datasheet for
- the power consumption values */
-#define COMP_MODE_HIGHSPEED (0x00000000U) /*!< High Speed */
-#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
-#define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1 /*!< Low power mode */
-#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-/** @defgroup COMPEx_Hysteresis COMP Extended Hysteresis
- * @{
- */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
-#define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
-#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
-#define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST /*!< Hysteresis level high */
-
-#else
-
-#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F301x8/STM32F302x8/STM32F303x8/STM32F334x8/STM32F318xx/STM32F328xx Product devices)
- * @{
- */
-/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
-/* Blanking source for COMP2 */
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP2 */
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP2 */
-#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP2 */
-/* Blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
-/* Blanking source for COMP6 */
-#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
-#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
-/**
- * @}
- */
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xE) ||\
- defined(STM32F302xC)
-/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F302xE/STM32F302xC Product devices)
- * @{
- */
-/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
-/* Blanking source common for COMP1 and COMP2 */
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */
-/* Blanking source common for COMP1 and COMP2 */
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP1 and COMP2 */
-/* Blanking source common for COMP1 and COMP2 */
-#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP1 and COMP2 */
-/* Blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
-/* Blanking source for COMP6 */
-#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
-#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
-/**
- * @}
- */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F303xE/STM32F398xx/STM32F303xC/STM32F358xx Product devices)
- * @{
- */
-/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
-/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */
-/* Blanking source common for COMP1 and COMP2 */
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for COMP1 and COMP2 */
-/* Blanking source common for COMP1, COMP2 and COMP5 */
-#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC3 selected as blanking source for COMP1, COMP2 and COMP5 */
-/* Blanking source common for COMP3 and COMP6 */
-#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP3 and COMP6 */
-/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for COMP4, COMP5, COMP6 and COMP7 */
-/* Blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
-#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
-/* Blanking source common for COMP6 and COMP7 */
-#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 and COMP7 */
-/**
- * @}
- */
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
- * @{
- */
-/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
-/**
- * @}
- */
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/** @defgroup COMP_Flag COMP Flag
- * @{
- */
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK /*!< Lock flag */
-#else
-#define COMP_FLAG_LOCK COMP_CSR_LOCK /*!< Lock flag */
-#endif /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Macros COMP Extended Exported Macros
- * @{
- */
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/**
- * @brief Enable the specified comparator.
- * @param __HANDLE__ COMP handle.
- * @retval None
- */
-#define __HAL_COMP_ENABLE(__HANDLE__) \
- do { \
- uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
- \
- if((__HANDLE__)->Instance == COMP2) \
- { \
- regshift = COMP_CSR_COMP2_SHIFT; \
- } \
- SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
- } while(0U)
-
-/**
- * @brief Disable the specified comparator.
- * @param __HANDLE__ COMP handle.
- * @retval None
- */
-#define __HAL_COMP_DISABLE(__HANDLE__) \
- do { \
- uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
- \
- if((__HANDLE__)->Instance == COMP2) \
- { \
- regshift = COMP_CSR_COMP2_SHIFT; \
- } \
- CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
- } while(0U)
-
-/**
- * @brief Lock a comparator instance
- * @param __HANDLE__ COMP handle
- * @retval None.
- */
-#define __HAL_COMP_LOCK(__HANDLE__) \
- do { \
- uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
- \
- if((__HANDLE__)->Instance == COMP2) \
- { \
- regshift = COMP_CSR_COMP2_SHIFT; \
- } \
- SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); \
- } while(0U)
-
-/** @brief Check whether the specified COMP flag is set or not.
- * @param __HANDLE__ COMP Handle.
- * @param __FLAG__ flag to check.
- * This parameter can be one of the following values:
- * @arg @ref COMP_FLAG_LOCK lock flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \
- (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \
- (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__))))
-
-#else
-
-/**
- * @brief Enable the specified comparator.
- * @param __HANDLE__ COMP handle.
- * @retval None
- */
-#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
-
-/**
- * @brief Disable the specified comparator.
- * @param __HANDLE__ COMP handle.
- * @retval None
- */
-#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
-
-/**
- * @brief Lock a comparator instance
- * @param __HANDLE__ COMP handle
- * @retval None.
- */
-#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
-
-/** @brief Check whether the specified COMP flag is set or not.
- * @param __HANDLE__ COMP Handle.
- * @param __FLAG__ flag to check.
- * This parameter can be one of the following values:
- * @arg @ref COMP_FLAG_LOCK lock flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/**
- * @brief Enable the COMP1 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP1 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Generate a software interrupt on the COMP1 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Enable the COMP1 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Disable the COMP1 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Check whether the COMP1 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
-
-/**
- * @brief Clear the COMP1 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F373xC || STM32F378xx */
-
-/**
- * @brief Enable the COMP2 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP2 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Generate a software interrupt on the COMP2 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Enable the COMP2 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Disable the COMP2 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Check whether the COMP2 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
-
-/**
- * @brief Clear the COMP2 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-/**
- * @brief Enable the COMP3 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Disable the COMP3 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Enable the COMP3 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Disable the COMP3 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Enable the COMP3 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP3 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP3 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Disable the COMP3 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Generate a software interrupt on the COMP3 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Enable the COMP3 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Disable the COMP3 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Check whether the COMP3 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP3_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP3)
-
-/**
- * @brief Clear the COMP3 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP3)
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-/**
- * @brief Enable the COMP4 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Disable the COMP4 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Enable the COMP4 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Disable the COMP4 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Enable the COMP4 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP4 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP4 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Disable the COMP4 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Generate a software interrupt on the COMP4 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Enable the COMP4 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Disable the COMP4 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Check whether the COMP4 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP4_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP4)
-
-/**
- * @brief Clear the COMP4 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP4)
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-/**
- * @brief Enable the COMP5 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Disable the COMP5 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Enable the COMP5 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Disable the COMP5 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Enable the COMP5 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP5 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP5 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Disable the COMP5 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Generate a software interrupt on the COMP5 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Enable the COMP5 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Disable the COMP5 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Check whether the COMP5 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP5_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP5)
-
-/**
- * @brief Clear the COMP5 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP5)
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-/**
- * @brief Enable the COMP6 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Disable the COMP6 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Enable the COMP6 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Disable the COMP6 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Enable the COMP6 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP6 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP6 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Disable the COMP6 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Generate a software interrupt on the COMP6 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Enable the COMP6 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Disable the COMP6 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Check whether the COMP6 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP6_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP6)
-
-/**
- * @brief Clear the COMP6 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP6)
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/**
- * @brief Enable the COMP7 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Disable the COMP7 EXTI line rising edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Enable the COMP7 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Disable the COMP7 EXTI line falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Enable the COMP7 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the COMP7 EXTI line rising & falling edge trigger.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Enable the COMP7 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Disable the COMP7 EXTI line in interrupt mode.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Generate a software interrupt on the COMP7 EXTI line.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Enable the COMP7 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Disable the COMP7 EXTI line in event mode.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Check whether the COMP7 EXTI line flag is set or not.
- * @retval RESET or SET
- */
-#define __HAL_COMP_COMP7_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP7)
-
-/**
- * @brief Clear the COMP7 EXTI flag.
- * @retval None
- */
-#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP7)
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMPEx_Private_Constants COMP Extended Private Constants
- * @{
- */
-/** @defgroup COMPEx_ExtiLineEvent COMP Extended EXTI lines
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
-#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
-#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
-
-#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-
-#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
-#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
-#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
-
-#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
-#define COMP_EXTI_LINE_COMP3 EXTI_IMR_MR29 /*!< External interrupt line 29 connected to COMP3 */
-#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
-#define COMP_EXTI_LINE_COMP5 EXTI_IMR_MR31 /*!< External interrupt line 31 connected to COMP5 */
-#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
-#define COMP_EXTI_LINE_COMP7 EXTI_IMR2_MR33 /*!< External interrupt line 33 connected to COMP7 */
-
-#define COMP_EXTI_LINE_REG2_MASK (EXTI_IMR2_MR33 | EXTI_IMR2_MR32) /*!< Mask for External interrupt line control in register xxx2 */
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/** @defgroup COMPEx_Misc COMP Extended miscellaneous defines
- * @{
- */
-
-/* CSR masks redefinition for internal use */
-#define COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL /*!< COMP_CSR_COMPxINSEL Mask */
-#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL /*!< COMP_CSR_COMPxOUTSEL Mask */
-#define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/* CSR register reset value */
-#define COMP_CSR_RESET_VALUE (0x00000000U)
-#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
-#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
-/* CSR COMP1/COMP2 shift */
-#define COMP_CSR_COMP1_SHIFT 0U
-#define COMP_CSR_COMP2_SHIFT 16U
-#else
-/* CSR register reset value */
-#define COMP_CSR_RESET_VALUE (0x00000000U)
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define COMP_CSR_COMPxNONINSEL_MASK (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define COMP_CSR_COMPxNONINSEL_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMPxNONINSEL | COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
-#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
-#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
-#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define COMP_CSR_COMPxNONINSEL_MASK (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
-#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
-#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
-#define COMP_CSR_COMPxBLANKING_MASK (0x00000000U) /*!< Mask empty: feature not available */
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMPEx_Private_Macros COMP Extended Private Macros
- * @{
- */
-/** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/**
- * @brief Get the specified EXTI line for a comparator instance
- * @param __INSTANCE__ specifies the COMP instance.
- * @retval value of @ref COMPEx_ExtiLineEvent
- */
-#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
- ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
- COMP_EXTI_LINE_COMP6)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-/**
- * @brief Get the specified EXTI line for a comparator instance
- * @param __INSTANCE__ specifies the COMP instance.
- * @retval value of @ref COMPEx_ExtiLineEvent
- */
-#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
- ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
- ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
- COMP_EXTI_LINE_COMP6)
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-/**
- * @brief Get the specified EXTI line for a comparator instance
- * @param __INSTANCE__ specifies the COMP instance.
- * @retval value of @ref COMPEx_ExtiLineEvent
- */
-#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
- ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
- ((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 : \
- ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
- ((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 : \
- ((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 : \
- COMP_EXTI_LINE_COMP7)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Get the specified EXTI line for a comparator instance
- * @param __INSTANCE__ specifies the COMP instance.
- * @retval value of @ref COMPEx_ExtiLineEvent
- */
-#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
- COMP_EXTI_LINE_COMP2)
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/** @defgroup COMPEx_Private_Macros_Misc COMP Extended miscellaneous private macros
- * @{
- */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Init a comparator instance
- * @param __HANDLE__ COMP handle
- * @note The common output selection is checked versus the COMP instance to set the right output configuration
- * @retval None.
- */
-
-#define COMP_INIT(__HANDLE__) \
- do { \
- uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
- uint32_t compoutput = (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK; \
- \
- if((__HANDLE__)->Instance == COMP2) \
- { \
- regshift = COMP_CSR_COMP2_SHIFT; \
- } \
- \
- MODIFY_REG(COMP->CSR, \
- (COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
- COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
- COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift, \
- ((__HANDLE__)->Init.InvertingInput | \
- (__HANDLE__)->Init.NonInvertingInput | \
- compoutput | \
- (__HANDLE__)->Init.OutputPol | \
- (__HANDLE__)->Init.Hysteresis | \
- (__HANDLE__)->Init.Mode) << regshift); \
- \
- if((__HANDLE__)->Init.WindowMode != COMP_WINDOWMODE_DISABLE) \
- { \
- COMP->CSR |= COMP_CSR_WNDWEN; \
- } \
- } while(0U)
-
-/**
- * @brief DeInit a comparator instance
- * @param __HANDLE__ COMP handle
- * @retval None.
- */
-#define COMP_DEINIT(__HANDLE__) \
- do { \
- uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
- \
- if((__HANDLE__)->Instance == COMP2) \
- { \
- regshift = COMP_CSR_COMP2_SHIFT; \
- } \
- MODIFY_REG(COMP->CSR, \
- COMP_CSR_RESET_PARAMETERS_MASK << regshift, \
- COMP_CSR_RESET_VALUE << regshift); \
- } while(0U)
-
-
-/**
- * @brief Enable the Exti Line rising edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__))
-
-/**
- * @brief Disable the Exti Line rising edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
-
-/**
- * @brief Enable the Exti Line falling edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__))
-
-/**
- * @brief Disable the Exti Line falling edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
-
-/**
- * @brief Enable the COMP Exti Line interrupt generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__))
-
-/**
- * @brief Disable the COMP Exti Line interrupt generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
-
-/**
- * @brief Enable the COMP Exti Line event generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__))
-
-/**
- * @brief Disable the COMP Exti Line event generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
-
-/**
- * @brief Check whether the specified EXTI line flag is set or not.
- * @param __FLAG__ specifies the COMP Exti sources to be checked.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval The state of __FLAG__ (SET or RESET).
- */
-#define COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__))
-
-/**
- * @brief Clear the COMP Exti flags.
- * @param __FLAG__ specifies the COMP Exti sources to be cleared.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__))
-
-#else /* STM32F30x, STM32F32xx, STM32F35x, STM32F39x, STM32F33x */
-
-
-/**
- * @brief Init a comparator instance
- * @param __HANDLE__ COMP handle
- * @retval None.
- */
-#define COMP_INIT(__HANDLE__) \
- do { \
- __IO uint32_t csrreg = 0U; \
- \
- csrreg = READ_REG((__HANDLE__)->Instance->CSR); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxNONINSEL_MASK, (__HANDLE__)->Init.NonInvertingInput); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxBLANKING_MASK, (__HANDLE__)->Init.BlankingSrce); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxOUTSEL_MASK, (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxPOL_MASK, (__HANDLE__)->Init.OutputPol); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxHYST_MASK, (__HANDLE__)->Init.Hysteresis); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode); \
- MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode); \
- WRITE_REG((__HANDLE__)->Instance->CSR, csrreg); \
- } while(0U)
-
-/**
- * @brief DeInit a comparator instance
- * @param __HANDLE__ COMP handle
- * @retval None.
- */
-#define COMP_DEINIT(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->CSR, COMP_CSR_RESET_VALUE)
-
-/**
- * @brief Enable the Exti Line rising edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->RTSR2, (__EXTILINE__)) : SET_BIT(EXTI->RTSR, (__EXTILINE__)))
-
-/**
- * @brief Disable the Exti Line rising edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->RTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)))
-
-/**
- * @brief Enable the Exti Line falling edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->FTSR2, (__EXTILINE__)) : SET_BIT(EXTI->FTSR, (__EXTILINE__)))
-
-/**
- * @brief Disable the Exti Line falling edge trigger.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->FTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)))
-
-/**
- * @brief Enable the COMP Exti Line interrupt generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_ENABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->IMR2, (__EXTILINE__)) : SET_BIT(EXTI->IMR, (__EXTILINE__)))
-
-/**
- * @brief Disable the COMP Exti Line interrupt generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_DISABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->IMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->IMR, (__EXTILINE__)))
-
-/**
- * @brief Enable the COMP Exti Line event generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->EMR2, (__EXTILINE__)) : SET_BIT(EXTI->EMR, (__EXTILINE__)))
-
-/**
- * @brief Disable the COMP Exti Line event generation.
- * @param __EXTILINE__ specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->EMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->EMR, (__EXTILINE__)))
-
-/**
- * @brief Check whether the specified EXTI line flag is set or not.
- * @param __FLAG__ specifies the COMP Exti sources to be checked.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval The state of __FLAG__ (SET or RESET).
- */
-#define COMP_EXTI_GET_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? READ_BIT(EXTI->PR2, (__FLAG__)) : READ_BIT(EXTI->PR, (__FLAG__)))
-
-/**
- * @brief Clear the COMP Exti flags.
- * @param __FLAG__ specifies the COMP Exti sources to be cleared.
- * This parameter can be a value of @ref COMPEx_ExtiLineEvent
- * @retval None.
- */
-#define COMP_EXTI_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? WRITE_REG(EXTI->PR2, (__FLAG__)) : WRITE_REG(EXTI->PR, (__FLAG__)))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-
-/**
- * @brief Manage inverting input comparator inverting input connected to a GPIO
- * for STM32F302x, STM32F32xx, STM32F33x.
- * - On devices STM32F302x, STM32F32xx, STM32F33x, there is
- * only 1 comparator inverting input connected to a GPIO.
- * Legacy definition of literal COMP_INVERTINGINPUT_IO1
- * was initially the only selection, but depending on
- * comparator instance it corresponds to COMP_INVERTINGINPUT_IO2
- * (for instances COMP4, COMP6).
- * Since, COMP_INVERTINGINPUT_IO2 has been created and this macro
- * selects the correct literal COMP_INVERTINGINPUT_IOx in function
- * of comparator instance.
- * - On other STM32F3 devices, this macro performs no action.
- * @param __COMP_INSTANCE__ COMP instance
- * @param __INVERTINGINPUT__ COMP inverting input
- * @retval None.
- */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) \
- (((__INVERTINGINPUT__) != COMP_INVERTINGINPUT_IO1) \
- ? ( \
- (__INVERTINGINPUT__) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP2) \
- ? ( \
- (COMP_INVERTINGINPUT_IO1) \
- ) \
- : \
- ( \
- (COMP_INVERTINGINPUT_IO2) \
- ) \
- ) \
- )
-#else
-#define COMP_INVERTINGINPUT_SELECTION(__COMP_INSTANCE__, __INVERTINGINPUT__) \
- (__INVERTINGINPUT__)
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup COMPEx_IS_COMP_Definitions COMP Extended Private macros to check input parameters
- * @{
- */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1))
-
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
-
-/* STM32F301x6/x8, STM32F302x6/x8, STM32F318xx devices comparator instances non inverting source values */
-#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
- ((((INSTANCE) == COMP2) && \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
- || \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
-
-#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- ((((INSTANCE) == COMP2) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO2) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
-
-/*!< Non inverting input not available */
-#define IS_COMP_NONINVERTINGINPUT(INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
-
-#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
-
-#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- ((((INSTANCE) == COMP2) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO2))
-
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
-
-/* STM32F302xB/xC, STM32F303xB/xC, STM32F358xx devices comparator instances non inverting source values */
-#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
- ((((INSTANCE) == COMP1) && \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
- || \
- ((((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO2))))
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
- ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
- ((MODE) == COMP_MODE_MEDIUMSPEED) || \
- ((MODE) == COMP_MODE_LOWPOWER) || \
- ((MODE) == COMP_MODE_ULTRALOWPOWER))
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
-
-#if defined(STM32F302xC)
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP1) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F302xC */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP1) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP3) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP5) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
- || \
- (((INSTANCE) == COMP7) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP3) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP5) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
- || \
- (((INSTANCE) == COMP7) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F303xC || STM32F358xx */
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO2))
-
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
-
-/* STM32F302xE/STM32F303xE/STM32F398xx devices comparator instances non inverting source values */
-#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
- ((((INSTANCE) == COMP1) && \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
- || \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
-
-#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
-
-#if defined(STM32F302xE)
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP1) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F302xE */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP1) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
- || \
- (((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR))) \
- || \
- (((INSTANCE) == COMP3) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
- || \
- (((INSTANCE) == COMP5) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
- ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
- || \
- (((INSTANCE) == COMP7) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
- ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-
-/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP3) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
- || \
- (((INSTANCE) == COMP4) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
- || \
- (((INSTANCE) == COMP5) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
- || \
- (((INSTANCE) == COMP6) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
- || \
- (((INSTANCE) == COMP7) && \
- (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-
-#endif /* STM32F303xE || STM32F398xx */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
-
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
-
-/* STM32F373xB/xC, STM32F378xx devices comparator instances non inverting source values */
-#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
- ((((INSTANCE) == COMP1) && \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
- || \
- (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
- ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
- ((MODE) == COMP_MODE_MEDIUMSPEED) || \
- ((MODE) == COMP_MODE_LOWPOWER) || \
- ((MODE) == COMP_MODE_ULTRALOWPOWER))
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))
-
-#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
- ((((INSTANCE) == COMP1) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
- || \
- (((INSTANCE) == COMP2) && \
- (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))))
-
-#define IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE)) /*!< Not available: check always true */
-
-/* STM32F373xB/STM32F373xC/STM32F378xx devices comparator instances blanking source values */
-#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
- ((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
- ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_COMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h
deleted file mode 100644
index ce0b102f86a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_conf.h
- * @author MCD Application Team
- * @brief HAL configuration file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CONF_H
-#define __STM32F3xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-#define HAL_CEC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_PCCARD_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_HRTIM_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SDADC_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SMBUS_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_TSC_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
- */
-#if !defined (HSI_STARTUP_TIMEOUT)
- #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE (40000U)
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-/**
- * @brief External Low Speed oscillator (LSE) value.
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief Time out for LSE start up value in ms.
- */
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
- * - External clock not generated on EVAL 373
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
-#define INSTRUCTION_CACHE_ENABLE 0U
-#define DATA_CACHE_ENABLE 0U
-#define USE_SPI_CRC 1U
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/*#define USE_FULL_ASSERT 1U*/
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f3xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f3xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32f3xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f3xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f3xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f3xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f3xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32f3xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f3xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f3xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f3xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f3xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f3xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f3xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
- #include "stm32f3xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f3xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f3xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f3xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32f3xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f3xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f3xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f3xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SDADC_MODULE_ENABLED
- #include "stm32f3xx_hal_sdadc.h"
-#endif /* HAL_SDADC_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f3xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f3xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f3xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f3xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32f3xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f3xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f3xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(char* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
deleted file mode 100644
index b4d76ae52b8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CORTEX_H
-#define __STM32F3xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
-#define MPU_HARDFAULT_NMI (0x00000002U)
-#define MPU_PRIVILEGED_DEFAULT (0x00000004U)
-#define MPU_HFNMI_PRIVDEF (0x00000006U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01U)
-#define MPU_REGION_DISABLE ((uint8_t)0x00U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported Macros -----------------------------------------------------------*/
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
-
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
- * @{
- */
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
- * @brief CORTEX private functions
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-
-void HAL_MPU_Disable(void);
-void HAL_MPU_Enable(uint32_t MPU_Control);
-
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h
deleted file mode 100644
index f4a56c9f273..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CRC_H
-#define __STM32F3xx_HAL_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRC CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
- * @{
- */
-/**
- * @brief CRC HAL State Structure definition
- */
-typedef enum
-{
- HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
- HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
-}HAL_CRC_StateTypeDef;
-
-
-/**
- * @brief CRC Init Structure definition
- */
-typedef struct
-{
- uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
- If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1.
- In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
-
- uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
- If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
- 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
-
- uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation,
- e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
-
- uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
- Value can be either one of
- @arg CRC_POLYLENGTH_32B (32-bit CRC),
- @arg CRC_POLYLENGTH_16B (16-bit CRC),
- @arg CRC_POLYLENGTH_8B (8-bit CRC),
- @arg CRC_POLYLENGTH_7B (7-bit CRC). */
-
- uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
- is set to DEFAULT_INIT_VALUE_ENABLE. */
-
- uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
- Can be either one of the following values
- @arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion
- @arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- @arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */
-
- uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
- Can be either
- @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
- @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U */
-}CRC_InitTypeDef;
-
-
-/**
- * @brief CRC Handle Structure definition
- */
-typedef struct
-{
- CRC_TypeDef *Instance; /*!< Register base address */
-
- CRC_InitTypeDef Init; /*!< CRC configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< CRC Locking object */
-
- __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-
- uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
- Can be either
- @arg CRC_INPUTDATA_FORMAT_BYTES, input data is a stream of bytes (8-bit data)
- @arg CRC_INPUTDATA_FORMAT_HALFWORDS, input data is a stream of half-words (16-bit data)
- @arg CRC_INPUTDATA_FORMAT_WORDS, input data is a stream of words (32-bit data)
-
- Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
- must occur if InputBufferFormat is not one of the three values listed above */
-}CRC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
- * @{
- */
-/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
- * @{
- */
-#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
- * @{
- */
-#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
- * @{
- */
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
-#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7U */
-/**
- * @}
- */
-
-/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
- * @{
- */
-#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
-#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
-/**
- * @}
- */
-
-/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
- * @{
- */
-#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */
-#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
-#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */
-#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */
-/**
- * @}
- */
-
-/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
- * @{
- */
-#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */
-#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */
-#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */
-#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
- * @{
- */
-/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
- * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
- * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
- * the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U) /*!< Undefined input data format */
-#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U) /*!< Input data in byte format */
-#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U) /*!< Input data in half-word format */
-#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U) /*!< Input data in word format */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @brief Reset CRC handle state.
- * @param __HANDLE__ CRC handle.
- * @retval None
- */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
- * @brief Reset CRC Data Register.
- * @param __HANDLE__ CRC handle
- * @retval None
- */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
- * @brief Set CRC INIT non-default value
-* @param __HANDLE__ CRC handle
- * @param __INIT__ 32-bit initial value
- * @retval None
- */
-#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
-
-/**
- * @brief Store a 8-bit data in the Independent Data(ID) register.
- * @param __HANDLE__ CRC handle
- * @param __VALUE__ 8-bit value to be stored in the ID register
- * @retval None
- */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
- * @brief Return the 8-bit data stored in the Independent Data(ID) register.
- * @param __HANDLE__ CRC handle
- * @retval 8-bit value of the ID register
- */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
- * @}
- */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup CRC_Private_Macros CRC Private Macros
- * @{
- */
-
-#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
- ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
-
-#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
- ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
-
-#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
- ((LENGTH) == CRC_POLYLENGTH_16B) || \
- ((LENGTH) == CRC_POLYLENGTH_8B) || \
- ((LENGTH) == CRC_POLYLENGTH_7B))
-
-#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
- ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
- ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
-
-/**
- * @}
- */
-
-/* Include CRC HAL Extended module */
-#include "stm32f3xx_hal_crc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @addtogroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
- * @}
- */
-
-/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /** @defgroup HAL_CRC_Alias_Exported_Functions CRC aliases for Exported Functions
- * @{
- */
-/* Aliases for inter STM32 series compatibility */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h
deleted file mode 100644
index 722d1363b81..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_crc_ex.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CRC_EX_H
-#define __STM32F3xx_HAL_CRC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRCEx CRCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
- * @{
- */
-
-/** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
- * @{
- */
-#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */
-#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */
-#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
-#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */
-/**
- * @}
- */
-
-/** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
- * @{
- */
-#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */
-#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
- * @{
- */
-
-/**
- * @brief Set CRC output reversal
- * @param __HANDLE__ CRC handle
- * @retval None.
- */
-#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
-
-/**
- * @brief Unset CRC output reversal
- * @param __HANDLE__ CRC handle
- * @retval None.
- */
-#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
-
-/**
- * @brief Set CRC non-default polynomial
- * @param __HANDLE__ CRC handle
- * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
- * @retval None.
- */
-#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros
- * @{
- */
-
-#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
-
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
- ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
- * @{
- */
-
-/** @addtogroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
- * @brief Extended Initialization and Configuration functions.
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h
deleted file mode 100644
index 1267f84cf01..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_DAC_H
-#define __STM32F3xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
-
-}HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC Configuration regular Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DACEx_trigger_selection */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer
- For a given DAC channel, is this paramater applies then DAC_OutputSwitch
- does not apply */
-
- uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
- This parameter can be a value of @ref DAC_OutputSwitch
- For a given DAC channel, is this paramater applies then DAC_OutputBuffer
- does not apply */
-
-}DAC_ChannelConfTypeDef;
-
-/**
- * @brief DAC handle Structure definition
- */
-typedef struct __DAC_HandleTypeDef
-{
- DAC_TypeDef *Instance; /*!< Register base address */
-
- __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
-
- HAL_LockTypeDef Lock; /*!< DAC locking object */
-
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */
-
- __IO uint32_t ErrorCode; /*!< DAC Error code */
-
-}DAC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_Error_Code DAC Error Code
- * @{
- */
-#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
-#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer DAC output buffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
-
-/**
- * @}
- */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup DAC_output_switch DAC output switch
- * @{
- */
-#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U)
-#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
-
-/**
- * @}
- */
-
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
-/** @defgroup DAC_data_alignement DAC data alignement
- * @{
- */
-#define DAC_ALIGN_12B_R (0x00000000U)
-#define DAC_ALIGN_12B_L (0x00000004U)
-#define DAC_ALIGN_8B_R (0x00000008U)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition DAC flags definition
- * @{
- */
-#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition DAC interrupts definition
- * @{
- */
-#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @brief Reset DAC handle state
- * @param __HANDLE__ specifies the DAC handle.
- * @retval None
- */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
- * @param __HANDLE__ specifies the DAC handle.
- * @param __DAC_Channel__ specifies the DAC channel
- * @retval None
- */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel
- * @param __HANDLE__ specifies the DAC handle
- * @param __DAC_Channel__ specifies the DAC channel.
- * @retval None
- */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
-
-/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief Check whether the specified DAC interrupt source is enabled or not
- * @param __HANDLE__ DAC handle
- * @param __INTERRUPT__ DAC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected DAC's flag status
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to get.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the DAC's flag
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @addtogroup DAC_Private_Macros
- * @{
- */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
- ((STATE) == DAC_OUTPUTSWITCH_ENABLE))
-
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-
-
-
-/**
- * @}
- */
-
-
-/* Include DAC HAL Extended module */
-#include "stm32f3xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F3xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h
deleted file mode 100644
index 7c358227800..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_dac_ex.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_DAC_EX_H
-#define __STM32F3xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DACEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
- * @{
- */
-
-/** @defgroup DACEx_trigger_selection DACEx trigger selection
- * @{
- */
-
-#if defined(STM32F301x8) || defined(STM32F318xx)
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F301x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F302x8)
-
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F302x8 */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
- Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
-#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
- Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-
-#if defined(STM32F303x8) || defined(STM32F328xx)
-
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#endif /* STM32F303x8 || STM32F328xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
-#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F334x8)
-
-#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
- Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
-
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
- Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
-#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
- Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
-
-#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
- Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
-#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
-
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#endif /* STM32F334x8 */
-
-/**
- * @}
- */
-
-/** @defgroup DACEx_Channel_selection DACEx Channel selection
- * @{
- */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
-
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
-#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
-#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
-
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
- * @{
- */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_HAL_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
deleted file mode 100644
index a5b9c22c0f4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_DEF
-#define __STM32F3xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-#if defined USE_LEGACY
-#include "Legacy/stm32_hal_legacy.h"
-#endif
-#include © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_DMA_H
-#define __STM32F3xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Callback ID structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
- uint32_t ChannelIndex; /*!< DMA Channel Index */
-} DMA_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
-#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @{
- */
-#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @{
- */
-#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @{
- */
-#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @{
- */
-#define DMA_FLAG_GL1 (0x00000001U)
-#define DMA_FLAG_TC1 (0x00000002U)
-#define DMA_FLAG_HT1 (0x00000004U)
-#define DMA_FLAG_TE1 (0x00000008U)
-#define DMA_FLAG_GL2 (0x00000010U)
-#define DMA_FLAG_TC2 (0x00000020U)
-#define DMA_FLAG_HT2 (0x00000040U)
-#define DMA_FLAG_TE2 (0x00000080U)
-#define DMA_FLAG_GL3 (0x00000100U)
-#define DMA_FLAG_TC3 (0x00000200U)
-#define DMA_FLAG_HT3 (0x00000400U)
-#define DMA_FLAG_TE3 (0x00000800U)
-#define DMA_FLAG_GL4 (0x00001000U)
-#define DMA_FLAG_TC4 (0x00002000U)
-#define DMA_FLAG_HT4 (0x00004000U)
-#define DMA_FLAG_TE4 (0x00008000U)
-#define DMA_FLAG_GL5 (0x00010000U)
-#define DMA_FLAG_TC5 (0x00020000U)
-#define DMA_FLAG_HT5 (0x00040000U)
-#define DMA_FLAG_TE5 (0x00080000U)
-#define DMA_FLAG_GL6 (0x00100000U)
-#define DMA_FLAG_TC6 (0x00200000U)
-#define DMA_FLAG_HT6 (0x00400000U)
-#define DMA_FLAG_TE6 (0x00800000U)
-#define DMA_FLAG_GL7 (0x01000000U)
-#define DMA_FLAG_TC7 (0x02000000U)
-#define DMA_FLAG_HT7 (0x04000000U)
-#define DMA_FLAG_TE7 (0x08000000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state
- * @param __HANDLE__ DMA handle.
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Enable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
-
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Enables the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified DMA Channel interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval The state of DMA_IT (SET or RESET).
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
- * @param __HANDLE__ DMA handle
- *
- * @retval The number of remaining data units in the current DMA Channel transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
- * @}
- */
-
-/* Include DMA HAL Extended module */
-#include "stm32f3xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Input and Output operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @brief DMA private macros
- * @{
- */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h
deleted file mode 100644
index 409ec13652d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_DMA_EX_H
-#define __STM32F3xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
- * @{
- */
-/* Interrupt & Flag management */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- DMA_FLAG_TC5)
-
-/**
- * @brief Returns the current DMA Channel half transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- DMA_FLAG_HT5)
-
-/**
- * @brief Returns the current DMA Channel transfer error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- DMA_FLAG_TE5)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
- DMA_FLAG_GL5)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
- (DMA1->ISR & (__FLAG__)))
-
-/**
- * @brief Clears the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
- (DMA1->IFCR = (__FLAG__)))
-
-/**
- * @}
- */
-
-#else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
-/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
- * @{
- */
-
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- DMA_FLAG_TC7)
-
-/**
- * @brief Returns the current DMA Channel half transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- DMA_FLAG_HT7)
-
-/**
- * @brief Returns the current DMA Channel transfer error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- DMA_FLAG_TE7)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- DMA_FLAG_GL7)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
-
-/**
- * @brief Clears the DMA Channel pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-/**
- * @}
- */
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-
-#endif /* __STM32F3xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h
deleted file mode 100644
index 12a5e6fcd7d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of Flash HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_FLASH_H
-#define __STM32F3xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Constants
- * @{
- */
-#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Macros
- * @{
- */
-
-#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
- ((__LATENCY__) == FLASH_LATENCY_1) || \
- ((__LATENCY__) == FLASH_LATENCY_2))
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0U,
- FLASH_PROC_PAGEERASE = 1U,
- FLASH_PROC_MASSERASE = 2U,
- FLASH_PROC_PROGRAMHALFWORD = 3U,
- FLASH_PROC_PROGRAMWORD = 4U,
- FLASH_PROC_PROGRAMDOUBLEWORD = 5U
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-
- __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
-
- __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
-
- __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
-
- HAL_LockTypeDef Lock; /*!< FLASH locking object */
-
- __IO uint32_t ErrorCode; /*!< FLASH error code
- This parameter can be a value of @ref FLASH_Error_Codes */
-} FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
- * @{
- */
-
-#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
-#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
-#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
- * @{
- */
-#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_FLASH_EX_H
-#define __STM32F3xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/** @addtogroup FLASHEx_Private_Constants
- * @{
- */
-
-#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Macros
- * @{
- */
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
- ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
-
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
- ((VALUE) == OB_WRPSTATE_ENABLE))
-
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-
-#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
-#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
- ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
-#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
- || defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
- ((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
- ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
- ((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
- ((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU))))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
- || defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
- * @{
- */
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
- This parameter can be a value of @ref FLASHEx_Type_Erase */
-
- uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
- This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
-
- uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
- This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
-
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Options bytes program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
- This parameter can be a value of @ref FLASHEx_OB_Type */
-
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
- This parameter can be a value of @ref FLASHEx_OB_WRP_State */
-
- uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
- This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
-
- uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
- This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
-
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
- @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
- @ref FLASHEx_OB_RAM_Parity_Check_Enable.
- @if STM32F373xC
- And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
- @endif
- @if STM32F378xx
- And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
- @endif
- */
-
- uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
- This parameter can be a value of @ref FLASHEx_OB_Data_Address */
-
- uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
-} FLASH_OBProgramInitTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
- * @{
- */
-#define FLASH_PAGE_SIZE 0x800
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
- * @{
- */
-#define FLASH_TYPEERASE_PAGES (0x00U) /*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_GPIO_EX_H
-#define __STM32F3xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @brief GPIO Extended HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
- * @{
- */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
- * @{
- */
-
-#if defined (STM32F302xC)
-/*---------------------------------- STM32F302xC ------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-
-#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F302xC */
-
-#if defined (STM32F303xC)
-/*---------------------------------- STM32F303xC ------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-
-#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F303xC */
-
-#if defined (STM32F303xE)
-/*---------------------------------- STM32F303xE ------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F303xE */
-
-#if defined (STM32F302xE)
-/*---------------------------------- STM32F302xE ------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F302xE */
-
-#if defined (STM32F398xx)
-/*---------------------------------- STM32F398xx ------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F398xx */
-
-#if defined (STM32F358xx)
-/*---------------------------------- STM32F358xx -------------------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F358xx */
-
-#if defined (STM32F373xC)
-/*---------------------------------- STM32F373xC--------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
-#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
-
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F373xC */
-
-
-#if defined (STM32F378xx)
-/*---------------------------------------- STM32F378xx--------------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
-#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F378xx */
-
-#if defined (STM32F303x8)
-/*---------------------------------- STM32F303x8--------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F303x8 */
-
-#if defined (STM32F334x8) || defined (STM32F328xx)
-/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_HRTIM1 ((uint8_t)0x03U) /* HRTIM1 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_HRTIM1 ((uint8_t)0x0CU) /* HRTIM1 Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
-#define GPIO_AF13_HRTIM1 ((uint8_t)0x0DU) /* HRTIM1 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F334x8 || STM32F328xx */
-
-#if defined (STM32F301x8) || defined (STM32F318xx)
-/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F301x8 || STM32F318xx */
-
-#if defined (STM32F302x8)
-/*---------------------------------- STM32F302x8------------------------------------------*/
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
-#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
-/*------------------------------------------------------------------------------------------*/
-#endif /* STM32F302x8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
- * @{
- */
-
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
-* @{
- */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U : 5U)
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U : 5U)
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :\
- ((__GPIOx__) == (GPIOG))? 6U : 7U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h
deleted file mode 100644
index 0f4d9232833..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h
+++ /dev/null
@@ -1,3607 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_hrtim.h
- * @author MCD Application Team
- * @brief Header file of HRTIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_HRTIM_H
-#define __STM32F3xx_HAL_HRTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F334x8)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HRTIM HRTIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
- * @{
- */
-/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
- * @{
- */
-#define MAX_HRTIM_TIMER 6U
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
- * @{
- */
-
-/**
- * @brief HRTIM Configuration Structure definition - Time base related parameters
- */
-typedef struct
-{
- uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
- This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
- uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
- The HRTIM instance can be configured to act as a slave (waiting for a trigger
- to be synchronized) or a master (generating a synchronization signal) or both.
- This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
- uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
- the HRTIM instance is configured as a slave).
- This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
- uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
- (significant only when the HRTIM instance is configured as a master).
- This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
- uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
- outputs (significant only when the HRTIM instance is configured as a master).
- This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
-} HRTIM_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
- HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
-} HAL_HRTIM_StateTypeDef;
-
-/**
- * @brief HRTIM Timer Structure definition
- */
-typedef struct
-{
- uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
- When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
- When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
- uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
- When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
- When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
- uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
- uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
- uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
- uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
- uint32_t DMASize; /*!< Size of the DMA transfer */
-} HRTIM_TimerParamTypeDef;
-
-/**
- * @brief HRTIM Handle Structure definition
- */
-typedef struct __HRTIM_HandleTypeDef
-{
- HRTIM_TypeDef * Instance; /*!< Register base address */
-
- HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
-
- HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
-
- DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
- DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
-} HRTIM_HandleTypeDef;
-
-/**
- * @brief Simple output compare mode configuration definition
- */
-typedef struct {
- uint32_t Period; /*!< Specifies the timer period.
- The period value must be above 3 periods of the fHRTIM clock.
- Maximum value is = 0xFFDFU */
- uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
- uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
- This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
- uint32_t Mode; /*!< Specifies the counter operating mode.
- This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
-} HRTIM_TimeBaseCfgTypeDef;
-
-/**
- * @brief Simple output compare mode configuration definition
- */
-typedef struct {
- uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
- This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity.
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
-} HRTIM_SimpleOCChannelCfgTypeDef;
-
-/**
- * @brief Simple PWM output mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t Polarity; /*!< Specifies the output polarity.
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
-} HRTIM_SimplePWMChannelCfgTypeDef;
-
-/**
- * @brief Simple capture mode configuration definition
- */
-typedef struct {
- uint32_t Event; /*!< Specifies the external event triggering the capture.
- This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
- This parameter can be a value of @ref HRTIM_External_Event_Polarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
- This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
- This parameter can be a value of @ref HRTIM_External_Event_Filter */
-} HRTIM_SimpleCaptureChannelCfgTypeDef;
-
-/**
- * @brief Simple One Pulse mode configuration definition
- */
-typedef struct {
- uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
- The compare value must be above or equal to 3 periods of the fHRTIM clock */
- uint32_t OutputPolarity; /*!< Specifies the output polarity.
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
- uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
- This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
- uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
- This parameter can be a value of @ref HRTIM_External_Event_Polarity */
- uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
- This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
- uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
- This parameter can be a value of @ref HRTIM_External_Event_Filter */
-} HRTIM_SimpleOnePulseChannelCfgTypeDef;
-
-/**
- * @brief Timer configuration definition
- */
-typedef struct {
- uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
- Specifies which interrupts requests must enabled for the timer.
- This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
- or @ref HRTIM_Timing_Unit_Interrupt_Enable */
- uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
- Specifies which DMA requests must be enabled for the timer.
- This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
- or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
- uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
- Specifies the address of the source address of the DMA transfer */
- uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
- Specifies the address of the destination address of the DMA transfer */
- uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
- Specifies the size of the DMA transfer */
- uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
- Specifies whether or not hald mode is enabled
- This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
- uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
- Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
- This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
- uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
- Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
- This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
- uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
- Indicates whether or not the a DAC synchronization event is generated.
- This parameter can be any value of @ref HRTIM_DAC_Synchronization */
- uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
- Specifies whether or not register preload is enabled.
- This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
- uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
- Specifies how the update occurs with respect to a burst DMA transaction or
- update enable inputs (Slave timers only).
- This parameter can be any value of @ref HRTIM_Update_Gating */
- uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
- Specifies how the timer behaves during a burst mode operation.
- This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
- uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
- Specifies whether or not registers update is triggered by the repetition event.
- This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
- uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
- Specifies whether or not the push-pull mode is enabled.
- This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
- uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
- Specifies which fault channels are enabled for the timer.
- This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
- uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
- Specifies whether or not fault enabling status is write protected.
- This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
- uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
- Specifies whether or not dead-time insertion is enabled for the timer.
- This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
- uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
- Specifies the delayed protection mode.
- This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
- uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
- Specifies source(s) triggering the timer registers update.
- This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
- uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
- Specifies source(s) triggering the timer counter reset.
- This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
- uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
- Specifies whether or not registers update is triggered when the timer counter is reset.
- This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
-} HRTIM_TimerCfgTypeDef;
-
-/**
- * @brief Compare unit configuration definition
- */
-typedef struct {
- uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
- The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
- The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
- uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
- This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
- uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
- CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
-} HRTIM_CompareCfgTypeDef;
-
-/**
- * @brief Capture unit configuration definition
- */
-typedef struct {
- uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
- This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
-} HRTIM_CaptureCfgTypeDef;
-
-/**
- * @brief Output configuration definition
- */
-typedef struct {
- uint32_t Polarity; /*!< Specifies the output polarity.
- This parameter can be any value of @ref HRTIM_Output_Polarity */
- uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
- This parameter can be a combination of @ref HRTIM_Output_Set_Source */
- uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
- This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
- uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
- This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
- uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
- This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
- uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
- This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
- uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
- This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
- uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
- This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
-} HRTIM_OutputCfgTypeDef;
-
-/**
- * @brief External event filtering in timing units configuration definition
- */
-typedef struct {
- uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
- This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
- uint32_t Latch; /*!< Specifies whether or not the signal is latched.
- This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
-} HRTIM_TimerEventFilteringCfgTypeDef;
-
-/**
- * @brief Dead time feature configuration definition
- */
-typedef struct {
- uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
- This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
- uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
- This parameter can be a number between 0x0 and 0x1FFU */
- uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
- This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
- uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
- This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
- uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
- This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
- uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
- This parameter can be a number between 0x0 and 0x1FFU */
- uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
- This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
- uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
- This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
- uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
- This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
-} HRTIM_DeadTimeCfgTypeDef ;
-
-/**
- * @brief Chopper mode configuration definition
- */
-typedef struct {
- uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
- This parameter can be a value of @ref HRTIM_Chopper_Frequency */
- uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
- This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
- uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
- This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
-} HRTIM_ChopperModeCfgTypeDef;
-
-/**
- * @brief External event channel configuration definition
- */
-typedef struct {
- uint32_t Source; /*!< Identifies the source of the external event.
- This parameter can be a value of @ref HRTIM_External_Event_Sources */
- uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
- This parameter can be a value of @ref HRTIM_External_Event_Polarity */
- uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
- This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
- uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
- This parameter can be a value of @ref HRTIM_External_Event_Filter */
- uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
- This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
-} HRTIM_EventCfgTypeDef;
-
-/**
- * @brief Fault channel configuration definition
- */
-typedef struct {
- uint32_t Source; /*!< Identifies the source of the fault.
- This parameter can be a value of @ref HRTIM_Fault_Sources */
- uint32_t Polarity; /*!< Specifies the polarity of the fault event.
- This parameter can be a value of @ref HRTIM_Fault_Polarity */
- uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
- This parameter can be a value of @ref HRTIM_Fault_Filter */
- uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
- This parameter can be a value of @ref HRTIM_Fault_Lock */
-} HRTIM_FaultCfgTypeDef;
-
-/**
- * @brief Burst mode configuration definition
- */
-typedef struct {
- uint32_t Mode; /*!< Specifies the burst mode operating mode.
- This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
- uint32_t ClockSource; /*!< Specifies the burst mode clock source.
- This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
- uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
- This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
- uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
- This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
- uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
- This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
- uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
- This parameter can be a number between 0x0 and 0xFFFF */
- uint32_t Period; /*!< Specifies burst mode repetition period.
- This parameter can be a number between 0x1 and 0xFFFF */
-} HRTIM_BurstModeCfgTypeDef;
-
-/**
- * @brief ADC trigger configuration definition
- */
-typedef struct {
- uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
- This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
- uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
- This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
-} HRTIM_ADCTriggerCfgTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
- * @{
- */
-
-/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
- * @{
- * @brief Constants defining the timer indexes
- */
-#define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */
-#define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */
-#define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */
-#define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */
-#define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */
-#define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */
-#define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
- * @{
- * @brief Constants defining timer identifiers
- */
-#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
-#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
-#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
-#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
-#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
-#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
- * @{
- * @brief Constants defining compare unit identifiers
- */
-#define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */
-#define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */
-#define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */
-#define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */
- /**
- * @}
- */
-
-/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
- * @{
- * @brief Constants defining capture unit identifiers
- */
-#define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */
-#define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
- * @{
- * @brief Constants defining timer output identifiers
- */
-#define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */
-#define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */
-#define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */
-#define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */
-#define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */
-#define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */
-#define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */
-#define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */
-#define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */
-#define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
- * @{
- * @brief Constants defining ADC triggers identifiers
- */
-#define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */
-#define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
-#define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
-#define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
-
-#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
- (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
- ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
- ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
- ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
- * @{
- * @brief Constants defining external event channel identifiers
- */
-#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */
-#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */
-#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */
-#define HRTIM_EVENT_3 (0x00000004U) /*!< External event channel 3 identifier */
-#define HRTIM_EVENT_4 (0x00000008U) /*!< External event channel 4 identifier */
-#define HRTIM_EVENT_5 (0x00000010U) /*!< External event channel 5 identifier */
-#define HRTIM_EVENT_6 (0x00000020U) /*!< External event channel 6 identifier */
-#define HRTIM_EVENT_7 (0x00000040U) /*!< External event channel 7 identifier */
-#define HRTIM_EVENT_8 (0x00000080U) /*!< External event channel 8 identifier */
-#define HRTIM_EVENT_9 (0x00000100U) /*!< External event channel 9 identifier */
-#define HRTIM_EVENT_10 (0x00000200U) /*!< External event channel 10 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
- * @{
- * @brief Constants defining fault channel identifiers
- */
-#define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */
-#define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */
-#define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */
-#define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */
-#define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */
-/**
- * @}
- */
-
-
- /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
- * @{
- * @brief Constants defining timer high-resolution clock prescaler ratio.
- */
-#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
- * @{
- * @brief Constants defining timer counter operating mode.
- */
-#define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
-#define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
-#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
- * @{
- * @brief Constants defining half mode enabling status.
- */
-#define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */
-#define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
- * @{
- * @brief Constants defining the timer behavior following the synchronization event
- */
-#define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
-#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
- * @{
- * @brief Constants defining the timer behavior following the synchronization event
- */
-#define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
-#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
- * @{
- * @brief Constants defining on which output the DAC synchronization event is sent
- */
-#define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */
-#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
-#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
-#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
- * @{
- * @brief Constants defining whether a write access into a preloadable
- * register is done into the active or the preload register.
- */
-#define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
-#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
- * @{
- * @brief Constants defining how the update occurs relatively to the burst DMA
- * transaction and the external update request on update enable inputs 1 to 3.
- */
-#define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
-#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
-#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
-#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
-#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
-#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
-#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
-#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
-#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
- * @{
- * @brief Constants defining how the timer behaves during a burst
- mode operation.
- */
-#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U /*!< Timer counter clock is maintained and the timer operates normally */
-#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
- * @{
- * @brief Constants defining whether registers are updated when the timer
- * repetition period is completed (either due to roll-over or
- * reset events)
- */
-#define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */
-#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
-/**
- * @}
- */
-
-
-/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
- * @{
- * @brief Constants defining whether or not the puhs-pull mode is enabled for
- * a timer.
- */
-#define HRTIM_TIMPUSHPULLMODE_DISABLED (0x00000000U) /*!< Push-Pull mode disabled */
-#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
- * @{
- * @brief Constants defining whether a faut channel is enabled for a timer
- */
-#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */
-#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
-#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
-#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
-#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
-#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
- * @{
- * @brief Constants defining whether or not fault enabling bits are write
- * protected for a timer
- */
-#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
-#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
- * @{
- * @brief Constants defining whether or not fault the dead time insertion
- * feature is enabled for a timer
- */
-#define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
-#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
- * @{
- * @brief Constants defining all possible delayed protection modes
- * for a timer. Also definethe source and outputs on which the delayed
- * protection schemes are applied
- */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
-
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
- * @{
- * @brief Constants defining whether the registers update is done synchronously
- * with any other timer or master update
- */
-#define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
-#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
-#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
-#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
-#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
-#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
-#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
- * @{
- * @brief Constants defining the events that can be selected to trigger the reset
- * of the timer counter
- */
-#define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
-#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
-#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
-#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
-#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
-#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
-#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
-#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
-#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
-#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
-#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
-#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
-#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
-#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
-#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
-#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
-#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
- * @{
- * @brief Constants defining whether the register are updated upon Timerx
- * counter reset or roll-over to 0 after reaching the period value
- * in continuous mode
- */
-#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
-#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
- * @{
- * @brief Constants defining whether the compare register is behaving in
- * regular mode (compare match issued as soon as counter equal compare),
- * or in auto-delayed mode
- */
-#define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */
-#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
-#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
-#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
- * @{
- * @brief Constants defining the behavior of the output signal when the timer
- operates in basic output compare mode
- */
-#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */
-#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */
-#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */
-
-#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
- (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
- ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
- ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
- * @{
- * @brief Constants defining the polarity of a timer output
- */
-#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
-#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
- * @{
- * @brief Constants defining the events that can be selected to configure the
- * set crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
-#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
-#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
- * @{
- * @brief Constants defining the events that can be selected to configure the
- * set crossbar of a timer output
- */
-#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
-#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
- * @{
- * @brief Constants defining whether or not the timer output transition to its
- IDLE state when burst mode is entered
- */
-#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
-#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
- /**
- * @}
- */
-
-/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
- * @{
- * @brief Constants defining the output level when output is in IDLE state
- */
-#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
-#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
- * @{
- * @brief Constants defining the output level when output is in FAULT state
- */
-#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
-#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
-#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
-#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
- * @{
- * @brief Constants defining whether or not chopper mode is enabled for a timer
- output
- */
-#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
-#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
- * @{
- * @brief Constants defining the idle mode entry is delayed by forcing a
- deadtime insertion before switching the outputs to their idle state
- */
-#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
-#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
- * @{
- * @brief Constants defining the events that can be selected to trigger the
- * capture of the timing unit counter
- */
-#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */
-#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
-#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
-#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
-#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
-#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
-#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
-#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
-#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
-#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
-#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
-#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
-#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
-#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
- * @{
- * @brief Constants defining the event filtering apploed to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
- * @{
- * @brief Constants defining whether or not the external event is
- * memorized (latched) and generated as soon as the blanking period
- * is completed or the window ends
- */
-#define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
-#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
- * @{
- * @brief Constants defining division ratio between the timer clock frequency
- * (fHRTIM) and the deadtime generator clock (fDTG)
- */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
- * @{
- * @brief Constants defining whether the deadtime is positive or negative
- * (overlapping signal) on rising edge
- */
-#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on rising edge */
-#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
- * @{
- * @brief Constants defining whether or not the deadtime (rising sign and
- * value) is write protected
- */
-#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Deadtime rising value and sign is writeable */
-#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
- * @{
- * @brief Constants defining whether or not the deadtime rising sign is write
- * protected
- */
-#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime rising sign is writeable */
-#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
- * @{
- * @brief Constants defining whether the deadtime is positive or negative
- * (overlapping signal) on falling edge
- */
-#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */
-#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
- * @{
- * @brief Constants defining whether or not the deadtime (falling sign and
- * value) is write protected
- */
-#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */
-#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
- * @{
- * @brief Constants defining whether or not the deadtime falling sign is write
- * protected
- */
-#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */
-#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
- * @{
- * @brief Constants defining the frequency of the generated high frequency carrier
- */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
- /**
- * @}
- */
-
-/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
- * @{
- * @brief Constants defining the duty cycle of the generated high frequency carrier
- * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
- */
-#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */
-#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
-#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
- * @{
- * @brief Constants defining the pulse width of the first pulse of the generated
- * high frequency carrier
- */
-#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */
-#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
-#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
-#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
-#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
-#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
-#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
-#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
-#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
-#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
-#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
-#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
-#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
-#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
-#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
-#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
- * @{
- * @brief Constants defining the options for synchronizing multiple HRTIM
- * instances, as a master unit (generating a synchronization signal)
- * or as a slave (waiting for a trigger to be synchronized)
- */
-#define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
-#define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
-#define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
- * @{
- * @brief Constants defining defining the synchronization input source
- */
-#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
-#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
-#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
- * @{
- * @brief Constants defining the source and event to be sent on the
- * synchronization outputs
- */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
- * @{
- * @brief Constants defining the routing and conditioning of the synchronization output event
- */
-#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
-#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
-#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
- * @{
- * @brief Constants defining available sources associated to external events
- */
-#define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */
-#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */
-#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */
-#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
- * @{
- * @brief Constants defining the polarity of an external event
- */
-#define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */
-#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
- * @{
- * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
- * of an external event
- */
-#define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */
-#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
-#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
-#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
- * @{
- * @brief Constants defining whether or not an external event is programmed in
- fast mode
- */
-
-#define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
-#define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
- * @{
- * @brief Constants defining the frequency used to sample an external event 6
- * input and the length (N) of the digital filter applied
- */
-#define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */
-#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */
-#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */
-#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
-#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */
-#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
-#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
-#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
-#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */
-#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
-#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
-#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
-#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
-#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
-#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
-#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
- * @{
- * @brief Constants defining division ratio between the timer clock frequency
- * fHRTIM) and the external event signal sampling clock (fEEVS)
- * used by the digital filters
- */
-#define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */
-#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */
-#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */
-#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
- * @{
- * @brief Constants defining whether a faults is be triggered by any external
- * or internal fault source
- */
-#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */
-#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
- * @{
- * @brief Constants defining the polarity of a fault event
- */
-#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */
-#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
- * @{
- * @ brief Constants defining the frequency used to sample the fault input and
- * the length (N) of the digital filter applied
- */
-#define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */
-#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */
-#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */
-#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
-#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */
-#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
-#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
-#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
-#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */
-#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
-#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
-#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
-#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
-#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
-#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
-#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
- * @{
- * @brief Constants defining whether or not the fault programming bits are
- write protected
- */
-#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */
-#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
- * @{
- * @brief Constants defining the division ratio between the timer clock
- * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
- * by the digital filters.
- */
-#define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */
-#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */
-#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */
-#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
- * @{
- * @brief Constants defining if the burst mode is entered once or if it is
- * continuously operating
- */
-#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
-#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
- * @{
- * @brief Constants defining the clock source for the burst mode counter
- */
-#define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
-#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
-#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
- * @{
- * @brief Constants defining the prescaling ratio of the fHRTIM clock
- * for the burst mode controller
- */
-#define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */
-#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */
-#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */
-#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
-#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */
-#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
-#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
-#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
-#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */
-#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
-#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
-#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
-#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
-#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
-#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
-#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
- * @{
- * @brief Constants defining whether or not burst mode registers preload
- mechanism is enabled, i.e. a write access into a preloadable register
- (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
- */
-#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
-#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
- * @{
- * @brief Constants defining the events that can be used tor trig the burst
- * mode operation
- */
-#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */
-#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
-#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */
-#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
-#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
-#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
-#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
-#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
-#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
-#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
-#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
-#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
-#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
-#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
-#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
-#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
-#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
-#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
-#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
-#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
-#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
-#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
-#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
-#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
-#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
-#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
-#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
-#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
- * @{
- * @brief constants defining the source triggering the update of the
- HRTIM_ADCxR register (transfer from preload to active register).
- */
-#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */
-#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
-#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
-#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
-#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
-#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
- * @{
- * @brief constants defining the events triggering ADC conversion.
- * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
- * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
- */
-#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
-
-#define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
- * @{
- * @brief Constants defining the DLL calibration periods (in micro seconds)
- */
-#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
-#define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
-#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
-#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
-#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
- * @{
- * @brief Constants defining the registers that can be written during a burst
- * DMA operation
- */
-#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
-#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
- * @{
- * @brief Constants used to enable or disable the burst mode controller
- */
-#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
-#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
- * @{
- * @brief Constants used to enable or disable a fault channel
- */
-#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
-#define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */
-
-#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
- (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
- ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
- * @{
- * @brief Constants used to force timer registers update
- */
-#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
-#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
-#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
-#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
-#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
-#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
- * @{
- * @brief Constants used to force timer counter reset
- */
-#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
-#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
-#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
-#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
-#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
-#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_Level HRTIM Output Level
- * @{
- * @brief Constants defining the level of a timer output
- */
-#define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Forces the output to its active state */
-#define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Forces the output to its inactive state */
-
-#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
- (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
- ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Output_State HRTIM Output State
- * @{
- * @brief Constants defining the state of a timer output
- */
-#define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
- inactive level as programmed in the crossbar unit */
-#define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
- outputs are disabled by software or during a burst mode operation */
-#define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
- FAULTx inputs */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
- * @{
- * @brief Constants defining the operating state of the burst mode controller
- */
-#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */
-#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
- * @{
- * @brief Constants defining on which output the signal is currently applied
- * in push-pull mode
- */
-#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
-#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
- * @{
- * @brief Constants defining on which output the signal was applied, in
- * push-pull mode balanced fault mode or delayed idle mode, when the
- * protection was triggered
- */
-#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
-#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
- * @{
- */
-#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
-#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
-#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
-#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
-#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
-#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
-#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
-#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
-#define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
- * @{
- */
-#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
-#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
-#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
-#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
-#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
-#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
-#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
-#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
- * @{
- */
-#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
-#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
-#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
-#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
-#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
-#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
-#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
-#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
-#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
-#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
-#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
-#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
-#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
-#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
-#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
- * @{
- */
-#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
-#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
-#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
-#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
-#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
-#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
-#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
-#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
- * @{
- */
-#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
-#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
-#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
-#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
-#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
-#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
-#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
- * @{
- */
-#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
-#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
-#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
-#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
-#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
-#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
-#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
-#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
-#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
-#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
-#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
-#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
-#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
-#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
- * @{
- */
-#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */
-#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
-#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
-#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
-#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
-#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
-#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
-#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
- * @{
- */
-#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */
-#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
-#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
-#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
-#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
-#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
-#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
-#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
-#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
-#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
-#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
-#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
-#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
-#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
-#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
- * @{
- */
-
-#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
- (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
-
-#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
- (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
- ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
-
-#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
-
-#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
- (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
- ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
- ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
- ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
-
-#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
- (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
- ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
-
-#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
-
-#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
- ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
- (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
- ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
- (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
- ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
- (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
- ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
- (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
- ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
- (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
- ((OUTPUT) == HRTIM_OUTPUT_TE2))))
-
-#define IS_HRTIM_EVENT(EVENT)\
- (((EVENT) == HRTIM_EVENT_1) || \
- ((EVENT) == HRTIM_EVENT_2) || \
- ((EVENT) == HRTIM_EVENT_3) || \
- ((EVENT) == HRTIM_EVENT_4) || \
- ((EVENT) == HRTIM_EVENT_5) || \
- ((EVENT) == HRTIM_EVENT_6) || \
- ((EVENT) == HRTIM_EVENT_7) || \
- ((EVENT) == HRTIM_EVENT_8) || \
- ((EVENT) == HRTIM_EVENT_9) || \
- ((EVENT) == HRTIM_EVENT_10))
-
-#define IS_HRTIM_FAULT(FAULT)\
- (((FAULT) == HRTIM_FAULT_1) || \
- ((FAULT) == HRTIM_FAULT_2) || \
- ((FAULT) == HRTIM_FAULT_3) || \
- ((FAULT) == HRTIM_FAULT_4) || \
- ((FAULT) == HRTIM_FAULT_5))
-
-#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
- (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
- ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
-
-#define IS_HRTIM_MODE(MODE)\
- (((MODE) == HRTIM_MODE_CONTINUOUS) || \
- ((MODE) == HRTIM_MODE_SINGLESHOT) || \
- ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
-
-#define IS_HRTIM_MODE_ONEPULSE(MODE)\
- (((MODE) == HRTIM_MODE_SINGLESHOT) || \
- ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
-
-
-#define IS_HRTIM_HALFMODE(HALFMODE)\
- (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
- ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
-
-#define IS_HRTIM_SYNCSTART(SYNCSTART)\
- (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
- ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
-
-#define IS_HRTIM_SYNCRESET(SYNCRESET)\
- (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
- ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
-
-#define IS_HHRTIM_DACSYNC(DACSYNC)\
- (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
- ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
- ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
- ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
-
-#define IS_HRTIM_PRELOAD(PRELOAD)\
- (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
- ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
-
-#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
- (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
-
-#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
- (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
- ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
-
-#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
- (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
- ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
-
-#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
- (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
- ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
-
-#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
- (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
- ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
-
-#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
-
-
-#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
- (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
- ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
-
-#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
- ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
- ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
- ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
- || \
- (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
- ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
-
-#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
- ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
- || \
- (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
- (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
- ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
-
-#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
-
-#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
-
-
-#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
- (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
- ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
-
-#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
- (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
-
-/* Auto delayed mode is only available for compare units 2 and 4U */
-#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
- ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
- (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
- || \
- (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
- (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
- ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
-
-#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
- (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
- ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
-
-#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
- (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
-
-#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
- (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
-
-#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
- (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
- ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
-
-#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
- (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
- ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
-
-#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
- (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
- ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
- ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
- ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
-
-#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
- (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
- ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
-
-#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
- (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
- ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
-
-#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
- (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
- ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
-
-#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
- (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
- ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
-
-#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
- (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
- ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
-
-#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
- (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
- ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
-
-#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
- (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
- ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
-
-#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
- (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
- ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
-
-#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
- (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
- ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
-
-#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
- (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
- ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
-
-#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
- (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
- ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
-
-#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
- (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
- ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
-
-#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
- (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
- ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
-
-#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
- (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
- ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
-
-#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
- (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
- ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
-
-#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
- (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
- ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
- ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
-
-#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
- (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
- ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
- ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
- ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
-
-#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
- (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
- ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
- ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
-
-#define IS_HRTIM_EVENTSRC(EVENTSRC)\
- (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
- ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
- ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
- ((EVENTSRC) == HRTIM_EVENTSRC_4))
-
-#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
- ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
- (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
- ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
- || \
- (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
- ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
- ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
-
-#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
- (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
- ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
- ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
- ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
-
-#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
- (((((EVENT) == HRTIM_EVENT_1) || \
- ((EVENT) == HRTIM_EVENT_2) || \
- ((EVENT) == HRTIM_EVENT_3) || \
- ((EVENT) == HRTIM_EVENT_4) || \
- ((EVENT) == HRTIM_EVENT_5)) && \
- (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
- ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
- || \
- (((EVENT) == HRTIM_EVENT_6) || \
- ((EVENT) == HRTIM_EVENT_7) || \
- ((EVENT) == HRTIM_EVENT_8) || \
- ((EVENT) == HRTIM_EVENT_9) || \
- ((EVENT) == HRTIM_EVENT_10)))
-
-
-#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
- ((((EVENT) == HRTIM_EVENT_1) || \
- ((EVENT) == HRTIM_EVENT_2) || \
- ((EVENT) == HRTIM_EVENT_3) || \
- ((EVENT) == HRTIM_EVENT_4) || \
- ((EVENT) == HRTIM_EVENT_5)) \
- || \
- ((((EVENT) == HRTIM_EVENT_6) || \
- ((EVENT) == HRTIM_EVENT_7) || \
- ((EVENT) == HRTIM_EVENT_8) || \
- ((EVENT) == HRTIM_EVENT_9) || \
- ((EVENT) == HRTIM_EVENT_10)) && \
- (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
- ((FILTER) == HRTIM_EVENTFILTER_1) || \
- ((FILTER) == HRTIM_EVENTFILTER_2) || \
- ((FILTER) == HRTIM_EVENTFILTER_3) || \
- ((FILTER) == HRTIM_EVENTFILTER_4) || \
- ((FILTER) == HRTIM_EVENTFILTER_5) || \
- ((FILTER) == HRTIM_EVENTFILTER_6) || \
- ((FILTER) == HRTIM_EVENTFILTER_7) || \
- ((FILTER) == HRTIM_EVENTFILTER_8) || \
- ((FILTER) == HRTIM_EVENTFILTER_9) || \
- ((FILTER) == HRTIM_EVENTFILTER_10) || \
- ((FILTER) == HRTIM_EVENTFILTER_11) || \
- ((FILTER) == HRTIM_EVENTFILTER_12) || \
- ((FILTER) == HRTIM_EVENTFILTER_13) || \
- ((FILTER) == HRTIM_EVENTFILTER_14) || \
- ((FILTER) == HRTIM_EVENTFILTER_15))))
-
-#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
- (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
- ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
- ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
- ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
-#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
- (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
- ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
-
-#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
- (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
- ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
-
-#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
- (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
- ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
-
-#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
- (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
- ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
-
-#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
- (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
- ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
- ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
- ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
-
-#define IS_HRTIM_BURSTMODE(BURSTMODE)\
- (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
- ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
-
-#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
- (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
- ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
-
-#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
- (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
- ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
-
-#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
- (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
- ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
-
-#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
- (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
- ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
-
-#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
- (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
- ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
- ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
- ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
- ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
- ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
-
-#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
- (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
- ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
- ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
- ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
- ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
-
-#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
- ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
-
-#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
- (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
- ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
-
-#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
-
-#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
-
-#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
-
-
-#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
-
-
-#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
-
-
-#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
-
-#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
- * @{
- */
-
-/** @brief Reset HRTIM handle state
- * @param __HANDLE__ HRTIM handle.
- * @retval None
- */
-#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
-
-/** @brief Enables or disables the timer counter(s)
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __TIMERS__ timers to enable/disable
- * This parameter can be any combinations of the following values:
- * @arg HRTIM_TIMERID_MASTER: Master timer identifier
- * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
- * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
- * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
- * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
- * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
-
-/* The counter of a timing unit is disabled only if all the timer outputs */
-/* are disabled and no capture is configured */
-#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
-#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
-#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
-#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
-#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
-#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
- do {\
- if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
- }\
- }\
- if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
- {\
- if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
- {\
- ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
- }\
- }\
- } while(0U)
-
-/** @brief Enables or disables the specified HRTIM common interrupts.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
- * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
- * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
-#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Master timer interrupts.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
-#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Timerx interrupts.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __TIMER__ specified the timing unit (Timer A to E)
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
-#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
-
-/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 enable
- * @arg HRTIM_IT_FLT4: Fault 4 enable
- * @arg HRTIM_IT_FLT5: Fault 5 enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __TIMER__ specified the timing unit (Timer A to E)
- * @param __INTERRUPT__ specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
- * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clears the specified HRTIM common pending flag.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
- * @arg HRTIM_IT_FLT3: Fault 3 clear flag
- * @arg HRTIM_IT_FLT4: Fault 4 clear flag
- * @arg HRTIM_IT_FLT5: Fault 5 clear flag
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
- * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
-
-/** @brief Clears the specified HRTIM Master pending flag.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
- * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
- * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
- * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
-
-/** @brief Clears the specified HRTIM Timerx pending flag.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __TIMER__ specified the timing unit (Timer A to E)
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
- * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
- * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
- * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
- * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
- * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
- * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
- * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
- * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
- * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
- * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
- * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
-
-/* DMA HANDLING */
-/** @brief Enables or disables the specified HRTIM common interrupts.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
- * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
- * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
- * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
- * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
- * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
- * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
- * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
- * @retval None
- */
-#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
-#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
-
-/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __DMA__ specifies the DMA request to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
- * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
- * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
- * @retval None
- */
-#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
-#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
-
-/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
- * @param __HANDLE__ specifies the HRTIM Handle.
- * @param __TIMER__ specified the timing unit (Timer A to E)
- * @param __DMA__ specifies the DMA request to enable or disable.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
- * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
- * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
- * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
- * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
- * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
- * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
- * @retval None
- */
-#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
-#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
-
-#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
-
-#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
-
-#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
-#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
-
-/** @brief Sets the HRTIM timer Counter Register value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COUNTER__ specifies the Counter Register new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
-
-/** @brief Gets the HRTIM timer Counter Register value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval HRTIM timer Counter Register value
- */
-#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
-
-/** @brief Sets the HRTIM timer Period value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __PERIOD__ specifies the Period Register new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
-
-/** @brief Gets the HRTIM timer Period Register value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval timer Period Register
- */
-#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
-
-/** @brief Sets the HRTIM timer clock prescaler value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @param __PRESCALER__ specifies the clock prescaler new value.
- * This parameter can be one of the following values:
- * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
- * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
- * @retval None
- */
-#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
- (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
-
-/** @brief Gets the HRTIM timer clock prescaler value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x5 for master timer
- * @arg 0x0 to 0x4 for timers A to E
- * @retval timer clock prescaler value
- */
-#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
-
-/** @brief Sets the HRTIM timer Compare Register value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COMPAREUNIT__ timer compare unit
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param __COMPARE__ specifies the Compare new value.
- * @retval None
- */
-#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
- : \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
-
-/** @brief Gets the HRTIM timer Compare Register value on runtime
- * @param __HANDLE__ HRTIM Handle.
- * @param __TIMER__ HRTIM timer
- * This parameter can be one of the following values:
- * @arg 0x0 to 0x4 for timers A to E
- * @param __COMPAREUNIT__ timer compare unit
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @retval Compare value
- */
-#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
- (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
- ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
- : \
- (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
- ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
- ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HRTIM_Exported_Functions
-* @{
-*/
-
-/** @addtogroup HRTIM_Exported_Functions_Group1
-* @{
-*/
-
-/* Initialization and Configuration functions ********************************/
-HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
-
-void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
-
-void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t CalibrationRate);
-
-HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t CalibrationRate);
-
-HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group2
-* @{
-*/
-
-/* Simple time base related functions *****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group3
-* @{
-*/
-/* Simple output compare related functions ************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group4
-* @{
-*/
-/* Simple PWM output related functions ****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group5
-* @{
-*/
-/* Simple capture related functions *******************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group6
-* @{
-*/
-/* Simple one pulse related functions *****************************************/
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel,
- HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group7
-* @{
-*/
-HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
- HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef* pEventCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Prescaler);
-
-HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Fault,
- HRTIM_FaultCfgTypeDef* pFaultCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Prescaler);
-
-void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Faults,
- uint32_t Enable);
-
-HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t ADCTrigger,
- HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group8
-* @{
-*/
-/* Waveform related functions *************************************************/
-HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef* pCompareCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- HRTIM_CaptureCfgTypeDef* pCaptureCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- uint32_t OutputLevel);
-
-HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Event,
- HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t RegistersToUpdate);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
- uint32_t OutputsToStart);
-
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
- uint32_t OutputsToStop);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Enable);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t BurstBufferAddress,
- uint32_t BurstBufferLength);
-
-HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group9
-* @{
-*/
-/* HRTIM peripheral state functions */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
-
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit);
-
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t Output);
-
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
-
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Exported_Functions_Group10
-* @{
-*/
-/* IRQ handler */
-void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-
-/* HRTIM events related callback functions */
-void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
-void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
-
-/* Timer events related callback functions */
-void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx);
-void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F334x8) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_HRTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
deleted file mode 100644
index 7cf51e30414..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
+++ /dev/null
@@ -1,708 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_I2C_H
-#define __STM32F3xx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
- * @{
- */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
- * @brief I2C Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
- section in Reference manual */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-} I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
- * @brief HAL State structure definition
- * @note HAL I2C State value coding follow below described bitmap :\n
- * b7-b6 Error information\n
- * 00 : No Error\n
- * 01 : Abort (Abort user request on going)\n
- * 10 : Timeout\n
- * 11 : Error\n
- * b5 IP initilisation status\n
- * 0 : Reset (IP not initialized)\n
- * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
- * b4 (not used)\n
- * x : Should be set to 0\n
- * b3\n
- * 0 : Ready or Busy (No Listen mode ongoing)\n
- * 1 : Listen (IP in Address Listen Mode)\n
- * b2 Intrinsic process state\n
- * 0 : Ready\n
- * 1 : Busy (IP busy with some configuration or internal operations)\n
- * b1 Rx state\n
- * 0 : Ready (no Rx operation ongoing)\n
- * 1 : Busy (Rx operation ongoing)\n
- * b0 Tx state\n
- * 0 : Ready (no Tx operation ongoing)\n
- * 1 : Busy (Tx operation ongoing)
- * @{
- */
-typedef enum
-{
- HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
- HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
- HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
- HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-
-} HAL_I2C_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
- * @brief HAL Mode structure definition
- * @note HAL I2C Mode value coding follow below described bitmap :\n
- * b7 (not used)\n
- * x : Should be set to 0\n
- * b6\n
- * 0 : None\n
- * 1 : Memory (HAL I2C communication is in Memory Mode)\n
- * b5\n
- * 0 : None\n
- * 1 : Slave (HAL I2C communication is in Slave Mode)\n
- * b4\n
- * 0 : None\n
- * 1 : Master (HAL I2C communication is in Master Mode)\n
- * b3-b2-b1-b0 (not used)\n
- * xxxx : Should be set to 0000
- * @{
- */
-typedef enum
-{
- HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
- * @brief I2C Error Code definition
- * @{
- */
-#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
-#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
-/**
- * @}
- */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
- * @brief I2C handle Structure definition
- * @{
- */
-typedef struct __I2C_HandleTypeDef
-{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
- be a value of @ref I2C_XFEROPTIONS */
-
- __IO uint32_t PreviousState; /*!< I2C communication Previous state */
-
- HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
- __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
-} I2C_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
- * @{
- */
-#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
-/**
- * @}
- */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
- * @{
- */
-#define I2C_DUALADDRESS_DISABLE (0x00000000U)
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-/**
- * @}
- */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
- * @{
- */
-#define I2C_OA2_NOMASK ((uint8_t)0x00U)
-#define I2C_OA2_MASK01 ((uint8_t)0x01U)
-#define I2C_OA2_MASK02 ((uint8_t)0x02U)
-#define I2C_OA2_MASK03 ((uint8_t)0x03U)
-#define I2C_OA2_MASK04 ((uint8_t)0x04U)
-#define I2C_OA2_MASK05 ((uint8_t)0x05U)
-#define I2C_OA2_MASK06 ((uint8_t)0x06U)
-#define I2C_OA2_MASK07 ((uint8_t)0x07U)
-/**
- * @}
- */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
- * @{
- */
-#define I2C_GENERALCALL_DISABLE (0x00000000U)
-#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
-/**
- * @}
- */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
- * @{
- */
-#define I2C_NOSTRETCH_DISABLE (0x00000000U)
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
- * @{
- */
-#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
- * @{
- */
-#define I2C_DIRECTION_TRANSMIT (0x00000000U)
-#define I2C_DIRECTION_RECEIVE (0x00000001U)
-/**
- * @}
- */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
- * @{
- */
-#define I2C_RELOAD_MODE I2C_CR2_RELOAD
-#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
-#define I2C_SOFTEND_MODE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
- * @{
- */
-#define I2C_NO_STARTSTOP (0x00000000U)
-#define I2C_GENERATE_STOP I2C_CR2_STOP
-#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_GENERATE_START_WRITE I2C_CR2_START
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
- * @brief I2C Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-/**
- * @}
- */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
- * @{
- */
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_AF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-#define I2C_FLAG_DIR I2C_ISR_DIR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @brief Reset I2C handle state.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief Enable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief Disable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified I2C interrupt source is enabled or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_ERRI Errors interrupt enable
- * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
- * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
- * @arg @ref I2C_IT_NACKI NACK received interrupt enable
- * @arg @ref I2C_IT_ADDRI Address match interrupt enable
- * @arg @ref I2C_IT_RXI RX interrupt enable
- * @arg @ref I2C_IT_TXI TX interrupt enable
- *
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified I2C flag is set or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
- * @arg @ref I2C_FLAG_RXNE Receive data register not empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
- * @arg @ref I2C_FLAG_TCR Transfer complete reload
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- * @arg @ref I2C_FLAG_BUSY Bus busy
- * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
- *
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref I2C_FLAG_TXE Transmit data register empty
- * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
- * @arg @ref I2C_FLAG_STOPF STOP detection flag
- * @arg @ref I2C_FLAG_BERR Bus error
- * @arg @ref I2C_FLAG_ARLO Arbitration lost
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun
- * @arg @ref I2C_FLAG_PECERR PEC error in reception
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref I2C_FLAG_ALERT SMBus alert
- *
- * @retval None
- */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief Enable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
- * @}
- */
-
-/* Include I2C HAL Extended module */
-#include "stm32f3xx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* IO operation functions ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
- * @}
- */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @{
- */
-/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
- * @{
- */
-
-#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
- ((MASK) == I2C_OA2_MASK01) || \
- ((MASK) == I2C_OA2_MASK02) || \
- ((MASK) == I2C_OA2_MASK03) || \
- ((MASK) == I2C_OA2_MASK04) || \
- ((MASK) == I2C_OA2_MASK05) || \
- ((MASK) == I2C_OA2_MASK06) || \
- ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
- ((MODE) == I2C_AUTOEND_MODE) || \
- ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
- ((REQUEST) == I2C_GENERATE_START_READ) || \
- ((REQUEST) == I2C_GENERATE_START_WRITE) || \
- ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
- ((REQUEST) == I2C_NEXT_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
-#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
-#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions are defined in stm32f3xx_hal_i2c.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h
deleted file mode 100644
index 5be5fd601a8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2c_ex.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_I2C_EX_H
-#define __STM32F3xx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2CEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
- * @{
- */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
- * @{
- */
-#define I2C_ANALOGFILTER_ENABLE 0x00000000U
-#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-/**
- * @}
- */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
- * @{
- */
-#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
-#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
-#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
-#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
-#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
-#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
-#if defined(SYSCFG_CFGR1_I2C2_FMP)
-#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
-#endif
-#if defined(SYSCFG_CFGR1_I2C3_FMP)
-#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
-#else
-#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
- * @{
- */
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
- ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
- * @{
- */
-/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h
deleted file mode 100644
index 3360ecfebe2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2s.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_I2S_H
-#define __STM32F3xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2S
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-
- uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
- This parameter can be a value of @ref I2S_Clock_Source */
-
- uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
- This parameter can be a value of @ref I2S_FullDuplex_Mode */
-
-}I2S_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
-}HAL_I2S_StateTypeDef;
-
-/**
- * @brief I2S handle Structure definition
- */
-typedef struct
-{
- SPI_TypeDef *Instance; /*!< I2S registers base address */
-
- I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received.
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
-
- __IO uint32_t ErrorCode; /*!< I2S Error code
- This parameter can be a value of @ref I2S_Error */
-
-}I2S_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
- * @{
- */
-/** @defgroup I2S_Error I2S Error
- * @{
- */
-#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
-#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
-#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define I2S_CLOCK_EXTERNAL (0x00000001U)
-#define I2S_CLOCK_SYSCLK (0x00000002U)
-
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
- ((CLOCK) == I2S_CLOCK_SYSCLK))
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode I2S Mode
- * @{
- */
-#define I2S_MODE_SLAVE_TX (0x00000000U)
-#define I2S_MODE_SLAVE_RX (0x00000100U)
-#define I2S_MODE_MASTER_TX (0x00000200U)
-#define I2S_MODE_MASTER_RX (0x00000300U)
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX)|| \
- ((MODE) == I2S_MODE_MASTER_RX))
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard I2S Standard
- * @{
- */
-#define I2S_STANDARD_PHILIPS (0x00000000U)
-#define I2S_STANDARD_MSB (0x00000010U)
-#define I2S_STANDARD_LSB (0x00000020U)
-#define I2S_STANDARD_PCM_SHORT (0x00000030U)
-#define I2S_STANDARD_PCM_LONG (0x000000B0U)
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format I2S Data Format
- * @{
- */
-#define I2S_DATAFORMAT_16B (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
-#define I2S_DATAFORMAT_24B (0x00000003U)
-#define I2S_DATAFORMAT_32B (0x00000005U)
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
- * @{
- */
-#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
- * @{
- */
-#define I2S_AUDIOFREQ_192K (192000U)
-#define I2S_AUDIOFREQ_96K (96000U)
-#define I2S_AUDIOFREQ_48K (48000U)
-#define I2S_AUDIOFREQ_44K (44100U)
-#define I2S_AUDIOFREQ_32K (32000U)
-#define I2S_AUDIOFREQ_22K (22050U)
-#define I2S_AUDIOFREQ_16K (16000U)
-#define I2S_AUDIOFREQ_11K (11025U)
-#define I2S_AUDIOFREQ_8K (8000U)
-#define I2S_AUDIOFREQ_DEFAULT (2U)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-/**
- * @}
- */
-
-/** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
- * @{
- */
-#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
-#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
-
-#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
- ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
- * @{
- */
-#define I2S_CPOL_LOW (0x00000000U)
-#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
-/**
- * @}
- */
-
-/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
- * @{
- */
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup I2S_Flag_definition I2S Flag definition
- * @{
- */
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
-
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @brief Reset I2S handle state
- * @param __HANDLE__ I2S handle.
- * @retval None
- */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
-
-/** @brief Enable or disable the specified I2S interrupts.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the I2S Handle.
- * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__ specifies the I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2S flag is set or not.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
- * @arg I2S_FLAG_TXE: Transmit buffer empty flag
- * @arg I2S_FLAG_UDR: Underrun flag
- * @arg I2S_FLAG_OVR: Overrun flag
- * @arg I2S_FLAG_FRE: Frame error flag
- * @arg I2S_FLAG_CHSIDE: Channel Side flag
- * @arg I2S_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- }while(0U)
-/** @brief Clears the I2S UDR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg;\
- tmpreg = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg); \
- }while(0U)
-/**
- * @}
- */
-
-/* Include I2S HAL Extended module */
-#include "stm32f3xx_hal_i2s_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h
deleted file mode 100644
index 99f102f9770..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2s_ex.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_I2S_EX_H
-#define __STM32F3xx_HAL_I2S_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2SEx I2SEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
- * @{
- */
-#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
-#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
-
-/** @brief Enable or disable the specified I2SExt peripheral.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
-
-/** @brief Enable or disable the specified I2SExt interrupts.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
-#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
-
-/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the I2S Handle.
- * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__ specifies the I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2SExt flag is set or not.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
- * @arg I2S_FLAG_TXE: Transmit buffer empty flag
- * @arg I2S_FLAG_UDR: Underrun flag
- * @arg I2S_FLAG_OVR: Overrun flag
- * @arg I2S_FLAG_FRE: Frame error flag
- * @arg I2S_FLAG_CHSIDE: Channel Side flag
- * @arg I2S_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2SExt OVR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
- (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
-/** @brief Clears the I2SExt UDR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- /**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
- * @{
- */
-
-#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
-/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
- * @{
- */
-
-/* Extended features functions ************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
-/**
- * @}
- */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2S I2S
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
-/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
-/* Callback used in non blocking modes (DMA only) */
-void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_I2S_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h
deleted file mode 100644
index 8594766dc3e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h
+++ /dev/null
@@ -1,788 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_irda.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the IRDA
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_IRDA_H
-#define __STM32F3xx_HAL_IRDA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
- * @{
- */
-
-/**
- * @brief IRDA Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
- The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref IRDAEx_Word_Length */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref IRDA_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Transfer_Mode */
-
- uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
- to achieve low-power frequency.
- @note Prescaler value 0 is forbidden */
-
- uint16_t PowerMode; /*!< Specifies the IRDA power mode.
- This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
-
-/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
- * - gState contains IRDA state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
-
-/**
- * @brief IRDA clock sources definition
- */
-typedef enum
-{
- IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}IRDA_ClockSourceTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< IRDA registers base address */
-
- IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
- uint16_t Mask; /*!< IRDA RX RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< IRDA Error code
- This parameter can be a value of @ref IRDA_Error */
-
-}IRDA_HandleTypeDef;
-
-/**
- * @brief IRDA Configuration enumeration values definition
- */
-typedef enum
-{
- IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */
- IRDA_PARITY = 0x01U, /*!< IRDA frame parity */
- IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */
- IRDA_MODE = 0x03U, /*!< IRDA communication mode */
- IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */
- IRDA_POWERMODE = 0x05U /*!< IRDA power mode */
-}IRDA_ControlTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
- * @{
- */
-
-/** @defgroup IRDA_Error IRDA Error
- * @{
- */
-#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Parity IRDA Parity
- * @{
- */
-#define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
- * @{
- */
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
- * @{
- */
-#define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_State IRDA State
- * @{
- */
-#define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */
-#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Mode IRDA Mode
- * @{
- */
-#define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */
-#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
-/**
- * @}
- */
-
-/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */
-#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
- * @{
- */
-#define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */
-#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
- * @{
- */
-#define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */
-#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
- * @{
- */
-#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Flags IRDA Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */
-#define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */
-#define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */
-#define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */
-#define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */
-#define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */
-#define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */
-#define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */
-#define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */
-#define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */
-#define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */
-#define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-#define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */
-#define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */
-#define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */
-#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */
-#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */
-#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
- * @{
- */
-#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
- * @{
- */
-#define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
- * @{
- */
-
-/** @brief Reset IRDA handle state.
- * @param __HANDLE__ IRDA handle.
- * @retval None
- */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0U)
-
-/** @brief Flush the IRDA DR register.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0U)
-
-/** @brief Clear the specified IRDA pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref IRDA_CLEAR_PEF
- * @arg @ref IRDA_CLEAR_FEF
- * @arg @ref IRDA_CLEAR_NEF
- * @arg @ref IRDA_CLEAR_OREF
- * @arg @ref IRDA_CLEAR_TCF
- * @arg @ref IRDA_CLEAR_IDLEF
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
-
-
-/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
-
-/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
-
-/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
-
-/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
-
-/** @brief Check whether the specified IRDA flag is set or not.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref IRDA_FLAG_BUSY Busy flag
- * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
- * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
- * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
- * @arg @ref IRDA_FLAG_TC Transmission Complete flag
- * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
- * @arg @ref IRDA_FLAG_ORE OverRun Error flag
- * @arg @ref IRDA_FLAG_NE Noise Error flag
- * @arg @ref IRDA_FLAG_FE Framing Error flag
- * @arg @ref IRDA_FLAG_PE Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief Enable the specified IRDA interrupt.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-/** @brief Disable the specified IRDA interrupt.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-
-/** @brief Check whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __IT__ specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_ORE OverRun Error interrupt
- * @arg @ref IRDA_IT_NE Noise Error interrupt
- * @arg @ref IRDA_IT_FE Framing Error interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
-
-/** @brief Check whether the specified IRDA interrupt source is enabled or not.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __IT__ specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref IRDA_IT_TC Transmission complete interrupt
- * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
- * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
- * @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
-
-
-/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
- * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-
-/** @brief Set a specific IRDA request flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __REQ__ specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
- * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
- * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief Enable the IRDA one bit sample method.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the IRDA one bit sample method.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART/USART associated to IRDA Handle.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART/USART associated to IRDA Handle.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
- * @{
- */
-
-/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
- * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
- * @retval True or False
- */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
-
-/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
- * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
- * @retval True or False
- */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
-
-/**
- * @brief Ensure that IRDA frame parity is valid.
- * @param __PARITY__ IRDA frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
- ((__PARITY__) == IRDA_PARITY_EVEN) || \
- ((__PARITY__) == IRDA_PARITY_ODD))
-
-/**
- * @brief Ensure that IRDA communication mode is valid.
- * @param __MODE__ IRDA communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-
-/**
- * @brief Ensure that IRDA power mode is valid.
- * @param __MODE__ IRDA power mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
- ((__MODE__) == IRDA_POWERMODE_NORMAL))
-
-/**
- * @brief Ensure that IRDA state is valid.
- * @param __STATE__ IRDA state mode.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
- ((__STATE__) == IRDA_STATE_ENABLE))
-
-/**
- * @brief Ensure that IRDA associated UART/USART mode is valid.
- * @param __MODE__ IRDA associated UART/USART mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
- ((__MODE__) == IRDA_MODE_ENABLE))
-
-/**
- * @brief Ensure that IRDA sampling rate is valid.
- * @param __ONEBIT__ IRDA sampling rate.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that IRDA DMA TX mode is valid.
- * @param __DMATX__ IRDA DMA TX mode.
- * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
-#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
- ((__DMATX__) == IRDA_DMA_TX_ENABLE))
-
-/**
- * @brief Ensure that IRDA DMA RX mode is valid.
- * @param __DMARX__ IRDA DMA RX mode.
- * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
- ((__DMARX__) == IRDA_DMA_RX_ENABLE))
-
-/**
- * @brief Ensure that IRDA request is valid.
- * @param __PARAM__ IRDA request.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
-/**
- * @}
- */
-
-/* Include IRDA HAL Extended module */
-#include "stm32f3xx_hal_irda_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h
deleted file mode 100644
index 0ccb541e0ac..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_irda_ex.h
- * @author MCD Application Team
- * @brief Header file of IRDA HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_IRDA_EX_H
-#define __STM32F3xx_HAL_IRDA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
- * @{
- */
-
-/** @defgroup IRDAEx_Word_Length IRDA Word Length
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
-#else
-#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
- * @{
- */
-
-/** @brief Report the IRDA clock source.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @param __CLOCKSOURCE__ output variable.
- * @retval IRDA clocking source, written in __CLOCKSOURCE__.
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
- case RCC_UART4CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if ((__HANDLE__)->Instance == UART5) \
- { \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
- case RCC_UART5CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART5CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART5CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART5CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#else
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
-
-
-/** @brief Compute the mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F334x8)
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
-} while(0U)
-#else
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
-} while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F334x8 */
-/**
- * @brief Ensure that IRDA frame length is valid.
- * @param __LENGTH__ IRDA frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
- ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
- ((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#else
-#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
- ((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_IRDA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h
deleted file mode 100644
index 093b5e99a09..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_IWDG_H
-#define __STM32F3xx_HAL_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup IWDG IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
- * @{
- */
-
-/**
- * @brief IWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
- This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
-
- uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
-
-} IWDG_InitTypeDef;
-
-/**
- * @brief IWDG Handle Structure definition
- */
-typedef struct
-{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
- IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-
-}IWDG_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
- * @{
- */
-#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128U */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256U */
-/**
- * @}
- */
-
-/** @defgroup IWDG_Window_option IWDG Window option
- * @{
- */
-#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the IWDG peripheral.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
- * @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
- * @{
- */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
- * @{
- */
-/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
- * @{
- */
-/**
- * @brief IWDG Key Register BitMask
- */
-#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
- * @{
- */
-/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
- * @brief Check IWDG prescaler value.
- * @param __PRESCALER__ IWDG prescaler value
- * @retval None
- */
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
- * @brief Check IWDG reload value.
- * @param __RELOAD__ IWDG reload value
- * @retval None
- */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
-
-/**
- * @brief Check IWDG window value.
- * @param __WINDOW__ IWDG window value
- * @retval None
- */
-#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h
deleted file mode 100644
index 0c290fc55f6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_nand.h
- * @author MCD Application Team
- * @brief Header file of NAND HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_NAND_H
-#define __STM32F3xx_HAL_NAND_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#include "stm32f3xx_ll_fmc.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NAND
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
- * @{
- */
-
-/**
- * @brief HAL NAND State structures definition
- */
-typedef enum
-{
- HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
- * @brief NAND Memory electronic signature Structure definition
- */
-typedef struct
-{
- /*State = HAL_NAND_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* IO operation functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-#define NAND_DEVICE1 FMC_BANK2
-#define NAND_DEVICE2 FMC_BANK3
-#define NAND_WRITE_TIMEOUT 0x01000000U
-
-#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS 0x00000100U
-#define NAND_INVALID_ADDRESS 0x00000200U
-#define NAND_TIMEOUT_ERROR 0x00000400U
-#define NAND_BUSY 0x00000000U
-#define NAND_ERROR 0x00000001U
-#define NAND_READY 0x00000040U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__ NAND memory address.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
-
-/**
- * @brief NAND memory Column address computation.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/**
- * @brief NAND memory Columns cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND Column address cycling value.
- */
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h
deleted file mode 100644
index a5cd859f0db..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_nor.h
- * @author MCD Application Team
- * @brief Header file of NOR HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_NOR_H
-#define __STM32F3xx_HAL_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#include "stm32f3xx_ll_fmc.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NOR
- * @{
- */
-
-
-/** @addtogroup NOR_Private_Constants
- * @{
- */
-
-/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x10U)
-#define CFI2_ADDRESS ((uint16_t)0x11U)
-#define CFI3_ADDRESS ((uint16_t)0x12U)
-#define CFI4_ADDRESS ((uint16_t)0x13U)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0U)
-#define NOR_MEMORY_16B ((uint8_t)0x1U)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 FMC_BANK1_1
-#define NOR_MEMORY_ADRESS2 FMC_BANK1_2
-#define NOR_MEMORY_ADRESS3 FMC_BANK1_3
-#define NOR_MEMORY_ADRESS4 FMC_BANK1_4
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Private_Macros
- * @{
- */
-
-/**
- * @brief NOR memory address shifting.
- * @param __NOR_ADDRESS NOR base address
- * @param __NOR_MEMORY_WIDTH_ NOR memory width
- * @param __ADDRESS__ NOR memory address
- * @retval NOR shifted address value
- */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
- ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
- * @brief NOR memory write data to specified address.
- * @param __ADDRESS__ NOR memory address
- * @param __DATA__ Data to write
- * @retval None
- */
-#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup NOR_Exported_Types NOR Exported Types
- * @{
- */
-
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
-}HAL_NOR_StateTypeDef;
-
-/**
- * @brief FMC NOR Status typedef
- */
-typedef enum
-{
- HAL_NOR_STATUS_SUCCESS = 0U,
- HAL_NOR_STATUS_ONGOING,
- HAL_NOR_STATUS_ERROR,
- HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef;
-
-/**
- * @brief FMC NOR ID typedef
- */
-typedef struct
-{
- uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
- These codes can be accessed by performing read operations with specific
- control signals and addresses set.They can also be accessed by issuing
- an Auto Select command. */
-}NOR_IDTypeDef;
-
-/**
- * @brief FMC NOR CFI typedef
- */
-typedef struct
-{
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface
- which contains a description of various electrical and timing parameters,
- density information and functions supported by the memory. */
-}NOR_CFITypeDef;
-
-/**
- * @brief NOR handle Structure definition
- */
-typedef struct
-{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
- __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
-}NOR_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup NOR_Exported_Macros NOR Exported Macros
- * @{
- */
-
-/** @brief Reset NOR handle state
- * @param __HANDLE__ NOR handle
- * @retval None
- */
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NOR Control functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h
deleted file mode 100644
index 9c970e95578..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_opamp.h
- * @author MCD Application Team
- * @brief Header file of OPAMP HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_OPAMP_H
-#define __STM32F3xx_HAL_OPAMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup OPAMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
- * @{
- */
-
-/**
- * @brief OPAMP Init structure definition
- */
-
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the OPAMP mode
- This parameter must be a value of @ref OPAMP_Mode
- mode is either Standalone, - Follower or PGA */
-
- uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
- - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
- This parameter must be a value of @ref OPAMP_InvertingInput
- InvertingInput is either VM0 or VM1
- - In PGA mode: i.e when mode is OPAMP_PGA_MODE
- & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
- This parameter is Not Applicable */
-
- uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
- This parameter must be a value of @ref OPAMP_NonInvertingInput
- NonInvertingInput is either VP0, VP1, VP2 or VP3 */
-
- uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
- This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
-
- uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
- TimerControlledMuxmode is enabled
- i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
- - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
- This parameter must be a value of @ref OPAMP_InvertingInputSecondary
- InvertingInputSecondary is either VM0 or VM1
- - In PGA mode: i.e when mode is OPAMP_PGA_MODE
- & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
- This parameter is Not Applicable */
-
- uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
- TimerControlledMuxmode is enabled
- i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
- This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
- NonInvertingInput is either VP0, VP1, VP2 or VP3 */
-
- uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
- i.e. when mode is OPAMP_PGA_MODE
- This parameter must be a value of @ref OPAMP_PgaConnect
- Either: not connected, connected to VM0, connected to VM1
- (VM0 or VM1 are typically used for external filtering) */
-
- uint32_t PgaGain; /*!< Specifies the gain in PGA mode
- i.e. when mode is OPAMP_PGA_MODE.
- This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */
-
- uint32_t UserTrimming; /*!< Specifies the trimming mode
- This parameter must be a value of @ref OPAMP_UserTrimming
- UserTrimming is either factory or user trimming */
-
- uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
-
- uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
- i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
-
-}OPAMP_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-
-typedef enum
-{
- HAL_OPAMP_STATE_RESET = 0x00000000U, /*!< OPMAP is not yet Initialized */
-
- HAL_OPAMP_STATE_READY = 0x00000001U, /*!< OPAMP is initialized and ready for use */
- HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
-
- HAL_OPAMP_STATE_BUSY = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
- HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U, /*!< OPAMP is locked
- only system reset allows reconfiguring the opamp. */
-
-}HAL_OPAMP_StateTypeDef;
-
-/**
- * @brief OPAMP Handle Structure definition to @brief OPAMP Handle Structure definition
- */
-typedef struct
-{
- OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
- OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
- HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
-
-} OPAMP_HandleTypeDef;
-
-/**
- * @brief OPAMP_TrimmingValueTypeDef @brief definition
- */
-
-typedef uint32_t OPAMP_TrimmingValueTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
- * @{
- */
-
-/** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
- * @{
- */
-/* Used for Init phase */
-#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
- | OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
- | OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
- | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Mode OPAMP Mode
- * @{
- */
-#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< standalone mode */
-#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
-#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
-
-
-#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
- ((INPUT) == OPAMP_PGA_MODE) || \
- ((INPUT) == OPAMP_FOLLOWER_MODE))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL_0 /*!< VP3 (PA5 for OPAMP1, VP1 PB14 for OPAMP2, VP3 PA5 for OPAMP3, VP2 PB11 for OPAMP4)
- connected to OPAMPx non inverting input */
-
-#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
- ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
- * @{
- */
-
-#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< inverting input connected to VM0 */
-#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
-
-#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
- * @{
- */
- #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U) /*!< Timer controlled Mux mode disabled */
- #define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
-
- #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
- ((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
-/**
- * @}
- */
-
- /** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
- * @{
- */
-
-#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
- connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
- connected to OPAMPx non inverting input */
-
-#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
- ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
- * @{
- */
-
-#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000U) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
- connected to OPAMPx inverting input */
-#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
- connected to OPAMPx inverting input */
-
-#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
- ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
- * @{
- */
-
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000U) /*!< In PGA mode, the non inverting input is not connected */
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
-
-#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
- ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
- ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
- * @{
- */
-
-#define OPAMP_PGA_GAIN_2 (0x00000000U) /*!< PGA gain = 2 */
-#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
-#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
-#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
-
-#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
- ((GAIN) == OPAMP_PGA_GAIN_4) || \
- ((GAIN) == OPAMP_PGA_GAIN_8) || \
- ((GAIN) == OPAMP_PGA_GAIN_16))
-/**
- * @}
- */
-
-/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
- * @{
- */
-
-#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */
-#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
-
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
- ((TRIMMING) == OPAMP_TRIMMING_USER))
-
-/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
- * @{
- */
-
-#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy trimming value */
-
-#define OPAMP_FACTORYTRIMMING_N (0x00000000U) /*!< Offset trimming N */
-#define OPAMP_FACTORYTRIMMING_P (0x00000001U) /*!< Offset trimming P */
-
-#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
- ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_TrimmingValue OPAMP Trimming Value
- * @{
- */
-
-#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
-
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_Input OPAMP Input
- * @{
- */
-
-#define OPAMP_INPUT_INVERTING ( 24U) /*!< Inverting input */
-#define OPAMP_INPUT_NONINVERTING ( 19U) /*!< Non inverting input */
-
-#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
- ((INPUT) == OPAMP_INPUT_NONINVERTING))
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_VREF OPAMP VREF
- * @{
- */
-
-#define OPAMP_VREF_3VDDA (0x00000000U) /*!< OPMAP Vref = 3.3U% VDDA */
-#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10U% VDDA */
-#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50U% VDDA */
-#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90U% VDDA */
-
-#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
- ((VREF) == OPAMP_VREF_10VDDA) || \
- ((VREF) == OPAMP_VREF_50VDDA) || \
- ((VREF) == OPAMP_VREF_90VDDA))
-
-/**
- * @}
- */
-
- /** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
- */
-
-#define OPAMP_VREF_NOTCONNECTEDTO_ADC (0x00000000U) /*!< VREF not connected to ADC */
-#define OPAMP_VREF_CONNECTEDTO_ADC (0x00000001U) /*!< VREF not connected to ADC */
-
-#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
- ((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
-
-
- /**
- * @}
- */
-
- /**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
- * @{
- */
-
-/** @brief Reset OPAMP handle state
- * @param __HANDLE__ OPAMP handle.
- * @retval None
- */
-#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Include OPAMP HAL Extended module */
-#include "stm32f3xx_hal_opamp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
- * @{
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* Peripheral State functions **************************************************/
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
-OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h
deleted file mode 100644
index 41176c7e9b4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_opamp_ex.h
- * @author MCD Application Team
- * @brief Header file of OPAMP HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_OPAMP_EX_H
-#define __STM32F3xx_HAL_OPAMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup OPAMPEx OPAMPEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
- * @{
- */
-
-/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
- * @{
- */
-
-/* I/O operation functions *****************************************************/
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC)
-
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
-
-#endif /* STM32F302xE || */
- /* STM32F302xC */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_OPAMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h
deleted file mode 100644
index fe633cc44f6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pccard.h
- * @author MCD Application Team
- * @brief Header file of PCCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_PCCARD_H
-#define __STM32F3xx_HAL_PCCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#include "stm32f3xx_ll_fmc.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCCARD
- * @{
- */
-
-/** @addtogroup PCCARD_Private_Constants
- * @{
- */
-
-#define PCCARD_DEVICE_ADDRESS FMC_BANK4
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
-#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
-
-/* Compact Flash-ATA registers description */
-#define ATA_DATA ((uint8_t)0x00U) /* Data register */
-#define ATA_SECTOR_COUNT ((uint8_t)0x02U) /* Sector Count register */
-#define ATA_SECTOR_NUMBER ((uint8_t)0x03U) /* Sector Number register */
-#define ATA_CYLINDER_LOW ((uint8_t)0x04U) /* Cylinder low register */
-#define ATA_CYLINDER_HIGH ((uint8_t)0x05U) /* Cylinder high register */
-#define ATA_CARD_HEAD ((uint8_t)0x06U) /* Card/Head register */
-#define ATA_STATUS_CMD ((uint8_t)0x07U) /* Status(read)/Command(write) register */
-#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0EU) /* Alternate Status(read)/Command(write) register */
-#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
-#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202U) /* Card Configuration and Status Register */
-
-/* Compact Flash-ATA commands */
-#define ATA_READ_SECTOR_CMD ((uint8_t)0x20U)
-#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30U)
-#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0U)
-#define ATA_IDENTIFY_CMD ((uint8_t)0xECU)
-
-/* Compact Flash status */
-#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60U)
-#define PCCARD_BUSY ((uint8_t)0x80U)
-#define PCCARD_PROGR ((uint8_t)0x01U)
-#define PCCARD_READY ((uint8_t)0x40U)
-
-#define PCCARD_SECTOR_SIZE (255U) /* In half words */
-
-
-/* Compact Flash redefinition */
-#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
-#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
-#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
-#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
-#define HAL_CF_Reset HAL_PCCARD_Reset
-
-#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
-#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
-
-#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define CF_ERROR HAL_PCCARD_STATUS_ERROR
-#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-#define HAL_PCCARD_StatusTypeDef HAL_PCCARD_StatusTypeDef
-
-
-#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
-#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
-#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
-#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
-
-#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
-#define CF_BUSY PCCARD_BUSY
-#define CF_PROGR PCCARD_PROGR
-#define CF_READY PCCARD_READY
-
-#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
- * @{
- */
-
-/**
- * @brief HAL PCCARD State structures definition
- */
-typedef enum
-{
- HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
- HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
- HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
- HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
-}HAL_PCCARD_StateTypeDef;
-
-typedef enum
-{
- HAL_PCCARD_STATUS_SUCCESS = 0U,
- HAL_PCCARD_STATUS_ONGOING,
- HAL_PCCARD_STATUS_ERROR,
- HAL_PCCARD_STATUS_TIMEOUT
-}HAL_PCCARD_StatusTypeDef;
-
-/**
- * @brief FMC_PCCARD handle Structure definition
- */
-typedef struct
-{
- FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
-
- FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
-
- __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
-
- HAL_LockTypeDef Lock; /*!< PCCARD Lock */
-
-}PCCARD_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
- * @{
- */
-
-/** @brief Reset PCCARD handle state
- * @param __HANDLE__ specifies the PCCARD handle.
- * @retval None
- */
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
- * @{
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
-
-/**
- * @}
- */
-
-/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_PCCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h
deleted file mode 100644
index 01d73e61651..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h
+++ /dev/null
@@ -1,891 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pcd.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_PCD_H
-#define __STM32F3xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
- * @{
- */
-
-/**
- * @brief PCD State structure definition
- */
-typedef enum
-{
- HAL_PCD_STATE_RESET = 0x00U,
- HAL_PCD_STATE_READY = 0x01U,
- HAL_PCD_STATE_ERROR = 0x02U,
- HAL_PCD_STATE_BUSY = 0x03U,
- HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
-/**
- * @brief PCD double buffered endpoint direction
- */
-typedef enum
-{
- PCD_EP_DBUF_OUT,
- PCD_EP_DBUF_IN,
- PCD_EP_DBUF_ERR,
-}PCD_EP_DBUF_DIR;
-
-/**
- * @brief PCD endpoint buffer number
- */
-typedef enum
-{
- PCD_EP_NOBUF,
- PCD_EP_BUF0,
- PCD_EP_BUF1
-}PCD_EP_BUF_NUM;
-
-/**
- * @brief PCD Initialization Structure definition
- */
-typedef struct
-{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Core_Speed */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref PCD_EP0_MPS */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_Core_PHY */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
-
-}PCD_InitTypeDef;
-
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref PCD_EP_Type */
-
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-
-}PCD_EPTypeDef;
-
-typedef USB_TypeDef PCD_TypeDef;
-
-/**
- * @brief PCD Handle Structure definition
- */
-typedef struct
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-
-} PCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Include PCD HAL Extension module */
-#include "stm32f3xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup PCD_Core_Speed PCD Core Speed
- * @{
- */
-#define PCD_SPEED_HIGH 0U /* Not Supported */
-#define PCD_SPEED_FULL 2U
-/**
- * @}
- */
-
- /** @defgroup PCD_Core_PHY PCD Core PHY
- * @{
- */
-#define PCD_PHY_EMBEDDED 2U
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__))))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
-
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\
- EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
- } while(0U)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
- EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
- EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
- } while(0U)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
- EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
- EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
- EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
- } while(0U)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
- * @{
- */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
- * @{
- */
-#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-/**
- * @}
- */
-
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
- * @{
- */
-#define DEP0CTL_MPS_64 0U
-#define DEP0CTL_MPS_32 1U
-#define DEP0CTL_MPS_16 2U
-#define DEP0CTL_MPS_8 3U
-
-#define PCD_EP0MPS_64 DEP0CTL_MPS_64
-#define PCD_EP0MPS_32 DEP0CTL_MPS_32
-#define PCD_EP0MPS_16 DEP0CTL_MPS_16
-#define PCD_EP0MPS_08 DEP0CTL_MPS_8
-/**
- * @}
- */
-
-/** @defgroup PCD_EP_Type PCD EP Type
- * @{
- */
-#define PCD_EP_TYPE_CTRL 0U
-#define PCD_EP_TYPE_ISOC 1U
-#define PCD_EP_TYPE_BULK 2U
-#define PCD_EP_TYPE_INTR 3U
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP PCD ENDP
- * @{
- */
-#define PCD_ENDP0 ((uint8_t)0U)
-#define PCD_ENDP1 ((uint8_t)1U)
-#define PCD_ENDP2 ((uint8_t)2U)
-#define PCD_ENDP3 ((uint8_t)3U)
-#define PCD_ENDP4 ((uint8_t)4U)
-#define PCD_ENDP5 ((uint8_t)5U)
-#define PCD_ENDP6 ((uint8_t)6U)
-#define PCD_ENDP7 ((uint8_t)7U)
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
- * @{
- */
-#define PCD_SNG_BUF 0U
-#define PCD_DBL_BUF 1U
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Internal macros -----------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
-
-
-
-/**
- * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wType Endpoint Type.
- * @retval None
- */
-#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
-
-/**
- * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval Endpoint Type
- */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
-
-
-/**
- * @brief free buffer used from the application realizing it to the line
- toggles bit SW_BUF in the double buffered endpoint register
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bDir Direction
- * @retval None
- */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
- if ((bDir) == PCD_EP_DBUF_OUT)\
- { /* OUT double buffered endpoint */\
- PCD_TX_DTOG((USBx), (bEpNum));\
- }\
- else if ((bDir) == PCD_EP_DBUF_IN)\
- { /* IN double buffered endpoint */\
- PCD_RX_DTOG((USBx), (bEpNum));\
- }\
-}
-
-/**
- * @brief gets direction of the double buffered endpoint
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval EP_DBUF_OUT, EP_DBUF_IN,
- * EP_DBUF_ERR if the endpoint counter not yet programmed.
- */
-#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
- if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
- return(PCD_EP_DBUF_OUT);\
- else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
- return(PCD_EP_DBUF_IN);\
- else\
- return(PCD_EP_DBUF_ERR);\
-}
-
-/**
- * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wState new state
- * @retval None
- */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
- \
- _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wState))!= 0U)\
- { \
- _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
- { \
- _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
- } /* PCD_SET_EP_TX_STATUS */
-
-/**
- * @brief sets the status for rx transfer (bits STAT_TX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wState new state
- * @retval None
- */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
- register uint16_t _wRegVal; \
- \
- _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & (wState))!= 0U) \
- { \
- _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
- { \
- _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
- } /* PCD_SET_EP_RX_STATUS */
-
-/**
- * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wStaterx new state.
- * @param wStatetx new state.
- * @retval None
- */
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
- register uint32_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
- } /* PCD_SET_EP_TXRX_STATUS */
-
-/**
- * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
- * /STAT_RX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval status
- */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
-
-/**
- * @brief sets directly the VALID tx/rx-status into the endpoint register
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
- * @brief checks stall condition in an endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval TRUE = endpoint in stall condition.
- */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
- == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
- == USB_EP_RX_STALL)
-
-/**
- * @brief set & clear EP_KIND bit.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
-
-/**
- * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Sets/clears directly EP_KIND bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
-
-/**
- * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
-#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
-
-/**
- * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
- { \
- PCD_RX_DTOG((USBx),(bEpNum));\
- }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
- {\
- PCD_TX_DTOG((USBx),(bEpNum));\
- }
-
-/**
- * @brief Sets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bAddr Address.
- * @retval None
- */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
- USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
-
-/**
- * @brief Gets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-/**
- * @brief sets address of the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wAddr address to be set (must be word aligned).
- * @retval None
- */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
-
-/**
- * @brief Gets address of the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval address of the buffer.
- */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Sets counter of rx buffer with no. of blocks.
- * @param dwReg Register
- * @param wCount Counter.
- * @param wNBlocks no. of Blocks.
- * @retval None
- */
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 5U;\
- if(((wCount) & 0x1fU) == 0U)\
- { \
- (wNBlocks)--;\
- } \
- *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
- }/* PCD_CALC_BLK32 */
-
-
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 1U;\
- if(((wCount) & 0x1U) != 0U)\
- { \
- (wNBlocks)++;\
- } \
- *pdwReg = (uint16_t)((wNBlocks) << 10U);\
- }/* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
- uint16_t wNBlocks;\
- if((wCount) > 62U) \
- { \
- PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
- } \
- else \
- { \
- PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
- } \
- }/* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
- }
-
-/**
- * @brief sets counter for the tx/rx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wCount Counter value.
- * @retval None
- */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
-
-/**
- * @brief gets counter of the tx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval Counter value
- */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
-
-/**
- * @brief Sets buffer 0/1 address in a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @retval Counter value
- */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
-
-/**
- * @brief Sets addresses in a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @param wBuf1Addr = buffer 1 address.
- * @retval None
- */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
- PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
- PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
- } /* PCD_SET_EP_DBUF_ADDR */
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bDir endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
- * @param wCount Counter value
- * @retval None
- */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
- /* OUT endpoint */ \
- {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
- else if((bDir) == PCD_EP_DBUF_IN)\
- { \
- *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } \
- } /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
- {/* OUT endpoint */ \
- PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
- } \
- else if((bDir) == PCD_EP_DBUF_IN)\
- {/* IN endpoint */ \
- *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } \
- } /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
- PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
- PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
- } /
-
-/**
- * @brief Gets buffer 0/1 rx/tx counter for double buffering.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-/**
- * @}
- */
-
-/** @defgroup PCD_Instance_definition PCD Instance definition
- * @{
- */
-#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* Peripheral State functions **************************************************/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/** @addtogroup PCDEx_Private_Functions PCD Extended Private Functions
- * @{
- */
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h
deleted file mode 100644
index 78bd5ae4837..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pcd_ex.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_PCD_EX_H
-#define __STM32F3xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCDEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCDEx_Exported_Macros PCD Extended Exported Macros
- * @{
- */
-/**
- * @brief Gets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval None
- */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F373xC)
-
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
-
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
- PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
- }
-
-#endif /* STM32F302xC || STM32F303xC || */
- /* STM32F373xC */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302x8)
-
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U)))))
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\
- PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
- }
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302x8 */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
-
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h
deleted file mode 100644
index 91c10a3c0b5..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_PWR_H
-#define __STM32F3xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
- * @{
- */
-
-#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */
-#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */
-#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag PWR Flag
- * @{
- */
-#define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */
-#define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */
-#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
- * @{
- */
-
-/** @brief Check PWR flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
- * voltage VREFINT is ready.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the PWR's pending flags.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
- ((PIN) == PWR_WAKEUP_PIN2) || \
- ((PIN) == PWR_WAKEUP_PIN3))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
- * @}
- */
-
-/* Include PWR HAL Extended module */
-#include "stm32f3xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h
deleted file mode 100644
index e892e7b2478..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pwr_ex.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_PWR_EX_H
-#define __STM32F3xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWREx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
- This parameter can be a value of @ref PWREx_PVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWREx_PVD_Mode */
-}PWR_PVDTypeDef;
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */
-#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */
-#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */
-#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */
-#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */
-#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */
-#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */
-/**
- * @}
- */
-
-/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
- * @{
- */
-#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */
-#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */
-#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */
-/**
- * @}
- */
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/**
- * @brief Enable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Disable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Enable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Disable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-/**
- * @brief PVD EXTI line configuration: set falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
-
-/**
- * @brief PVD EXTI line configuration: set rising edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Clear the PVD EXTI flag.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_NORMAL))
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
- ((SDADC) == PWR_SDADC_ANALOG2) || \
- ((SDADC) == PWR_SDADC_ANALOG3))
-#endif /* STM32F373xC || STM32F378xx */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
- * @{
- */
-/* Peripheral Extended control functions **************************************/
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-void HAL_PWREx_EnableSDADC(uint32_t Analogx);
-void HAL_PWREx_DisableSDADC(uint32_t Analogx);
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h
deleted file mode 100644
index b2e8f19d89e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h
+++ /dev/null
@@ -1,1756 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RCC_H
-#define __STM32F3xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/** @addtogroup RCC_Private_Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
-#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
-#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
-/**
- * @}
- */
-
-/** @defgroup RCC_Register_Offset Register offsets
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET 0x00
-#define RCC_CFGR_OFFSET 0x04
-#define RCC_CIR_OFFSET 0x08
-#define RCC_BDCR_OFFSET 0x20
-#define RCC_CSR_OFFSET 0x24
-
-/**
- * @}
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
-#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
-
-/* --- BDCR Registers ---*/
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
-
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
-
-/**
- * @}
- */
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1U)
-#define BDCR_REG_INDEX ((uint8_t)2U)
-#define CSR_REG_INDEX ((uint8_t)3U)
-#define CFGR_REG_INDEX ((uint8_t)4U)
-
-#define RCC_FLAG_MASK ((uint8_t)0x1FU)
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
-#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
- ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
- ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
- ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
- ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
- ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
- ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
- ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
-#else
-#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
- ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
-#endif
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
-#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
- ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
- ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
- ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
- ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
- ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
- ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
- ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
-
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
- ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
- ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
- ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
- ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
- ((__MUL__) == RCC_PLL_MUL16))
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-#if defined(RCC_CFGR3_USART2SW)
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-#endif /* RCC_CFGR3_USART2SW */
-#if defined(RCC_CFGR3_USART3SW)
-#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
-#endif /* RCC_CFGR3_USART3SW */
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
-
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
-
-#endif
-} RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
- */
-typedef struct
-{
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
- uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
- This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
-
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
-
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-
-} RCC_OscInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
-
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
-#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
-#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
-#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
-#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
-#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
-#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
-#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
-#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
- * @{
- */
-#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
-#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
-#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
-#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
-#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
-#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
-#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
-#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
-#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
-#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
-#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
-#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
-#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
-#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
-#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
-
-/**
- * @}
- */
-
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
-/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
- * @{
- */
-
-#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
-#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
-#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
-#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
-#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
-#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
-#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
-#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
-#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
-#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
-#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
-#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
-#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
-#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
-#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
-#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
-
-/**
- * @}
- */
-
-#endif
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
-/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
- * @{
- */
-
-#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
-#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
-#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
-#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
-#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
-#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
-#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
-#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
-#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
-#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
-#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
-#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
-#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
-#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
-#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
-
-/**
- * @}
- */
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
-
-#if defined(RCC_CFGR3_USART2SW)
-/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
- * @{
- */
-#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
-#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
-#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
-#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
-
-/**
- * @}
- */
-#endif /* RCC_CFGR3_USART2SW */
-
-#if defined(RCC_CFGR3_USART3SW)
-/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
- * @{
- */
-#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
-#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
-#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
-#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
-
-/**
- * @}
- */
-#endif /* RCC_CFGR3_USART3SW */
-
-/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
- * @{
- */
-#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
-#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
-
-/**
- * @}
- */
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-#define RCC_MCO1 (0x00000000U)
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: XXXYYYYYb
- * - YYYYY : Flag position in the register
- * - XXX : Register index
- * - 001: CR register
- * - 010: BDCR register
- * - 011: CSR register
- * - 100: CFGR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
-#if defined(RCC_CSR_V18PWRRSTF)
-#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
-#endif
-#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
-
-/* Flags in the CFGR register */
-#if defined(RCC_CFGR_MCOF)
-#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
-#endif /* RCC_CFGR_MCOF */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
- * @brief Enable or disable the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TSC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
-#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
-#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
-#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
-#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief EGet the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
- * @brief Force or release AHB peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
-#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-
-#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
-#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
- (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
- * @{
- */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if ((__STATE__) == RCC_HSE_OFF) \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- else if ((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if ((__STATE__) == RCC_LSE_OFF) \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- else if ((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the USART1 clock (USART1CLK).
- * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
- * This parameter can be one of the following values:
- @if STM32F302xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F303xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F358xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F302xE
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F303xE
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F398xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F373xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F378xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F301x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F302x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F318xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F303x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F334x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F328xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
- */
-#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
-
-/** @brief Macro to get the USART1 clock source.
- * @retval The clock source can be one of the following values:
- @if STM32F302xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F303xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F358xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F302xE
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F303xE
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F398xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F373xC
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F378xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
- @endif
- @if STM32F301x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F302x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F318xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F303x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F334x8
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- @if STM32F328xx
- * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
- @endif
- * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
- * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
- */
-#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
-
-#if defined(RCC_CFGR3_USART2SW)
-/** @brief Macro to configure the USART2 clock (USART2CLK).
- * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- */
-#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
-
-/** @brief Macro to get the USART2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
- * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
- */
-#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
-#endif /* RCC_CFGR3_USART2SW */
-
-#if defined(RCC_CFGR3_USART3SW)
-/** @brief Macro to configure the USART3 clock (USART3CLK).
- * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- */
-#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
-
-/** @brief Macro to get the USART3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
- * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
- */
-#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
-#endif /* RCC_CFGR3_USART2SW */
-/**
- * @}
- */
-
-/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the I2C1 clock (I2C1CLK).
- * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
- */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
-
-/** @brief Macro to get the I2C1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
- * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
- */
-#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
- * @{
- */
-
-/** @brief Macro to enable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-
-/** @brief Macro to disable the main PLL.
- * @note The main PLL can not be disabled if it is used as system clock source
- */
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-
-/** @brief Get oscillator clock selected as PLL input clock
- * @retval The clock source used for PLL entry. The returned value can be one
- * of the following:
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
- * @{
- */
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
- * @{
- */
-
-#if defined(RCC_CFGR_MCOPRE)
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
- * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
- * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
- * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
- * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
- * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
- * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
- * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
- */
-#else
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
- */
-#endif
-#if defined(RCC_CFGR_MCOPRE)
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-#else
-
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-
-#endif
-
-/**
- * @}
- */
-
- /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
- * @{
- */
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it cannot be changed unless the
- * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
- * a Power On Reset (POR).
- *
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
- * the RTC cannot be used in STOP and STANDBY modes.
- * @note The system must always be configured so as to get a PCLK frequency greater than or
- * equal to the RTCCLK frequency for a proper operation of the RTC.
- */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-/** @brief Macro to get the RTC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macro to enable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-
-/** @brief Macro to disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief Macro to force the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-
-/** @brief Macros to release the Backup domain reset.
- */
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
-
-/** @brief Check RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
- * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
- * @arg @ref RCC_FLAG_PINRST Pin reset.
- * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
- * @arg @ref RCC_FLAG_SFTRST Software reset.
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
- @if defined(STM32F301x8)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F302x8)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F302xC)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
- @endif
- @if defined(STM32F302xE)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F303x8)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F303xC)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
- @endif
- @if defined(STM32F303xE)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F334x8)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- @if defined(STM32F358xx)
- * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
- @endif
- @if defined(STM32F373xC)
- * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
- @endif
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
- (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
- (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
- RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extension module */
-#include "stm32f3xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ******************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h
deleted file mode 100644
index aadf44b0758..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,3843 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RCC_EX_H
-#define __STM32F3xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#if defined(RCC_CFGR_PLLNODIV)
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
- ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
- ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
-#else
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
- ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
- ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
-#endif /* RCC_CFGR_PLLNODIV */
-
-#if defined(STM32F301x8) || defined(STM32F318xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
- RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
- RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
-#endif /* STM32F301x8 || STM32F318xx */
-#if defined(STM32F302x8)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
- RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
- RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
- RCC_PERIPHCLK_TIM17))
-#endif /* STM32F302x8 */
-#if defined(STM32F302xC)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
- RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
-#endif /* STM32F302xC */
-#if defined(STM32F303xC)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
-#endif /* STM32F303xC */
-#if defined(STM32F302xE)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
- RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
- RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
- RCC_PERIPHCLK_TIM17))
-#endif /* STM32F302xE */
-#if defined(STM32F303xE)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
- RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
- RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
-#endif /* STM32F303xE */
-#if defined(STM32F398xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
- RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
- RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
- RCC_PERIPHCLK_TIM20))
-#endif /* STM32F398xx */
-#if defined(STM32F358xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
- RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
- RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
-#endif /* STM32F358xx */
-#if defined(STM32F303x8)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
- RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
-#endif /* STM32F303x8 */
-#if defined(STM32F334x8)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
- RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
- RCC_PERIPHCLK_RTC))
-#endif /* STM32F334x8 */
-#if defined(STM32F328xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
- RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
-#endif /* STM32F328xx */
-#if defined(STM32F373xC)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
-#endif /* STM32F373xC */
-#if defined(STM32F378xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
- RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
-#endif /* STM32F378xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
-#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
-#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
- ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
-#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
-#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
- ((SOURCE) == RCC_TIM1CLK_PLLCLK))
-#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
- ((SOURCE) == RCC_TIM15CLK_PLLCLK))
-#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
- ((SOURCE) == RCC_TIM16CLK_PLLCLK))
-#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
- ((SOURCE) == RCC_TIM17CLK_PLLCLK))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
-#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
-#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
-#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
- ((SOURCE) == RCC_TIM1CLK_PLLCLK))
-#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
-#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
-#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
-#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
-#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
-#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
- ((SOURCE) == RCC_TIM1CLK_PLLCLK))
-#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
- ((SOURCE) == RCC_TIM2CLK_PLLCLK))
-#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
- ((SOURCE) == RCC_TIM34CLK_PLLCLK))
-#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
- ((SOURCE) == RCC_TIM15CLK_PLLCLK))
-#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
- ((SOURCE) == RCC_TIM16CLK_PLLCLK))
-#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
- ((SOURCE) == RCC_TIM17CLK_PLLCLK))
-#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
-#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
- ((SOURCE) == RCC_TIM20CLK_PLLCLK))
-#endif /* STM32F303xE || STM32F398xx */
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
- ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
-#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
- ((SOURCE) == RCC_TIM8CLK_PLLCLK))
-#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
- ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
-#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
- ((SOURCE) == RCC_TIM1CLK_PLLCLK))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-#if defined(STM32F334x8)
-#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
- ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
-#endif /* STM32F334x8 */
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
-#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
-#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
- ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
-#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_CECCLKSOURCE_LSE))
-#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
- ((DIV) == RCC_SDADCSYSCLK_DIV48))
-#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-#if defined(RCC_CFGR_MCOPRE)
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
- ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
- ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
- ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
-#else
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
-#endif /* RCC_CFGR_MCOPRE */
-
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
- ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-/**
- * @brief RCC extended clocks structure definition
- */
-#if defined(STM32F301x8) || defined(STM32F318xx)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< I2C3 clock source
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
- uint32_t Adc1ClockSelection; /*!< ADC1 clock source
- This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim15ClockSelection; /*!< TIM15 clock source
- This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
-
- uint32_t Tim16ClockSelection; /*!< TIM16 clock source
- This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
-
- uint32_t Tim17ClockSelection; /*!< TIM17 clock source
- This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F301x8 || STM32F318xx */
-
-#if defined(STM32F302x8)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< I2C3 clock source
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
- uint32_t Adc1ClockSelection; /*!< ADC1 clock source
- This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim15ClockSelection; /*!< TIM15 clock source
- This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
-
- uint32_t Tim16ClockSelection; /*!< TIM16 clock source
- This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
-
- uint32_t Tim17ClockSelection; /*!< TIM17 clock source
- This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F302x8 */
-
-#if defined(STM32F302xC)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F302xC */
-
-#if defined(STM32F303xC)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
- This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim8ClockSelection; /*!< TIM8 clock source
- This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F303xC */
-
-#if defined(STM32F302xE)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< I2C3 clock source
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim2ClockSelection; /*!< TIM2 clock source
- This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
-
- uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
- This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
-
- uint32_t Tim15ClockSelection; /*!< TIM15 clock source
- This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
-
- uint32_t Tim16ClockSelection; /*!< TIM16 clock source
- This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
-
- uint32_t Tim17ClockSelection; /*!< TIM17 clock source
- This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F302xE */
-
-#if defined(STM32F303xE)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< I2C3 clock source
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
- This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim2ClockSelection; /*!< TIM2 clock source
- This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
-
- uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
- This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
-
- uint32_t Tim8ClockSelection; /*!< TIM8 clock source
- This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
-
- uint32_t Tim15ClockSelection; /*!< TIM15 clock source
- This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
-
- uint32_t Tim16ClockSelection; /*!< TIM16 clock source
- This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
-
- uint32_t Tim17ClockSelection; /*!< TIM17 clock source
- This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
-
- uint32_t Tim20ClockSelection; /*!< TIM20 clock source
- This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F303xE */
-
-#if defined(STM32F398xx)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t I2c3ClockSelection; /*!< I2C3 clock source
- This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
- This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim2ClockSelection; /*!< TIM2 clock source
- This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
-
- uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
- This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
-
- uint32_t Tim8ClockSelection; /*!< TIM8 clock source
- This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
-
- uint32_t Tim15ClockSelection; /*!< TIM15 clock source
- This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
-
- uint32_t Tim16ClockSelection; /*!< TIM16 clock source
- This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
-
- uint32_t Tim17ClockSelection; /*!< TIM17 clock source
- This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
-
- uint32_t Tim20ClockSelection; /*!< TIM20 clock source
- This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F398xx */
-
-#if defined(STM32F358xx)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t Uart4ClockSelection; /*!< UART4 clock source
- This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
-
- uint32_t Uart5ClockSelection; /*!< UART5 clock source
- This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
- This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
-
- uint32_t I2sClockSelection; /*!< I2S clock source
- This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Tim8ClockSelection; /*!< TIM8 clock source
- This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F358xx */
-
-#if defined(STM32F303x8)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F303x8 */
-
-#if defined(STM32F334x8)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
- uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
- This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F334x8 */
-
-#if defined(STM32F328xx)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
- This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
-
- uint32_t Tim1ClockSelection; /*!< TIM1 clock source
- This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F328xx */
-
-#if defined(STM32F373xC)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t Adc1ClockSelection; /*!< ADC1 clock source
- This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
-
- uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
- This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
-
- uint32_t CecClockSelection; /*!< HDMI CEC clock source
- This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
-
- uint32_t USBClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F373xC */
-
-#if defined(STM32F378xx)
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
- uint32_t Usart2ClockSelection; /*!< USART2 clock source
- This parameter can be a value of @ref RCC_USART2_Clock_Source */
-
- uint32_t Usart3ClockSelection; /*!< USART3 clock source
- This parameter can be a value of @ref RCC_USART3_Clock_Source */
-
- uint32_t I2c1ClockSelection; /*!< I2C1 clock source
- This parameter can be a value of @ref RCC_I2C1_Clock_Source */
-
- uint32_t I2c2ClockSelection; /*!< I2C2 clock source
- This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
-
- uint32_t Adc1ClockSelection; /*!< ADC1 clock source
- This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
-
- uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
- This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
-
- uint32_t CecClockSelection; /*!< HDMI CEC clock source
- This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
-
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F378xx */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
- * @{
- */
-/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
-#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
-#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
-#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
-#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
-#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
-#if defined(RCC_CFGR_PLLNODIV)
-#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
-#endif /* RCC_CFGR_PLLNODIV */
-#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F318xx)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC1 (0x00000080U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_I2C3 (0x00008000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_TIM15 (0x00040000U)
-#define RCC_PERIPHCLK_TIM16 (0x00080000U)
-#define RCC_PERIPHCLK_TIM17 (0x00100000U)
-
-#endif /* STM32F301x8 || STM32F318xx */
-
-#if defined(STM32F302x8)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC1 (0x00000080U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_I2C3 (0x00008000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-#define RCC_PERIPHCLK_TIM15 (0x00040000U)
-#define RCC_PERIPHCLK_TIM16 (0x00080000U)
-#define RCC_PERIPHCLK_TIM17 (0x00100000U)
-
-
-#endif /* STM32F302x8 */
-
-#if defined(STM32F302xC)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-
-#endif /* STM32F302xC */
-
-#if defined(STM32F303xC)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_ADC34 (0x00000100U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_TIM8 (0x00002000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-
-#endif /* STM32F303xC */
-
-#if defined(STM32F302xE)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-#define RCC_PERIPHCLK_I2C3 (0x00040000U)
-#define RCC_PERIPHCLK_TIM2 (0x00100000U)
-#define RCC_PERIPHCLK_TIM34 (0x00200000U)
-#define RCC_PERIPHCLK_TIM15 (0x00400000U)
-#define RCC_PERIPHCLK_TIM16 (0x00800000U)
-#define RCC_PERIPHCLK_TIM17 (0x01000000U)
-
-#endif /* STM32F302xE */
-
-#if defined(STM32F303xE)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_ADC34 (0x00000100U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_TIM8 (0x00002000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-#define RCC_PERIPHCLK_I2C3 (0x00040000U)
-#define RCC_PERIPHCLK_TIM2 (0x00100000U)
-#define RCC_PERIPHCLK_TIM34 (0x00200000U)
-#define RCC_PERIPHCLK_TIM15 (0x00400000U)
-#define RCC_PERIPHCLK_TIM16 (0x00800000U)
-#define RCC_PERIPHCLK_TIM17 (0x01000000U)
-#define RCC_PERIPHCLK_TIM20 (0x02000000U)
-
-#endif /* STM32F303xE */
-
-#if defined(STM32F398xx)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_ADC34 (0x00000100U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_TIM8 (0x00002000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_I2C3 (0x00040000U)
-#define RCC_PERIPHCLK_TIM2 (0x00100000U)
-#define RCC_PERIPHCLK_TIM34 (0x00200000U)
-#define RCC_PERIPHCLK_TIM15 (0x00400000U)
-#define RCC_PERIPHCLK_TIM16 (0x00800000U)
-#define RCC_PERIPHCLK_TIM17 (0x01000000U)
-#define RCC_PERIPHCLK_TIM20 (0x02000000U)
-
-
-#endif /* STM32F398xx */
-
-#if defined(STM32F358xx)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_UART4 (0x00000008U)
-#define RCC_PERIPHCLK_UART5 (0x00000010U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_ADC34 (0x00000100U)
-#define RCC_PERIPHCLK_I2S (0x00000200U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_TIM8 (0x00002000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-
-#endif /* STM32F358xx */
-
-#if defined(STM32F303x8)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-
-#endif /* STM32F303x8 */
-
-#if defined(STM32F334x8)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-
-
-#endif /* STM32F334x8 */
-
-#if defined(STM32F328xx)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_ADC12 (0x00000080U)
-#define RCC_PERIPHCLK_TIM1 (0x00001000U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-
-#endif /* STM32F328xx */
-
-#if defined(STM32F373xC)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC1 (0x00000080U)
-#define RCC_PERIPHCLK_CEC (0x00000400U)
-#define RCC_PERIPHCLK_SDADC (0x00000800U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-#define RCC_PERIPHCLK_USB (0x00020000U)
-
-#endif /* STM32F373xC */
-
-#if defined(STM32F378xx)
-#define RCC_PERIPHCLK_USART1 (0x00000001U)
-#define RCC_PERIPHCLK_USART2 (0x00000002U)
-#define RCC_PERIPHCLK_USART3 (0x00000004U)
-#define RCC_PERIPHCLK_I2C1 (0x00000020U)
-#define RCC_PERIPHCLK_I2C2 (0x00000040U)
-#define RCC_PERIPHCLK_ADC1 (0x00000080U)
-#define RCC_PERIPHCLK_CEC (0x00000400U)
-#define RCC_PERIPHCLK_SDADC (0x00000800U)
-#define RCC_PERIPHCLK_RTC (0x00010000U)
-
-#endif /* STM32F378xx */
-/**
- * @}
- */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
-#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
-#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
- * @{
- */
-#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
-#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
- * @{
- */
-#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
-#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
-#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
-#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
-#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
-#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
-#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
-#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
-#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
-#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
-#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
-#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
-#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
-#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
- * @{
- */
-#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
- * @{
- */
-#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
-#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
- * @{
- */
-#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
-#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
- * @{
- */
-#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
-#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
-
-/**
- * @}
- */
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
-#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
-#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
- * @{
- */
-
-/* ADC1 & ADC2 */
-#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
-#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
-#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
-#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
-#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
-#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
-#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
-#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
-#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
-#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
-#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
-#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
-#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
-#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
-
-/**
- * @}
- */
-/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
- * @{
- */
-#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
- * @{
- */
-#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
-#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
-#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
-#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
- * @{
- */
-#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
-#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
-#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
-#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
-
-/**
- * @}
- */
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
-#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
-#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
- * @{
- */
-#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
-#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
- * @{
- */
-
-/* ADC1 & ADC2 */
-#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
-#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
-#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
-#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
-#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
-#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
-#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
-#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
-#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
-#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
-#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
-#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
-#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
- * @{
- */
-#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
-#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
- * @{
- */
-#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
- * @{
- */
-#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
-#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
- * @{
- */
-#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
-#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
- * @{
- */
-#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
-#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
- * @{
- */
-#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
-#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
- * @{
- */
-#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
-#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
- * @{
- */
-#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
-#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
-#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
-#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
- * @{
- */
-#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
-#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
-#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
-#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
- * @{
- */
-#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
-#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
-
-/**
- * @}
- */
-#endif /* STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-
-/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
- * @{
- */
-
-/* ADC3 & ADC4 */
-#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
-#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
-#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
-#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
-#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
-#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
-#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
-#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
-#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
-#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
-#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
-#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
-#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
- * @{
- */
-#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
-#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
-
-/**
- * @}
- */
-
-#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
-#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
-#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
- * @{
- */
-/* ADC1 & ADC2 */
-#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
-#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
-#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
-#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
-#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
-#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
-#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
-#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
-#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
-#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
-#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
-#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
-#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
- * @{
- */
-#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
-#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
-
-/**
- * @}
- */
-
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-
-/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
- * @{
- */
-#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
-#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
-
-/**
- * @}
- */
-
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
- * @{
- */
-#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
-#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
-#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
-#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
- * @{
- */
-#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
-#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
- * @{
- */
-
-/* ADC1 */
-#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
-#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
-#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
-#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
- * @{
- */
-#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
-#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
- * @{
- */
-#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
-#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
-#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
-#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
-#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
-#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
-#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
-#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
-#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
-#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
-#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
-#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
-#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
-#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
-#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
-#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
-#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
-
-/**
- * @}
- */
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
- * @{
- */
-
-#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
-#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-
-/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
- * @{
- */
-#if defined(RCC_CFGR_MCOPRE)
-
-#define RCC_MCODIV_1 (0x00000000U)
-#define RCC_MCODIV_2 (0x10000000U)
-#define RCC_MCODIV_4 (0x20000000U)
-#define RCC_MCODIV_8 (0x30000000U)
-#define RCC_MCODIV_16 (0x40000000U)
-#define RCC_MCODIV_32 (0x50000000U)
-#define RCC_MCODIV_64 (0x60000000U)
-#define RCC_MCODIV_128 (0x70000000U)
-
-#else
-
-#define RCC_MCODIV_1 (0x00000000U)
-
-#endif /* RCC_CFGR_MCOPRE */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
- * @{
- */
-
-#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
-#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
-#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
-#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-/** @brief Macro to configure the PLL clock source, multiplication and division factors.
- * @note This macro must be used only when the PLL is disabled.
- *
- * @param __RCC_PLLSource__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
- * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
- * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
- * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
- do { \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
- } while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-/** @brief Macro to configure the PLL clock source and multiplication factor.
- * @note This macro must be used only when the PLL is disabled.
- *
- * @param __RCC_PLLSource__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
- * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
- /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
- * @note Predivision factor can not be changed if PLL is used as system clock
- * In this case, you have to select another source of the system clock, disable the PLL and
- * then change the HSE predivision factor.
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
- */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
-
-/**
- * @brief Macro to get prediv1 factor for PLL.
- */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
-
-/**
- * @}
- */
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
- /* STM32F373xC || STM32F378xx */
-
-/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
- * @brief Enable or disable the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
-#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
-#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_ADC34_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
-#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
-
-#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
-#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_FMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_CEC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) \
- || defined(STM32F303xC) || defined(STM32F358xx) \
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-#define __HAL_RCC_USB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if !defined(STM32F301x8)
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
-#endif /* STM32F301x8*/
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
-#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
-#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
-#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
- UNUSED(tmpreg); \
- } while(0U)
-#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
-#endif /* STM32F303xE || STM32F398xx */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
-
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
-
-#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
-
-#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
-
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) \
- || defined(STM32F303xC) || defined(STM32F358xx) \
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
-
-#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if !defined(STM32F301x8)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
-
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
-#endif /* STM32F301x8*/
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
-
-#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
-#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
-#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
-#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
-
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
-#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
-#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
-#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
-
-#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
-#endif /* STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
- * @brief Force or release AHB peripheral reset.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
-
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
-#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
-#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
-
-#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
-#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
-
-#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
-/* Aliases for STM32 F3 compatibility */
-#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
-#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
-
-#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
-
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
-#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
-#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-
-#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if !defined(STM32F301x8)
-#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
-
-#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
-#endif /* STM32F301x8*/
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
-
-#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
-#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
-#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
-#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
-
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
-#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
-#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
-#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
-
-#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
-#endif /* STM32F303xE || STM32F398xx */
-
-/**
- * @}
- */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the I2C2 clock (I2C2CLK).
- * @param __I2C2CLKSource__ specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
-
-/** @brief Macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
-
-/** @brief Macro to configure the I2C3 clock (I2C3CLK).
- * @param __I2C3CLKSource__ specifies the I2C3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
-
-/** @brief Macro to get the I2C3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the TIM1 clock (TIM1CLK).
- * @param __TIM1CLKSource__ specifies the TIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
-
-/** @brief Macro to get the TIM1 clock (TIM1CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
-
-/** @brief Macro to configure the TIM15 clock (TIM15CLK).
- * @param __TIM15CLKSource__ specifies the TIM15 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
- * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
- */
-#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
-
-/** @brief Macro to get the TIM15 clock (TIM15CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
- * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
- */
-#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
-
-/** @brief Macro to configure the TIM16 clock (TIM16CLK).
- * @param __TIM16CLKSource__ specifies the TIM16 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
- * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
- */
-#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
-
-/** @brief Macro to get the TIM16 clock (TIM16CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
- * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
- */
-#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
-
-/** @brief Macro to configure the TIM17 clock (TIM17CLK).
- * @param __TIM17CLKSource__ specifies the TIM17 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
- * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
- */
-#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
-
-/** @brief Macro to get the TIM17 clock (TIM17CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
- * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
- */
-#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
- * @{
- */
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __I2SCLKSource__ specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
- * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- */
-#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
-
-/** @brief Macro to get the I2S clock source (I2SCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
- * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- */
-#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the ADC1 clock (ADC1CLK).
- * @param __ADC1CLKSource__ specifies the ADC1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
- * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
- */
-#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
-
-/** @brief Macro to get the ADC1 clock
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
- * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
- * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
- */
-#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
-/**
- * @}
- */
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the I2C2 clock (I2C2CLK).
- * @param __I2C2CLKSource__ specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
-
-/** @brief Macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
- * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
- * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
- */
-#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
-
-/** @brief Macro to get the ADC1 & ADC2 clock
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
- * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
- */
-#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the TIM1 clock (TIM1CLK).
- * @param __TIM1CLKSource__ specifies the TIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
-
-/** @brief Macro to get the TIM1 clock (TIM1CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __I2SCLKSource__ specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
- * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- */
-#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
-
-/** @brief Macro to get the I2S clock source (I2SCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
- * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
- * used as I2S clock source
- */
-#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the UART4 clock (UART4CLK).
- * @param __UART4CLKSource__ specifies the UART4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- */
-#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
-
-/** @brief Macro to get the UART4 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
- * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
- */
-#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
-
-/** @brief Macro to configure the UART5 clock (UART5CLK).
- * @param __UART5CLKSource__ specifies the UART5 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- */
-#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
-
-/** @brief Macro to get the UART5 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
- * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
- */
-#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
- * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
- * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
- */
-#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
-
-/** @brief Macro to get the ADC3 & ADC4 clock
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
- * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
- * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
- */
-#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the TIM8 clock (TIM8CLK).
- * @param __TIM8CLKSource__ specifies the TIM8 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
- * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
- */
-#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
-
-/** @brief Macro to get the TIM8 clock (TIM8CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
- * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
- */
-#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
-
-/**
- * @}
- */
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
- * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
- * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
- */
-#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
-
-/** @brief Macro to get the ADC1 & ADC2 clock
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
- * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
- * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
- */
-#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the TIM1 clock (TIM1CLK).
- * @param __TIM1CLKSource__ specifies the TIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
-
-/** @brief Macro to get the TIM1 clock (TIM1CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
- * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
- */
-#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
-/**
- * @}
- */
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F334x8)
-/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the HRTIM1 clock.
- * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
- * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
- */
-#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
-
-/** @brief Macro to get the HRTIM1 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
- * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
- */
-#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
-/**
- * @}
- */
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
- * @{
- */
-/** @brief Macro to configure the I2C2 clock (I2C2CLK).
- * @param __I2C2CLKSource__ specifies the I2C2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
-
-/** @brief Macro to get the I2C2 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
- * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
- */
-#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
- * @{
- */
-/** @brief Macro to configure the ADC1 clock (ADC1CLK).
- * @param __ADC1CLKSource__ specifies the ADC1 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
- */
-#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
-
-/** @brief Macro to get the ADC1 clock (ADC1CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
- * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
- */
-#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
- * @{
- */
-/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
- * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
- */
-#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
-
-/** @brief Macro to get the SDADCx clock prescaler.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
- * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
- */
-#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
- * @{
- */
-/** @brief Macro to configure the CEC clock.
- * @param __CECCLKSource__ specifies the CEC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
- * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
- */
-#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
-
-/** @brief Macro to get the HDMI CEC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
- * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
- */
-#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
-/**
- * @}
- */
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-
-/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
- * @{
- */
-/** @brief Macro to configure the USB clock (USBCLK).
- * @param __USBCLKSource__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
-
-/** @brief Macro to get the USB clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
- * @{
- */
-/** @brief Macro to configure the I2C3 clock (I2C3CLK).
- * @param __I2C3CLKSource__ specifies the I2C3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
-
-/** @brief Macro to get the I2C3 clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
- * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
- */
-#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the TIM2 clock (TIM2CLK).
- * @param __TIM2CLKSource__ specifies the TIM2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
- * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
- */
-#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
-
-/** @brief Macro to get the TIM2 clock (TIM2CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
- * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
- */
-#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
-
-/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
- * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
- * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
- */
-#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
-
-/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
- * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
- */
-#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
-
-/** @brief Macro to configure the TIM15 clock (TIM15CLK).
- * @param __TIM15CLKSource__ specifies the TIM15 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
- * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
- */
-#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
-
-/** @brief Macro to get the TIM15 clock (TIM15CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
- * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
- */
-#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
-
-/** @brief Macro to configure the TIM16 clock (TIM16CLK).
- * @param __TIM16CLKSource__ specifies the TIM16 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
- * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
- */
-#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
-
-/** @brief Macro to get the TIM16 clock (TIM16CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
- * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
- */
-#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
-
-/** @brief Macro to configure the TIM17 clock (TIM17CLK).
- * @param __TIM17CLKSource__ specifies the TIM17 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
- * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
- */
-#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
-
-/** @brief Macro to get the TIM17 clock (TIM17CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
- * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
- */
-#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
-
-/**
- * @}
- */
-
-#endif /* STM32f302xE || STM32f303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
- * @{
- */
-/** @brief Macro to configure the TIM20 clock (TIM20CLK).
- * @param __TIM20CLKSource__ specifies the TIM20 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
- * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
- */
-#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
-
-/** @brief Macro to get the TIM20 clock (TIM20CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
- * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
- */
-#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
-
-/**
- * @}
- */
-#endif /* STM32f303xE || STM32F398xx */
-
-/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
- * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
- * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
- * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
- * @retval None
- */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
- RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h
deleted file mode 100644
index c909e94c399..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h
+++ /dev/null
@@ -1,842 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RTC_H
-#define __STM32F3xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RTC RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
-}HAL_RTCStateTypeDef;
-
-/**
- * @brief RTC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
- uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
- uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
- This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
- uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
- This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
- uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
- This parameter corresponds to a time unit range between [0-1] Second
- with [1 Sec / SecondFraction +1] granularity */
-
- uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
- corresponding to Synchronous pre-scaler factor value (PREDIV_S)
- This parameter corresponds to a time unit range between [0-1] Second
- with [1 Sec / SecondFraction +1] granularity.
- This field will be used only by HAL_RTC_GetTime function */
-
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
- This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
- in CR register to store the operation.
- This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t Date; /*!< Specifies the RTC Date.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
- uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
- This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
- uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint32_t Alarm; /*!< Specifies the alarm .
- This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/**
- * @brief RTC Handle Structure definition
- */
-typedef struct
-{
- RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
-
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
- * @{
- */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
- * @{
- */
-#define RTC_HOURFORMAT_24 0x00000000U
-#define RTC_HOURFORMAT_12 RTC_CR_FMT
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
- * @{
- */
-#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
-#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
- * @{
- */
-#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
-#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
- * @{
- */
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
- * @{
- */
-#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
-#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
-#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
-/**
- * @}
- */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
- * @{
- */
-#define RTC_STOREOPERATION_RESET 0x00000000U
-#define RTC_STOREOPERATION_SET RTC_CR_BCK
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
- * @{
- */
-#define RTC_FORMAT_BIN 0x000000000U
-#define RTC_FORMAT_BCD 0x000000001U
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
- * @{
- */
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
-#define RTC_MONTH_MARCH ((uint8_t)0x03)
-#define RTC_MONTH_APRIL ((uint8_t)0x04)
-#define RTC_MONTH_MAY ((uint8_t)0x05)
-#define RTC_MONTH_JUNE ((uint8_t)0x06)
-#define RTC_MONTH_JULY ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
- * @{
- */
-#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
- * @{
- */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
- * @{
- */
-#define RTC_ALARMMASK_NONE 0x00000000U
-#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_NONE | \
- RTC_ALARMMASK_DATEWEEKDAY | \
- RTC_ALARMMASK_HOURS | \
- RTC_ALARMMASK_MINUTES | \
- RTC_ALARMMASK_SECONDS)
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
- * @{
- */
-#define RTC_ALARM_A RTC_CR_ALRAE
-#define RTC_ALARM_B RTC_CR_ALRBE
-/**
- * @}
- */
-
- /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
- * @{
- */
-#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are ignored in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are ignored in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are ignored in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are ignored in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are ignored in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are ignored in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are ignored in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are ignored in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are ignored in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are ignored in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are ignored in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are ignored in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
- to activate alarm. */
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
- * @{
- */
-#define RTC_IT_TS RTC_CR_TSIE
-#define RTC_IT_WUT RTC_CR_WUTIE
-#define RTC_IT_ALRB RTC_CR_ALRBIE
-#define RTC_IT_ALRA RTC_CR_ALRAIE
-#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
-#endif /* RTC_TAMPER3_SUPPORT */
-#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
-#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
-#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
-#define RTC_FLAG_TSF RTC_ISR_TSF
-#define RTC_FLAG_WUTF RTC_ISR_WUTF
-#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
-#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
-#define RTC_FLAG_INITF RTC_ISR_INITF
-#define RTC_FLAG_RSF RTC_ISR_RSF
-#define RTC_FLAG_INITS RTC_ISR_INITS
-#define RTC_FLAG_SHPF RTC_ISR_SHPF
-#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
-#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
-#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @brief Reset RTC handle state
- * @param __HANDLE__ RTC handle.
- * @retval None
- */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
- } while(0U)
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0U)
-
-/**
- * @brief Enable the RTC ALARMA peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
- * @brief Disable the RTC ALARMA peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
- * @brief Enable the RTC ALARMB peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
- * @brief Disable the RTC ALARMB peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
- * @brief Enable the RTC Alarm interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Alarm interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @arg RTC_FLAG_ALRAWF
- * @arg RTC_FLAG_ALRBWF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
-
-/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Clear the RTC Alarm associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-/**
- * @}
- */
-
-/* Include RTC HAL Extended module */
-#include "stm32f3xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
- * @{
- */
-
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
- * @{
- */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
- * @{
- */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK 0x007F7F7FU
-#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
-#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
- RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
- RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
- RTC_FLAG_INITF | RTC_FLAG_RSF | \
- RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
-
-#define RTC_TIMEOUT_VALUE 1000
-
-#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-/**
- * @}
- */
-/* Private macros -----------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
- * @{
- */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
- * @{
- */
-
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
- ((PM) == RTC_HOURFORMAT12_PM))
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-
-#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
-
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions -------------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
- * @{
- */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h
deleted file mode 100644
index 671b78e8284..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1022 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rtc_ex.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RTC_EX_H
-#define __STM32F3xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RTCEx RTCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
- * @{
- */
-
-/**
- * @brief RTC Tamper structure definition
- */
-typedef struct
-{
- uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
-
- uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
-
- uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
- This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
- uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
- This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
- uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
- This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
- uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
- This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
-
- uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
- This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
- * @{
- */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
- * @{
- */
-#define RTC_OUTPUT_DISABLE 0x00000000U
-#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
-#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
-#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
- * @{
- */
-#if RTC_BKP_NUMBER > 0U
-#define RTC_BKP_DR0 0x00000000U
-#define RTC_BKP_DR1 0x00000001U
-#define RTC_BKP_DR2 0x00000002U
-#define RTC_BKP_DR3 0x00000003U
-#define RTC_BKP_DR4 0x00000004U
-#endif /* RTC_BKP_NUMBER > 0U */
-
-#if RTC_BKP_NUMBER > 5U
-#define RTC_BKP_DR5 0x00000005U
-#define RTC_BKP_DR6 0x00000006U
-#define RTC_BKP_DR7 0x00000007U
-#define RTC_BKP_DR8 0x00000008U
-#define RTC_BKP_DR9 0x00000009U
-#define RTC_BKP_DR10 0x0000000AU
-#define RTC_BKP_DR11 0x0000000BU
-#define RTC_BKP_DR12 0x0000000CU
-#define RTC_BKP_DR13 0x0000000DU
-#define RTC_BKP_DR14 0x0000000EU
-#define RTC_BKP_DR15 0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5U */
-
-#if RTC_BKP_NUMBER > 16U
-#define RTC_BKP_DR16 0x00000010U
-#define RTC_BKP_DR17 0x00000011U
-#define RTC_BKP_DR18 0x00000012U
-#define RTC_BKP_DR19 0x00000013U
-#endif /* RTC_BKP_NUMBER > 16U */
-
-#if RTC_BKP_NUMBER > 20U
-#define RTC_BKP_DR20 0x00000014U
-#define RTC_BKP_DR21 0x00000015U
-#define RTC_BKP_DR22 0x00000016U
-#define RTC_BKP_DR23 0x00000017U
-#define RTC_BKP_DR24 0x00000018U
-#define RTC_BKP_DR25 0x00000019U
-#define RTC_BKP_DR26 0x0000001AU
-#define RTC_BKP_DR27 0x0000001BU
-#define RTC_BKP_DR28 0x0000001CU
-#define RTC_BKP_DR29 0x0000001DU
-#define RTC_BKP_DR30 0x0000001EU
-#define RTC_BKP_DR31 0x0000001FU
-#endif /* RTC_BKP_NUMBER > 20U */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
- * @{
- */
-#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
-#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
-/**
- * @}
- */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
- * @{
- */
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
- * @{
- */
-#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
-#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
- * @{
- */
-#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
-#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
-#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
- * @{
- */
-#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
- consecutive samples at the active level. */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
- * @{
- */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768U */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384U */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
- * @{
- */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definition
- * @{
- */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
- * @{
- */
-#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
- * @{
- */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
- * @{
- */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
- * @{
- */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */
-/**
- * @}
- */
-
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ 0x00000000U
-#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
- * @{
- */
-#define RTC_SHIFTADD1S_RESET 0x00000000U
-#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
- * @{
- */
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC Extended WakeUp Timer
- * @{
- */
-/**
- * @brief Enable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
- * @brief Disable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
- * @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/* WAKE-UP TIMER EXTI */
-/* ------------------ */
-/**
- * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable event on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable event on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
-
-/**
- * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Clear the RTC WakeUp Timer associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-/**
- * @}
- */
-
-/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Extended Timestamp
- * @{
- */
-/**
- * @brief Enable the RTC TimeStamp peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
- * @brief Disable the RTC TimeStamp peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @}
- */
-
-/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Extended Tamper
- * @{
- */
-
-/**
- * @brief Enable the RTC Tamper1 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
-
-/**
- * @brief Disable the RTC Tamper1 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
-
-/**
- * @brief Enable the RTC Tamper2 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
-
-/**
- * @brief Disable the RTC Tamper2 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
- * @brief Enable the RTC Tamper3 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
-
-/**
- * @brief Disable the RTC Tamper3 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
- * @brief Enable the RTC Tamper interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Tamper interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
- * @note (*) RTC_IT_TAMP3 not present on all the devices
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP: Tamper interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
- /**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F (*)
- * @note (*) RTC_FLAG_TAMP3F not present on all the devices
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F (*)
- * @note (*) RTC_FLAG_TAMP3F not present on all the devices
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
-/**
- * @}
- */
-
-/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Extended Tamper Timestamp EXTI
- * @{
- */
-
-/* TAMPER TIMESTAMP EXTI */
-/* --------------------- */
-/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
-
-/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-/**
- * @}
- */
-
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Extended Calibration
- * @{
- */
-
-/**
- * @brief Enable the RTC calibration output.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
- * @brief Disable the calibration output.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
- * @brief Enable the clock reference detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
- * @brief Disable the clock reference detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
- * @brief Get the selected RTC shift operation's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_SHPF
- * @retval None
- */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
- * @{
- */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @{
- */
-
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/* Extended RTC features functions *******************************************/
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
- * @{
- */
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
- * @{
- */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
- * @{
- */
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-
-
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
- ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
- ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
-
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
- ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
- ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h
deleted file mode 100644
index 02a87d11c82..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h
+++ /dev/null
@@ -1,704 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_sdadc.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the SDADC
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_SDADC_H
-#define __STM32F3xx_SDADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SDADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDADC_Exported_Types SDADC Exported Types
- * @{
- */
-
-
-/**
- * @brief HAL SDADC States definition
- */
-typedef enum
-{
- HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */
- HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */
- HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */
- HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */
- HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */
- HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */
- HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */
-}HAL_SDADC_StateTypeDef;
-
-/**
- * @brief SDADC Init Structure definition
- */
-typedef struct
-{
- uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
- This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
- uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
- This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
- uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
- This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
- uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
- Note: This parameter is common to all SDADC instances.
- This parameter can be a value of @ref SDADC_Reference_Voltage */
-}SDADC_InitTypeDef;
-
-/**
- * @brief SDADC handle Structure definition
- */
-typedef struct
-{
- SDADC_TypeDef *Instance; /*!< SDADC registers base address */
- SDADC_InitTypeDef Init; /*!< SDADC init parameters */
- DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
- uint32_t RegularContMode; /*!< Regular conversion continuous mode */
- uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
- uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
- uint32_t InjConvRemaining; /*!< Injected conversion remaining */
- uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
- uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
- uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
- uint32_t RegularMultimode; /*!< current type of regular multimode */
- uint32_t InjectedMultimode; /*!< Current type of injected multimode */
- HAL_SDADC_StateTypeDef State; /*!< SDADC state */
- uint32_t ErrorCode; /*!< SDADC Error code */
-}SDADC_HandleTypeDef;
-
-/**
- * @brief SDADC Configuration Register Parameter Structure
- */
-typedef struct
-{
- uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
- This parameter can be any value of @ref SDADC_InputMode */
- uint32_t Gain; /*!< Specifies the gain setting.
- This parameter can be any value of @ref SDADC_Gain */
- uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
- This parameter can be any value of @ref SDADC_CommonMode */
- uint32_t Offset; /*!< Specifies the 12-bit offset value.
- This parameter can be any value lower or equal to 0x00000FFFU */
-}SDADC_ConfParamTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDADC_Exported_Constants SDADC Exported Constants
- * @{
- */
-
-/** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
- * @{
- */
-#define SDADC_LOWPOWER_NONE (0x00000000U)
-#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
-#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
-/**
- * @}
- */
-
-/** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
- * @{
- */
-#define SDADC_FAST_CONV_DISABLE (0x00000000U)
-#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
-/**
- * @}
- */
-
-/** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
- * @{
- */
-#define SDADC_SLOW_CLOCK_DISABLE (0x00000000U)
-#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
-/**
- * @}
- */
-
-/** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
- * @{
- */
-#define SDADC_VREF_EXT (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */
-#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
-#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
-#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
-/**
- * @}
- */
-
-/** @defgroup SDADC_ConfIndex SDADC Configuration Index
- * @{
- */
-
-#define SDADC_CONF_INDEX_0 (0x00000000U) /*!< Configuration 0 Register selected */
-#define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */
-#define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */
-/**
- * @}
- */
-
-/** @defgroup SDADC_InputMode SDADC Input Mode
- * @{
- */
-#define SDADC_INPUT_MODE_DIFF (0x00000000U) /*!< Conversions are executed in differential mode */
-#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
-#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
-/**
- * @}
- */
-
-/** @defgroup SDADC_Gain SDADC Gain
- * @{
- */
-#define SDADC_GAIN_1 (0x00000000U) /*!< Gain equal to 1U */
-#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */
-#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */
-#define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */
-#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */
-#define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */
-#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */
-/**
- * @}
- */
-
-/** @defgroup SDADC_CommonMode SDADC Common Mode
- * @{
- */
-#define SDADC_COMMON_MODE_VSSA (0x00000000U) /*!< Select SDADC VSSA as common mode */
-#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
-#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
-/**
- * @}
- */
-
-
-
-/** @defgroup SDADC_Channel_Selection SDADC Channel Selection
- * @{
- */
-
-/* SDADC Channels ------------------------------------------------------------*/
-/* The SDADC channels are defined as follows:
- - in 16-bit LSB the channel mask is set
- - in 16-bit MSB the channel number is set
- e.g. for channel 5 definition:
- - the channel mask is 0x00000020 (bit 5 is set)
- - the channel number 5 is 0x00050000
- --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */
-#define SDADC_CHANNEL_0 (0x00000001U)
-#define SDADC_CHANNEL_1 (0x00010002U)
-#define SDADC_CHANNEL_2 (0x00020004U)
-#define SDADC_CHANNEL_3 (0x00030008U)
-#define SDADC_CHANNEL_4 (0x00040010U)
-#define SDADC_CHANNEL_5 (0x00050020U)
-#define SDADC_CHANNEL_6 (0x00060040U)
-#define SDADC_CHANNEL_7 (0x00070080U)
-#define SDADC_CHANNEL_8 (0x00080100U)
-/**
- * @}
- */
-
-/** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
- * @{
- */
-#define SDADC_CALIBRATION_SEQ_1 (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
-#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
-#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
-/**
- * @}
- */
-
-/** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
- * @{
- */
-#define SDADC_CONTINUOUS_CONV_OFF (0x00000000U) /*!< Conversion are not continuous */
-#define SDADC_CONTINUOUS_CONV_ON (0x00000001U) /*!< Conversion are continuous */
-/**
- * @}
- */
-
-/** @defgroup SDADC_Trigger SDADC Trigger
- * @{
- */
-#define SDADC_SOFTWARE_TRIGGER (0x00000000U) /*!< Software trigger */
-#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
-#define SDADC_EXTERNAL_TRIGGER (0x00000002U) /*!< External trigger */
-/**
- * @}
- */
-
-/** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
- * @{
- */
-#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_EXTI11 (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
-#define SDADC_EXT_TRIG_EXTI15 (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
-/**
- * @}
- */
-
-/** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
- * @{
- */
-#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
-#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
-#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
- * @{
- */
-#define SDADC_INJECTED_DELAY_NONE (0x00000000U) /*!< No delay on injected conversion */
-#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
-/**
- * @}
- */
-
-/** @defgroup SDADC_MultimodeType SDADC Multimode Type
- * @{
- */
-#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */
-#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
-/**
- * @}
- */
-
-/** @defgroup SDADC_ErrorCode SDADC Error Code
- * @{
- */
-#define SDADC_ERROR_NONE (0x00000000U) /*!< No error */
-#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001U) /*!< Overrun occurs during regular conversion */
-#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002U) /*!< Overrun occurs during injected conversion */
-#define SDADC_ERROR_DMA (0x00000003U) /*!< DMA error occurs */
-/**
- * @}
- */
-
-/** @defgroup SDADC_interrupts_definition SDADC interrupts definition
- * @{
- */
-#define SDADC_IT_EOCAL SDADC_CR1_EOCALIE /*!< End of calibration interrupt enable */
-#define SDADC_IT_JEOC SDADC_CR1_JEOCIE /*!< Injected end of conversion interrupt enable */
-#define SDADC_IT_JOVR SDADC_CR1_JOVRIE /*!< Injected data overrun interrupt enable */
-#define SDADC_IT_REOC SDADC_CR1_REOCIE /*!< Regular end of conversion interrupt enable */
-#define SDADC_IT_ROVR SDADC_CR1_ROVRIE /*!< Regular data overrun interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SDADC_flags_definition SDADC flags definition
- * @{
- */
-#define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF /*!< End of calibration flag */
-#define SDADC_FLAG_JEOC SDADC_ISR_JEOCF /*!< End of injected conversion flag */
-#define SDADC_FLAG_JOVR SDADC_ISR_JOVRF /*!< Injected conversion overrun flag */
-#define SDADC_FLAG_REOC SDADC_ISR_REOCF /*!< End of regular conversion flag */
-#define SDADC_FLAG_ROVR SDADC_ISR_ROVRF /*!< Regular conversion overrun flag */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SDADC_Exported_Macros SDADC Exported Macros
- * @{
- */
-
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user. */
-
-/** @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
- * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
- * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
- * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
- * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
- * @retval None
- */
-#define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
- * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
- * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
- * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
- * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
- * @retval None
- */
-#define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__ ADC handle
- * @param __INTERRUPT__ ADC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
- * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
- * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
- * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
- * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected ADC's flag status.
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg SDADC_FLAG_EOCAL: End of calibration flag
- * @arg SDADC_FLAG_JEOC: End of injected conversion flag
- * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
- * @arg SDADC_FLAG_REOC: End of regular conversion flag
- * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
- * @retval None
- */
-#define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the ADC's pending flags
- * @param __HANDLE__ ADC handle
- * @param __FLAG__ ADC flag
- * This parameter can be any combination of the following values:
- * @arg SDADC_FLAG_EOCAL: End of calibration flag
- * @arg SDADC_FLAG_JEOC: End of injected conversion flag
- * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
- * @arg SDADC_FLAG_REOC: End of regular conversion flag
- * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
- * @retval None
- */
-#define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
-
-/** @brief Reset SDADC handle state
- * @param __HANDLE__ SDADC handle.
- * @retval None
- */
-#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SDADC_Private_Macros SDADC Private Macros
- * @{
- */
-
-#define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
- ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
- ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
-
-#define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
- ((FAST) == SDADC_FAST_CONV_ENABLE))
-
-#define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
- ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
-
-#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
- ((VREF) == SDADC_VREF_VREFINT1) || \
- ((VREF) == SDADC_VREF_VREFINT2) || \
- ((VREF) == SDADC_VREF_VDDA))
-
-#define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
- ((CONF) == SDADC_CONF_INDEX_1) || \
- ((CONF) == SDADC_CONF_INDEX_2))
-
-#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
- ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
- ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
-
-#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
- ((GAIN) == SDADC_GAIN_2) || \
- ((GAIN) == SDADC_GAIN_4) || \
- ((GAIN) == SDADC_GAIN_8) || \
- ((GAIN) == SDADC_GAIN_16) || \
- ((GAIN) == SDADC_GAIN_32) || \
- ((GAIN) == SDADC_GAIN_1_2))
-
-#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
- ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
- ((MODE) == SDADC_COMMON_MODE_VDDA))
-
-#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
-
-/* Just one channel of the 9 channels can be selected for regular conversion */
-#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
- ((CHANNEL) == SDADC_CHANNEL_1) || \
- ((CHANNEL) == SDADC_CHANNEL_2) || \
- ((CHANNEL) == SDADC_CHANNEL_3) || \
- ((CHANNEL) == SDADC_CHANNEL_4) || \
- ((CHANNEL) == SDADC_CHANNEL_5) || \
- ((CHANNEL) == SDADC_CHANNEL_6) || \
- ((CHANNEL) == SDADC_CHANNEL_7) || \
- ((CHANNEL) == SDADC_CHANNEL_8))
-
-/* Any or all of the 9 channels can be selected for injected conversion */
-#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
-
-
-#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
- ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
- ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
-
-#define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
- ((MODE) == SDADC_CONTINUOUS_CONV_ON))
-
-
-#define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
- ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
-
-#define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
- ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
- ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
-
-
-#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
- ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
- ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
- ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
-
-#define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
- ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
- ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
-
-
-#define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
- ((DELAY) == SDADC_INJECTED_DELAY))
-
-#define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
- ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
- * @{
- */
-
-/** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
-void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
-
-/**
- * @}
- */
-
-/** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
- * @{
- */
-
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
- uint32_t ConfIndex,
- SDADC_ConfParamTypeDef* ConfParamStruct);
-HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ConfIndex);
-HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ContinuousMode);
-HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ContinuousMode);
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
- uint32_t InjectedExtTrigger,
- uint32_t ExtTriggerEdge);
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
- uint32_t InjectedDelay);
-HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
-HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
-
-/**
- * @}
- */
-
-/** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
-HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
-
-HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
-
-HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
-HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
-
-HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
-
-uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
-uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
-uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
-uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
-
-void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
-
-HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
-
-void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
-void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
-
-/**
- * @}
- */
-
-/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
-uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F3xx_SDADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h
deleted file mode 100644
index 1b16961b638..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h
+++ /dev/null
@@ -1,1070 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smartcard.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SMARTCARD_H
-#define __STM32F3xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
- * @{
- */
-
-/**
- * @brief SMARTCARD Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
- The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits.
- This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
-
- uint16_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref SMARTCARD_Parity
- @note The parity is enabled by default (PCE is forced to 1U).
- Since the WordLength is forced to 8 bits + parity, M is
- forced to 1 and the parity bit is the 9th bit. */
-
- uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref SMARTCARD_Mode */
-
- uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
- uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
- uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
- uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
-
- uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */
-
- uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
-
- uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
- in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_Enable */
-
- uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
- This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
-
- uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
- it is used to implement the Character Wait Time (CWT) and
- Block Wait Time (BWT). It is coded over 24 bits. */
-
- uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
- This parameter can be any value from 0x0 to 0xFFU */
-
- uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
- receive and transmit mode). When set to 0U, retransmission is
- disabled. Otherwise, its maximum value is 7 (before signalling
- an error) */
-
-}SMARTCARD_InitTypeDef;
-
-/**
- * @brief SMARTCARD advanced features initalization structure definition
- */
-typedef struct
-{
- uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
- advanced features may be initialized at the same time. This parameter
- can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Tx_Inv */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Rx_Inv */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
- vs negative/inverted logic).
- This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref SMARTCARD_MSB_First */
-}SMARTCARD_AdvFeatureInitTypeDef;
-
-/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
- * - gState contains SMARTCARD state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
-
-/**
- * @brief SMARTCARD handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< SmartCard Error code
- This parameter can be a value of @ref SMARTCARD_Error */
-
-}SMARTCARD_HandleTypeDef;
-
-/**
- * @brief SMARTCARD clock sources
- */
-typedef enum
-{
- SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
-}SMARTCARD_ClockSourceTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
- * @{
- */
-
-/** @defgroup SMARTCARD_Error SMARTCARD Error
- * @{
- */
-#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
- * @{
- */
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
- * @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
- * @{
- */
-#define SMARTCARD_POLARITY_LOW (0x00000000U) /*!< SMARTCARD frame low polarity */
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
- * @{
- */
-#define SMARTCARD_PHASE_1EDGE (0x00000000U) /*!< SMARTCARD frame phase on first clock transition */
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
- * @{
- */
-#define SMARTCARD_LASTBIT_DISABLE (0x00000000U) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
- * @{
- */
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< SMARTCARD frame one-bit sample disabled */
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
-/**
- * @}
- */
-
-
-/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
- * @{
- */
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
-#define SMARTCARD_NACK_DISABLE (0x00000000U) /*!< SMARTCARD NACK transmission enabled */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
- * @{
- */
-#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U) /*!< SMARTCARD receiver timeout disabled */
-#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
- * @{
- */
-#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
-#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
- * @{
- */
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
- * @{
- */
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
- * @{
- */
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
- * @{
- */
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
- * @{
- */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
-#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
-#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
-#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
-#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
-#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
-#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
-#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
-#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
-#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
-#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
-#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
-#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-
-#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */
-#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */
-#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */
-
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */
-#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */
-#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */
-
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
- * @{
- */
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
-#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
- * @{
- */
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
- * @{
- */
-#define SMARTCARD_GTPR_GT_LSB_POS ( 8U) /*!< SMARTCARD guard time value LSB position in GTPR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
- * @{
- */
-#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U) /*!< SMARTCARD block length LSB position in RTOR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
- * @{
- */
-#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /*!< SMARTCARD interruptions flags mask */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
- * @{
- */
-#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive data flush request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
- * @{
- */
-
-/** @brief Reset SMARTCARD handle states.
- * @param __HANDLE__ SMARTCARD handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- } while(0U)
-
-/** @brief Flush the Smartcard Data registers.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
- } while(0U)
-
-/** @brief Clear the specified SMARTCARD pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
- * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
- * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
- * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
- * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
- * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
- * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
- * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
-
-/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
-
-/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
-
-/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
-
-/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
-
-/** @brief Check whether the specified Smartcard flag is set or not.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
- * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
- * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
- * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
- * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
- * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
- * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
- * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
- * @arg @ref SMARTCARD_FLAG_NE Noise error flag
- * @arg @ref SMARTCARD_FLAG_FE Framing error flag
- * @arg @ref SMARTCARD_FLAG_PE Parity error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief Enable the specified SmartCard interrupt.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief Disable the specified SmartCard interrupt.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-
-/** @brief Check whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __IT__ specifies the SMARTCARD interrupt to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt
- * @arg @ref SMARTCARD_IT_NE Noise error interrupt
- * @arg @ref SMARTCARD_IT_FE Framing error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
-
-/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __IT__ specifies the SMARTCARD interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
- (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
-
-
-/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt.
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
- * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
- * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
- * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
- * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
- * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
- * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
- * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Set a specific SMARTCARD request flag.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __REQ__ specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
- * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief Enable the SMARTCARD one bit sample method.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the SMARTCARD one bit sample method.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable the USART associated to the SMARTCARD Handle.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private macros -------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
- * @{
- */
-
-/** @brief Check the Baud rate range.
- * @note The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz)
- * divided by the oversampling used on the SMARTCARD (i.e. 16).
- * @param __BAUDRATE__ Baud rate set by the configuration function.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
-
-/** @brief Check the block length range.
- * @note The maximum SMARTCARD block length is 0xFF.
- * @param __LENGTH__ block length.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
-
-/** @brief Check the receiver timeout value.
- * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
- * @param __TIMEOUTVALUE__ receiver timeout value.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-
-/** @brief Check the SMARTCARD autoretry counter value.
- * @note The maximum number of retransmissions is 0x7.
- * @param __COUNT__ number of retransmissions.
- * @retval Test result (TRUE or FALSE)
- */
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
-
-/**
- * @brief Ensure that SMARTCARD frame length is valid.
- * @param __LENGTH__ SMARTCARD frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-
-/**
- * @brief Ensure that SMARTCARD frame number of stop bits is valid.
- * @param __STOPBITS__ SMARTCARD frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
- ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
-
-/**
- * @brief Ensure that SMARTCARD frame parity is valid.
- * @param __PARITY__ SMARTCARD frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
- ((__PARITY__) == SMARTCARD_PARITY_ODD))
-
-/**
- * @brief Ensure that SMARTCARD communication mode is valid.
- * @param __MODE__ SMARTCARD communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
-
-/**
- * @brief Ensure that SMARTCARD frame polarity is valid.
- * @param __CPOL__ SMARTCARD frame polarity.
- * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-
-/**
- * @brief Ensure that SMARTCARD frame phase is valid.
- * @param __CPHA__ SMARTCARD frame phase.
- * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
- */
-#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-
-/**
- * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
- * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
- * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
- */
-#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
- ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame sampling is valid.
- * @param __ONEBIT__ SMARTCARD frame sampling.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD NACK transmission setting is valid.
- * @param __NACK__ SMARTCARD NACK transmission setting.
- * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
- */
-#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
- ((__NACK__) == SMARTCARD_NACK_DISABLE))
-
-/**
- * @brief Ensure that SMARTCARD receiver timeout setting is valid.
- * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
- * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
- */
-#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD advanced features initialization is valid.
- * @param __INIT__ SMARTCARD advanced features initialization.
- * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
- SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
- SMARTCARD_ADVFEATURE_SWAP_INIT | \
- SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
- SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-
-/**
- * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
- * @param __TXINV__ SMARTCARD frame TX inversion setting.
- * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
- ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
- * @param __RXINV__ SMARTCARD frame RX inversion setting.
- * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
- ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame data inversion setting is valid.
- * @param __DATAINV__ SMARTCARD frame data inversion setting.
- * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
- ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
- * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
- * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
- ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD frame overrun setting is valid.
- * @param __OVERRUN__ SMARTCARD frame overrun setting.
- * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
- */
-#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
- ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
- * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
- * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
- * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
- * @brief Ensure that SMARTCARD frame MSB first setting is valid.
- * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
- * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
- */
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
- * @brief Ensure that SMARTCARD request parameter is valid.
- * @param __PARAM__ SMARTCARD request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
-
-/**
- * @}
- */
-
-/* Include SMARTCARD HAL Extended module */
-#include "stm32f3xx_hal_smartcard_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
- * @{
- */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
- * @{
- */
-
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h
deleted file mode 100644
index 3402769cc7d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smartcard_ex.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SMARTCARD_EX_H
-#define __STM32F3xx_HAL_SMARTCARD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARDEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
- * @{
- */
-
-/** @brief Report the SMARTCARD clock source.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __CLOCKSOURCE__ output variable.
- * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
- */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#else
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#endif
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation methods *******************************************************/
-
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
- * @{
- */
-
-/* Peripheral Control functions ***********************************************/
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_SMARTCARD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h
deleted file mode 100644
index 8682dce4d2e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h
+++ /dev/null
@@ -1,699 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smbus.h
- * @author MCD Application Team
- * @brief Header file of SMBUS HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SMBUS_H
-#define __STM32F3xx_HAL_SMBUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMBUS
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
- * @{
- */
-
-/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
- * @brief SMBUS Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
- uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
- This parameter can be a value of @ref SMBUS_Analog_Filter */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
- This parameter can be a value of @ref SMBUS_addressing_mode */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref SMBUS_dual_addressing_mode */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref SMBUS_own_address2_masks. */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref SMBUS_nostretch_mode */
-
- uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
- This parameter can be a value of @ref SMBUS_packet_error_check_mode */
-
- uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
- This parameter can be a value of @ref SMBUS_peripheral_mode */
-
- uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
-} SMBUS_InitTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_state_definition HAL state definition
- * @brief HAL State definition
- * @{
- */
-#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
-#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
-#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
- * @brief SMBUS Error Code definition
- * @{
- */
-#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
-#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
-#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
-#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
-#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
-#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
-#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
-/**
- * @}
- */
-
-/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
- * @brief SMBUS handle Structure definition
- * @{
- */
-typedef struct
-{
- I2C_TypeDef *Instance; /*!< SMBUS registers base address */
-
- SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
-
- uint16_t XferSize; /*!< SMBUS transfer size */
-
- __IO uint16_t XferCount; /*!< SMBUS transfer counter */
-
- __IO uint32_t XferOptions; /*!< SMBUS transfer options */
-
- __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
-
- HAL_LockTypeDef Lock; /*!< SMBUS locking object */
-
- __IO uint32_t State; /*!< SMBUS communication state */
-
- __IO uint32_t ErrorCode; /*!< SMBUS Error code */
-
-} SMBUS_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
- * @{
- */
-
-/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
- * @{
- */
-#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
-#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-/**
- * @}
- */
-
-/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
- * @{
- */
-#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
-#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
- * @{
- */
-
-#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
-#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
- * @{
- */
-
-#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
-#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
-#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
-#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
-#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
-#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
-#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
-#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
-/**
- * @}
- */
-
-
-/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
- * @{
- */
-#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
-#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
- * @{
- */
-#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
-#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
- * @{
- */
-#define SMBUS_PEC_DISABLE (0x00000000U)
-#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
- * @{
- */
-#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
-/**
- * @}
- */
-
-/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
- * @{
- */
-
-#define SMBUS_SOFTEND_MODE (0x00000000U)
-#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
-#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
-#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
-/**
- * @}
- */
-
-/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
- * @{
- */
-
-#define SMBUS_NO_STARTSTOP (0x00000000U)
-#define SMBUS_GENERATE_STOP I2C_CR2_STOP
-#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
-/**
- * @}
- */
-
-/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
- * @{
- */
-
-/* List of XferOptions in usage of :
- * 1- Restart condition when direction change
- * 2- No Restart condition in other use cases
- */
-#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
-#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
-#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
-#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
-#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
-#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
-#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
-#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
- * @brief SMBUS Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define SMBUS_IT_ERRI I2C_CR1_ERRIE
-#define SMBUS_IT_TCI I2C_CR1_TCIE
-#define SMBUS_IT_STOPI I2C_CR1_STOPIE
-#define SMBUS_IT_NACKI I2C_CR1_NACKIE
-#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
-#define SMBUS_IT_RXI I2C_CR1_RXIE
-#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
-#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
-#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
-#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
- * @brief Flag definition
- * Elements values convention: 0xXXXXYYYY
- * - XXXXXXXX : Flag mask
- * @{
- */
-
-#define SMBUS_FLAG_TXE I2C_ISR_TXE
-#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
-#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
-#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
-#define SMBUS_FLAG_AF I2C_ISR_NACKF
-#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
-#define SMBUS_FLAG_TC I2C_ISR_TC
-#define SMBUS_FLAG_TCR I2C_ISR_TCR
-#define SMBUS_FLAG_BERR I2C_ISR_BERR
-#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
-#define SMBUS_FLAG_OVR I2C_ISR_OVR
-#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
-#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
-#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
-#define SMBUS_FLAG_DIR I2C_ISR_DIR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
- * @{
- */
-
-/** @brief Reset SMBUS handle state.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-
-/** @brief Enable the specified SMBUS interrupts.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
- * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
- * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
- * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
- * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
- * @arg @ref SMBUS_IT_RXI RX interrupt enable
- * @arg @ref SMBUS_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief Disable the specified SMBUS interrupts.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
- * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
- * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
- * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
- * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
- * @arg @ref SMBUS_IT_RXI RX interrupt enable
- * @arg @ref SMBUS_IT_TXI TX interrupt enable
- *
- * @retval None
- */
-#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
- * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
- * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
- * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
- * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
- * @arg @ref SMBUS_IT_RXI RX interrupt enable
- * @arg @ref SMBUS_IT_TXI TX interrupt enable
- *
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SMBUS flag is set or not.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
- * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
- * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
- * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
- * @arg @ref SMBUS_FLAG_AF NACK received flag
- * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
- * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
- * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
- * @arg @ref SMBUS_FLAG_BERR Bus error
- * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
- * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
- * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
- * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref SMBUS_FLAG_ALERT SMBus alert
- * @arg @ref SMBUS_FLAG_BUSY Bus busy
- * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
- *
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-
-/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
- * @arg @ref SMBUS_FLAG_AF NACK received flag
- * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
- * @arg @ref SMBUS_FLAG_BERR Bus error
- * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
- * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
- * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
- * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
- * @arg @ref SMBUS_FLAG_ALERT SMBus alert
- *
- * @retval None
- */
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Enable the specified SMBUS peripheral.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified SMBUS peripheral.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
- * @param __HANDLE__ specifies the SMBUS Handle.
- * @retval None
- */
-#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
- * @{
- */
-
-#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
-
-#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-
-#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
- ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
-
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
-
-#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
- ((MASK) == SMBUS_OA2_MASK01) || \
- ((MASK) == SMBUS_OA2_MASK02) || \
- ((MASK) == SMBUS_OA2_MASK03) || \
- ((MASK) == SMBUS_OA2_MASK04) || \
- ((MASK) == SMBUS_OA2_MASK05) || \
- ((MASK) == SMBUS_OA2_MASK06) || \
- ((MASK) == SMBUS_OA2_MASK07))
-
-#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
- ((CALL) == SMBUS_GENERALCALL_ENABLE))
-
-#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
- ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
-
-#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
- ((PEC) == SMBUS_PEC_ENABLE))
-
-#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
-
-
-#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
- ((REQUEST) == SMBUS_NO_STARTSTOP))
-
-
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
- IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-
-#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
-#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
-#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-
-#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-
-#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
- * @{
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup Blocking_mode_Polling Blocking mode Polling
- * @{
- */
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
- * @{
- */
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
-
-/* Peripheral State and Errors functions **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
- * @{
- */
-/* Private functions are defined in stm32f3xx_hal_smbus.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h
deleted file mode 100644
index a43b6ef0d23..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h
+++ /dev/null
@@ -1,703 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SPI_H
-#define __STM32F3xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
- CRC Length is only used with Data8 and Data16, not other data size
- This parameter can be a value of @ref SPI_CRC_length */
-
- uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
- This parameter can be a value of @ref SPI_NSSP_Mode
- This mode is activated by the NSSP bit in the SPIx_CR2 register and
- it takes effect only if the SPI interface is configured as Motorola SPI
- master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
- CPOL setting is ignored).. */
-} SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum
-{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
-} HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
-
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-} SPI_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_Error_Code SPI Error Code
- * @{
- */
-#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE (0x00000000U)
-#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_4BIT (0x00000300U)
-#define SPI_DATASIZE_5BIT (0x00000400U)
-#define SPI_DATASIZE_6BIT (0x00000500U)
-#define SPI_DATASIZE_7BIT (0x00000600U)
-#define SPI_DATASIZE_8BIT (0x00000700U)
-#define SPI_DATASIZE_9BIT (0x00000800U)
-#define SPI_DATASIZE_10BIT (0x00000900U)
-#define SPI_DATASIZE_11BIT (0x00000A00U)
-#define SPI_DATASIZE_12BIT (0x00000B00U)
-#define SPI_DATASIZE_13BIT (0x00000C00U)
-#define SPI_DATASIZE_14BIT (0x00000D00U)
-#define SPI_DATASIZE_15BIT (0x00000E00U)
-#define SPI_DATASIZE_16BIT (0x00000F00U)
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW (0x00000000U)
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE (0x00000000U)
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
-/**
- * @}
- */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
- * @{
- */
-#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB (0x00000000U)
-#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE (0x00000000U)
-#define SPI_TIMODE_ENABLE SPI_CR2_FRF
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
- * @{
- * This parameter can be one of the following values:
- * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
- * SPI_CRC_LENGTH_8BIT : CRC 8bit
- * SPI_CRC_LENGTH_16BIT : CRC 16bit
- */
-#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
-#define SPI_CRC_LENGTH_8BIT (0x00000001U)
-#define SPI_CRC_LENGTH_16BIT (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
- * @{
- * This parameter can be one of the following values:
- * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
- * RXNE event is generated if the FIFO
- * level is greater or equal to 1/2(16-bits).
- * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4(8 bits). */
-#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_CR2_TXEIE
-#define SPI_IT_RXNE SPI_CR2_RXNEIE
-#define SPI_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
-/**
- * @}
- */
-
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
- * @{
- */
-#define SPI_FTLVL_EMPTY (0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
-#define SPI_FTLVL_HALF_FULL (0x00001000U)
-#define SPI_FTLVL_FULL (0x00001800U)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
- * @{
- */
-#define SPI_FRLVL_EMPTY (0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
-#define SPI_FRLVL_HALF_FULL (0x00000400U)
-#define SPI_FRLVL_FULL (0x00000600U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI handle.
- * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
- * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
- * @arg SPI_FLAG_FRLVL: SPI fifo reception level
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0U)
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while(0U)
-
-/** @brief Clear the SPI FRE pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
- }while(0U)
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_15BIT) || \
- ((DATASIZE) == SPI_DATASIZE_14BIT) || \
- ((DATASIZE) == SPI_DATASIZE_13BIT) || \
- ((DATASIZE) == SPI_DATASIZE_12BIT) || \
- ((DATASIZE) == SPI_DATASIZE_11BIT) || \
- ((DATASIZE) == SPI_DATASIZE_10BIT) || \
- ((DATASIZE) == SPI_DATASIZE_9BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT) || \
- ((DATASIZE) == SPI_DATASIZE_7BIT) || \
- ((DATASIZE) == SPI_DATASIZE_6BIT) || \
- ((DATASIZE) == SPI_DATASIZE_5BIT) || \
- ((DATASIZE) == SPI_DATASIZE_4BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
- ((NSSP) == SPI_NSS_PULSE_DISABLE))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
- ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
- ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
- ((LENGTH) == SPI_CRC_LENGTH_16BIT))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
-
-#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
-
-
-/**
- * @}
- */
-
-/* Include SPI HAL Extended module */
-#include "stm32f3xx_hal_spi_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h
deleted file mode 100644
index 25fcdee9357..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_spi_ex.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SPI_EX_H
-#define __STM32F3xx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPIEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPIEx_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SPIEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h
deleted file mode 100644
index 7d1e6f5b328..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_sram.h
- * @author MCD Application Team
- * @brief Header file of SRAM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_SRAM_H
-#define __STM32F3xx_HAL_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#include "stm32f3xx_ll_fmc.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SRAM
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
- * @{
- */
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
- HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
-
-}HAL_SRAM_StateTypeDef;
-
-/**
- * @brief SRAM handle Structure definition
- */
-typedef struct
-{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< SRAM locking object */
-
- __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
-
- DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-
-}SRAM_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
-
-/** @brief Reset SRAM handle state
- * @param __HANDLE__ SRAM handle
- * @retval None
- */
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
-
-/* SRAM Control functions ****************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* SRAM Peripheral State functions ********************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h
deleted file mode 100644
index 6cb103b1257..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h
+++ /dev/null
@@ -1,1623 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_TIM_H
-#define __STM32F3xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1U) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
- * @brief TIM Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-}TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIMEx_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-}TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct {
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIMEx_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-typedef struct
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref TIM_DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
-}TIM_HandleTypeDef;
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP (0x0000U)
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE (0x0000U)
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH (0x0000U)
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH (0x0000U)
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE (0x0000U)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#if defined(TIM_SR_B2IF)
-#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
-#endif
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF (0x0000U)
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
- * @{
- */
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW (0x0000U)
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-/**
- * @}
- */
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET (0x0000U)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
-#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 (0x0000U)
-#define TIM_TS_ITR1 (0x0010U)
-#define TIM_TS_ITR2 (0x0020U)
-#define TIM_TS_ITR3 (0x0030U)
-#define TIM_TS_TI1F_ED (0x0040U)
-#define TIM_TS_TI1FP1 (0x0050U)
-#define TIM_TS_TI2FP2 (0x0060U)
-#define TIM_TS_ETRF (0x0070U)
-#define TIM_TS_NONE (0xFFFFU)
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
- * @}
- */
-
- /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 (0x0000U)
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE (0x0001U)
-#define TIM_CCx_DISABLE (0x0000U)
-#define TIM_CCxN_ENABLE (0x0004U)
-#define TIM_CCxN_DISABLE (0x0000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state
- * @param __HANDLE__ TIM handle.
- * @retval None
- */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0U)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0U)
-
-/* The Main Output Enable of a timer instance is disabled unconditionally */
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled uncondiotionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/**
- * @brief Enables the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Enables the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/**
- * @brief Disables the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/**
- * @brief Checks whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clears the specified TIM interrupt flag.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Checks whether the specified TIM interrupt has occurred or not.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the TIM interrupt source to check.
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Clear the TIM interrupt pending bits
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter
- * @param __HANDLE__ TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Sets the TIM active prescaler register value on update event.
- * @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the active prescaler register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Sets the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __COUNTER__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Gets the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Sets the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Autoreload Register value on runtime
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Sets the TIM Clock Division value on runtime without calling
- * another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __CKD__ specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Clock Division value on runtime
- * @param __HANDLE__ TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Sets the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Input Capture prescaler on runtime
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * (+) Counter overflow/underflow
- * (+) Setting the UG bit
- * (+) Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
- * @brief Sets the TIM Capture x input polarity on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0U)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private Constants -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-/** @brief Set TIM IC prescaler
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @param __ICPSC__ specifies the prescaler value.
- * @retval None
- */
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-/** @brief Reset TIM IC prescaler
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-/** @brief Set TIM IC polarity
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @param __POLARITY__ specifies TIM Channel Polarity
- * @retval None
- */
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-/** @brief Reset TIM IC polarity
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32f3xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2
- * @{
- */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3
- * @{
- */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4
- * @{
- */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5
- * @{
- */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6
- * @{
- */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7
- * @{
- */
-/* Interrupt Handler functions **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group9
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group10
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h
deleted file mode 100644
index 178a4601411..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h
+++ /dev/null
@@ -1,1243 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_TIM_EX_H
-#define __STM32F3xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
-} TIM_HallSensor_InitTypeDef;
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief TIM Master configuration Structure definition
- * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
- * output
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Break and Dead time configuration Structure definition
- * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the brek input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
- uint32_t Break2State; /*!< TIM Break2 State
- This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity
- This parameter can be a value of @ref TIMEx_Break2_Polarity */
- uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- * @note Advanced timers provide TRGO2 internal line which is redirected
- * to the ADC
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
- This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
- * @{
- */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup TIMEx_Channel TIMEx Channel
- * @{
- */
-#define TIM_CHANNEL_1 (0x0000U)
-#define TIM_CHANNEL_2 (0x0004U)
-#define TIM_CHANNEL_3 (0x0008U)
-#define TIM_CHANNEL_4 (0x000CU)
-#define TIM_CHANNEL_ALL (0x0018U)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING (0x0000U)
-#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
-#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE (0x0000U)
-#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Event_Source TIMEx Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
- * @{
- */
-#define TIM_DMABASE_CR1 (0x00000000U)
-#define TIM_DMABASE_CR2 (0x00000001U)
-#define TIM_DMABASE_SMCR (0x00000002U)
-#define TIM_DMABASE_DIER (0x00000003U)
-#define TIM_DMABASE_SR (0x00000004U)
-#define TIM_DMABASE_EGR (0x00000005U)
-#define TIM_DMABASE_CCMR1 (0x00000006U)
-#define TIM_DMABASE_CCMR2 (0x00000007U)
-#define TIM_DMABASE_CCER (0x00000008U)
-#define TIM_DMABASE_CNT (0x00000009U)
-#define TIM_DMABASE_PSC (0x0000000AU)
-#define TIM_DMABASE_ARR (0x0000000BU)
-#define TIM_DMABASE_RCR (0x0000000CU)
-#define TIM_DMABASE_CCR1 (0x0000000DU)
-#define TIM_DMABASE_CCR2 (0x0000000EU)
-#define TIM_DMABASE_CCR3 (0x0000000FU)
-#define TIM_DMABASE_CCR4 (0x00000010U)
-#define TIM_DMABASE_BDTR (0x00000011U)
-#define TIM_DMABASE_DCR (0x00000012U)
-#define TIM_DMABASE_OR (0x00000013U)
-/**
- * @}
- */
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup TIMEx_Channel TIMEx Channel
- * @{
- */
-#define TIM_CHANNEL_1 (0x0000U)
-#define TIM_CHANNEL_2 (0x0004U)
-#define TIM_CHANNEL_3 (0x0008U)
-#define TIM_CHANNEL_4 (0x000CU)
-#define TIM_CHANNEL_5 (0x0010U)
-#define TIM_CHANNEL_6 (0x0014U)
-#define TIM_CHANNEL_ALL (0x003CU)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING (0x0000U)
-#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
-
-#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
-#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
-#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
- * @{
- */
-#define TIM_BREAK2_DISABLE (0x00000000U)
-#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
- * @{
- */
-#define TIM_BREAK2POLARITY_LOW (0x00000000U)
-#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
- * @{
- */
-#define TIM_TRGO2_RESET (0x00000000U)
-#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
-#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
-#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE (0x0000U)
-#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIMEx Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 (0x00000000U)
-#define TIM_DMABASE_CR2 (0x00000001U)
-#define TIM_DMABASE_SMCR (0x00000002U)
-#define TIM_DMABASE_DIER (0x00000003U)
-#define TIM_DMABASE_SR (0x00000004U)
-#define TIM_DMABASE_EGR (0x00000005U)
-#define TIM_DMABASE_CCMR1 (0x00000006U)
-#define TIM_DMABASE_CCMR2 (0x00000007U)
-#define TIM_DMABASE_CCER (0x00000008U)
-#define TIM_DMABASE_CNT (0x00000009U)
-#define TIM_DMABASE_PSC (0x0000000AU)
-#define TIM_DMABASE_ARR (0x0000000BU)
-#define TIM_DMABASE_RCR (0x0000000CU)
-#define TIM_DMABASE_CCR1 (0x0000000DU)
-#define TIM_DMABASE_CCR2 (0x0000000EU)
-#define TIM_DMABASE_CCR3 (0x0000000FU)
-#define TIM_DMABASE_CCR4 (0x00000010U)
-#define TIM_DMABASE_BDTR (0x00000011U)
-#define TIM_DMABASE_DCR (0x00000012U)
-#define TIM_DMABASE_CCMR3 (0x00000015U)
-#define TIM_DMABASE_CCR5 (0x00000016U)
-#define TIM_DMABASE_CCR6 (0x00000017U)
-#define TIM_DMABASE_OR (0x00000018U)
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup TIMEx_Remap TIMEx Remapping
- * @{
- */
-#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
-#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
-/**
- * @}
- */
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-
-
-#if defined(STM32F334x8)
-/** @defgroup TIMEx_Remap TIMEx Remapping 1
- * @{
- */
-#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
-#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
- * @{
- */
-#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
-/**
- * @}
- */
-#endif /* STM32F334x8 */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup TIMEx_Remap TIMEx Remapping 1
- * @{
- */
-#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
-#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
- * @{
- */
-#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
-#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
-/**
- * @}
- */
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/** @defgroup TIMEx_Remap TIMEx Remapping 1
- * @{
- */
-#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
-#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
-#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
- * @{
- */
-#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
-#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
-#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
-/**
- * @}
- */
-#endif /* STM32F303xE || STM32F398xx */
-
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup TIMEx_Remap TIMEx remapping
- * @{
- */
-#define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
-#define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */
-#define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
-#define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
-#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
-#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
-#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
-#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
-/**
- * @}
- */
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
- * @{
- */
-#define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @}
- */
-
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
- ((BASE) == TIM_DMABASE_CR2) || \
- ((BASE) == TIM_DMABASE_SMCR) || \
- ((BASE) == TIM_DMABASE_DIER) || \
- ((BASE) == TIM_DMABASE_SR) || \
- ((BASE) == TIM_DMABASE_EGR) || \
- ((BASE) == TIM_DMABASE_CCMR1) || \
- ((BASE) == TIM_DMABASE_CCMR2) || \
- ((BASE) == TIM_DMABASE_CCER) || \
- ((BASE) == TIM_DMABASE_CNT) || \
- ((BASE) == TIM_DMABASE_PSC) || \
- ((BASE) == TIM_DMABASE_ARR) || \
- ((BASE) == TIM_DMABASE_RCR) || \
- ((BASE) == TIM_DMABASE_CCR1) || \
- ((BASE) == TIM_DMABASE_CCR2) || \
- ((BASE) == TIM_DMABASE_CCR3) || \
- ((BASE) == TIM_DMABASE_CCR4) || \
- ((BASE) == TIM_DMABASE_BDTR) || \
- ((BASE) == TIM_DMABASE_DCR) || \
- ((BASE) == TIM_DMABASE_OR))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_5) || \
- ((CHANNEL) == TIM_CHANNEL_6) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2) || \
- ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
- ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
- ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
- ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
- ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-
-#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
- ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
-
-#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
- ((STATE) == TIM_BREAK2_DISABLE))
-
-#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
- ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
-
-#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
- ((SOURCE) == TIM_TRGO2_ENABLE) || \
- ((SOURCE) == TIM_TRGO2_UPDATE) || \
- ((SOURCE) == TIM_TRGO2_OC1) || \
- ((SOURCE) == TIM_TRGO2_OC1REF) || \
- ((SOURCE) == TIM_TRGO2_OC2REF) || \
- ((SOURCE) == TIM_TRGO2_OC3REF) || \
- ((SOURCE) == TIM_TRGO2_OC3REF) || \
- ((SOURCE) == TIM_TRGO2_OC4REF) || \
- ((SOURCE) == TIM_TRGO2_OC5REF) || \
- ((SOURCE) == TIM_TRGO2_OC6REF) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
- ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
- ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
- ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
- ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
- ((BASE) == TIM_DMABASE_CR2) || \
- ((BASE) == TIM_DMABASE_SMCR) || \
- ((BASE) == TIM_DMABASE_DIER) || \
- ((BASE) == TIM_DMABASE_SR) || \
- ((BASE) == TIM_DMABASE_EGR) || \
- ((BASE) == TIM_DMABASE_CCMR1) || \
- ((BASE) == TIM_DMABASE_CCMR2) || \
- ((BASE) == TIM_DMABASE_CCER) || \
- ((BASE) == TIM_DMABASE_CNT) || \
- ((BASE) == TIM_DMABASE_PSC) || \
- ((BASE) == TIM_DMABASE_ARR) || \
- ((BASE) == TIM_DMABASE_RCR) || \
- ((BASE) == TIM_DMABASE_CCR1) || \
- ((BASE) == TIM_DMABASE_CCR2) || \
- ((BASE) == TIM_DMABASE_CCR3) || \
- ((BASE) == TIM_DMABASE_CCR4) || \
- ((BASE) == TIM_DMABASE_BDTR) || \
- ((BASE) == TIM_DMABASE_CCMR3) || \
- ((BASE) == TIM_DMABASE_CCR5) || \
- ((BASE) == TIM_DMABASE_CCR6) || \
- ((BASE) == TIM_DMABASE_OR))
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
- ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
- ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
- ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
- ((REMAP) == TIM_TIM16_GPIO) ||\
- ((REMAP) == TIM_TIM16_RTC) ||\
- ((REMAP) == TIM_TIM16_HSE) ||\
- ((REMAP) == TIM_TIM16_MCO))
-
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-
-#if defined(STM32F334x8)
-#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
- ((REMAP1) == TIM_TIM16_GPIO) ||\
- ((REMAP1) == TIM_TIM16_RTC) ||\
- ((REMAP1) == TIM_TIM16_HSE) ||\
- ((REMAP1) == TIM_TIM16_MCO))
-
-#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\
- ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\
- ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\
- ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\
- ((REMAP2) == TIM_TIM16_NONE))
-
-#endif /* STM32F334x8 */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
-
-#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
- ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
- ((REMAP1) == TIM_TIM16_GPIO) ||\
- ((REMAP1) == TIM_TIM16_RTC) ||\
- ((REMAP1) == TIM_TIM16_HSE) ||\
- ((REMAP1) == TIM_TIM16_MCO))
-
-#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
- ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
- ((REMAP2) == TIM_TIM16_NONE))
-
-#endif /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
-
-#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
- ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
- ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
- ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
- ((REMAP1) == TIM_TIM16_GPIO) ||\
- ((REMAP1) == TIM_TIM16_RTC) ||\
- ((REMAP1) == TIM_TIM16_HSE) ||\
- ((REMAP1) == TIM_TIM16_MCO) ||\
- ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
- ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
- ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
- ((REMAP1) == TIM_TIM20_ADC3_AWD3))
-
-#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
- ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
- ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
- ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
- ((REMAP2) == TIM_TIM16_NONE) ||\
- ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
- ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
- ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
- ((REMAP2) == TIM_TIM20_ADC4_AWD3))
-
-#endif /* STM32F303xE || STM32F398xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
- ((REMAP) == TIM_TIM2_ETH_PTP) ||\
- ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
- ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
- ((REMAP) == TIM_TIM14_GPIO) ||\
- ((REMAP) == TIM_TIM14_RTC) ||\
- ((REMAP) == TIM_TIM14_HSE) ||\
- ((REMAP) == TIM_TIM14_MCO))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
- * @{
- */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval None
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-
-/**
- * @brief Sets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
- * @brief Resets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
-
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval None
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
-
-/**
- * @brief Sets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
-
-/**
- * @brief Resets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8)
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6
- * @{
- */
-/* Extended Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7
- * @{
- */
-/* Extended Peripheral State functions **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F3xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h
deleted file mode 100644
index 2649760f82b..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h
+++ /dev/null
@@ -1,724 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tsc.h
- * @author MCD Application Team
- * @brief Header file of TSC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_TSC_H
-#define __STM32F3xx_HAL_TSC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TSC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TSC_Exported_Types TSC Exported Types
- * @{
- */
-
-/**
- * @brief TSC state structure definition
- */
-typedef enum
-{
- HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
- HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
- HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
- HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
-} HAL_TSC_StateTypeDef;
-
-/**
- * @brief TSC group status structure definition
- */
-typedef enum
-{
- TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
- TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
-} TSC_GroupStatusTypeDef;
-
-/**
- * @brief TSC init structure definition
- */
-typedef struct
-{
- uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
- This parameter can be a value of @ref TSC_CTPulseHL_Config */
- uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
- This parameter can be a value of @ref TSC_CTPulseLL_Config */
- uint32_t SpreadSpectrum; /*!< Spread spectrum activation
- This parameter can be a value of @ref TSC_CTPulseLL_Config */
- uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
- This parameter must be a number between Min_Data = 0 and Max_Data = 127U */
- uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
- This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
- uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
- This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
- uint32_t MaxCountValue; /*!< Max count value
- This parameter can be a value of @ref TSC_MaxCount_Value */
- uint32_t IODefaultMode; /*!< IO default mode
- This parameter can be a value of @ref TSC_IO_Default_Mode */
- uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
- This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
- uint32_t AcquisitionMode; /*!< Acquisition mode
- This parameter can be a value of @ref TSC_Acquisition_Mode */
- uint32_t MaxCountInterrupt; /*!< Max count interrupt activation
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t ChannelIOs; /*!< Channel IOs mask */
- uint32_t ShieldIOs; /*!< Shield IOs mask */
- uint32_t SamplingIOs; /*!< Sampling IOs mask */
-} TSC_InitTypeDef;
-
-/**
- * @brief TSC IOs configuration structure definition
- */
-typedef struct
-{
- uint32_t ChannelIOs; /*!< Channel IOs mask */
- uint32_t ShieldIOs; /*!< Shield IOs mask */
- uint32_t SamplingIOs; /*!< Sampling IOs mask */
-} TSC_IOConfigTypeDef;
-
-/**
- * @brief TSC handle Structure definition
- */
-typedef struct
-{
- TSC_TypeDef *Instance; /*!< Register base address */
- TSC_InitTypeDef Init; /*!< Initialization parameters */
- __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
- HAL_LockTypeDef Lock; /*!< Lock feature */
-} TSC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TSC_Exported_Constants TSC Exported Constants
- * @{
- */
-
-/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
- * @{
- */
-#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))
-#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))
-#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))
-#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))
-#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))
-#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))
-#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))
-#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))
-#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))
-#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
-#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
-#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
-#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
-#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
-#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
-#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
-/**
- * @}
- */
-
-/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
- * @{
- */
-#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))
-#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))
-#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))
-#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))
-#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))
-#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))
-#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))
-#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))
-#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))
-#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
-#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
-#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
-#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
-#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
-#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
-#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
-/**
- * @}
- */
-
-/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
- * @{
- */
-#define TSC_SS_PRESC_DIV1 (0U)
-#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
-/**
- * @}
- */
-
-/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
- * @{
- */
-#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
-#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
-#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
-#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
-#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
-#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
-#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
-#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
-/**
- * @}
- */
-
-/** @defgroup TSC_MaxCount_Value Max Count Value
- * @{
- */
-#define TSC_MCV_255 ((uint32_t)(0U << 5U))
-#define TSC_MCV_511 ((uint32_t)(1U << 5U))
-#define TSC_MCV_1023 ((uint32_t)(2U << 5U))
-#define TSC_MCV_2047 ((uint32_t)(3U << 5U))
-#define TSC_MCV_4095 ((uint32_t)(4U << 5U))
-#define TSC_MCV_8191 ((uint32_t)(5U << 5U))
-#define TSC_MCV_16383 ((uint32_t)(6U << 5U))
-/**
- * @}
- */
-
-/** @defgroup TSC_IO_Default_Mode IO Default Mode
- * @{
- */
-#define TSC_IODEF_OUT_PP_LOW (0U)
-#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
-/**
- * @}
- */
-
-/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
- * @{
- */
-#define TSC_SYNC_POLARITY_FALLING (0U)
-#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
-/**
- * @}
- */
-
-/** @defgroup TSC_Acquisition_Mode Acquisition Mode
- * @{
- */
-#define TSC_ACQ_MODE_NORMAL (0U)
-#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
-/**
- * @}
- */
-
-/** @defgroup TSC_IO_Mode IO Mode
- * @{
- */
-#define TSC_IOMODE_UNUSED (0U)
-#define TSC_IOMODE_CHANNEL (1U)
-#define TSC_IOMODE_SHIELD (2U)
-#define TSC_IOMODE_SAMPLING (3U)
-/**
- * @}
- */
-
-/** @defgroup TSC_interrupts_definition Interrupts definition
- * @{
- */
-#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
-#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
-/**
- * @}
- */
-
-/** @defgroup TSC_flags_definition Flags definition
- * @{
- */
-#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
-#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
-/**
- * @}
- */
-
-/** @defgroup TSC_Group_definition Group definition
- * @{
- */
-#define TSC_NB_OF_GROUPS (8U)
-
-#define TSC_GROUP1 (0x00000001U)
-#define TSC_GROUP2 (0x00000002U)
-#define TSC_GROUP3 (0x00000004U)
-#define TSC_GROUP4 (0x00000008U)
-#define TSC_GROUP5 (0x00000010U)
-#define TSC_GROUP6 (0x00000020U)
-#define TSC_GROUP7 (0x00000040U)
-#define TSC_GROUP8 (0x00000080U)
-#define TSC_ALL_GROUPS (0x000000FFU)
-
-#define TSC_GROUP1_IDX (0U)
-#define TSC_GROUP2_IDX (1U)
-#define TSC_GROUP3_IDX (2U)
-#define TSC_GROUP4_IDX (3U)
-#define TSC_GROUP5_IDX (4U)
-#define TSC_GROUP6_IDX (5U)
-#define TSC_GROUP7_IDX (6U)
-#define TSC_GROUP8_IDX (7U)
-
-#define TSC_GROUP1_IO1 (0x00000001U)
-#define TSC_GROUP1_IO2 (0x00000002U)
-#define TSC_GROUP1_IO3 (0x00000004U)
-#define TSC_GROUP1_IO4 (0x00000008U)
-#define TSC_GROUP1_ALL_IOS (0x0000000FU)
-
-#define TSC_GROUP2_IO1 (0x00000010U)
-#define TSC_GROUP2_IO2 (0x00000020U)
-#define TSC_GROUP2_IO3 (0x00000040U)
-#define TSC_GROUP2_IO4 (0x00000080U)
-#define TSC_GROUP2_ALL_IOS (0x000000F0U)
-
-#define TSC_GROUP3_IO1 (0x00000100U)
-#define TSC_GROUP3_IO2 (0x00000200U)
-#define TSC_GROUP3_IO3 (0x00000400U)
-#define TSC_GROUP3_IO4 (0x00000800U)
-#define TSC_GROUP3_ALL_IOS (0x00000F00U)
-
-#define TSC_GROUP4_IO1 (0x00001000U)
-#define TSC_GROUP4_IO2 (0x00002000U)
-#define TSC_GROUP4_IO3 (0x00004000U)
-#define TSC_GROUP4_IO4 (0x00008000U)
-#define TSC_GROUP4_ALL_IOS (0x0000F000U)
-
-#define TSC_GROUP5_IO1 (0x00010000U)
-#define TSC_GROUP5_IO2 (0x00020000U)
-#define TSC_GROUP5_IO3 (0x00040000U)
-#define TSC_GROUP5_IO4 (0x00080000U)
-#define TSC_GROUP5_ALL_IOS (0x000F0000U)
-
-#define TSC_GROUP6_IO1 (0x00100000U)
-#define TSC_GROUP6_IO2 (0x00200000U)
-#define TSC_GROUP6_IO3 (0x00400000U)
-#define TSC_GROUP6_IO4 (0x00800000U)
-#define TSC_GROUP6_ALL_IOS (0x00F00000U)
-
-#define TSC_GROUP7_IO1 (0x01000000U)
-#define TSC_GROUP7_IO2 (0x02000000U)
-#define TSC_GROUP7_IO3 (0x04000000U)
-#define TSC_GROUP7_IO4 (0x08000000U)
-#define TSC_GROUP7_ALL_IOS (0x0F000000U)
-
-#define TSC_GROUP8_IO1 (0x10000000U)
-#define TSC_GROUP8_IO2 (0x20000000U)
-#define TSC_GROUP8_IO3 (0x40000000U)
-#define TSC_GROUP8_IO4 (0x80000000U)
-#define TSC_GROUP8_ALL_IOS (0xF0000000U)
-
-#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup TSC_Exported_Macros TSC Exported Macros
- * @{
- */
-
-/** @brief Reset TSC handle state.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
-
-/**
- * @brief Enable the TSC peripheral.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
-
-/**
- * @brief Disable the TSC peripheral.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
-
-/**
- * @brief Start acquisition.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
-
-/**
- * @brief Stop acquisition.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
-
-/**
- * @brief Set IO default mode to output push-pull low.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
-
-/**
- * @brief Set IO default mode to input floating.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
-
-/**
- * @brief Set synchronization polarity to falling edge.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
-
-/**
- * @brief Set synchronization polarity to rising edge and high level.
- * @param __HANDLE__ TSC handle
- * @retval None
- */
-#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
-
-/**
- * @brief Enable TSC interrupt.
- * @param __HANDLE__ TSC handle
- * @param __INTERRUPT__ TSC interrupt
- * @retval None
- */
-#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
- * @brief Disable TSC interrupt.
- * @param __HANDLE__ TSC handle
- * @param __INTERRUPT__ TSC interrupt
- * @retval None
- */
-#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
-
-/** @brief Check whether the specified TSC interrupt source is enabled or not.
- * @param __HANDLE__ TSC Handle
- * @param __INTERRUPT__ TSC interrupt
- * @retval SET or RESET
- */
-#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Check whether the specified TSC flag is set or not.
- * @param __HANDLE__ TSC handle
- * @param __FLAG__ TSC flag
- * @retval SET or RESET
- */
-#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/**
- * @brief Clear the TSC's pending flag.
- * @param __HANDLE__ TSC handle
- * @param __FLAG__ TSC flag
- * @retval None
- */
-#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enable schmitt trigger hysteresis on a group of IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
-
-/**
- * @brief Disable schmitt trigger hysteresis on a group of IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
-
-/**
- * @brief Open analog switch on a group of IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
-
-/**
- * @brief Close analog switch on a group of IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
-
-/**
- * @brief Enable a group of IOs in channel mode.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
-
-/**
- * @brief Disable a group of channel IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
-
-/**
- * @brief Enable a group of IOs in sampling mode.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
-
-/**
- * @brief Disable a group of sampling IOs.
- * @param __HANDLE__ TSC handle
- * @param __GX_IOY_MASK__ IOs mask
- * @retval None
- */
-#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
-
-/**
- * @brief Enable acquisition groups.
- * @param __HANDLE__ TSC handle
- * @param __GX_MASK__ Groups mask
- * @retval None
- */
-#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
-
-/**
- * @brief Disable acquisition groups.
- * @param __HANDLE__ TSC handle
- * @param __GX_MASK__ Groups mask
- * @retval None
- */
-#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
-
-/** @brief Gets acquisition group status.
- * @param __HANDLE__ TSC Handle
- * @param __GX_INDEX__ Group index
- * @retval SET or RESET
- */
-#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
-((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup TSC_Private_Macros TSC Private Macros
- * @{
- */
-
-#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
- ((VAL) == TSC_CTPH_2CYCLES) || \
- ((VAL) == TSC_CTPH_3CYCLES) || \
- ((VAL) == TSC_CTPH_4CYCLES) || \
- ((VAL) == TSC_CTPH_5CYCLES) || \
- ((VAL) == TSC_CTPH_6CYCLES) || \
- ((VAL) == TSC_CTPH_7CYCLES) || \
- ((VAL) == TSC_CTPH_8CYCLES) || \
- ((VAL) == TSC_CTPH_9CYCLES) || \
- ((VAL) == TSC_CTPH_10CYCLES) || \
- ((VAL) == TSC_CTPH_11CYCLES) || \
- ((VAL) == TSC_CTPH_12CYCLES) || \
- ((VAL) == TSC_CTPH_13CYCLES) || \
- ((VAL) == TSC_CTPH_14CYCLES) || \
- ((VAL) == TSC_CTPH_15CYCLES) || \
- ((VAL) == TSC_CTPH_16CYCLES))
-
-#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
- ((VAL) == TSC_CTPL_2CYCLES) || \
- ((VAL) == TSC_CTPL_3CYCLES) || \
- ((VAL) == TSC_CTPL_4CYCLES) || \
- ((VAL) == TSC_CTPL_5CYCLES) || \
- ((VAL) == TSC_CTPL_6CYCLES) || \
- ((VAL) == TSC_CTPL_7CYCLES) || \
- ((VAL) == TSC_CTPL_8CYCLES) || \
- ((VAL) == TSC_CTPL_9CYCLES) || \
- ((VAL) == TSC_CTPL_10CYCLES) || \
- ((VAL) == TSC_CTPL_11CYCLES) || \
- ((VAL) == TSC_CTPL_12CYCLES) || \
- ((VAL) == TSC_CTPL_13CYCLES) || \
- ((VAL) == TSC_CTPL_14CYCLES) || \
- ((VAL) == TSC_CTPL_15CYCLES) || \
- ((VAL) == TSC_CTPL_16CYCLES))
-
-#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-
-#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
-
-#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
-
-#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
- ((VAL) == TSC_PG_PRESC_DIV2) || \
- ((VAL) == TSC_PG_PRESC_DIV4) || \
- ((VAL) == TSC_PG_PRESC_DIV8) || \
- ((VAL) == TSC_PG_PRESC_DIV16) || \
- ((VAL) == TSC_PG_PRESC_DIV32) || \
- ((VAL) == TSC_PG_PRESC_DIV64) || \
- ((VAL) == TSC_PG_PRESC_DIV128))
-
-#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
- ((VAL) == TSC_MCV_511) || \
- ((VAL) == TSC_MCV_1023) || \
- ((VAL) == TSC_MCV_2047) || \
- ((VAL) == TSC_MCV_4095) || \
- ((VAL) == TSC_MCV_8191) || \
- ((VAL) == TSC_MCV_16383))
-
-#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
-
-#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
-
-#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
-
-#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
- ((VAL) == TSC_IOMODE_CHANNEL) || \
- ((VAL) == TSC_IOMODE_SHIELD) || \
- ((VAL) == TSC_IOMODE_SAMPLING))
-
-#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-
-#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TSC_Exported_Functions
- * @{
- */
-
-/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
- /* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
-void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
-void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
-/**
- * @}
- */
-
-/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
-/**
- * @}
- */
-
-/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
-/**
- * @}
- */
-
-/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
-/**
- * @}
- */
-
-/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* TSC IRQHandler and Callbacks used in Interrupt mode */
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
-void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
-void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F3xx_TSC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h
deleted file mode 100644
index c63fbb49ea2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h
+++ /dev/null
@@ -1,1446 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_uart.h
- * @author MCD Application Team
- * @brief Header file of UART HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_UART_H
-#define __STM32F3xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
- * @{
- */
-
-/**
- * @brief UART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following formula:
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
- - If oversampling is 8U,
- Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length. */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode. */
-
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control. */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U).
- This parameter can be a value of @ref UART_Over_Sampling. */
-
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
-}UART_InitTypeDef;
-
-/**
- * @brief UART Advanced Features initalization structure definition
- */
-typedef struct
-{
- uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
- Advanced Features may be initialized at the same time .
- This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref UART_Tx_Inv. */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref UART_Rx_Inv. */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
- vs negative/inverted logic).
- This parameter can be a value of @ref UART_Data_Inv. */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref UART_Rx_Tx_Swap. */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref UART_Overrun_Disable. */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
-
- uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
- This parameter can be a value of @ref UART_AutoBaudRate_Enable */
-
- uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
- detection is carried out.
- This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref UART_MSB_First. */
-} UART_AdvFeatureInitTypeDef;
-
-/**
- * @brief UART wake up from stop mode parameters
- */
-typedef struct
-{
- uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
- This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
- If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
- be filled up. */
-
- uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref UART_WakeUp_Address_Length. */
-
- uint8_t Address; /*!< UART/USART node address (7-bit long max). */
-} UART_WakeUpTypeDef;
-
-/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
- * - gState contains UART state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
-
-/**
- * @brief UART clock sources definition
- */
-typedef enum
-{
- UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
-
-/**
- * @brief UART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< UART registers base address */
-
- UART_InitTypeDef Init; /*!< UART communication parameters */
-
- UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
-
- uint16_t Mask; /*!< UART Rx RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< UART Error code */
-
-}UART_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
- * @{
- */
-
-/** @defgroup UART_Error UART Error
- * @{
- */
-#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
- * @{
- */
-#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
-#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
-#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup UART_Parity UART Parity
- * @{
- */
-#define UART_PARITY_NONE (0x00000000U) /*!< No parity */
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
- * @{
- */
-#define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
-/**
- * @}
- */
-
-/** @defgroup UART_Mode UART Transfer Mode
- * @{
- */
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup UART_State UART State
- * @{
- */
-#define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
- * @{
- */
-#define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16U */
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
- * @{
- */
-#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */
-#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
-/**
- * @}
- */
-
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
- * @{
- */
-#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN UART Local Interconnection Network mode
- * @{
- */
-#define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */
-#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
-/**
- * @}
- */
-
-/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Tx UART DMA Tx
- * @{
- */
-#define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Rx UART DMA Rx
- * @{
- */
-#define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
- * @{
- */
-#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
- * @{
- */
-#define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
- * @{
- */
-#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
-/**
- * @}
- */
-
-/** @defgroup UART_Flags UART Status Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */
-#define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */
-#define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */
-#define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */
-#define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */
-#define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */
-#define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */
-#define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */
-#define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */
-#define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */
-#define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */
-#define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */
-#define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag */
-#define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */
-#define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */
-#define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */
-#define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */
-#define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */
-#define UART_FLAG_NE (0x00000004U) /*!< UART noise error */
-#define UART_FLAG_FE (0x00000002U) /*!< UART frame error */
-#define UART_FLAG_PE (0x00000001U) /*!< UART parity error */
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UART Interrupts Definition
- * Elements values convention: 000ZZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZZ : Flag position in the ISR register(5bits)
- * @{
- */
-#define UART_IT_PE (0x0028U) /*!< UART parity error interruption */
-#define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */
-#define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */
-#define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */
-#define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */
-#define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */
-#define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */
-#define UART_IT_CM (0x112EU) /*!< UART character match interruption */
-#define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */
-#define UART_IT_ERR (0x0060U) /*!< UART error interruption */
-#define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */
-#define UART_IT_NE (0x0200U) /*!< UART noise error interruption */
-#define UART_IT_FE (0x0100U) /*!< UART frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
- * @{
- */
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
-#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
-#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
-/**
- * @}
- */
-
-/** @defgroup UART_Request_Parameters UART Request Parameters
- * @{
- */
-#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
- * @{
- */
-#define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
-#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
-#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
-#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
-#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */
-#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
-/**
- * @}
- */
-
-/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
- * @{
- */
-#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
-#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
- * @{
- */
-#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
- * @{
- */
-#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
-#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
- * @{
- */
-#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
-#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
-/**
- * @}
- */
-
-/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
- * @{
- */
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
-/**
- * @}
- */
-
-/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
- * @{
- */
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
-/**
- * @}
- */
-
-/** @defgroup UART_MSB_First UART Advanced Feature MSB First
- * @{
- */
-#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
- * @{
- */
-#define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
- * @{
- */
-#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */
-#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
-/**
- * @}
- */
-
-/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
- * @{
- */
-#define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
- * @{
- */
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
-/**
- * @}
- */
-
-/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
- * @{
- */
-#define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */
-/**
- * @}
- */
-
-/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
- * @{
- */
-#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /*!< UART polling-based communications time-out value */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
- * @{
- */
-
-/** @brief Reset UART handle states.
- * @param __HANDLE__ UART handle.
- * @retval None
- */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0U)
-/** @brief Flush the UART Data registers.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0U)
-
-/** @brief Clear the specified UART pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
- * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
- * @retval None
- */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the UART PE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
-
-/** @brief Clear the UART FE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
-
-/** @brief Clear the UART NE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
-
-/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
-
-/** @brief Clear the UART IDLE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
-
-/** @brief Check whether the specified UART flag is set or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
- * @arg @ref UART_FLAG_RWU Receiver wake up flag
- * @arg @ref UART_FLAG_SBKF Send Break flag
- * @arg @ref UART_FLAG_CMF Character match flag
- * @arg @ref UART_FLAG_BUSY Busy flag
- * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
- * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
- * @arg @ref UART_FLAG_EOBF End of block flag
- * @arg @ref UART_FLAG_RTOF Receiver timeout flag
- * @arg @ref UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5)
- * @arg @ref UART_FLAG_LBDF LIN Break detection flag
- * @arg @ref UART_FLAG_TXE Transmit data register empty flag
- * @arg @ref UART_FLAG_TC Transmission Complete flag
- * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
- * @arg @ref UART_FLAG_IDLE Idle Line detection flag
- * @arg @ref UART_FLAG_ORE Overrun Error flag
- * @arg @ref UART_FLAG_NE Noise Error flag
- * @arg @ref UART_FLAG_FE Framing Error flag
- * @arg @ref UART_FLAG_PE Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-
-/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __INTERRUPT__ specifies the UART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
-/** @brief Check whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_ORE Overrun Error interrupt
- * @arg @ref UART_IT_NE Noise Error interrupt
- * @arg @ref UART_IT_FE Framing Error interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
-
-/** @brief Check whether the specified UART interrupt source is enabled or not.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
- * @arg @ref UART_IT_LBD LIN Break detection interrupt
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
-
-/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
- * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
- * @retval None
- */
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Set a specific UART request flag.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __REQ__ specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
- * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
- * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
- * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
- * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
- * @retval None
- */
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
-
-/** @brief Enable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief Enable CTS flow control.
- * @note This macro allows to enable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0U)
-
-/** @brief Disable CTS flow control.
- * @note This macro allows to disable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0U)
-
-/** @brief Enable RTS flow control.
- * @note This macro allows to enable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0U)
-
-/** @brief Disable RTS flow control.
- * @note This macro allows to disable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0U)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
- * @param __PCLK__ UART clock.
- * @param __BAUD__ Baud rate set by the user.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
- * @param __PCLK__ UART clock.
- * @param __BAUD__ Baud rate set by the user.
- * @retval Division result
- */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
-
-/** @brief Check UART Baud rate.
- * @param __BAUDRATE__ Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
- */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
-
-/** @brief Check UART assertion time.
- * @param __TIME__ 5-bit value assertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/** @brief Check UART deassertion time.
- * @param __TIME__ 5-bit value deassertion time.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-
-/**
- * @brief Ensure that UART frame number of stop bits is valid.
- * @param __STOPBITS__ UART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
- ((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_1_5) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-
-/**
- * @brief Ensure that UART frame parity is valid.
- * @param __PARITY__ UART frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
- ((__PARITY__) == UART_PARITY_EVEN) || \
- ((__PARITY__) == UART_PARITY_ODD))
-
-/**
- * @brief Ensure that UART hardware flow control is valid.
- * @param __CONTROL__ UART hardware flow control.
- * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
- */
-#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
- (((__CONTROL__) == UART_HWCONTROL_NONE) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS) || \
- ((__CONTROL__) == UART_HWCONTROL_CTS) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-
-/**
- * @brief Ensure that UART communication mode is valid.
- * @param __MODE__ UART communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-
-/**
- * @brief Ensure that UART state is valid.
- * @param __STATE__ UART state.
- * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
-#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
- ((__STATE__) == UART_STATE_ENABLE))
-
-/**
- * @brief Ensure that UART oversampling is valid.
- * @param __SAMPLING__ UART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == UART_OVERSAMPLING_8))
-
-/**
- * @brief Ensure that UART frame sampling is valid.
- * @param __ONEBIT__ UART frame sampling.
- * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
-#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-
-/**
- * @brief Ensure that Address Length detection parameter is valid.
- * @param __ADDRESS__ UART Adress length value.
- * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
- */
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
- ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-
-/**
- * @brief Ensure that UART auto Baud rate detection mode is valid.
- * @param __MODE__ UART auto Baud rate detection mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-
-/**
- * @brief Ensure that UART receiver timeout setting is valid.
- * @param __TIMEOUT__ UART receiver timeout setting.
- * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
- */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-
-/**
- * @brief Ensure that UART LIN state is valid.
- * @param __LIN__ UART LIN state.
- * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
- */
-#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
- ((__LIN__) == UART_LIN_ENABLE))
-
-/**
- * @brief Ensure that UART LIN break detection length is valid.
- * @param __LENGTH__ UART LIN break detection length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-
-/**
- * @brief Ensure that UART DMA TX state is valid.
- * @param __DMATX__ UART DMA TX state.
- * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
-#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
- ((__DMATX__) == UART_DMA_TX_ENABLE))
-
-/**
- * @brief Ensure that UART DMA RX state is valid.
- * @param __DMARX__ UART DMA RX state.
- * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
-#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
- ((__DMARX__) == UART_DMA_RX_ENABLE))
-
-/**
- * @brief Ensure that UART half-duplex state is valid.
- * @param __HDSEL__ UART half-duplex state.
- * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
- */
-#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
- ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up method is valid.
- * @param __WAKEUP__ UART wake-up method .
- * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
- */
-#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-/**
- * @brief Ensure that UART advanced features initialization is valid.
- * @param __INIT__ UART advanced features initialization.
- * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
- */
-#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
- UART_ADVFEATURE_TXINVERT_INIT | \
- UART_ADVFEATURE_RXINVERT_INIT | \
- UART_ADVFEATURE_DATAINVERT_INIT | \
- UART_ADVFEATURE_SWAP_INIT | \
- UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
- UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
- UART_ADVFEATURE_MSBFIRST_INIT))
-
-/**
- * @brief Ensure that UART frame TX inversion setting is valid.
- * @param __TXINV__ UART frame TX inversion setting.
- * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
- ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX inversion setting is valid.
- * @param __RXINV__ UART frame RX inversion setting.
- * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
- ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame data inversion setting is valid.
- * @param __DATAINV__ UART frame data inversion setting.
- * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
- ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-
-/**
- * @brief Ensure that UART frame RX/TX pins swap setting is valid.
- * @param __SWAP__ UART frame RX/TX pins swap setting.
- * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
- */
-#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
- ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-
-/**
- * @brief Ensure that UART frame overrun setting is valid.
- * @param __OVERRUN__ UART frame overrun setting.
- * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
- */
-#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
- ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-
-/**
- * @brief Ensure that UART auto Baud rate state is valid.
- * @param __AUTOBAUDRATE__ UART auto Baud rate state.
- * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-
-/**
- * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
- * @param __DMA__ UART DMA enabling or disabling on error setting.
- * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
- */
-#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/**
- * @brief Ensure that UART frame MSB first setting is valid.
- * @param __MSBFIRST__ UART frame MSB first setting.
- * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
- */
-#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
-
-/**
- * @brief Ensure that UART stop mode state is valid.
- * @param __STOPMODE__ UART stop mode state.
- * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
- ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
- * @brief Ensure that UART mute mode state is valid.
- * @param __MUTE__ UART mute mode state.
- * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
- */
-#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
- ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up selection is valid.
- * @param __WAKE__ UART wake-up selection.
- * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
- */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
- ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
- ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
-
-/**
- * @brief Ensure that UART driver enable polarity is valid.
- * @param __POLARITY__ UART driver enable polarity.
- * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
- */
-#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
- ((__POLARITY__) == UART_DE_POLARITY_LOW))
-
-/**
- * @brief Ensure that UART request parameter is valid.
- * @param __PARAM__ UART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
- ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
- ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-
-/**
- * @}
- */
-
-/* Include UART HAL Extended module */
-#include "stm32f3xx_hal_uart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Errors functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
- * @{
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h
deleted file mode 100644
index 18e4518c8e5..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_uart_ex.h
- * @author MCD Application Team
- * @brief Header file of UART HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_UART_EX_H
-#define __STM32F3xx_HAL_UART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UARTEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
- * @{
- */
-
-/** @defgroup UARTEx_Word_Length UARTEx Word Length
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
-#else
-#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
- * @{
- */
-
-/** @brief Report the UART clock source.
- * @param __HANDLE__ specifies the UART Handle.
- * @param __CLOCKSOURCE__ output variable.
- * @retval UART clocking source, written in __CLOCKSOURCE__.
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == UART4) \
- { \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
- case RCC_UART4CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART4CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART4CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART4CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if ((__HANDLE__)->Instance == UART5) \
- { \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
- case RCC_UART5CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_UART5CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_UART5CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_UART5CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#else
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-
-/** @brief Compute the UART mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define UART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
-} while(0U)
-#else
-#define UART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
-} while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Ensure that UART frame length is valid.
- * @param __LENGTH__ UART frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
- ((__LENGTH__) == UART_WORDLENGTH_8B) || \
- ((__LENGTH__) == UART_WORDLENGTH_9B))
-#else
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
- ((__LENGTH__) == UART_WORDLENGTH_9B))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_UART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h
deleted file mode 100644
index 104fad20be9..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h
+++ /dev/null
@@ -1,710 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_usart.h
- * @author MCD Application Team
- * @brief Header file of USART HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_USART_H
-#define __STM32F3xx_HAL_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
- The baud rate is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USARTEx_Word_Length. */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits. */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode. */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity. */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase. */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit. */
-}USART_InitTypeDef;
-
-/**
- * @brief HAL USART State structures definition
- */
-typedef enum
-{
- HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
-
-/**
- * @brief USART clock sources definitions
- */
-typedef enum
-{
- USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}USART_ClockSourceTypeDef;
-
-
-/**
- * @brief USART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- USART_InitTypeDef Init; /*!< USART communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< USART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< USART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
-
- uint16_t Mask; /*!< USART Rx RDR register mask */
-
- DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code */
-
-}USART_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_Error USART Error
- * @{
- */
-#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
- * @{
- */
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
-#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_Parity USART Parity
- * @{
- */
-#define USART_PARITY_NONE (0x00000000U) /*!< No parity */
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
-/**
- * @}
- */
-
-/** @defgroup USART_Mode USART Mode
- * @{
- */
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock USART Clock
- * @{
- */
-#define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
- * @{
- */
-#define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
- * @{
- */
-#define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit USART Last Bit
- * @{
- */
-#define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_Request_Parameters USART Request Parameters
- * @{
- */
-#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-/**
- * @}
- */
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
-#define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
-#define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
-#define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
-#define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
-#define USART_FLAG_LBDF (0x00000100U) /*!< USART LIN break detection flag */
-#define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
-#define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
-#define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
-#define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
-#define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
-#define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
-#define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
-#define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-
-#define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
-#define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
-#define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
-#define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
-#define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
-#define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
-#define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
-#define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
-#define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
-/**
- * @}
- */
-
-/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
- * @{
- */
-#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-/**
- * @}
- */
-
-/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
- * @{
- */
-#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @brief Reset USART handle state.
- * @param __HANDLE__ USART handle.
- * @retval None
- */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief Flush the USART Data registers.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
- } while(0U)
-
-/** @brief Check whether the specified USART flag is set or not.
- * @param __HANDLE__ specifies the USART Handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
- * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
- * @arg @ref USART_FLAG_BUSY Busy flag
- * @arg @ref USART_FLAG_CTS CTS Change flag
- * @arg @ref USART_FLAG_TXE Transmit data register empty flag
- * @arg @ref USART_FLAG_TC Transmission Complete flag
- * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
- * @arg @ref USART_FLAG_IDLE Idle Line detection flag
- * @arg @ref USART_FLAG_ORE OverRun Error flag
- * @arg @ref USART_FLAG_NE Noise Error flag
- * @arg @ref USART_FLAG_FE Framing Error flag
- * @arg @ref USART_FLAG_PE Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified USART pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg @ref USART_CLEAR_PEF
- * @arg @ref USART_CLEAR_FEF
- * @arg @ref USART_CLEAR_NEF
- * @arg @ref USART_CLEAR_OREF
- * @arg @ref USART_CLEAR_IDLEF
- * @arg @ref USART_CLEAR_TCF
- * @arg @ref USART_CLEAR_CTSF
- * @retval None
- */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief Clear the USART PE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
-
-/** @brief Clear the USART FE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
-
-/** @brief Clear the USART NE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
-
-/** @brief Clear the USART ORE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
-
-/** @brief Clear the USART IDLE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
-
-/** @brief Enable the specified USART interrupt.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __INTERRUPT__ specifies the USART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-/** @brief Disable the specified USART interrupt.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __INTERRUPT__ specifies the USART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-
-/** @brief Check whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __IT__ specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_ORE OverRun Error interrupt
- * @arg @ref USART_IT_NE Noise Error interrupt
- * @arg @ref USART_IT_FE Framing Error interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
-
-/** @brief Check whether the specified USART interrupt source is enabled or not.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __IT__ specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_ORE OverRun Error interrupt
- * @arg @ref USART_IT_NE Noise Error interrupt
- * @arg @ref USART_IT_FE Framing Error interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
- (((uint16_t)(__IT__)) & USART_IT_MASK)))
-
-
-/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt.
- * This parameter can be one of the following values:
- * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
- * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @retval None
- */
-#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-/** @brief Set a specific USART request flag.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __REQ__ specifies the request flag to set.
- * This parameter can be one of the following values:
- * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
- * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
- * @retval None
- */
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
-
-/** @brief Enable the USART one bit sample method.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Disable the USART one bit sample method.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief Enable USART.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable USART.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-
-/** @brief Check USART Baud rate.
- * @param __BAUDRATE__ Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8).
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
-
-/**
- * @brief Ensure that USART frame number of stop bits is valid.
- * @param __STOPBITS__ USART frame number of stop bits.
- * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
-#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
- ((__STOPBITS__) == USART_STOPBITS_1) || \
- ((__STOPBITS__) == USART_STOPBITS_1_5) || \
- ((__STOPBITS__) == USART_STOPBITS_2))
-
-/**
- * @brief Ensure that USART frame parity is valid.
- * @param __PARITY__ USART frame parity.
- * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
-#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
- ((__PARITY__) == USART_PARITY_EVEN) || \
- ((__PARITY__) == USART_PARITY_ODD))
-
-/**
- * @brief Ensure that USART communication mode is valid.
- * @param __MODE__ USART communication mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
-
-/**
- * @brief Ensure that USART clock state is valid.
- * @param __CLOCK__ USART clock state.
- * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
- */
-#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
- ((__CLOCK__) == USART_CLOCK_ENABLE))
-
-/**
- * @brief Ensure that USART frame polarity is valid.
- * @param __CPOL__ USART frame polarity.
- * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
-#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
-
-/**
- * @brief Ensure that USART frame phase is valid.
- * @param __CPHA__ USART frame phase.
- * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
- */
-#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
-
-/**
- * @brief Ensure that USART frame last bit clock pulse setting is valid.
- * @param __LASTBIT__ USART frame last bit clock pulse setting.
- * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
- */
-#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
- ((__LASTBIT__) == USART_LASTBIT_ENABLE))
-
-/**
- * @brief Ensure that USART request parameter is valid.
- * @param __PARAM__ USART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
-
-/**
- * @}
- */
-
-/* Include USART HAL Extended module */
-#include "stm32f3xx_hal_usart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
- * @{
- */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h
deleted file mode 100644
index 11c50b1ff9a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_usart_ex.h
- * @author MCD Application Team
- * @brief Header file of USART HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_USART_EX_H
-#define __STM32F3xx_HAL_USART_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USARTEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
- * @{
- */
-
-/** @defgroup USARTEx_Word_Length USARTEx Word Length
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
-#else
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
- * @{
- */
-
-/** @brief Report the USART clock source.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __CLOCKSOURCE__ output variable.
- * @retval the USART clocking source, written in __CLOCKSOURCE__.
- */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#else
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0U)
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-/** @brief Compute the USART mask to apply to retrieve the received data
- * according to the word length and to the parity bits activation.
- * @note If PCE = 1, the parity bit is not included in the data extracted
- * by the reception API().
- * This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
-} while(0U)
-#else
-#define USART_MASK_COMPUTATION(__HANDLE__) \
- do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
-} while(0U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-
-/**
- * @brief Ensure that USART frame length is valid.
- * @param __LENGTH__ USART frame length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
- ((__LENGTH__) == USART_WORDLENGTH_8B) || \
- ((__LENGTH__) == USART_WORDLENGTH_9B))
-#else
-#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
- ((__LENGTH__) == USART_WORDLENGTH_9B))
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_USART_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h
deleted file mode 100644
index e77336d8c3d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_WWDG_H
-#define __STM32F3xx_HAL_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
- * @{
- */
-
-/**
- * @brief WWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
- This parameter can be a value of @ref WWDG_Prescaler */
-
- uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU */
-
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU */
-
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
- This parameter can be a value of @ref WWDG_EWI_Mode */
-
-}WWDG_InitTypeDef;
-
-/**
- * @brief WWDG handle Structure definition
- */
-typedef struct
-{
- WWDG_TypeDef *Instance; /*!< Register base address */
-
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-
-}WWDG_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
- * @{
- */
-#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
- * @brief WWDG Flag definition
- * @{
- */
-#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
- * @{
- */
-#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096U)/1U */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096U)/2U */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096U)/4U */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096U)/8U */
-/**
- * @}
- */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
- * @{
- */
-#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
-#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
- * @{
- */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
- ((__MODE__) == WWDG_EWI_DISABLE))
-/**
- * @}
- */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the WWDG peripheral.
- * @param __HANDLE__ WWDG handle
- * @retval None
- */
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
- * @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
- * @brief Check whether the selected WWDG interrupt has occurred or not.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the it to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief Clear the WWDG interrupt pending bits.
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified WWDG flag is set or not.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the WWDG's pending flags.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval None
- */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Check whether the specified WWDG interrupt source is enabled or not.
- * @param __HANDLE__ WWDG Handle.
- * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early Wakeup Interrupt
- * @retval state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/**
- * @}
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h
deleted file mode 100644
index a6739c8797a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_adc.h
+++ /dev/null
@@ -1,10833 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_ADC_H
-#define __STM32F3xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. */
-/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
-/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
-/* features (refer to reference manual). */
-/* - STM32F37x: */
-/* ADC IP 1Msamples/sec, 1 ADC instance */
-/* This file contains the drivers of these ADC IP, located in 2 area */
-/* delimited by compilation switches. */
-
-#if defined(ADC5_V1_1)
-
-#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
-
-/** @defgroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Internal mask for ADC group regular sequencer: */
-/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
-/* - sequencer register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group regular sequencer configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
-#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
-#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
-#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
-
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
-#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group regular sequencer bits information to be inserted */
-/* into ADC group regular sequencer ranks literals definition. */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
-
-
-
-/* Internal mask for ADC group injected sequencer: */
-/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
-/* - data register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group injected data register */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
-#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
-#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
-#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
-
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
-#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group injected sequencer bits information to be inserted */
-/* into ADC group injected sequencer ranks literals definition. */
-#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
-#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
-#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
-#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
-
-
-
-/* Internal mask for ADC group regular trigger: */
-/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
-/* - regular trigger source */
-/* - regular trigger edge */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
- ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \
- ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \
- ((ADC_CFGR_EXTSEL) << (4U * 3U)) )
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
-
-/* Definition of ADC group regular trigger bits information. */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
-
-
-
-/* Internal definitions for ADC group regular trigger sources: */
-/* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources */
-/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
-/* available on the selected device). */
-
-#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-/* Internal mask offset for ADC group injected trigger sources */
-/* available only on specific ADC instances. */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_REG_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
-#define ADC_REG_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
-#endif
-
-/* Internal mask for ADC group injected trigger: */
-/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
-/* - injected trigger source */
-/* - injected trigger edge */
-#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
-
-/* Definition of ADC group injected trigger bits information. */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
-
-
-
-/* Internal definitions for ADC group injected trigger sources: */
-/* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources */
-/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
-/* available on the selected device). */
-
-#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-/* Internal mask offset for ADC group injected trigger sources */
-/* available only on specific ADC instances. */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_INJ_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
-#define ADC_INJ_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
-#endif
-
-
-
-
-/* Internal mask for ADC channel: */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
-/* - channel identifier defined by number */
-/* - channel identifier defined by bitfield */
-/* - channel differentiation between external channels (connected to */
-/* GPIO pins) and internal channels (connected to internal paths) */
-/* - channel sampling time defined by SMPRx register offset */
-/* and SMPx bits positions into SMPRx register */
-#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
-#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
-
-/* Internal register offset for ADC channel sampling time configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
-#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
-
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
-
-/* Definition of channels ID number information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
-#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
-
-/* Definition of channels ID bitfield information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
-#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
-#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
-#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
-#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
-#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
-#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
-#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
-#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
-#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
-#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
-#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
-#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
-#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
-#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
-#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
-#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
-#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
-#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
-
-/* Definition of channels sampling time information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
-#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
-#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
-#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
-#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
-#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
-#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
-#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
-#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
-#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
-#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
-#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
-#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
-#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
-#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
-#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
-#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
-#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
-#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
-
-
-/* Internal mask for ADC mode single or differential ended: */
-/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
-/* the relevant bits for: */
-/* (concatenation of multiple bits used in different registers) */
-/* - ADC calibration: calibration start, calibration factor get or set */
-/* - ADC channels: set each ADC channel ending mode */
-#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
-#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
-#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
-#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
-
-
-/* Internal mask for ADC analog watchdog: */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
-/* (concatenation of multiple bits used in different analog watchdogs, */
-/* (feature of several watchdogs not available on all STM32 families)). */
-/* - analog watchdog 1: monitored channel defined by number, */
-/* selection of ADC group (ADC groups regular and-or injected). */
-/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
-/* selection on groups. */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
-#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
-#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
-
-/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
-/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
-#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
-#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
-
-#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
-#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
-#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
-#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
-
-
-/* Internal mask for ADC offset: */
-/* Internal register offset for ADC offset number configuration */
-#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
-#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
-#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
-#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
-#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
-
-
-/* ADC registers bits positions */
-#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
-#define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
-#define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
-#define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
-#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
-
-
-/* ADC registers bits groups */
-#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
-
-
-/* ADC internal channels related definitions */
-/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
-/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature 25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP (( int32_t) 25) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
- */
-#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
- */
-#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of ADC common parameters
- * and multimode
- * (all ADC instances belonging to the same ADC common instance).
- * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
- * is conditioned to ADC instances state (all ADC instances
- * sharing the same ADC common instance):
- * All ADC instances sharing the same ADC common instance must be
- * disabled.
- */
-typedef struct
-{
- uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
- This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 serie, if ADC group injected is used, some
- clock ratio constraints between ADC clock and AHB clock
- must be respected. Refer to reference manual.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
- This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
-
- uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
- This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
-
- uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
- This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-} LL_ADC_CommonInitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t Resolution; /*!< Set ADC resolution.
- This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
-
- uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
- This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
-
- uint32_t LowPowerMode; /*!< Set ADC low power mode.
- This parameter can be a value of @ref ADC_LL_EC_LP_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
- (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
- In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group regular sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
- This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
- Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
- This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
- uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
- data preserved or overwritten.
- This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
- (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
- In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group injected sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
-
- uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
- Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
-
-} LL_ADC_INJ_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
- * @brief Flags defines which can be used with LL_ADC_ReadReg function
- * @{
- */
-#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
-#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
-#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
-#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
-#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
-#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
-#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
-#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
-#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
-#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
-#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
-#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
-#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
-#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
-#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
-#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
-#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
-#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
-#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
-#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
-#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
-#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
-#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
-#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
-#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
-#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
-#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
-#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
-#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
- * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
- * @{
- */
-#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
-#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
-#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
-#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
-#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
-#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
-#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
-#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
-#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
-#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
- * @{
- */
-/* List of ADC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
- * @{
- */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
-#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
- * @{
- */
-/* Note: Other measurement paths to internal channels may be available */
-/* (connections to other peripherals). */
-/* If they are not listed below, they do not require any specific */
-/* path enable. In this case, Access to measurement path is done */
-/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
-#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
- * @{
- */
-#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
-#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
-#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
- * @{
- */
-#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
- * @{
- */
-#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */
-#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
- * @{
- */
-#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
-#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
-#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
-#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
- * @{
- */
-#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
-#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
- * @{
- */
-#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
- * @{
- */
-#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
-#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
-#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
-#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
-#if defined(OPAMP1_CSR_OPAMP1EN)
-#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
-#endif
-#if defined(OPAMP2_CSR_OPAMP2EN)
-#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
-#endif
-#if defined(OPAMP3_CSR_OPAMP3EN)
-#define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
-#endif
-#if defined(OPAMP4_CSR_OPAMP4EN)
-#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
- * @{
- */
-#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
-#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for */
-/* ADC instances ADCx available on the selected device) */
-/* Note: Literal without suffix "ADCxy" means that external trigger */
-/* is available on all ADC instances. */
-/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
-/* register SYSCFG_CFGR4. Refer to reference manual. */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif /* STM32F303xE || STM32F398xx */
-
-/* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for */
-/* ADC instances ADCx available on the selected device) */
-/* Note: Literal without suffix "ADCxy" means that external trigger */
-/* is available on all ADC instances. */
-/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
-/* register SYSCFG_CFGR4. Refer to reference manual. */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif /* STM32F303xE || STM32F398xx */
-
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F334x8)
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
- * @{
- */
-#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
-* @{
-*/
-#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
- * @{
- */
-#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
-* @{
-*/
-#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
-#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
- * @{
- */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
-#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- * @{
- */
-#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
-#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
-#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
-#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
-#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
-#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
-#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
-#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
-#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
-#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
-#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
-#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
-#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
-#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
-#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
-#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
- * @{
- */
-#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
-#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for */
-/* ADC instances ADCx available on the selected device) */
-/* Note: Literal without suffix "ADCxy" means that external trigger */
-/* is available on all ADC instances. */
-/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
-/* register SYSCFG_CFGR4. Refer to reference manual. */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif /* STM32F303xE || STM32F398xx */
-
-/* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for */
-/* ADC instances ADCx available on the selected device) */
-/* Note: Literal without suffix "ADCxy" means that external trigger */
-/* is available on all ADC instances. */
-/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event). */
-/* JEXT2 is the main trigger, JEXT5 is kept as spare trigger for */
-/* future devices. */
-/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
-/* register SYSCFG_CFGR4. Refer to reference manual. */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif /* STM32F303xE || STM32F398xx */
-
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F334x8)
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
- * @{
- */
-#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
-#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
-#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
-* @{
-*/
-#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
-#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
- * @{
- */
-#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
-#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
- * @{
- */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
-#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- * @{
- */
-#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
-#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
-#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
-#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- * @{
- */
-#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
-#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_4CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 4.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 19.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_61CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_181CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 181.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_601CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
- * @{
- */
-#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
-#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
-#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- * @{
- */
-#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
-#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
- * @{
- */
-#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
-#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
-#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
-#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
-#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
-#if defined(OPAMP1_CSR_OPAMP1EN)
-#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
-#endif
-#if defined(OPAMP2_CSR_OPAMP2EN)
-#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
-#endif
-#if defined(OPAMP3_CSR_OPAMP3EN)
-#define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
-#endif
-#if defined(OPAMP4_CSR_OPAMP4EN)
-#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
-#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
-#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
- * @{
- */
-#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
-#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
-/**
- * @}
- */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */
-#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
-#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
-#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
- * @{
- */
-#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
- * @{
- */
-#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
-#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
- * @{
- */
-#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
-#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
-#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
-/**
- * @}
- */
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-
-/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
- * @note Only ADC IP HW delays are defined in ADC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
-/* not timeout values. */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
-/* - ADC calibration time: maximum delay is 112/fADC. */
-/* (refer to device datasheet, parameter "tCAL") */
-/* - ADC enable time: maximum delay is 1 conversion cycle. */
-/* (refer to device datasheet, parameter "tSTAB") */
-/* - ADC disable time: maximum delay should be a few ADC clock cycles */
-/* - ADC stop conversion time: maximum delay should be a few ADC clock */
-/* cycles */
-/* - ADC conversion time: duration depending on ADC clock and ADC */
-/* configuration. */
-/* (refer to device reference manual, section "Timing") */
-
-/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
-/* Delay set to maximum value (refer to device datasheet, */
-/* parameter "tADCVREG_STUP"). */
-/* Unit: us */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
-
-/* Delay for internal voltage reference stabilization time. */
-/* Delay set to maximum value (refer to device datasheet, */
-/* parameter "tstart_vrefint"). */
-/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay for temperature sensor stabilization time. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
-
-/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
-/* are required between ADC end of calibration and ADC enable. */
-/* Wait time can be computed in user application by waiting for the */
-/* equivalent number of CPU cycles, by taking into account */
-/* ratio of CPU clock versus ADC clock prescalers. */
-/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get ADC channel number in decimal format
- * from literals LL_ADC_CHANNEL_x.
- * @note Example:
- * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
- * will return decimal number "4".
- * @note The input can be a value from functions where a channel
- * number is returned, either defined with number
- * or with bitfield (only one bit must be set).
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.
- * @retval Value between Min_Data=0 and Max_Data=18
- */
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
- ? ( \
- ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
- ) \
- : \
- ( \
- POSITION_VAL((__CHANNEL__)) \
- ) \
- )
-
-/**
- * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
- * from number in decimal format.
- * @note Example:
- * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- * will return a data equivalent to "LL_ADC_CHANNEL_4".
- * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
- * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9U) \
- ? ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
- (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- : \
- ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
- (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- )
-
-/**
- * @brief Helper macro to determine whether the selected channel
- * corresponds to literal definitions of driver.
- * @note The different literal definitions of ADC channels are:
- * - ADC internal channel:
- * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
- * - ADC external channel (channel connected to a GPIO pin):
- * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
- * @note The channel parameter must be a value defined from literal
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
- * must not be a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
- * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
-
-/**
- * @brief Helper macro to convert a channel defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * to its equivalent parameter definition of a ADC external channel
- * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
- * @note The channel parameter can be, additionally to a value
- * defined from parameter definition of a ADC internal channel
- * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is returned
- * from ADC registers.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
- * @brief Helper macro to determine whether the internal channel
- * selected is available on the ADC instance selected.
- * @note The channel parameter must be a value defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * must not be a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __ADC_INSTANCE__ ADC instance
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.
- * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
- * Value "1" if the internal channel selected is available on the ADC instance selected.
- */
-#if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC2) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC3) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC4) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) \
- ) \
- : \
- (0U) \
- )
-#elif defined (ADC1) && defined (ADC2)
-#if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC2) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
- ) \
- : \
- (0U) \
- )
-#elif defined(OPAMP2_CSR_OPAMP2EN)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC2) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
- ) \
- : \
- (0U) \
- )
-#else
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC2) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
- ) \
- : \
- (0U) \
- )
-#endif
-#elif defined (ADC1)
-#if defined(OPAMP1_CSR_OPAMP1EN)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
- )
-#else
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
- )
-#endif
-#endif
-
-/**
- * @brief Helper macro to define ADC analog watchdog parameter:
- * define a single channel to monitor with analog watchdog
- * from sequencer channel and groups definition.
- * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
- * Example:
- * LL_ADC_SetAnalogWDMonitChannels(
- * ADC1, LL_ADC_AWD1,
- * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
- * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
- *
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
- * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- * @param __GROUP__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_GROUP_REGULAR
- * @arg @ref LL_ADC_GROUP_INJECTED
- * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
- * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
- *
- * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
- * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
- * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
- * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
- * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
- * (5) On STM32F3, ADC channel available only on all ADC instances, but
- * only one ADC instance is allowed to be connected to VrefInt at the same time.
- */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
- (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
- : \
- ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
- : \
- (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
- )
-
-/**
- * @brief Helper macro to set the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
- * or @ref LL_ADC_SetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to set the value of
- * analog watchdog threshold high (on 8 bits):
- * LL_ADC_SetAnalogWDThresholds
- * (< ADCx param >,
- * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_BUS_H
-#define __STM32F3xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- * @{
- */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- * @{
- */
-#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
-#if defined(DMA2)
-#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
-#endif /*DMA2*/
-#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
-#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
-#if defined(FMC_Bank1)
-#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
-#endif /*FMC_Bank1*/
-#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
-#if defined(GPIOH)
-#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
-#endif /*GPIOH*/
-#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
-#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
-#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
-#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
-#if defined(GPIOE)
-#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
-#endif /*GPIOE*/
-#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
-#if defined(GPIOG)
-#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
-#endif /*GPIOH*/
-#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
-#if defined(RCC_AHBENR_ADC1EN)
-#define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
-#endif /*RCC_AHBENR_ADC1EN*/
-#if defined(ADC1_2_COMMON)
-#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
-#endif /*ADC1_2_COMMON*/
-#if defined(ADC3_4_COMMON)
-#define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
-#endif /*ADC3_4_COMMON*/
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- * @{
- */
-#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
-#if defined(TIM3)
-#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
-#endif /*TIM3*/
-#if defined(TIM4)
-#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
-#endif /*TIM4*/
-#if defined(TIM5)
-#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
-#endif /*TIM5*/
-#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
-#endif /*TIM7*/
-#if defined(TIM12)
-#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
-#endif /*TIM12*/
-#if defined(TIM13)
-#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
-#endif /*TIM13*/
-#if defined(TIM14)
-#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
-#endif /*TIM14*/
-#if defined(TIM18)
-#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
-#endif /*TIM18*/
-#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
-#if defined(SPI2)
-#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
-#endif /*SPI2*/
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
-#endif /*SPI3*/
-#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
-#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
-#endif /*UART4*/
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
-#endif /*UART5*/
-#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
-#if defined(I2C2)
-#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
-#endif /*I2C2*/
-#if defined(USB)
-#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
-#endif /*USB*/
-#if defined(CAN)
-#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
-#endif /*CAN*/
-#if defined(DAC2)
-#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
-#endif /*DAC2*/
-#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
-#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
-#if defined(CEC)
-#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
-#endif /*CEC*/
-#if defined(I2C3)
-#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
-#endif /*I2C3*/
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- * @{
- */
-#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
-#if defined(RCC_APB2ENR_ADC1EN)
-#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
-#endif /*RCC_APB2ENR_ADC1EN*/
-#if defined(TIM1)
-#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
-#endif /*TIM1*/
-#if defined(SPI1)
-#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
-#endif /*SPI1*/
-#if defined(TIM8)
-#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
-#endif /*TIM8*/
-#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
-#if defined(SPI4)
-#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
-#endif /*SPI4*/
-#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
-#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
-#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
-#if defined(TIM19)
-#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
-#endif /*TIM19*/
-#if defined(TIM20)
-#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
-#endif /*TIM20*/
-#if defined(HRTIM1)
-#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
-#endif /*HRTIM1*/
-#if defined(SDADC1)
-#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
-#endif /*SDADC1*/
-#if defined(SDADC2)
-#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
-#endif /*SDADC2*/
-#if defined(SDADC3)
-#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
-#endif /*SDADC3*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- * @{
- */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
- * @{
- */
-
-/**
- * @brief Enable AHB1 peripherals clock.
- * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHBENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHBENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB1 peripheral clock is enabled or not
- * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB1 peripherals clock.
- * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-/**
- * @brief Force AHB1 peripherals reset.
- * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
- * @brief Release AHB1 peripherals reset.
- * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
- * @{
- */
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
- * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
- * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
- * @{
- */
-
-/**
- * @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
- * @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h
deleted file mode 100644
index bb4e492b169..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h
+++ /dev/null
@@ -1,2275 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_comp.h
- * @author MCD Application Team
- * @brief Header file of COMP LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_COMP_H
-#define __STM32F3xx_LL_COMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
-/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
-/* COMP IP from 3 to 7 instances and other specific features */
-/* (comparator output blanking, ...) (refer to reference manual). */
-/* - STM32F37x: */
-/* COMP IP with 2 instances */
-/* This file contains the drivers of these COMP IP, located in 2 area */
-/* delimited by compilation switches. */
-
-#if defined(COMP_V1_3_0_0)
-
-#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
-
-/** @defgroup COMP_LL COMP
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_LL_Private_Constants COMP Private Constants
- * @{
- */
-
-/* COMP registers bits positions */
-#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMPxOUT) */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of COMP instance.
- */
-typedef struct
-{
- uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
- This parameter can be a value of @ref COMP_LL_EC_POWERMODE
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
-
- uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
- This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
-
- uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
- This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
-
- uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
- This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
-
- uint32_t OutputSelection; /*!< Set comparator output selection.
- This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
-
- uint32_t OutputPolarity; /*!< Set comparator output polarity.
- This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
-
- uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
- This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
-
-} LL_COMP_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
- * @{
- */
-
-/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
- * @{
- */
-#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
-#if defined(COMP2_CSR_COMP2WNDWEN)
-#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP2_CSR_COMP2WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
-#endif
-#if defined(COMP4_CSR_COMP4WNDWEN)
-#define LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (COMP4_CSR_COMP4WNDWEN) /*!< Window mode enable: Comparators instances pair COMP3 and COMP4 have their input plus connected together. The common input is COMP3 input plus (COMP4 input plus is no more accessible). */
-#endif
-#if defined(COMP6_CSR_COMP6WNDWEN)
-#define LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (COMP6_CSR_COMP6WNDWEN) /*!< Window mode enable: Comparators instances pair COMP5 and COMP6 have their input plus connected together. The common input is COMP5 input plus (COMP6 input plus is no more accessible). */
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
- * @{
- */
-#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
-#if defined(COMP_CSR_COMPxMODE)
-#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMPxMODE_0) /*!< COMP power mode to medium speed */
-#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMPxMODE_1) /*!< COMP power mode to low power */
-#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMPxMODE_1 | COMP_CSR_COMPxMODE_0) /*!< COMP power mode to ultra-low power */
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
- * @{
- */
-#if !defined(COMP_CSR_COMPxNONINSEL)
-#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, PA3 for COMP2 (except STM32F334xx: PA7), PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
-#define LL_COMP_INPUT_PLUS_IO2 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO2: Same as IO1 */
-#else
-#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
-#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 (pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7) (COMP instance availability depends on the selected device) */
-#endif
-#if defined(STM32F302xC) || defined(STM32F302xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
-#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
-
-/* Note: Comparator input plus specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-
-#elif defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8)
-#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP2 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */
-
-/* Note: Comparator input plus specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
- * @{
- */
-#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
-#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
-#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
-#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to VrefInt */
-#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
-#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F302xE)
-/* This device has no comparator input minus DAC1_CH2 */
-#else
-#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
-#endif
-#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8)
-#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2) */
-#else
-#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2, PD15 for COMP3, PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, PC0 for COMP7 (COMP instance availability depends on the selected device)) */
-#endif
-#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, PB15 for COMP6 (COMP instance availability depends on the selected device)) */
-#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F302x8) || defined(STM32F303x8) || defined(STM32F328xx)
-/* This device has no comparator input minus IO3 */
-#else
-#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
-#endif
-#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
-#if defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
-#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMPxINSEL_3 ) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */
-#else
-/* This device has no comparator input minus DAC2_CH1 */
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
- * @{
- */
-#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
-#if defined(COMP_CSR_COMPxHYST)
-#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMPxHYST_0) /*!< Hysteresis level low (available only on devices: STM32F303xB/C, STM32F358xC) */
-#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMPxHYST_1 ) /*!< Hysteresis level medium (available only on devices: STM32F303xB/C, STM32F358xC) */
-#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMPxHYST_1 | COMP_CSR_COMPxHYST_0) /*!< Hysteresis level high (available only on devices: STM32F303xB/C, STM32F358xC) */
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
- * @{
- */
-#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
-#if defined(COMP_CSR_COMPxOUT)
-/* Note: Output redirection common to all COMP instances, all STM32F3 serie */
-/* devices. */
-#define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */
-#define LL_COMP_OUTPUT_TIM1_BKIN2 (COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2 (BKIN2) */
-
-#if defined(STM32F301x8) || defined(STM32F318xx)
-/* Note: Output redirection specific to COMP instance: COMP2 */
-#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
-/* Note: Output redirection specific to COMP instance: COMP4 */
-#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP6 */
-#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
-
-/* Note: Output redirection specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-/* Note: Some output redirections cannot have a generic naming, */
-/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
-/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
-#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-/* Note: Output redirection specific to COMP instances, defined with */
-/* partially generic naming grouping COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-
-#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)|| defined(STM32F302x8)
-/* Note: Output redirection specific to COMP instance: COMP2, COMP4 */
-#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP2 */
-#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
-/* Note: Output redirection specific to COMP instance: COMP4 */
-#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP6 */
-#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
-
-/* Note: Output redirection specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-/* Note: Some output redirections cannot have a generic naming, */
-/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
-/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
-#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-/* Note: Output redirection specific to COMP instances, defined with */
-/* partially generic naming grouping COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4 */
-#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
-#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
-/* Note: Output redirection specific to COMP instance: COMP4 */
-#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP6 */
-#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
-
-/* Note: Output redirection specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-/* Note: Some output redirections cannot have a generic naming, */
-/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */
-/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
-#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-/* Note: Output redirection specific to COMP instances, defined with */
-/* partially generic naming grouping COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-
-#elif defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-/* Note: Output redirection common to all COMP instances */
-#define LL_COMP_OUTPUT_TIM8_BKIN (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input (BKIN) */
-#define LL_COMP_OUTPUT_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
-#define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_COMP_OUTPUT_TIM20_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input (BKIN) */
-#define LL_COMP_OUTPUT_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
-#define LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2, TIM8 break input 2 and TIM20 break input 2 (BKIN2) */
-#endif
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3, COMP7 */
-#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3, COMP7) */
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3 */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3) */
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4, COMP5 */
-#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP4, COMP5) */
-/* Note: Output redirection specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
-#define LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 OCREF clear (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
-/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
-#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */
-#endif
-/* Note: Output redirection specific to COMP instance: COMP3 */
-#define LL_COMP_OUTPUT_TIM3_IC2_COMP3 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM3 input capture 2 (specific to COMP instance: COMP3) */
-#define LL_COMP_OUTPUT_TIM4_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP3) */
-#define LL_COMP_OUTPUT_TIM15_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP3) */
-#define LL_COMP_OUTPUT_TIM15_BKIN_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */
-/* Note: Output redirection specific to COMP instance: COMP4 */
-#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
-#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
-/* Note: Output redirection specific to COMP instance: COMP5 */
-#define LL_COMP_OUTPUT_TIM2_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP5) */
-#define LL_COMP_OUTPUT_TIM4_IC3_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */
-#define LL_COMP_OUTPUT_TIM17_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM17 input capture 1 (specific to COMP instance: COMP5) */
-#define LL_COMP_OUTPUT_TIM16_BKIN_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 break input (BKIN) */
-/* Note: Output redirection specific to COMP instance: COMP6 */
-#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
-#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
-/* Note: Output redirection specific to COMP instance: COMP7 */
-#define LL_COMP_OUTPUT_TIM1_IC2_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP7) */
-#define LL_COMP_OUTPUT_TIM2_IC3_COMP7 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP7) */
-#define LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM17 OCREF clear (specific to COMP instance: COMP7) */
-#define LL_COMP_OUTPUT_TIM17_BKIN_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */
-
-/* Note: Output redirection specific to COMP instances, defined with */
-/* generic naming not taking into account COMP instance constraints. */
-/* Refer to literal definitions above for COMP instance constraints. */
-/* Note: Some output redirections cannot have a generic naming, */
-/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */
-/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
-#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM1_IC2 LL_COMP_OUTPUT_TIM1_IC2_COMP7 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC1 LL_COMP_OUTPUT_TIM2_IC1_COMP5 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC3 LL_COMP_OUTPUT_TIM2_IC3_COMP7 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC2 LL_COMP_OUTPUT_TIM3_IC2_COMP3 /*!< COMP output connected to TIM3 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP3 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC3 LL_COMP_OUTPUT_TIM4_IC3_COMP5 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM8_OCCLR LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 /*!< COMP output connected to TIM8 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_IC1 LL_COMP_OUTPUT_TIM15_IC1_COMP3 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP3 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP5 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM17_IC1 LL_COMP_OUTPUT_TIM17_IC1_COMP5 /*!< COMP output connected to TIM17 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM17_BKIN LL_COMP_OUTPUT_TIM17_BKIN_COMP7 /*!< COMP output connected to TIM17 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#define LL_COMP_OUTPUT_TIM17_OCCLR LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 /*!< COMP output connected to TIM17 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define LL_COMP_OUTPUT_TIM20_OCCLR LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 /*!< COMP output connected to TIM20 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
-#endif
-
-#endif
-#endif
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
- * @{
- */
-#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
-#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMPxPOL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
-/**
- * @}
- */
-
-/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
- * @{
- */
-#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U) /*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_CORTEX_H
-#define __STM32F3xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/** @defgroup CORTEX_LL CORTEX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
- * @{
- */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
- * @{
- */
-#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
- * @{
- */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
- * @{
- */
-#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
- * @{
- */
-#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
- * @{
- */
-#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
- * @{
- */
-#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
- * @{
- */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
- * @{
- */
-#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
- * @{
- */
-#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
- * @{
- */
-#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
- * @{
- */
-
-/**
- * @brief This function checks if the Systick counter flag is active or not.
- * @note It can be used in timeout function on application side.
- * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
- return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
- * @brief Configures the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
- if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
- {
- SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
- else
- {
- CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
-}
-
-/**
- * @brief Get the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
- return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Disable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Checks if the SYSTICK interrupt is enabled or disabled.
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
- return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
- * @{
- */
-
-/**
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Processor uses deep sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
- * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
- * empty main application.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Do not sleep when returning to Thread mode.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
- * processor.
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
- /* Set SEVEONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
- * excluded
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
- /* Clear SEVEONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
- * @{
- */
-
-/**
- * @brief Enable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
- /* Enable the system handler fault */
- SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @brief Disable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
- /* Disable the system handler fault */
- CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
- * @{
- */
-
-/**
- * @brief Get Implementer code
- * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
- * @retval Value should be equal to 0x41 for ARM
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
- * @brief Get Variant number (The r value in the rnpn product revision identifier)
- * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
- * @retval Value between 0 and 255 (0x0: revision 0)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
- * @brief Get Constant number
- * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
- * @retval Value should be equal to 0xF for Cortex-M4 devices
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
- * @brief Get Part number
- * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
- * @retval Value should be equal to 0xC24 for Cortex-M4
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
- * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
- * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
- * @retval Value between 0 and 255 (0x1: patch 1)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
- * @{
- */
-
-/**
- * @brief Enable MPU with input options
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
- * @param Options This parameter can be one of the following values:
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
- * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
- * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
- /* Enable the MPU*/
- WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
- /* Ensure MPU settings take effects */
- __DSB();
- /* Sequence instruction fetches using update settings */
- __ISB();
-}
-
-/**
- * @brief Disable MPU
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
- /* Disable MPU*/
- WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
- * @brief Check if MPU is enabled or not
- * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
- return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
- * @brief Enable a MPU region
- * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Enable the MPU region */
- SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @brief Configure and enable a region
- * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
- * MPU_RASR XN LL_MPU_ConfigRegion\n
- * MPU_RASR AP LL_MPU_ConfigRegion\n
- * MPU_RASR S LL_MPU_ConfigRegion\n
- * MPU_RASR C LL_MPU_ConfigRegion\n
- * MPU_RASR B LL_MPU_ConfigRegion\n
- * MPU_RASR SIZE LL_MPU_ConfigRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @param Address Value of region base address
- * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
- * @param Attributes This parameter can be a combination of the following values:
- * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
- * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
- * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
- * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
- * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
- * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
- * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
- * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
- * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
- * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
- * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
- * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Set base address */
- WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
- /* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
- * @brief Disable a region
- * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
- * MPU_RASR ENABLE LL_MPU_DisableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Disable the MPU region */
- CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @}
- */
-
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_crc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_crc.h
deleted file mode 100644
index b07d93a29f0..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_crc.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_CRC_H
-#define __STM32F3xx_LL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(CRC)
-
-/** @defgroup CRC_LL CRC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
- * @{
- */
-
-/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
- * @{
- */
-#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
-#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
- * @{
- */
-#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
-#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
-#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
-#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
- * @{
- */
-#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
-#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
- * @brief Normal representation of this polynomial value is
- * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
- * @{
- */
-#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
- * @{
- */
-#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
- * @{
- */
-
-/**
- * @brief Reset the CRC calculation unit.
- * @note If Programmable Initial CRC value feature
- * is available, also set the Data Register to the value stored in the
- * CRC_INIT register, otherwise, reset Data Register to its default value.
- * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
- * @param CRCx CRC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
-{
- SET_BIT(CRCx->CR, CRC_CR_RESET);
-}
-
-/**
- * @brief Configure size of the polynomial.
- * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
- * @param CRCx CRC Instance
- * @param PolySize This parameter can be one of the following values:
- * @arg @ref LL_CRC_POLYLENGTH_32B
- * @arg @ref LL_CRC_POLYLENGTH_16B
- * @arg @ref LL_CRC_POLYLENGTH_8B
- * @arg @ref LL_CRC_POLYLENGTH_7B
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
-{
- MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
-}
-
-/**
- * @brief Return size of the polynomial.
- * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
- * @param CRCx CRC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRC_POLYLENGTH_32B
- * @arg @ref LL_CRC_POLYLENGTH_16B
- * @arg @ref LL_CRC_POLYLENGTH_8B
- * @arg @ref LL_CRC_POLYLENGTH_7B
- */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
-}
-
-/**
- * @brief Configure the reversal of the bit order of the input data
- * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
- * @param CRCx CRC Instance
- * @param ReverseMode This parameter can be one of the following values:
- * @arg @ref LL_CRC_INDATA_REVERSE_NONE
- * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
- * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
- * @arg @ref LL_CRC_INDATA_REVERSE_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
-{
- MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
-}
-
-/**
- * @brief Return type of reversal for input data bit order
- * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
- * @param CRCx CRC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRC_INDATA_REVERSE_NONE
- * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
- * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
- * @arg @ref LL_CRC_INDATA_REVERSE_WORD
- */
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
-}
-
-/**
- * @brief Configure the reversal of the bit order of the Output data
- * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
- * @param CRCx CRC Instance
- * @param ReverseMode This parameter can be one of the following values:
- * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
- * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
-{
- MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
-}
-
-/**
- * @brief Configure the reversal of the bit order of the Output data
- * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
- * @param CRCx CRC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
- * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
- */
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
-}
-
-/**
- * @brief Initialize the Programmable initial CRC value.
- * @note If the CRC size is less than 32 bits, the least significant bits
- * are used to write the correct value
- * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
- * @rmtoll INIT INIT LL_CRC_SetInitialData
- * @param CRCx CRC Instance
- * @param InitCrc Value to be programmed in Programmable initial CRC value register
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
-{
- WRITE_REG(CRCx->INIT, InitCrc);
-}
-
-/**
- * @brief Return current Initial CRC value.
- * @note If the CRC size is less than 32 bits, the least significant bits
- * are used to read the correct value
- * @rmtoll INIT INIT LL_CRC_GetInitialData
- * @param CRCx CRC Instance
- * @retval Value programmed in Programmable initial CRC value register
- */
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->INIT));
-}
-
-/**
- * @brief Initialize the Programmable polynomial value
- * (coefficients of the polynomial to be used for CRC calculation).
- * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
- * @note Please check Reference Manual and existing Errata Sheets,
- * regarding possible limitations for Polynomial values usage.
- * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * @rmtoll POL POL LL_CRC_SetPolynomialCoef
- * @param CRCx CRC Instance
- * @param PolynomCoef Value to be programmed in Programmable Polynomial value register
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
-{
- WRITE_REG(CRCx->POL, PolynomCoef);
-}
-
-/**
- * @brief Return current Programmable polynomial value
- * @note Please check Reference Manual and existing Errata Sheets,
- * regarding possible limitations for Polynomial values usage.
- * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * @rmtoll POL POL LL_CRC_GetPolynomialCoef
- * @param CRCx CRC Instance
- * @retval Value programmed in Programmable Polynomial value register
- */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->POL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Write given 32-bit data to the CRC calculator
- * @rmtoll DR DR LL_CRC_FeedData32
- * @param CRCx CRC Instance
- * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
-{
- WRITE_REG(CRCx->DR, InData);
-}
-
-/**
- * @brief Write given 16-bit data to the CRC calculator
- * @rmtoll DR DR LL_CRC_FeedData16
- * @param CRCx CRC Instance
- * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
-{
- *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
-}
-
-/**
- * @brief Write given 8-bit data to the CRC calculator
- * @rmtoll DR DR LL_CRC_FeedData8
- * @param CRCx CRC Instance
- * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
-{
- *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
-}
-
-/**
- * @brief Return current CRC calculation result. 32 bits value is returned.
- * @rmtoll DR DR LL_CRC_ReadData32
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
- */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->DR));
-}
-
-/**
- * @brief Return current CRC calculation result. 16 bits value is returned.
- * @note This function is expected to be used in a 16 bits CRC polynomial size context.
- * @rmtoll DR DR LL_CRC_ReadData16
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
- */
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
-{
- return (uint16_t)READ_REG(CRCx->DR);
-}
-
-/**
- * @brief Return current CRC calculation result. 8 bits value is returned.
- * @note This function is expected to be used in a 8 bits CRC polynomial size context.
- * @rmtoll DR DR LL_CRC_ReadData8
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
- */
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
-{
- return (uint8_t)READ_REG(CRCx->DR);
-}
-
-/**
- * @brief Return current CRC calculation result. 7 bits value is returned.
- * @note This function is expected to be used in a 7 bits CRC polynomial size context.
- * @rmtoll DR DR LL_CRC_ReadData7
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
- */
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
-{
- return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
-}
-
-/**
- * @brief Return data stored in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Read_IDR
- * @param CRCx CRC Instance
- * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
- */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->IDR));
-}
-
-/**
- * @brief Store data in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Write_IDR
- * @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
-{
- *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
-}
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(CRC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h
deleted file mode 100644
index 26e78081756..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h
+++ /dev/null
@@ -1,1526 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_DAC_H
-#define __STM32F3xx_LL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (DAC1) || defined (DAC2)
-
-/** @defgroup DAC_LL DAC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Constants DAC Private Constants
- * @{
- */
-
-/* Internal masks for DAC channels definition */
-/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
-/* - channel bits position into register CR */
-/* - channel bits position into register SWTRIG */
-/* - channel register offset of data holding register DHRx */
-/* - channel register offset of data output register DORx */
-#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
-#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
-
-#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
-#else
-#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#endif /* DAC_CHANNEL2_SUPPORT */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-
-#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-#else
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/* DAC registers bits positions */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Macros DAC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
-*/
-#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
-*/
-#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of DAC instance.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
-
- uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
-
- uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
-
- uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
-
-} LL_DAC_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
- * @brief Flags defines which can be used with LL_DAC_ReadReg function
- * @{
- */
-/* DAC channel 1 flags */
-#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/* DAC channel 2 flags */
-#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_IT DAC interruptions
- * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
- * @{
- */
-#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_CHANNEL DAC channels
- * @{
- */
-#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
- * @{
- */
-#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#elif defined(STM32F301x8) || defined(STM32F318xx)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#elif defined(STM32F334x8)
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
-#define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
-#define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
-#define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
- * @{
- */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
- * @{
- */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
- * @{
- */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
- * @{
- */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
-#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
-
-#if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
-#define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
-#define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
-#endif
-/**
- * @}
- */
-
-
-/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
- * @{
- */
-#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
- * @{
- */
-/* List of DAC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC IP HW delays are defined in DAC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Delay for DAC channel voltage settling time from DAC channel startup */
-/* (transition from disable to enable). */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm (min), 50pF (max) */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tWAKEUP"). */
-/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
-/* Delay for DAC channel voltage settling time. */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm min, 50pF max */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSETTLING"). */
-/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
- * @{
- */
-
-/**
- * @brief Write a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get DAC channel number in decimal format
- * from literals LL_DAC_CHANNEL_x.
- * Example:
- * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
- * will return decimal number "1".
- * @note The input can be a value from functions where a channel
- * number is returned.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval 1...2 (value "2" depending on DAC channel 2 availability)
- */
-#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
-
-/**
- * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
- * from number in decimal format.
- * Example:
- * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
- * will return a data equivalent to "LL_DAC_CHANNEL_1".
- * @note If the input parameter does not correspond to a DAC channel,
- * this macro returns value '0'.
- * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- */
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
- ? ( \
- LL_DAC_CHANNEL_1 \
- ) \
- : \
- (((__DECIMAL_NB__) == 2U) \
- ? ( \
- LL_DAC_CHANNEL_2 \
- ) \
- : \
- ( \
- 0 \
- ) \
- ) \
- )
-#else
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
- ? ( \
- LL_DAC_CHANNEL_1 \
- ) \
- : \
- ( \
- 0 \
- ) \
- )
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @brief Helper macro to define the DAC conversion data full-scale digital
- * value corresponding to the selected DAC resolution.
- * @note DAC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
-
-/**
- * @brief Helper macro to calculate the DAC conversion data (unit: digital
- * value) corresponding to a voltage (unit: mVolt).
- * @note This helper macro is intended to provide input data in voltage
- * rather than digital value,
- * to be used with LL DAC functions such as
- * @ref LL_DAC_ConvertData12RightAligned().
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
- * (unit: mVolt).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval DAC conversion data (unit: digital value)
- */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
- __DAC_VOLTAGE__,\
- __DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
- * @{
- */
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
- * @{
- */
-
-/**
- * @brief Set the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note To set conversion trigger source, DAC channel must be disabled.
- * Otherwise, the setting is discarded.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
- * CR TSEL2 LL_DAC_SetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- *
- * (1) On STM32F3, parameter not available on all devices
- * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
- * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
- * CR TSEL2 LL_DAC_GetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
- * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- *
- * (1) On STM32F3, parameter not available on all devices
- * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
- * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
- */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_SetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param WaveAutoGeneration This parameter can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_GetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param NoiseLFSRMask This parameter can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Set the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param TriangleAmplitude This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the output buffer for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
- * CR BOFF2 LL_DAC_SetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param OutputBuffer This parameter can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
- * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
- *
- * (1) Feature specific to STM32F303x6/8 and STM32F328:
- * On DAC1 channel 2, output buffer is replaced by a switch
- * to connect DAC channel output to pin PA5.
- * On DAC2 channel 1, output buffer is replaced by a switch
- * to connect DAC channel output to pin PA6.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the output buffer state for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
- * CR BOFF2 LL_DAC_GetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
- * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
- *
- * (1) Feature specific to STM32F303x6/8 and STM32F328:
- * On DAC1 channel 2, output buffer is replaced by a switch
- * to connect DAC channel output to pin PA5.
- * On DAC2 channel 1, output buffer is replaced by a switch
- * to connect DAC channel output to pin PA6.
- */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
- * CR DMAEN2 LL_DAC_EnableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
- * CR DMAEN2 LL_DAC_DisableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC DMA transfer request state of the selected channel.
- * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
- * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
- * CR DMAEN2 LL_DAC_IsDMAReqEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Function to help to configure DMA transfer to DAC: retrieve the
- * DAC register address from DAC instance and a list of DAC registers
- * intended to be used (most commonly) with DMA transfer.
- * @note These DAC registers are data holding registers:
- * when DAC conversion is requested, DAC generates a DMA transfer
- * request to have data available in DAC data holding registers.
- * @note This macro is intended to be used with LL DMA driver, refer to
- * function "LL_DMA_ConfigAddresses()".
- * Example:
- * LL_DMA_ConfigAddresses(DMA1,
- * LL_DMA_CHANNEL_1,
- * (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param Register This parameter can be one of the following values:
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
- * @retval DAC register address
- */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
-{
- /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
- /* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
- * @{
- */
-
-/**
- * @brief Enable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Enable\n
- * CR EN2 LL_DAC_Enable
- * @note After enable from off state, DAC channel requires a delay
- * for output voltage to reach accuracy +/- 1 LSB.
- * Refer to device datasheet, parameter "tWAKEUP".
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Disable\n
- * CR EN2 LL_DAC_Disable
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC enable state of the selected channel.
- * (0: DAC channel is disabled, 1: DAC channel is enabled)
- * @rmtoll CR EN1 LL_DAC_IsEnabled\n
- * CR EN2 LL_DAC_IsEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Enable DAC trigger of the selected channel.
- * @note - If DAC trigger is disabled, DAC conversion is performed
- * automatically once the data holding register is updated,
- * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...
- * - If DAC trigger is enabled, DAC conversion is performed
- * only when a hardware of software trigger event is occurring.
- * Select trigger source using
- * function @ref LL_DAC_SetTriggerSource().
- * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
- * CR TEN2 LL_DAC_EnableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC trigger of the selected channel.
- * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
- * CR TEN2 LL_DAC_DisableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC trigger state of the selected channel.
- * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
- * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
- * CR TEN2 LL_DAC_IsTriggerEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Trig DAC conversion by software for the selected DAC channel.
- * @note Preliminarily, DAC trigger must be set to software trigger
- * using function @ref LL_DAC_SetTriggerSource()
- * with parameter "LL_DAC_TRIGGER_SOFTWARE".
- * and DAC trigger must be enabled using
- * function @ref LL_DAC_EnableTrigger().
- * @note For devices featuring DAC with 2 channels: this function
- * can perform a SW start of both DAC channels simultaneously.
- * Two channels can be selected as parameter.
- * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
- * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
- * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can a combination of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->SWTRIGR,
- (DAC_Channel & DAC_SWTR_CHX_MASK));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
- * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for the selected DAC channel.
- * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
- * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
- * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
- * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR12RD,
- (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for both DAC channels.
- * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
- * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
- /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
- /* the 4 LSB must be taken into account for the shift value. */
- MODIFY_REG(DACx->DHR12LD,
- (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
- ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
- * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
- * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR8RD,
- (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-#endif /* DAC_CHANNEL2_SUPPORT */
-/**
- * @brief Retrieve output data currently generated for the selected DAC channel.
- * @note Whatever alignment and resolution settings
- * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...),
- * output data format is 12 bits right aligned (LSB aligned on bit 0).
- * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
- * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
-
- return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-/**
- * @brief Get DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Get DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @brief Clear DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Clear DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_IT_Management IT management
- * @{
- */
-
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @brief Get DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
-}
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-/**
- * @brief Get DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
-}
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
-void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC1 || DAC2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h
deleted file mode 100644
index 1a8cae9f741..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h
+++ /dev/null
@@ -1,2012 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_DMA_H
-#define __STM32F3xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
- * @{
- */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
- (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- or as Source base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note: The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Channel
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- * @{
- */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_DMA_WriteReg function
- * @{
- */
-#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
-#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
-#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
-#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
-#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
-#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
-#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
-#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_DMA_ReadReg function
- * @{
- */
-#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
-#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
-#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
-#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
-#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
-#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
-#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
-#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
- * @{
- */
-#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
-#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- * @{
- */
-#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
-#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
- * @{
- */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
- * @{
- */
-#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
-#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
- * @{
- */
-#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
- * @{
- */
-#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
- * @{
- */
-#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
-#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
- * @{
- */
-#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
- * @{
- */
-#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
- * @{
- */
-/**
- * @brief Convert DMAx_Channely into DMAx
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval DMAx
- */
-#if defined(DMA2)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
-#else
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
-#endif
-
-/**
- * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval LL_DMA_CHANNEL_y
- */
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-
-/**
- * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
- * @param __DMA_INSTANCE__ DMAx
- * @param __CHANNEL__ LL_DMA_CHANNEL_y
- * @retval DMAx_Channely
- */
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
- DMA2_Channel7)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable DMA channel.
- * @rmtoll CCR EN LL_DMA_EnableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Disable DMA channel.
- * @rmtoll CCR EN LL_DMA_DisableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Check if DMA channel is enabled or disabled.
- * @rmtoll CCR EN LL_DMA_IsEnabledChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_EN) == (DMA_CCR_EN));
-}
-
-/**
- * @brief Configure all parameters link to DMA transfer.
- * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
- * CCR MEM2MEM LL_DMA_ConfigTransfer\n
- * CCR CIRC LL_DMA_ConfigTransfer\n
- * CCR PINC LL_DMA_ConfigTransfer\n
- * CCR MINC LL_DMA_ConfigTransfer\n
- * CCR PSIZE LL_DMA_ConfigTransfer\n
- * CCR MSIZE LL_DMA_ConfigTransfer\n
- * CCR PL LL_DMA_ConfigTransfer
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
- * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
- * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
- Configuration);
-}
-
-/**
- * @brief Set Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_SetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
- * @brief Get Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_GetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
- * @brief Set DMA mode circular or normal.
- * @note The circular buffer mode cannot be used if the memory-to-memory
- * data transfer is configured on the selected Channel.
- * @rmtoll CCR CIRC LL_DMA_SetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
- Mode);
-}
-
-/**
- * @brief Get DMA mode circular or normal.
- * @rmtoll CCR CIRC LL_DMA_GetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_CIRC));
-}
-
-/**
- * @brief Set Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
- PeriphOrM2MSrcIncMode);
-}
-
-/**
- * @brief Get Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PINC));
-}
-
-/**
- * @brief Set Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
- MemoryOrM2MDstIncMode);
-}
-
-/**
- * @brief Get Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MINC));
-}
-
-/**
- * @brief Set Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
- PeriphOrM2MSrcDataSize);
-}
-
-/**
- * @brief Get Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PSIZE));
-}
-
-/**
- * @brief Set Memory size.
- * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
- MemoryOrM2MDstDataSize);
-}
-
-/**
- * @brief Get Memory size.
- * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MSIZE));
-}
-
-/**
- * @brief Set Channel priority level.
- * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Priority This parameter can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
- Priority);
-}
-
-/**
- * @brief Get Channel priority level.
- * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PL));
-}
-
-/**
- * @brief Set Number of data to transfer.
- * @note This action has no effect if
- * channel is enabled.
- * @rmtoll CNDTR NDT LL_DMA_SetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT, NbData);
-}
-
-/**
- * @brief Get Number of data to transfer.
- * @note Once the channel is enabled, the return value indicate the
- * remaining bytes to be transmitted.
- * @rmtoll CNDTR NDT LL_DMA_GetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT));
-}
-
-/**
- * @brief Configure the Source and Destination addresses.
- * @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
- * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
- * CMAR MA LL_DMA_ConfigAddresses
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t Direction)
-{
- /* Direction Memory to Periph */
- if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
- }
- /* Direction Periph to Memory and Memory to Memory */
- else
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
- }
-}
-
-/**
- * @brief Set the Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
-}
-
-/**
- * @brief Get Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
- * @brief Get Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Set the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Get the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Get the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Channel 1 global interrupt flag.
- * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
-}
-
-/**
- * @brief Get Channel 2 global interrupt flag.
- * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
-}
-
-/**
- * @brief Get Channel 3 global interrupt flag.
- * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
-}
-
-/**
- * @brief Get Channel 4 global interrupt flag.
- * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
-}
-
-/**
- * @brief Get Channel 5 global interrupt flag.
- * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
-}
-
-/**
- * @brief Get Channel 6 global interrupt flag.
- * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
-}
-
-/**
- * @brief Get Channel 7 global interrupt flag.
- * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer complete flag.
- * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer complete flag.
- * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer complete flag.
- * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer complete flag.
- * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer complete flag.
- * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer complete flag.
- * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer complete flag.
- * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
-}
-
-/**
- * @brief Get Channel 1 half transfer flag.
- * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
-}
-
-/**
- * @brief Get Channel 2 half transfer flag.
- * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
-}
-
-/**
- * @brief Get Channel 3 half transfer flag.
- * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
-}
-
-/**
- * @brief Get Channel 4 half transfer flag.
- * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
-}
-
-/**
- * @brief Get Channel 5 half transfer flag.
- * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
-}
-
-/**
- * @brief Get Channel 6 half transfer flag.
- * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
-}
-
-/**
- * @brief Get Channel 7 half transfer flag.
- * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer error flag.
- * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer error flag.
- * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer error flag.
- * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer error flag.
- * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer error flag.
- * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer error flag.
- * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer error flag.
- * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
-}
-
-/**
- * @brief Clear Channel 1 global interrupt flag.
- * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
- * @brief Clear Channel 2 global interrupt flag.
- * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
- * @brief Clear Channel 3 global interrupt flag.
- * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
- * @brief Clear Channel 4 global interrupt flag.
- * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
- * @brief Clear Channel 5 global interrupt flag.
- * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-/**
- * @brief Clear Channel 6 global interrupt flag.
- * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-/**
- * @brief Clear Channel 7 global interrupt flag.
- * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer complete flag.
- * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer complete flag.
- * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer complete flag.
- * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer complete flag.
- * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer complete flag.
- * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer complete flag.
- * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer complete flag.
- * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-
-/**
- * @brief Clear Channel 1 half transfer flag.
- * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
- * @brief Clear Channel 2 half transfer flag.
- * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
- * @brief Clear Channel 3 half transfer flag.
- * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
- * @brief Clear Channel 4 half transfer flag.
- * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
- * @brief Clear Channel 5 half transfer flag.
- * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-/**
- * @brief Clear Channel 6 half transfer flag.
- * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-/**
- * @brief Clear Channel 7 half transfer flag.
- * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer error flag.
- * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer error flag.
- * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer error flag.
- * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer error flag.
- * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer error flag.
- * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer error flag.
- * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer error flag.
- * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
- * @{
- */
-/**
- * @brief Enable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Enable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Enable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Disable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Disable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Disable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Check if Transfer complete Interrupt is enabled.
- * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TCIE) == (DMA_CCR_TCIE));
-}
-
-/**
- * @brief Check if Half transfer Interrupt is enabled.
- * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_HTIE) == (DMA_CCR_HTIE));
-}
-
-/**
- * @brief Check if Transfer error Interrupt is enabled.
- * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TEIE) == (DMA_CCR_TEIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h
deleted file mode 100644
index 4aebae7cc93..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h
+++ /dev/null
@@ -1,1399 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_EXTI_H
-#define __STM32F3xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
- * @{
- */
-typedef struct
-{
-
- uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
- This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-#if defined(EXTI_32_63_SUPPORT)
-
- uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
- This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-#endif
-
- FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-
- uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
- uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
- * @{
- */
-#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
-#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
-#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
-#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
-#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
-#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
-#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
-#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
-#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
-#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
-#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
-#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
-#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
-#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
-#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
-#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
-#endif
-#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
-#endif
-#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
-
-#if defined(EXTI_32_63_SUPPORT)
-#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
-#if defined(EXTI_IMR2_IM33)
-#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
-#endif
-#if defined(EXTI_IMR2_IM34)
-#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
-#endif
-#if defined(EXTI_IMR2_IM35)
-#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
-#endif
-#if defined(EXTI_IMR2_IM36)
-#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
-#endif
-#if defined(EXTI_IMR2_IM37)
-#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
-#endif
-#if defined(EXTI_IMR2_IM38)
-#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
-#endif
-#if defined(EXTI_IMR2_IM39)
-#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
-#endif
-#if defined(EXTI_IMR2_IM40)
-#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
-#endif
-#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
-
-#endif
-
-#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
- * @{
- */
-#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
- * @{
- */
-#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
- * @}
- */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in EXTI register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in EXTI register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->IMR, ExtiLine);
-}
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->IMR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->IMR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
- * @note The reset value for the direct lines (lines from 32 to 34, line
- * 39) is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Enable ExtiLine Event request for Lines in range 32 to 63
- * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->EMR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Disable ExtiLine Event request for Lines in range 32 to 63
- * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->EMR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
- * @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_26
- * @arg @ref LL_EXTI_LINE_27
- * @arg @ref LL_EXTI_LINE_28
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
- * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_32
- * @arg @ref LL_EXTI_LINE_33
- * @arg @ref LL_EXTI_LINE_34
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @arg @ref LL_EXTI_LINE_39
- * @arg @ref LL_EXTI_LINE_ALL_32_63
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->RTSR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->RTSR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
- * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->FTSR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt line.
- * In this case, both generate a trigger condition.
- * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt line.
- * In this case, both generate a trigger condition.
- * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->FTSR2, ExtiLine);
-}
-#endif
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
- * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
- * @{
- */
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 0 to 31
- * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
- * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Generate a software Interrupt Event for Lines in range 32 to 63
- * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
- * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR2
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->SWIER2, ExtiLine);
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
- * @{
- */
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
-}
-#endif
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval @note This bit is set when the selected edge event arrives on the interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
- return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval @note This bit is set when the selected edge event arrives on the interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
-{
- return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
-}
-#endif
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_29
- * @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
- WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-#if defined(EXTI_32_63_SUPPORT)
-/**
- * @brief Clear ExtLine Flags for Lines in range 32 to 63
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_35
- * @arg @ref LL_EXTI_LINE_36
- * @arg @ref LL_EXTI_LINE_37
- * @arg @ref LL_EXTI_LINE_38
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
-{
- WRITE_REG(EXTI->PR2, ExtiLine);
-}
-#endif
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* EXTI */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h
deleted file mode 100644
index 37e45d5cc5d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h
+++ /dev/null
@@ -1,1082 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_fmc.h
- * @author MCD Application Team
- * @brief Header file of FMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_FMC_H
-#define __STM32F3xx_LL_FMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#if defined(FMC_BANK1)
-
-/** @addtogroup FMC_LL
- * @{
- */
-
-/** @addtogroup FMC_LL_Private_Macros
- * @{
- */
-
-#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
- ((__BANK__) == FMC_NORSRAM_BANK2) || \
- ((__BANK__) == FMC_NORSRAM_BANK3) || \
- ((__BANK__) == FMC_NORSRAM_BANK4))
-
-#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FMC_WRITE_BURST_ENABLE))
-
-#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
- ((__MODE__) == FMC_ACCESS_MODE_B) || \
- ((__MODE__) == FMC_ACCESS_MODE_C) || \
- ((__MODE__) == FMC_ACCESS_MODE_D))
-
-#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
- ((__BANK__) == FMC_NAND_BANK3))
-
-#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-
-#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FMC_NAND_ECC_ENABLE))
-
-#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
- * @{
- */
-#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time FMC_Setup_Time
- * @{
- */
-#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
- * @{
- */
-#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
- * @{
- */
-
-#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
- * @{
- */
-
-#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
- * @{
- */
-#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance
- * @{
- */
-#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
-
-/**
- * @}
- */
-#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FMC_WRAP_MODE_ENABLE))
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
-
-#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
-
-/** @defgroup FMC_Data_Latency FMC Data Latency
- * @{
- */
-#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
- * @{
- */
-#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
- * @{
- */
-#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
- * @{
- */
-#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
- * @{
- */
-#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
- * @{
- */
-
-#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
-#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
-#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
-#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
-
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank2_3
-#define FMC_PCCARD_DEVICE FMC_Bank4
-
-/**
- * @brief FMC_NORSRAM Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
- uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
- uint32_t MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory device.
- This parameter can be a value of @ref FMC_Memory_Type */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
- uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
- uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
- uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FMC_Wrap_Mode */
-
- uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
-
- uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
-
- uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
-
- uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
-
- uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
-
- uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
-
-}FMC_NORSRAM_InitTypeDef;
-
-/**
- * @brief FMC_NORSRAM Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
-
- uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
-
- uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-
-}FMC_NORSRAM_TimingTypeDef;
-
-/**
- * @brief FMC_NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
-
- uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
-
- uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_NAND_InitTypeDef;
-
-/**
- * @brief FMC_NAND_PCC Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_NAND_PCC_TimingTypeDef;
-
-/**
- * @brief FMC_NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_PCCARD_InitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
- * @{
- */
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
- * @{
- */
-
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Memory_Type FMC Memory Type
- * @{
- */
-
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
- * @{
- */
-
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
- * @{
- */
-
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
- * @{
- */
-
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
- * @{
- */
-
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
- * @{
- */
-
-#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Timing FMC Wait Timing
- * @{
- */
-
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Operation FMC Write Operation
- * @{
- */
-
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal FMC Wait Signal
- * @{
- */
-
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Extended_Mode FMC Extended Mode
- * @{
- */
-
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
- * @{
- */
-
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Burst FMC Write Burst
- * @{
- */
-
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock FMC Continous Clock
- * @{
- */
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
-/**
- * @}
- */
-
-/** @defgroup FMC_Access_Mode FMC Access Mode
- * @{
- */
-
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
-#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
-#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
- * @{
- */
-
-/** @defgroup FMC_NAND_Bank FMC NAND Bank
- * @{
- */
-#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_feature FMC Wait feature
- * @{
- */
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
- * @{
- */
-#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP)
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
- * @{
- */
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC FMC NAND ECC
- * @{
- */
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
- * @{
- */
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
- * @brief FMC Interrupt definition
- * @{
- */
-#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN)
-#define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN)
-#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Flag_definition FMC Flag definition
- * @brief FMC Flag definition
- * @{
- */
-#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS)
-#define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS)
-#define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
- * @{
- */
-
-/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
-
-/**
- * @brief Enable the NORSRAM device access.
- * @param __INSTANCE__ FMC_NORSRAM Instance
- * @param __BANK__ FMC_NORSRAM Bank
- * @retval none
- */
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
-
-/**
- * @brief Disable the NORSRAM device access.
- * @param __INSTANCE__ FMC_NORSRAM Instance
- * @param __BANK__ FMC_NORSRAM Bank
- * @retval none
- */
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Macros FMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
-
-/**
- * @brief Enable the NAND device access.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @retval None
- */
-#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
- SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
-
-/**
- * @brief Disable the NAND device access.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @retval None
- */
-#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
- * @brief macros to handle PCCARD read/write operations
- * @{
- */
-
-/**
- * @brief Enable the PCCARD device access.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @retval None
- */
-#define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
-
-/**
- * @brief Disable the PCCARD device access.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @retval None
- */
-#define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt FMC Interrupt
- * @brief macros to handle FMC interrupts
- * @{
- */
-
-/**
- * @brief Enable the NAND device interrupt.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @param __INTERRUPT__ FMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FMC_IT_LEVEL Interrupt level.
- * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
- * @retval None
- */
-#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
- SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
- * @brief Disable the NAND device interrupt.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @param __INTERRUPT__ FMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FMC_IT_LEVEL Interrupt level.
- * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
- * @retval None
- */
-#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
- * @brief Get flag status of the NAND device.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @param __FLAG__ FMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-
-/**
- * @brief Clear flag status of the NAND device.
- * @param __INSTANCE__ FMC_NAND Instance
- * @param __BANK__ FMC_NAND Bank
- * @param __FLAG__ FMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT FIFO empty flag.
- * @retval None
- */
-#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
-
-/**
- * @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @param __INTERRUPT__ FMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FMC_IT_LEVEL Interrupt level.
- * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
- * @retval None
- */
-#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
- * @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @param __INTERRUPT__ FMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FMC_IT_LEVEL Interrupt level.
- * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
- * @retval None
- */
-#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
- * @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @param __FLAG__ FMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__ FMC_PCCARD Instance
- * @param __FLAG__ FMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT FIFO empty flag.
- * @retval None
- */
-#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FMC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup FMC_NORSRAM
- * @{
- */
-
-/** @addtogroup FMC_NORSRAM_Group1
- * @{
- */
-
-/* FMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-
-/**
- * @}
- */
-
-/** @addtogroup FMC_NORSRAM_Group2
- * @{
- */
-
-/* FMC_NORSRAM Control functions */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FMC_NAND
- * @{
- */
-
-/* FMC_NAND Controller functions **********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FMC_NAND_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
-
-/**
- * @}
- */
-
-/* FMC_NAND Control functions */
-/** @addtogroup FMC_NAND_Exported_Functions_Group2
- * @{
- */
-
-HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FMC_PCCARD
- * @{
- */
-
-/* FMC_PCCARD Controller functions ********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FMC_PCCARD_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* FMC_BANK1 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h
deleted file mode 100644
index ae7edcc44bf..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h
+++ /dev/null
@@ -1,995 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_GPIO_H
-#define __STM32F3xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
-
-/** @defgroup GPIO_LL GPIO
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- * @{
- */
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- * @{
- */
-
-/**
- * @brief LL GPIO Init Structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
- uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
- uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
- uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_AF.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
- * @{
- */
-#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
- GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
- GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
- GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
- GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
- GPIO_BSRR_BS_15) /*!< Select all pins */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
- * @{
- */
-#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
- * @{
- */
-#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
- * @{
- */
-#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
-#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- * @{
- */
-#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
- * @{
- */
-#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- * @{
- */
-
-/**
- * @brief Configure gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_SetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
- MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_GetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->MODER,
- (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @param OutputType This parameter can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
- MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
- * @brief Return gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
-}
-
-/**
- * @brief Configure gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Speed This parameter can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
-{
- MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
- (Speed << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
- (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Pull This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
- MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->PUPDR,
- (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
- MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
- (Alternate << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
- * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->AFR[0],
- (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
- MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
- (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->AFR[1],
- (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
-}
-
-
-/**
- * @brief Lock configuration of several pins for a dedicated port.
- * @note When the lock sequence has been applied on a port bit, the
- * value of this port bit can no longer be modified until the
- * next reset.
- * @note Each lock bit freezes a specific configuration register
- * (control and alternate function registers).
- * @rmtoll LCKR LCKK LL_GPIO_LockPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- __IO uint32_t temp;
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- WRITE_REG(GPIOx->LCKR, PinMask);
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- temp = READ_REG(GPIOx->LCKR);
- (void) temp;
-}
-
-/**
- * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
- * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
- * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- * @param GPIOx GPIO Port
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
- return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
- * @{
- */
-
-/**
- * @brief Return full input data register value for a dedicated port.
- * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- * @param GPIOx GPIO Port
- * @retval Input data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Write output data register for the port.
- * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- * @param GPIOx GPIO Port
- * @param PortValue Level value for each pin of the port
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
- WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
- * @brief Return full output data register value for a dedicated port.
- * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- * @param GPIOx GPIO Port
- * @retval Output data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Set several pins to high level on dedicated gpio port.
- * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
- * @brief Set several pins to low level on dedicated gpio port.
- * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BRR, PinMask);
-}
-
-/**
- * @brief Toggle data value for several pin of dedicated port.
- * @rmtoll ODR ODy LL_GPIO_TogglePin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h
deleted file mode 100644
index 61bc9a039dd..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_hrtim.h
+++ /dev/null
@@ -1,10542 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_hrtim.h
- * @author MCD Application Team
- * @brief Header file of HRTIM LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_HRTIM_H
-#define __STM32F3xx_LL_HRTIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (HRTIM1)
-
-/** @defgroup HRTIM_LL HRTIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
- * @{
- */
-static const uint16_t REG_OFFSET_TAB_TIMER[] =
-{
- 0x00U, /* 0: MASTER */
- 0x80U, /* 1: TIMER A */
- 0x100U, /* 2: TIMER B */
- 0x180U, /* 3: TIMER C */
- 0x200U, /* 4: TIMER D */
- 0x280U, /* 5: TIMER E */
-};
-
-static const uint8_t REG_OFFSET_TAB_ADCxR[] =
-{
- 0x00U, /* 0: HRTIM_ADC1R */
- 0x04U, /* 1: HRTIM_ADC2R */
- 0x08U, /* 2: HRTIM_ADC3R */
- 0x0CU, /* 3: HRTIM_ADC4R */
-};
-
-static const uint16_t REG_OFFSET_TAB_SETxR[] =
-{
- 0x00U, /* 0: TA1 */
- 0x08U, /* 1: TA2 */
- 0x80U, /* 2: TB1 */
- 0x88U, /* 3: TB2 */
- 0x100U, /* 4: TC1 */
- 0x108U, /* 5: TC2 */
- 0x180U, /* 6: TD1 */
- 0x188U, /* 7: TD2 */
- 0x200U, /* 8: TE1 */
- 0x208U /* 9: TE2 */
-};
-
-static const uint16_t REG_OFFSET_TAB_OUTxR[] =
-{
- 0x00U, /* 0: TA1 */
- 0x00U, /* 1: TA2 */
- 0x80U, /* 2: TB1 */
- 0x80U, /* 3: TB2 */
- 0x100U, /* 4: TC1 */
- 0x100U, /* 5: TC2 */
- 0x180U, /* 6: TD1 */
- 0x180U, /* 7: TD2 */
- 0x200U, /* 8: TE1 */
- 0x200U /* 9: TE2 */
-};
-
-
-static const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
-{
- 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
- 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
-};
-
-static const uint8_t REG_OFFSET_TAB_EECR[] =
-{
- 0x00U, /* LL_HRTIM_EVENT_1 */
- 0x00U, /* LL_HRTIM_EVENT_2 */
- 0x00U, /* LL_HRTIM_EVENT_3 */
- 0x00U, /* LL_HRTIM_EVENT_4 */
- 0x00U, /* LL_HRTIM_EVENT_5 */
- 0x04U, /* LL_HRTIM_EVENT_6 */
- 0x04U, /* LL_HRTIM_EVENT_7 */
- 0x04U, /* LL_HRTIM_EVENT_8 */
- 0x04U, /* LL_HRTIM_EVENT_9 */
- 0x04U /* LL_HRTIM_EVENT_10 */
-};
-
-static const uint8_t REG_OFFSET_TAB_FLTINR[] =
-{
- 0x00U, /* LL_HRTIM_FAULT_1 */
- 0x00U, /* LL_HRTIM_FAULT_2 */
- 0x00U, /* LL_HRTIM_FAULT_3 */
- 0x00U, /* LL_HRTIM_FAULT_4 */
- 0x04U /* LL_HRTIM_FAULT_5 */
-};
-
-static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
-{
- 0x20000000U, /* 0: MASTER */
- 0x01FE0000U, /* 1: TIMER A */
- 0x01FE0000U, /* 2: TIMER B */
- 0x01FE0000U, /* 3: TIMER C */
- 0x01FE0000U, /* 4: TIMER D */
- 0x01FE0000U, /* 5: TIMER E */
-};
-
-static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
-{
- 12U, /* 0: MASTER */
- 0U, /* 1: TIMER A */
- 0U, /* 2: TIMER B */
- 0U, /* 3: TIMER C */
- 0U, /* 4: TIMER D */
- 0U, /* 5: TIMER E */
-};
-
-static const uint8_t REG_SHIFT_TAB_EExSRC[] =
-{
- 0U, /* LL_HRTIM_EVENT_1 */
- 6U, /* LL_HRTIM_EVENT_2 */
- 12U, /* LL_HRTIM_EVENT_3 */
- 18U, /* LL_HRTIM_EVENT_4 */
- 24U, /* LL_HRTIM_EVENT_5 */
- 0U, /* LL_HRTIM_EVENT_6 */
- 6U, /* LL_HRTIM_EVENT_7 */
- 12U, /* LL_HRTIM_EVENT_8 */
- 18U, /* LL_HRTIM_EVENT_9 */
- 24U /* LL_HRTIM_EVENT_10 */
-};
-
-static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
-{
- HRTIM_MCR_BRSTDMA, /* 0: MASTER */
- HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
- HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
- HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
- HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
- HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
-};
-
-static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
-{
- 2U, /* 0: MASTER */
- 0U, /* 1: TIMER A */
- 0U, /* 2: TIMER B */
- 0U, /* 3: TIMER C */
- 0U, /* 4: TIMER D */
- 0U, /* 5: TIMER E */
-};
-
-static const uint8_t REG_SHIFT_TAB_OUTxR[] =
-{
- 0U, /* 0: TA1 */
- 16U, /* 1: TA2 */
- 0U, /* 2: TB1 */
- 16U, /* 3: TB2 */
- 0U, /* 4: TC1 */
- 16U, /* 5: TC2 */
- 0U, /* 6: TD1 */
- 16U, /* 7: TD2 */
- 0U, /* 8: TE1 */
- 16U /* 9: TE2 */
-};
-
-static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
-{
- 0U, /* 0: TA1 */
- 1U, /* 1: TA2 */
- 0U, /* 2: TB1 */
- 1U, /* 3: TB2 */
- 0U, /* 4: TC1 */
- 1U, /* 5: TC2 */
- 0U, /* 6: TD1 */
- 1U, /* 7: TD2 */
- 0U, /* 8: TE1 */
- 1U /* 9: TE2 */
-};
-
-static const uint8_t REG_SHIFT_TAB_FLTxE[] =
-{
- 0U, /* LL_HRTIM_FAULT_1 */
- 8U, /* LL_HRTIM_FAULT_2 */
- 16U, /* LL_HRTIM_FAULT_3 */
- 24U, /* LL_HRTIM_FAULT_4 */
- 0U /* LL_HRTIM_FAULT_5 */
-};
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
- * @{
- */
-#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
- HRTIM_CR1_TAUDIS |\
- HRTIM_CR1_TBUDIS |\
- HRTIM_CR1_TCUDIS |\
- HRTIM_CR1_TDUDIS |\
- HRTIM_CR1_TEUDIS))
-
-#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
- HRTIM_CR2_TASWU |\
- HRTIM_CR2_TBSWU |\
- HRTIM_CR2_TCSWU |\
- HRTIM_CR2_TDSWU |\
- HRTIM_CR2_TESWU))
-
-#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
- HRTIM_CR2_TARST |\
- HRTIM_CR2_TBRST |\
- HRTIM_CR2_TCRST |\
- HRTIM_CR2_TDRST |\
- HRTIM_CR2_TERST))
-
-#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
- HRTIM_OENR_TA2OEN |\
- HRTIM_OENR_TB1OEN |\
- HRTIM_OENR_TB2OEN |\
- HRTIM_OENR_TC1OEN |\
- HRTIM_OENR_TC2OEN |\
- HRTIM_OENR_TD1OEN |\
- HRTIM_OENR_TD2OEN |\
- HRTIM_OENR_TE1OEN |\
- HRTIM_OENR_TE2OEN))
-
-#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
- HRTIM_ODISR_TA2ODIS |\
- HRTIM_ODISR_TB1ODIS |\
- HRTIM_ODISR_TB2ODIS |\
- HRTIM_ODISR_TC1ODIS |\
- HRTIM_ODISR_TC2ODIS |\
- HRTIM_ODISR_TD1ODIS |\
- HRTIM_ODISR_TD2ODIS |\
- HRTIM_ODISR_TE1ODIS |\
- HRTIM_ODISR_TE2ODIS))
-
-#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
- HRTIM_OUTR_IDLM1 |\
- HRTIM_OUTR_IDLES1 |\
- HRTIM_OUTR_FAULT1 |\
- HRTIM_OUTR_CHP1 |\
- HRTIM_OUTR_DIDL1))
-
-#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
- HRTIM_EECR1_EE1POL |\
- HRTIM_EECR1_EE1SNS |\
- HRTIM_EECR1_EE1FAST))
-
-#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
- HRTIM_FLTINR1_FLT1SRC))
-
-#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
- HRTIM_BMCR_BMCLK |\
- HRTIM_BMCR_BMOM))
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
- * @{
- */
-/* TO BE COMPLETED */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
- * @{
- */
-
-/** @defgroup HRTIM_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
- * @{
- */
-#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
-#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
-#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
-#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
-#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
-#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
-#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
-#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
-
-#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
-#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
-#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
-#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
-#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
-#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
-#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
-
-#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
-#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
-#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
-#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
-#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
-#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
-#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
-#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
-#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
-#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
-#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
-#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
-#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
-#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_IT IT Defines
- * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
- * @{
- */
-#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
-#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
-#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
-#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
-#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
-#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
-#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
-#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
-
-#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
-#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
-#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
-#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
-#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
-#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
-#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
-
-
-#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
-#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
-#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
-#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
-#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
-#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
-#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
-#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
-#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
-#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
-#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
-#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
-#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
-#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
- * @{
- * @brief Constants defining defining the synchronization input source.
- */
-#define LL_HRTIM_SYNCIN_SRC_NONE ((uint32_t)0x00000000U) /*!< HRTIM is not synchronized and runs in standalone mode */
-#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
-#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
- * @{
- * @brief Constants defining the source and event to be sent on the synchronization output.
- */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_START ((uint32_t)0x00000000U) /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
- * @{
- * @brief Constants defining the routing and conditioning of the synchronization output event.
- */
-#define LL_HRTIM_SYNCOUT_DISABLED ((uint32_t)0x00000000U) /*!< Synchronization output event is disabled */
-#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
-#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_TIMER TIMER ID
- * @{
- * @brief Constants identifying a timing unit.
- */
-#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
-#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
-#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
-#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
-#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
-#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_OUTPUT OUTPUT ID
- * @{
- * @brief Constants identifying an HRTIM output.
- */
-#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
-#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
-#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
-#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
-#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
-#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
-#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
-#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
-#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
-#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_COMPAREUNIT COMPARE UNIT ID
- * @{
- * @brief Constants identifying a compare unit.
- */
-#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
-#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_CAPTUREUNIT CAPTURE UNIT ID
- * @{
- * @brief Constants identifying a capture unit.
- */
-#define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
-#define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_FAULT FAULT ID
- * @{
- * @brief Constants identifying a fault channel.
- */
-#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
-#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
-#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
-#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
-#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_EVENT EXTERNAL EVENT ID
- * @{
- * @brief Constants identifying an external event channel.
- */
-#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
-#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
-#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
-#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
-#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
-#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
-#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
-#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
-#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
-#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_OUTPUTSTATE OUTPUT STATE
- * @{
- * @brief Constants defining the state of an HRTIM output.
- */
-#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
-#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
-#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_ADCTRIG ADC TRIGGER
- * @{
- * @brief Constants identifying an ADC trigger.
- */
-#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
-#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
-#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
-#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
- * @{
- * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
- */
-#define LL_HRTIM_ADCTRIG_UPDATE_MASTER ((uint32_t)0x00000000U) /*!< HRTIM_ADCxR register update is triggered by the Master timer */
-#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
-#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
-#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
-#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
-#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
- * @{
- * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
- */
-#define LL_HRTIM_ADCTRIG_SRC13_NONE ((uint32_t)0x00000000U) /*!< No ADC trigger event */
-#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
-#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
-#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
-#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
- * @{
- * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
- */
-#define LL_HRTIM_ADCTRIG_SRC24_NONE ((uint32_t)0x00000000U)/*!< No ADC trigger event */
-#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
-#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
-#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
-#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
-#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
-#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
-#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
-#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
-/**
- * @}
- */
-
-/** @defgroup HRTIM_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
- * @{
- * @brief Constants defining the DLL calibration mode.
- */
-#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT ((uint32_t)0x00000000U)/*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_I2C_H
-#define __STM32F3xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
- This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
-
- uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
- This parameter must be set by referring to the STM32CubeMX Tool and
- the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
-
- uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
-
- This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
-
- uint32_t DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
-
- uint32_t OwnAddress1; /*!< Specifies the device own address 1.
- This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-
- uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
-
- uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
- This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_I2C_WriteReg function
- * @{
- */
-#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
-#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
-#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
-#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
-#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
-#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
-#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
-#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
-#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2C_ReadReg function
- * @{
- */
-#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
-#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
-#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
-#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
-#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
-#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
-#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
-#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
-#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
-#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
-#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
-#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
-#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
- * @{
- */
-#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
-#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
-#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
-#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
-#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
-#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
-#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
- * @{
- */
-#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
-#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
- * @{
- */
-#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
-#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
- * @{
- */
-#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
-#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
- * @{
- */
-#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
- * @{
- */
-#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
-#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
- * @{
- */
-#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
- * @{
- */
-#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
-#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
- * @{
- */
-#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
-#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_MODE Transfer End Mode
- * @{
- */
-#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
-#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
- * @{
- */
-#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
- * @{
- */
-#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
-#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
- * @{
- */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
- * @{
- */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
- * @{
- */
-#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
-#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
-#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
- * @{
- */
-/**
- * @brief Configure the SDA setup, hold time and the SCL high, low period.
- * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
- * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
- * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
- * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
- * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
- * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
- */
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable I2C peripheral (PE = 1).
- * @rmtoll CR1 PE LL_I2C_Enable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Disable I2C peripheral (PE = 0).
- * @note When PE = 0, the I2C SCL and SDA lines are released.
- * Internal state machines and status bits are put back to their reset value.
- * When cleared, PE must be kept low for at least 3 APB clock cycles.
- * @rmtoll CR1 PE LL_I2C_Disable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Check if the I2C peripheral is enabled or disabled.
- * @rmtoll CR1 PE LL_I2C_IsEnabled
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
-}
-
-/**
- * @brief Configure Noise Filters (Analog and Digital).
- * @note If the analog filter is also enabled, the digital filter is added to analog filter.
- * The filters can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
- * CR1 DNF LL_I2C_ConfigFilters
- * @param I2Cx I2C Instance.
- * @param AnalogFilter This parameter can be one of the following values:
- * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
- * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
- * This parameter is used to configure the digital noise filter on SDA and SCL input.
- * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
-}
-
-/**
- * @brief Configure Digital Noise Filter.
- * @note If the analog filter is also enabled, the digital filter is added to analog filter.
- * This filter can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
- * @param I2Cx I2C Instance.
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
- * This parameter is used to configure the digital noise filter on SDA and SCL input.
- * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
-}
-
-/**
- * @brief Get the current Digital Noise Filter configuration.
- * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
-}
-
-/**
- * @brief Enable Analog Noise Filter.
- * @note This filter can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
- * @brief Disable Analog Noise Filter.
- * @note This filter can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
- * @brief Check if Analog Noise Filter is enabled or disabled.
- * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
-}
-
-/**
- * @brief Enable DMA transmission requests.
- * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA transmission requests.
- * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA transmission requests are enabled or disabled.
- * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
-}
-
-/**
- * @brief Enable DMA reception requests.
- * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA reception requests.
- * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA reception requests are enabled or disabled.
- * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
- * RXDR RXDATA LL_I2C_DMA_GetRegAddr
- * @param I2Cx I2C Instance
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
- * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
-{
- register uint32_t data_reg_addr = 0U;
-
- if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
- {
- /* return address of TXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->TXDR);
- }
- else
- {
- /* return address of RXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->RXDR);
- }
-
- return data_reg_addr;
-}
-
-/**
- * @brief Enable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Disable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Check if Clock stretching is enabled or disabled.
- * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
-}
-
-/**
- * @brief Enable hardware byte control in slave mode.
- * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
- * @brief Disable hardware byte control in slave mode.
- * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
- * @brief Check if hardware byte control in slave mode is enabled or disabled.
- * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
-}
-
-/**
- * @brief Enable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
- * WakeUpFromStop feature is supported by the I2Cx Instance.
- * @note This bit can only be programmed when Digital Filter is disabled.
- * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
- * @brief Disable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
- * WakeUpFromStop feature is supported by the I2Cx Instance.
- * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
- * @brief Check if Wakeup from STOP is enabled or disabled.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
- * WakeUpFromStop feature is supported by the I2Cx Instance.
- * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
-}
-
-/**
- * @brief Enable General Call.
- * @note When enabled the Address 0x00 is ACKed.
- * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
- * @brief Disable General Call.
- * @note When disabled the Address 0x00 is NACKed.
- * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
- * @brief Check if General Call is enabled or disabled.
- * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
-}
-
-/**
- * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
- * @note Changing this bit is not allowed, when the START bit is set.
- * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
- * @param I2Cx I2C Instance.
- * @param AddressingMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
- * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
-}
-
-/**
- * @brief Get the Master addressing mode.
- * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
- * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
- */
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
-}
-
-/**
- * @brief Set the Own Address1.
- * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
- * OAR1 OA1MODE LL_I2C_SetOwnAddress1
- * @param I2Cx I2C Instance.
- * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
- * @param OwnAddrSize This parameter can be one of the following values:
- * @arg @ref LL_I2C_OWNADDRESS1_7BIT
- * @arg @ref LL_I2C_OWNADDRESS1_10BIT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
- MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
- * @brief Enable acknowledge on Own Address1 match address.
- * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
- * @brief Disable acknowledge on Own Address1 match address.
- * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
- * @brief Check if Own Address1 acknowledge is enabled or disabled.
- * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
-}
-
-/**
- * @brief Set the 7bits Own Address2.
- * @note This action has no effect if own address2 is enabled.
- * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
- * OAR2 OA2MSK LL_I2C_SetOwnAddress2
- * @param I2Cx I2C Instance.
- * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
- * @param OwnAddrMask This parameter can be one of the following values:
- * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
- * @arg @ref LL_I2C_OWNADDRESS2_MASK01
- * @arg @ref LL_I2C_OWNADDRESS2_MASK02
- * @arg @ref LL_I2C_OWNADDRESS2_MASK03
- * @arg @ref LL_I2C_OWNADDRESS2_MASK04
- * @arg @ref LL_I2C_OWNADDRESS2_MASK05
- * @arg @ref LL_I2C_OWNADDRESS2_MASK06
- * @arg @ref LL_I2C_OWNADDRESS2_MASK07
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
-{
- MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
-}
-
-/**
- * @brief Enable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
- * @brief Disable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
- * @brief Check if Own Address1 acknowledge is enabled or disabled.
- * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
-}
-
-/**
- * @brief Configure the SDA setup, hold time and the SCL high, low period.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
- * @param I2Cx I2C Instance.
- * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
- * @note This parameter is computed with the STM32CubeMX Tool.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
-{
- WRITE_REG(I2Cx->TIMINGR, Timing);
-}
-
-/**
- * @brief Get the Timing Prescaler setting.
- * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
-}
-
-/**
- * @brief Get the SCL low period setting.
- * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
-}
-
-/**
- * @brief Get the SCL high period setting.
- * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
-}
-
-/**
- * @brief Get the SDA hold time.
- * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
-}
-
-/**
- * @brief Get the SDA setup time.
- * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
-}
-
-/**
- * @brief Configure peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
- * CR1 SMBDEN LL_I2C_SetMode
- * @param I2Cx I2C Instance.
- * @param PeripheralMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
-}
-
-/**
- * @brief Get peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
- * CR1 SMBDEN LL_I2C_GetMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
-}
-
-/**
- * @brief Enable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is drived low and
- * Alert Response Address Header acknowledge is enabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is supported.
- * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
- * @brief Disable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
- * Alert Response Address Header acknowledge is disabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is not supported.
- * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
- * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
-}
-
-/**
- * @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
- * @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
- * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
-}
-
-/**
- * @brief Configure the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
- * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
- * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
- * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
- * @param I2Cx I2C Instance.
- * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
- * @param TimeoutAMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
- * @param TimeoutB
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
- uint32_t TimeoutB)
-{
- MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
- TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
-}
-
-/**
- * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note These bits can only be programmed when TimeoutA is disabled.
- * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
- * @param I2Cx I2C Instance.
- * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
-{
- WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
-}
-
-/**
- * @brief Get the SMBus Clock TimeoutA setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
-}
-
-/**
- * @brief Set the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note This bit can only be programmed when TimeoutA is disabled.
- * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
- * @param I2Cx I2C Instance.
- * @param TimeoutAMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
-{
- WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
-}
-
-/**
- * @brief Get the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
-}
-
-/**
- * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note These bits can only be programmed when TimeoutB is disabled.
- * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
- * @param I2Cx I2C Instance.
- * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
-{
- WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
- * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
- * @brief Enable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
- * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
- * @param I2Cx I2C Instance.
- * @param ClockTimeout This parameter can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA
- * @arg @ref LL_I2C_SMBUS_TIMEOUTB
- * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
- SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
- * @brief Disable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
- * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
- * @param I2Cx I2C Instance.
- * @param ClockTimeout This parameter can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA
- * @arg @ref LL_I2C_SMBUS_TIMEOUTB
- * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
- CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
- * @brief Check if the SMBus Clock Timeout is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
- * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
- * @param I2Cx I2C Instance.
- * @param ClockTimeout This parameter can be one of the following values:
- * @arg @ref LL_I2C_SMBUS_TIMEOUTA
- * @arg @ref LL_I2C_SMBUS_TIMEOUTB
- * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
- return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable TXIS interrupt.
- * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
- * @brief Disable TXIS interrupt.
- * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
- * @brief Check if the TXIS Interrupt is enabled or disabled.
- * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
-}
-
-/**
- * @brief Enable RXNE interrupt.
- * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
- * @brief Disable RXNE interrupt.
- * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
- * @brief Check if the RXNE Interrupt is enabled or disabled.
- * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
-}
-
-/**
- * @brief Enable Address match interrupt (slave mode only).
- * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
- * @brief Disable Address match interrupt (slave mode only).
- * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
- * @brief Check if Address match interrupt is enabled or disabled.
- * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
-}
-
-/**
- * @brief Enable Not acknowledge received interrupt.
- * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
- * @brief Disable Not acknowledge received interrupt.
- * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
- * @brief Check if Not acknowledge received interrupt is enabled or disabled.
- * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
-}
-
-/**
- * @brief Enable STOP detection interrupt.
- * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
- * @brief Disable STOP detection interrupt.
- * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
- * @brief Check if STOP detection interrupt is enabled or disabled.
- * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
-}
-
-/**
- * @brief Enable Transfer Complete interrupt.
- * @note Any of these events will generate interrupt :
- * Transfer Complete (TC)
- * Transfer Complete Reload (TCR)
- * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
- * @brief Disable Transfer Complete interrupt.
- * @note Any of these events will generate interrupt :
- * Transfer Complete (TC)
- * Transfer Complete Reload (TCR)
- * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
- * @brief Check if Transfer Complete interrupt is enabled or disabled.
- * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
-}
-
-/**
- * @brief Enable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Arbitration Loss (ARLO)
- * Bus Error detection (BERR)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (ALERT)
- * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
- * @brief Disable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Arbitration Loss (ARLO)
- * Bus Error detection (BERR)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (ALERT)
- * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
- * @brief Check if Error interrupts are enabled or disabled.
- * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
- * @{
- */
-
-/**
- * @brief Indicate the status of Transmit data register empty flag.
- * @note RESET: When next data is written in Transmit data register.
- * SET: When Transmit data register is empty.
- * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
-}
-
-/**
- * @brief Indicate the status of Transmit interrupt flag.
- * @note RESET: When next data is written in Transmit data register.
- * SET: When Transmit data register is empty.
- * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
-}
-
-/**
- * @brief Indicate the status of Receive data register not empty flag.
- * @note RESET: When Receive data register is read.
- * SET: When the received data is copied in Receive data register.
- * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
-}
-
-/**
- * @brief Indicate the status of Address matched flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When the received slave address matched with one of the enabled slave address.
- * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
-}
-
-/**
- * @brief Indicate the status of Not Acknowledge received flag.
- * @note RESET: Clear default value.
- * SET: When a NACK is received after a byte transmission.
- * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
-}
-
-/**
- * @brief Indicate the status of Stop detection flag.
- * @note RESET: Clear default value.
- * SET: When a Stop condition is detected.
- * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
-}
-
-/**
- * @brief Indicate the status of Transfer complete flag (master mode).
- * @note RESET: Clear default value.
- * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
- * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
-}
-
-/**
- * @brief Indicate the status of Transfer complete flag (master mode).
- * @note RESET: Clear default value.
- * SET: When RELOAD=1 and NBYTES date have been transferred.
- * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
-}
-
-/**
- * @brief Indicate the status of Bus error flag.
- * @note RESET: Clear default value.
- * SET: When a misplaced Start or Stop condition is detected.
- * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
-}
-
-/**
- * @brief Indicate the status of Arbitration lost flag.
- * @note RESET: Clear default value.
- * SET: When arbitration lost.
- * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
-}
-
-/**
- * @brief Indicate the status of Overrun/Underrun flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
- * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
-}
-
-/**
- * @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When the received PEC does not match with the PEC register content.
- * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
-}
-
-/**
- * @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When a timeout or extended clock timeout occurs.
- * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
-}
-
-/**
- * @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: Clear default value.
- * SET: When SMBus host configuration, SMBus alert enabled and
- * a falling edge event occurs on SMBA pin.
- * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
-}
-
-/**
- * @brief Indicate the status of Bus Busy flag.
- * @note RESET: Clear default value.
- * SET: When a Start condition is detected.
- * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
-}
-
-/**
- * @brief Clear Address Matched flag.
- * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
-}
-
-/**
- * @brief Clear Not Acknowledge flag.
- * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
-}
-
-/**
- * @brief Clear Stop detection flag.
- * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
-}
-
-/**
- * @brief Clear Transmit data register empty flag (TXE).
- * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
- * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
-{
- WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
-}
-
-/**
- * @brief Clear Bus error flag.
- * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
-}
-
-/**
- * @brief Clear Arbitration lost flag.
- * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
-}
-
-/**
- * @brief Clear Overrun/Underrun flag.
- * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
-}
-
-/**
- * @brief Clear SMBus PEC error flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
-}
-
-/**
- * @brief Clear SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
-}
-
-/**
- * @brief Clear SMBus Alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Enable automatic STOP condition generation (master mode).
- * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
- * This bit has no effect in slave mode or when RELOAD bit is set.
- * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
- * @brief Disable automatic STOP condition generation (master mode).
- * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
- * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
- * @brief Check if automatic STOP condition is enabled or disabled.
- * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
-}
-
-/**
- * @brief Enable reload mode (master mode).
- * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
- * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
- * @brief Disable reload mode (master mode).
- * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
- * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
- * @brief Check if reload mode is enabled or disabled.
- * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
-}
-
-/**
- * @brief Configure the number of bytes for transfer.
- * @note Changing these bits when START bit is set is not allowed.
- * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
- * @param I2Cx I2C Instance.
- * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
-}
-
-/**
- * @brief Get the number of bytes configured for transfer.
- * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
-}
-
-/**
- * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- * @note Usage in Slave mode only.
- * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
- * @param I2Cx I2C Instance.
- * @param TypeAcknowledge This parameter can be one of the following values:
- * @arg @ref LL_I2C_ACK
- * @arg @ref LL_I2C_NACK
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
-}
-
-/**
- * @brief Generate a START or RESTART condition
- * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
- * This action has no effect when RELOAD is set.
- * @rmtoll CR2 START LL_I2C_GenerateStartCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_START);
-}
-
-/**
- * @brief Generate a STOP condition after the current byte transfer (master mode).
- * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
-}
-
-/**
- * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
- * @note The master sends the complete 10bit slave address read sequence :
- * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
- * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
- * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
- * @note The master only sends the first 7 bits of 10bit address in Read direction.
- * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
- * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
- * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
-}
-
-/**
- * @brief Configure the transfer direction (master mode).
- * @note Changing these bits when START bit is set is not allowed.
- * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
- * @param I2Cx I2C Instance.
- * @param TransferRequest This parameter can be one of the following values:
- * @arg @ref LL_I2C_REQUEST_WRITE
- * @arg @ref LL_I2C_REQUEST_READ
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
-}
-
-/**
- * @brief Get the transfer direction requested (master mode).
- * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_REQUEST_WRITE
- * @arg @ref LL_I2C_REQUEST_READ
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
-}
-
-/**
- * @brief Configure the slave address for transfer (master mode).
- * @note Changing these bits when START bit is set is not allowed.
- * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
- * @param I2Cx I2C Instance.
- * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
-}
-
-/**
- * @brief Get the slave address programmed for transfer.
- * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0x3F
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
- * CR2 ADD10 LL_I2C_HandleTransfer\n
- * CR2 RD_WRN LL_I2C_HandleTransfer\n
- * CR2 START LL_I2C_HandleTransfer\n
- * CR2 STOP LL_I2C_HandleTransfer\n
- * CR2 RELOAD LL_I2C_HandleTransfer\n
- * CR2 NBYTES LL_I2C_HandleTransfer\n
- * CR2 AUTOEND LL_I2C_HandleTransfer\n
- * CR2 HEAD10R LL_I2C_HandleTransfer
- * @param I2Cx I2C Instance.
- * @param SlaveAddr Specifies the slave address to be programmed.
- * @param SlaveAddrSize This parameter can be one of the following values:
- * @arg @ref LL_I2C_ADDRSLAVE_7BIT
- * @arg @ref LL_I2C_ADDRSLAVE_10BIT
- * @param TransferSize Specifies the number of bytes to be programmed.
- * This parameter must be a value between Min_Data=0 and Max_Data=255.
- * @param EndMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_MODE_RELOAD
- * @arg @ref LL_I2C_MODE_AUTOEND
- * @arg @ref LL_I2C_MODE_SOFTEND
- * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
- * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
- * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
- * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
- * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
- * @param Request This parameter can be one of the following values:
- * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
- * @arg @ref LL_I2C_GENERATE_STOP
- * @arg @ref LL_I2C_GENERATE_START_READ
- * @arg @ref LL_I2C_GENERATE_START_WRITE
- * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
- * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
- * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
- * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
- uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
- I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
-}
-
-/**
- * @brief Indicate the value of transfer direction (slave mode).
- * @note RESET: Write transfer, Slave enters in receiver mode.
- * SET: Read transfer, Slave enters in transmitter mode.
- * @rmtoll ISR DIR LL_I2C_GetTransferDirection
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_DIRECTION_WRITE
- * @arg @ref LL_I2C_DIRECTION_READ
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
-}
-
-/**
- * @brief Return the slave matched address.
- * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0x3F
- */
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
-}
-
-/**
- * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
- * This bit has no effect when RELOAD bit is set.
- * This bit has no effect in device mode when SBC bit is not set.
- * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
-}
-
-/**
- * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
-}
-
-/**
- * @brief Get the SMBus Packet Error byte calculated.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
-}
-
-/**
- * @brief Read Receive Data register.
- * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
- return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
-}
-
-/**
- * @brief Write in Transmit Data Register .
- * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
- * @param I2Cx I2C Instance.
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
- WRITE_REG(I2Cx->TXDR, Data);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_iwdg.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_iwdg.h
deleted file mode 100644
index d5bcc9d61b4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_iwdg.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_IWDG_H
-#define __STM32F3xx_LL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(IWDG)
-
-/** @defgroup IWDG_LL IWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
- * @{
- */
-
-#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_IWDG_ReadReg function
- * @{
- */
-#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
-#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
-#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
- * @{
- */
-#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
-#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
-#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
-#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
-#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
-#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
-#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
- * @{
- */
-/** @defgroup IWDG_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Start the Independent Watchdog
- * @note Except if the hardware watchdog option is selected
- * @rmtoll KR KEY LL_IWDG_Enable
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * @rmtoll KR KEY LL_IWDG_ReloadCounter
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
-}
-
-/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
-}
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
-}
-
-/**
- * @brief Select the prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_SetPrescaler
- * @param IWDGx IWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
-{
- WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
-}
-
-/**
- * @brief Get the selected prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_GetPrescaler
- * @param IWDGx IWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
-{
- return (uint32_t)(READ_REG(IWDGx->PR));
-}
-
-/**
- * @brief Specify the IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_SetReloadCounter
- * @param IWDGx IWDG Instance
- * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
-{
- WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
-}
-
-/**
- * @brief Get the specified IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_GetReloadCounter
- * @param IWDGx IWDG Instance
- * @retval Value between Min_Data=0 and Max_Data=0x0FFF
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
-{
- return (uint32_t)(READ_REG(IWDGx->RLR));
-}
-
-/**
- * @brief Specify high limit of the window value to be compared to the down-counter.
- * @rmtoll WINR WIN LL_IWDG_SetWindow
- * @param IWDGx IWDG Instance
- * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
-{
- WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
-}
-
-/**
- * @brief Get the high limit of the window value specified.
- * @rmtoll WINR WIN LL_IWDG_GetWindow
- * @param IWDGx IWDG Instance
- * @retval Value between Min_Data=0 and Max_Data=0x0FFF
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
-{
- return (uint32_t)(READ_REG(IWDGx->WINR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if flag Prescaler Value Update is set or not
- * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
-}
-
-/**
- * @brief Check if flag Reload Value Update is set or not
- * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
-}
-
-/**
- * @brief Check if flag Window Value Update is set or not
- * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
-}
-
-/**
- * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
- * @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR WVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
- * @param IWDGx IWDG Instance
- * @retval State of bits (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* IWDG) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h
deleted file mode 100644
index cb20141a4b1..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h
+++ /dev/null
@@ -1,903 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_opamp.h
- * @author MCD Application Team
- * @brief Header file of OPAMP LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_OPAMP_H
-#define __STM32F3xx_LL_OPAMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
-
-/** @defgroup OPAMP_LL OPAMP
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
- * @{
- */
-
-/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
-/* or PMOS. */
-/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
-/* - OPAMP trimming selection of transistors differential pair */
-/* - OPAMP trimming values of transistors differential pair */
-#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
-#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
- * @retval Register address
-*/
-#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
-
-
-
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of OPAMP instance.
- */
-typedef struct
-{
- uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
- This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
- @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
-
- This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
-
- uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
- This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
-
- This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
-
- uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
- This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
- @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
-
- This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
-
-} LL_OPAMP_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
- * @{
- */
-
-/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
- * @{
- */
-#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U) /*!< OPAMP functional mode */
-#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
- * @{
- */
-#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */
-#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< OPAMP functional mode, OPAMP operation in follower */
-#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
-#define LL_OPAMP_MODE_PGA_EXT_FILT_IO0 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO0. */
-#define LL_OPAMP_MODE_PGA_EXT_FILT_IO1 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO1. */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
- * @{
- */
-#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U) /*!< OPAMP PGA gain 2 */
-#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */
-#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */
-#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
- * @{
- */
-#define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO1 ((uint32_t)0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
- * @{
- */
-#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
- * @{
- */
-#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (LL_OPAMP_INPUT_NONINVERT_IO0 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC (LL_OPAMP_INPUT_NONINVERT_IO1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC (LL_OPAMP_INPUT_NONINVERT_IO2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC (LL_OPAMP_INPUT_NONINVERT_IO3 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA5 for OPAMP1, pin PD14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
- * @{
- */
-#define LL_OPAMP_INPUT_INVERT_IO0_SEC (LL_OPAMP_INPUT_INVERT_IO0 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_IO1_SEC (LL_OPAMP_INPUT_INVERT_IO1 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
- * @{
- */
-#define LL_OPAMP_INPUT_MUX_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP inputs multiplexer mode dosabled. */
-#define LL_OPAMP_INPUT_MUX_TIM1_CH6 (OPAMP_CSR_TCMEN) /*!< OPAMP inputs multiplexer mode enabled, controlled by TIM1 CC6. */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_VREF_OUTPUT OPAMP internal reference voltage path state to output
- * @{
- */
-#define LL_OPAMP_VREF_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP internal reference voltage path to output is disabled. */
-#define LL_OPAMP_VREF_OUTPUT_ENABLE (OPAMP_CSR_TSTREF) /*!< OPAMP internal reference voltage path to output is enabled. */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
- * @{
- */
-#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
-#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
- * @{
- */
-#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
-#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
-#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
-#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
-#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
-#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
- * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Delay for OPAMP startup time (transition from state disable to enable). */
-/* Note: OPAMP startup time depends on board application environment: */
-/* impedance connected to OPAMP output. */
-/* The delay below is specified under conditions: */
-/* - OPAMP in functional mode follower */
-/* - load impedance of 4kOhm (min), 50pF (max) */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tWAKEUP"). */
-/* Unit: us */
-#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 5U) /*!< Delay for OPAMP startup time */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
- * @{
- */
-/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
- * @{
- */
-/**
- * @brief Write a value in OPAMP register
- * @param __INSTANCE__ OPAMP Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in OPAMP register
- * @param __INSTANCE__ OPAMP Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
- * @{
- */
-
-/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
- * @{
- */
-
-/**
- * @brief Set OPAMP mode calibration or functional.
- * @note OPAMP mode corresponds to functional or calibration mode:
- * - functional mode: OPAMP operation in standalone, follower, ...
- * Set functional mode using function
- * @ref LL_OPAMP_SetFunctionalMode().
- * - calibration mode: offset calibration of the selected
- * transistors differential pair NMOS or PMOS.
- * @rmtoll CSR CALON LL_OPAMP_SetMode
- * @param OPAMPx OPAMP instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
- * @arg @ref LL_OPAMP_MODE_CALIBRATION
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
-}
-
-/**
- * @brief Get OPAMP mode calibration or functional.
- * @note OPAMP mode corresponds to functional or calibration mode:
- * - functional mode: OPAMP operation in standalone, follower, ...
- * Set functional mode using function
- * @ref LL_OPAMP_SetFunctionalMode().
- * - calibration mode: offset calibration of the selected
- * transistors differential pair NMOS or PMOS.
- * @rmtoll CSR CALON LL_OPAMP_GetMode
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
- * @arg @ref LL_OPAMP_MODE_CALIBRATION
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
-}
-
-/**
- * @brief Set OPAMP functional mode by setting internal connections.
- * OPAMP operation in standalone, follower, ...
- * @note This function reset bit of calibration mode to ensure
- * to be in functional mode, in order to have OPAMP parameters
- * (inputs selection, ...) set with the corresponding OPAMP mode
- * to be effective.
- * @rmtoll CSR VMSEL LL_OPAMP_SetFunctionalMode
- * @param OPAMPx OPAMP instance
- * @param FunctionalMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_MODE_STANDALONE
- * @arg @ref LL_OPAMP_MODE_FOLLOWER
- * @arg @ref LL_OPAMP_MODE_PGA
- * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
- * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
-{
- /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
-}
-
-/**
- * @brief Get OPAMP functional mode from setting of internal connections.
- * OPAMP operation in standalone, follower, ...
- * @rmtoll CSR VMSEL LL_OPAMP_GetFunctionalMode
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_MODE_STANDALONE
- * @arg @ref LL_OPAMP_MODE_FOLLOWER
- * @arg @ref LL_OPAMP_MODE_PGA
- * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
- * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
-}
-
-/**
- * @brief Set OPAMP PGA gain.
- * @note Preliminarily, OPAMP must be set in mode PGA
- * using function @ref LL_OPAMP_SetFunctionalMode().
- * @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
- * @param OPAMPx OPAMP instance
- * @param PGAGain This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_PGA_GAIN_2
- * @arg @ref LL_OPAMP_PGA_GAIN_4
- * @arg @ref LL_OPAMP_PGA_GAIN_8
- * @arg @ref LL_OPAMP_PGA_GAIN_16
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
-}
-
-/**
- * @brief Get OPAMP PGA gain.
- * @note Preliminarily, OPAMP must be set in mode PGA
- * using function @ref LL_OPAMP_SetFunctionalMode().
- * @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_PGA_GAIN_2
- * @arg @ref LL_OPAMP_PGA_GAIN_4
- * @arg @ref LL_OPAMP_PGA_GAIN_8
- * @arg @ref LL_OPAMP_PGA_GAIN_16
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
-}
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
- * @{
- */
-
-/**
- * @brief Set OPAMP non-inverting input connection.
- * @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
- * @param OPAMPx OPAMP instance
- * @param InputNonInverting This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
- *
- * (1) Parameter specific to OPAMP instances: OPAMP4.\n
- * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
-}
-
-/**
- * @brief Get OPAMP non-inverting input connection.
- * @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
- *
- * (1) Parameter specific to OPAMP instances: OPAMP4.\n
- * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
-}
-
-/**
- * @brief Set OPAMP inverting input connection.
- * @note OPAMP inverting input is used with OPAMP in mode standalone
- * or PGA with external capacitors for filtering circuit.
- * Otherwise (OPAMP in mode follower), OPAMP inverting input
- * is not used (not connected to GPIO pin).
- * @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
- * @param OPAMPx OPAMP instance
- * @param InputInverting This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
- * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
-{
- /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11) */
- /* to not modify OPAMP mode follower or PGA. */
- /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
- MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
-}
-
-/**
- * @brief Get OPAMP inverting input connection.
- * @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
- * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
-{
- register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
-
- /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
- /* input not connected. */
- return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
-}
-
-/**
- * @brief Set OPAMP non-inverting input secondary connection.
- * @rmtoll CSR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
- * @param OPAMPx OPAMP instance
- * @param InputNonInverting This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
- *
- * (1) Parameter specific to OPAMP instances: OPAMP4.\n
- * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSSEL, InputNonInverting);
-}
-
-/**
- * @brief Get OPAMP non-inverting input secondary connection.
- * @rmtoll CSR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
- * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
- *
- * (1) Parameter specific to OPAMP instances: OPAMP4.\n
- * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSSEL));
-}
-
-/**
- * @brief Set OPAMP inverting input secondary connection.
- * @note OPAMP inverting input is used with OPAMP in mode standalone
- * or PGA with external capacitors for filtering circuit.
- * Otherwise (OPAMP in mode follower), OPAMP inverting input
- * is not used (not connected to GPIO pin).
- * @rmtoll CSR VMSSEL LL_OPAMP_SetInputInvertingSecondary
- * @param OPAMPx OPAMP instance
- * @param InputInverting This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSSEL, InputInverting);
-}
-
-/**
- * @brief Get OPAMP inverting input secondary connection.
- * @rmtoll CSR VMSSEL LL_OPAMP_GetInputInvertingSecondary
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
- * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSSEL));
-}
-
-/**
- * @brief Set OPAMP inputs multiplexer mode.
- * @rmtoll CSR TCMEN LL_OPAMP_SetInputsMuxMode
- * @param OPAMPx OPAMP instance
- * @param InputsMuxMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
- * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TCMEN, InputsMuxMode);
-}
-
-/**
- * @brief Get OPAMP inputs multiplexer mode.
- * @rmtoll CSR TCMEN LL_OPAMP_GetInputsMuxMode
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
- * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TCMEN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
- * @{
- */
-
-/**
- * @brief Set OPAMP trimming mode.
- * @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
- * @param OPAMPx OPAMP instance
- * @param TrimmingMode This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_FACTORY
- * @arg @ref LL_OPAMP_TRIMMING_USER
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
-}
-
-/**
- * @brief Get OPAMP trimming mode.
- * @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_FACTORY
- * @arg @ref LL_OPAMP_TRIMMING_USER
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
-}
-
-/**
- * @brief Set OPAMP offset to calibrate the selected transistors
- * differential pair NMOS or PMOS.
- * @note Preliminarily, OPAMP must be set in mode calibration
- * using function @ref LL_OPAMP_SetMode().
- * @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
- * @param OPAMPx OPAMP instance
- * @param TransistorsDiffPair This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
- * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
- * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
- * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
- *
- * (1) Default parameters to be used for calibration
- * using two trimming steps (one with each transistors differential
- * pair NMOS and PMOS)
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
-{
- /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
- /* containing other bits reserved for other purpose. */
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
-}
-
-/**
- * @brief Get OPAMP offset to calibrate the selected transistors
- * differential pair NMOS or PMOS.
- * @note Preliminarily, OPAMP must be set in mode calibration
- * using function @ref LL_OPAMP_SetMode().
- * @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
- * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
- * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
- * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
- *
- * (1) Default parameters to be used for calibration
- * using two trimming steps (one with each transistors differential
- * pair NMOS and PMOS)
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
-{
- register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
-
- return (CalibrationSelection |
- ((OPAMP_CSR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_CSR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL))));
-}
-
-/**
- * @brief Set OPAMP calibration internal reference voltage to output.
- * @rmtoll CSR TSTREF LL_OPAMP_SetCalibrationVrefOutput
- * @param OPAMPx OPAMP instance
- * @param CalibrationVrefOutput This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
- * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx, uint32_t CalibrationVrefOutput)
-{
- MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TSTREF, CalibrationVrefOutput);
-}
-
-/**
- * @brief Get OPAMP calibration internal reference voltage to output.
- * @rmtoll CSR TSTREF LL_OPAMP_GetCalibrationVrefOutput
- * @param OPAMPx OPAMP instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
- * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TSTREF));
-}
-
-/**
- * @brief Get OPAMP calibration result of toggling output.
- * @note This functions returns:
- * 0 if OPAMP calibration output is reset
- * 1 if OPAMP calibration output is set
- * @rmtoll CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
- * @param OPAMPx OPAMP instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
-{
- return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL);
-}
-
-/**
- * @brief Set OPAMP trimming factor for the selected transistors
- * differential pair NMOS or PMOS, corresponding to the selected
- * power mode.
- * @rmtoll CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue\n
- * CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
- * @param OPAMPx OPAMP instance
- * @param TransistorsDiffPair This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_NMOS
- * @arg @ref LL_OPAMP_TRIMMING_PMOS
- * @param TrimmingValue 0x00...0x1F
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
-{
- MODIFY_REG(OPAMPx->CSR,
- (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
- TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
-}
-
-/**
- * @brief Get OPAMP trimming factor for the selected transistors
- * differential pair NMOS or PMOS, corresponding to the selected
- * power mode.
- * @rmtoll CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue\n
- * CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
- * @param OPAMPx OPAMP instance
- * @param TransistorsDiffPair This parameter can be one of the following values:
- * @arg @ref LL_OPAMP_TRIMMING_NMOS
- * @arg @ref LL_OPAMP_TRIMMING_PMOS
- * @retval 0x0...0x1F
- */
-__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair)
-{
- return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
- >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
- * @{
- */
-/**
- * @brief Enable OPAMP instance.
- * @note After enable from off state, OPAMP requires a delay
- * to fullfill wake up time specification.
- * Refer to device datasheet, parameter "tWAKEUP".
- * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
- * @param OPAMPx OPAMP instance
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
-{
- SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
-}
-
-/**
- * @brief Disable OPAMP instance.
- * @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
- * @param OPAMPx OPAMP instance
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
-{
- CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
-}
-
-/**
- * @brief Get OPAMP instance enable state
- * (0: OPAMP is disabled, 1: OPAMP is enabled)
- * @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
- * @param OPAMPx OPAMP instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
-{
- return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
-}
-
-/**
- * @brief Lock OPAMP instance.
- * @note Once locked, OPAMP configuration can be accessed in read-only.
- * @note The only way to unlock the OPAMP is a device hardware reset.
- * @rmtoll CSR LOCK LL_OPAMP_Lock
- * @param OPAMPx OPAMP instance
- * @retval None
- */
-__STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
-{
- SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
-}
-
-/**
- * @brief Get OPAMP lock state
- * (0: OPAMP is unlocked, 1: OPAMP is locked).
- * @note Once locked, OPAMP configuration can be accessed in read-only.
- * @note The only way to unlock the OPAMP is a device hardware reset.
- * @rmtoll CSR LOCK LL_OPAMP_IsLocked
- * @param OPAMPx OPAMP instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
-{
- return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
-ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
-void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h
deleted file mode 100644
index 806324a7741..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h
+++ /dev/null
@@ -1,570 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_PWR_H
-#define __STM32F3xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_PWR_WriteReg function
- * @{
- */
-#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_PWR_ReadReg function
- * @{
- */
-#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
-#if defined(PWR_PVD_SUPPORT)
-#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
-#endif /* PWR_PVD_SUPPORT */
-#if defined(PWR_CSR_VREFINTRDYF)
-#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
-#endif /* PWR_CSR_VREFINTRDYF */
-#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
-#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
-#endif /* PWR_CSR_EWUP3 */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
- * @{
- */
-#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
- * @}
- */
-
-#if defined(PWR_CR_LPDS)
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
- * @}
- */
-#endif /* PWR_CR_LPDS */
-
-#if defined(PWR_PVD_SUPPORT)
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
- * @{
- */
-#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
-#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
-#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
-#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
-#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
-/**
- * @}
- */
-#endif /* PWR_PVD_SUPPORT */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
- * @{
- */
-#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
-#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
-#endif /* PWR_CSR_EWUP3 */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
- * @{
- */
-#if defined(SDADC1)
-#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */
-#endif /* SDADC1 */
-#if defined(SDADC2)
-#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */
-#endif /* SDADC2 */
-#if defined(SDADC3)
-#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */
-#endif /* SDADC3 */
-/**
- * @}
- */
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in PWR register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in PWR register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enables the SDADC peripheral functionality
- * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
- * CR ENSD2 LL_PWR_EnableSDADC\n
- * CR ENSD3 LL_PWR_EnableSDADC
- * @param Analogx This parameter can be a combination of the following values:
- * @arg @ref LL_PWR_SDADC_ANALOG1
- * @arg @ref LL_PWR_SDADC_ANALOG2
- * @arg @ref LL_PWR_SDADC_ANALOG3
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
-{
- SET_BIT(PWR->CR, Analogx);
-}
-
-/**
- * @brief Disables the SDADC peripheral functionality
- * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
- * CR ENSD2 LL_PWR_EnableSDADC\n
- * CR ENSD3 LL_PWR_EnableSDADC
- * @param Analogx This parameter can be a combination of the following values:
- * @arg @ref LL_PWR_SDADC_ANALOG1
- * @arg @ref LL_PWR_SDADC_ANALOG2
- * @arg @ref LL_PWR_SDADC_ANALOG3
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
-{
- CLEAR_BIT(PWR->CR, Analogx);
-}
-
-/**
- * @brief Check if SDADCx has been enabled or not
- * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n
- * CR ENSD2 LL_PWR_IsEnabledSDADC\n
- * CR ENSD3 LL_PWR_IsEnabledSDADC
- * @param Analogx This parameter can be a combination of the following values:
- * @arg @ref LL_PWR_SDADC_ANALOG1
- * @arg @ref LL_PWR_SDADC_ANALOG2
- * @arg @ref LL_PWR_SDADC_ANALOG3
- * @retval None
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
-{
- return (READ_BIT(PWR->CR, Analogx) == (Analogx));
-}
-
-/**
- * @brief Enable access to the backup domain
- * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Check if the backup domain is enabled
- * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-
-#if defined(PWR_CR_LPDS)
-/**
- * @brief Set voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
- * @param RegulMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
- * @brief Get voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-#endif /* PWR_CR_LPDS */
-
-/**
- * @brief Set Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_SetPowerMode
- * @param PDMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
- MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
-}
-
-/**
- * @brief Get Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_GetPowerMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector
- * @rmtoll CR PLS LL_PWR_SetPVDLevel
- * @param PVDLevel This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
- MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
- * @brief Get the voltage threshold detection
- * @rmtoll CR PLS LL_PWR_GetPVDLevel
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
- * @brief Enable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_EnablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Disable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_DisablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Check if Power Voltage Detector is enabled
- * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-#endif /* PWR_PVD_SUPPORT */
-
-/**
- * @brief Enable the WakeUp PINx functionality
- * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
- * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
- * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
- *
- * (*) not available on all devices
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
- SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality
- * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
- * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
- * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
- *
- * (*) not available on all devices
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
- CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Check if the WakeUp PINx functionality is enabled
- * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
- * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
- * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
- *
- * (*) not available on all devices
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
- return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Wake-up Flag
- * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
- * @brief Get Standby Flag
- * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
- * @brief Indicate whether VDD voltage is below the selected PVD threshold
- * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-#endif /* PWR_PVD_SUPPORT */
-
-#if defined(PWR_CSR_VREFINTRDYF)
-/**
- * @brief Get Internal Reference VrefInt Flag
- * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
-}
-#endif /* PWR_CSR_VREFINTRDYF */
-/**
- * @brief Clear Standby Flag
- * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
- * @brief Clear Wake-up Flags
- * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_PWR_DeInit(void);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(PWR) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h
deleted file mode 100644
index 20089b752f1..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h
+++ /dev/null
@@ -1,2834 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_RCC_H
-#define __STM32F3xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Constants RCC Private Constants
- * @{
- */
-/* Defines used for the bit position in the register and perform offsets*/
-#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
-#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
-#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
-#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
-#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
-#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
-#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
-#define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
- * @{
- */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- * @{
- */
-
-/**
- * @brief RCC Clocks Frequency Structure
- */
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- * @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
- * HW set-up.
- * @{
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_RCC_WriteReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RCC_ReadReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
-#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-#if defined(RCC_CSR_V18PWRRSTF)
-#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
-#endif /* RCC_CSR_V18PWRRSTF */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
- * @{
- */
-#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
- * @{
- */
-#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
-#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- * @{
- */
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- * @{
- */
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- * @{
- */
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
- * @{
- */
-#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
-#if defined(RCC_CFGR_PLLNODIV)
-#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
-#endif /* RCC_CFGR_PLLNODIV */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
- * @{
- */
-#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
-#if defined(RCC_CFGR_MCOPRE)
-#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
-#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
-#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
-#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
-#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
-#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
-#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
-#endif /* RCC_CFGR_MCOPRE */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- * @{
- */
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
- * @{
- */
-#if defined(RCC_CFGR3_USART1SW_PCLK1)
-#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
-#else
-#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
-#endif /*RCC_CFGR3_USART1SW_PCLK1*/
-#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
-#if defined(RCC_CFGR3_USART2SW)
-#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
-#endif /* RCC_CFGR3_USART2SW */
-#if defined(RCC_CFGR3_USART3SW)
-#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
-#endif /* RCC_CFGR3_USART3SW */
-/**
- * @}
- */
-
-#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
-/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
- * @{
- */
-#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
-#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
-#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
-#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
-
-/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
- * @{
- */
-#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
-#if defined(RCC_CFGR3_I2C2SW)
-#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
-#endif /*RCC_CFGR3_I2C2SW*/
-#if defined(RCC_CFGR3_I2C3SW)
-#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
-#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
-#endif /*RCC_CFGR3_I2C3SW*/
-/**
- * @}
- */
-
-#if defined(RCC_CFGR_I2SSRC)
-/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
-#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR_I2SSRC */
-
-#if defined(RCC_CFGR3_TIMSW)
-/** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
- * @{
- */
-#define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
-#define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
-#if defined(RCC_CFGR3_TIM8SW)
-#define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
-#define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
-#endif /*RCC_CFGR3_TIM8SW*/
-#if defined(RCC_CFGR3_TIM15SW)
-#define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
-#define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
-#endif /*RCC_CFGR3_TIM15SW*/
-#if defined(RCC_CFGR3_TIM16SW)
-#define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
-#define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
-#endif /*RCC_CFGR3_TIM16SW*/
-#if defined(RCC_CFGR3_TIM17SW)
-#define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
-#define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
-#endif /*RCC_CFGR3_TIM17SW*/
-#if defined(RCC_CFGR3_TIM20SW)
-#define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
-#define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
-#endif /*RCC_CFGR3_TIM20SW*/
-#if defined(RCC_CFGR3_TIM2SW)
-#define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
-#define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
-#endif /*RCC_CFGR3_TIM2SW*/
-#if defined(RCC_CFGR3_TIM34SW)
-#define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
-#define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
-#endif /*RCC_CFGR3_TIM34SW*/
-/**
- * @}
- */
-
-#endif /* RCC_CFGR3_TIMSW */
-
-#if defined(HRTIM1)
-/** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
- * @{
- */
-#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
-#define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
-/**
- * @}
- */
-
-#endif /* HRTIM1 */
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
- * @{
- */
-#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
-#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
-/**
- * @}
- */
-
-#endif /* CEC */
-
-#if defined(USB)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
-/**
- * @}
- */
-
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE)
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
-/**
- * @}
- */
-
-#elif defined(RCC_CFGR2_ADC1PRES)
-/** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
-#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
-/**
- * @}
- */
-
-#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
-/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
- * @{
- */
-#define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
- * @{
- */
-#define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
-#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
-/**
- * @}
- */
-
-#else
-/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
-#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
-
-#endif /* RCC_CFGR_ADCPRE */
-
-#if defined(RCC_CFGR_SDPRE)
-/** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
- * @{
- */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
-#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR_SDPRE */
-
-/** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
- * @{
- */
-#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
-#if defined(RCC_CFGR3_USART2SW)
-#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
-#endif /* RCC_CFGR3_USART2SW */
-#if defined(RCC_CFGR3_USART3SW)
-#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
-#endif /* RCC_CFGR3_USART3SW */
-/**
- * @}
- */
-
-#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
-/** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
- * @{
- */
-#define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
-#define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
-
-/** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
- * @{
- */
-#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
-#if defined(RCC_CFGR3_I2C2SW)
-#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
-#endif /*RCC_CFGR3_I2C2SW*/
-#if defined(RCC_CFGR3_I2C3SW)
-#define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
-#endif /*RCC_CFGR3_I2C3SW*/
-/**
- * @}
- */
-
-#if defined(RCC_CFGR_I2SSRC)
-/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
- * @{
- */
-#define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR_I2SSRC */
-
-#if defined(RCC_CFGR3_TIMSW)
-/** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
- * @{
- */
-#define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
-#if defined(RCC_CFGR3_TIM2SW)
-#define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
-#endif /*RCC_CFGR3_TIM2SW*/
-#if defined(RCC_CFGR3_TIM8SW)
-#define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
-#endif /*RCC_CFGR3_TIM8SW*/
-#if defined(RCC_CFGR3_TIM15SW)
-#define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
-#endif /*RCC_CFGR3_TIM15SW*/
-#if defined(RCC_CFGR3_TIM16SW)
-#define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
-#endif /*RCC_CFGR3_TIM16SW*/
-#if defined(RCC_CFGR3_TIM17SW)
-#define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
-#endif /*RCC_CFGR3_TIM17SW*/
-#if defined(RCC_CFGR3_TIM20SW)
-#define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
-#endif /*RCC_CFGR3_TIM20SW*/
-#if defined(RCC_CFGR3_TIM34SW)
-#define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
-#endif /*RCC_CFGR3_TIM34SW*/
-/**
- * @}
- */
-
-#endif /* RCC_CFGR3_TIMSW */
-
-#if defined(HRTIM1)
-/** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
- * @{
- */
-#define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
-/**
- * @}
- */
-
-#endif /* HRTIM1 */
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
- * @{
- */
-#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
-/**
- * @}
- */
-
-#endif /* CEC */
-
-#if defined(USB)
-/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
-/**
- * @}
- */
-
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE)
-/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
- * @{
- */
-#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR_ADCPRE */
-
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-/** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
- * @{
- */
-#if defined(RCC_CFGR2_ADC1PRES)
-#define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
-#else
-#define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
-#if defined(RCC_CFGR2_ADCPRE34)
-#define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
-#endif /*RCC_CFGR2_ADCPRE34*/
-#endif /*RCC_CFGR2_ADC1PRES*/
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-
-#if defined(RCC_CFGR_SDPRE)
-/** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
- * @{
- */
-#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR_SDPRE */
-
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- * @{
- */
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
- * @{
- */
-#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
-#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
-#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
-#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
-#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
-#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
-#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
-#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
-#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
-#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
-#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
-#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
-#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
-#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
-#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
- * @{
- */
-#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
-#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
-#else
-#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
- * @{
- */
-#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
-#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
-#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
-#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
-#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
-#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
-#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
-#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
-#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
-#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
-#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
-#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
-#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
-#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
-#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
-#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RCC register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RCC register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- * @{
- */
-
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
- * , @ref LL_RCC_PLL_GetPrediv());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLMUL__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @param __PLLPREDIV__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PREDIV_DIV_1
- * @arg @ref LL_RCC_PREDIV_DIV_2
- * @arg @ref LL_RCC_PREDIV_DIV_3
- * @arg @ref LL_RCC_PREDIV_DIV_4
- * @arg @ref LL_RCC_PREDIV_DIV_5
- * @arg @ref LL_RCC_PREDIV_DIV_6
- * @arg @ref LL_RCC_PREDIV_DIV_7
- * @arg @ref LL_RCC_PREDIV_DIV_8
- * @arg @ref LL_RCC_PREDIV_DIV_9
- * @arg @ref LL_RCC_PREDIV_DIV_10
- * @arg @ref LL_RCC_PREDIV_DIV_11
- * @arg @ref LL_RCC_PREDIV_DIV_12
- * @arg @ref LL_RCC_PREDIV_DIV_13
- * @arg @ref LL_RCC_PREDIV_DIV_14
- * @arg @ref LL_RCC_PREDIV_DIV_15
- * @arg @ref LL_RCC_PREDIV_DIV_16
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
- (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
-
-#else
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
- * @param __PLLMUL__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
- ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-/**
- * @brief Helper macro to calculate the HCLK frequency
- * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
- * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
- * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- * @param __AHBPRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval HCLK clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
- * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB1PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval PCLK1 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
- * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB2PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval PCLK2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_LL_EF_HSE HSE
- * @{
- */
-
-/**
- * @brief Enable the Clock Security System.
- * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Disable the Clock Security System.
- * @note Cannot be disabled in HSE is ready (only by hardware)
- * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Enable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Disable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Check if HSE oscillator Ready
- * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI HSI
- * @{
- */
-
-/**
- * @brief Enable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Disable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Check if HSI clock is ready
- * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
-}
-
-/**
- * @brief Get HSI Calibration value
- * @note When HSITRIM is written, HSICAL is updated with the sum of
- * HSITRIM and the factory trim value
- * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
-}
-
-/**
- * @brief Set HSI Calibration trimming
- * @note user-programmable trimming value that is added to the HSICAL
- * @note Default value is 16, which, when added to the HSICAL value,
- * should trim the HSI to 16 MHz +/- 1 %
- * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @brief Get HSI Calibration trimming
- * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
- * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSE LSE
- * @{
- */
-
-/**
- * @brief Enable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Disable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Enable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Disable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Set LSE oscillator drive capability
- * @note The oscillator is in Xtal mode when it is not in bypass mode.
- * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
- * @param LSEDrive This parameter can be one of the following values:
- * @arg @ref LL_RCC_LSEDRIVE_LOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
- * @arg @ref LL_RCC_LSEDRIVE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
-{
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
-}
-
-/**
- * @brief Get LSE oscillator drive capability
- * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_LSEDRIVE_LOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
- * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
- * @arg @ref LL_RCC_LSEDRIVE_HIGH
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
-{
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
-}
-
-/**
- * @brief Check if LSE oscillator Ready
- * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSI LSI
- * @{
- */
-
-/**
- * @brief Enable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Disable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
- CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Check if LSI is Ready
- * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_System System
- * @{
- */
-
-/**
- * @brief Configure the system clock source
- * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
- * @brief Get the system clock source
- * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
- * @brief Set AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
- * @brief Set APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
- * @brief Set APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
- * @brief Get AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
- * @brief Get APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
- * @brief Get APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_MCO MCO
- * @{
- */
-
-/**
- * @brief Configure MCOx
- * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
- * CFGR MCOPRE LL_RCC_ConfigMCO\n
- * CFGR PLLNODIV LL_RCC_ConfigMCO
- * @param MCOxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
- * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
- * @arg @ref LL_RCC_MCO1SOURCE_HSI
- * @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_LSI
- * @arg @ref LL_RCC_MCO1SOURCE_LSE
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
- *
- * (*) value not defined in all devices
- * @param MCOxPrescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1_DIV_1
- * @arg @ref LL_RCC_MCO1_DIV_2 (*)
- * @arg @ref LL_RCC_MCO1_DIV_4 (*)
- * @arg @ref LL_RCC_MCO1_DIV_8 (*)
- * @arg @ref LL_RCC_MCO1_DIV_16 (*)
- * @arg @ref LL_RCC_MCO1_DIV_32 (*)
- * @arg @ref LL_RCC_MCO1_DIV_64 (*)
- * @arg @ref LL_RCC_MCO1_DIV_128 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-#if defined(RCC_CFGR_MCOPRE)
-#if defined(RCC_CFGR_PLLNODIV)
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
-#else
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
-#endif /* RCC_CFGR_PLLNODIV */
-#else
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
-#endif /* RCC_CFGR_MCOPRE */
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- * @{
- */
-
-/**
- * @brief Configure USARTx clock source
- * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
- * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
- * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
- * @param USARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
-{
- MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
-}
-
-#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
-/**
- * @brief Configure UARTx clock source
- * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
- * CFGR3 UART5SW LL_RCC_SetUARTClockSource
- * @param UARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
- * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
- * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
- * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
-{
- MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
-}
-#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
-
-/**
- * @brief Configure I2Cx clock source
- * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
- * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
- * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
- * @param I2CxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
-{
- MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
-}
-
-#if defined(RCC_CFGR_I2SSRC)
-/**
- * @brief Configure I2Sx clock source
- * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
-}
-#endif /* RCC_CFGR_I2SSRC */
-
-#if defined(RCC_CFGR3_TIMSW)
-/**
- * @brief Configure TIMx clock source
- * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
- * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
- * @param TIMxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
-{
- MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
-}
-#endif /* RCC_CFGR3_TIMSW */
-
-#if defined(HRTIM1)
-/**
- * @brief Configure HRTIMx clock source
- * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
- * @param HRTIMxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
-{
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
-}
-#endif /* HRTIM1 */
-
-#if defined(CEC)
-/**
- * @brief Configure CEC clock source
- * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
- * @param CECxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
- * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
-{
- MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
-}
-#endif /* CEC */
-
-#if defined(USB)
-/**
- * @brief Configure USB clock source
- * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
-}
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE)
-/**
- * @brief Configure ADC clock source
- * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
-}
-
-#elif defined(RCC_CFGR2_ADC1PRES)
-/**
- * @brief Configure ADC clock source
- * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
-}
-
-#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-/**
- * @brief Configure ADC clock source
- * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
- * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
- * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
-#if defined(RCC_CFGR2_ADCPRE34)
- MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
-#else
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
-#endif /* RCC_CFGR2_ADCPRE34 */
-}
-#endif /* RCC_CFGR_ADCPRE */
-
-#if defined(RCC_CFGR_SDPRE)
-/**
- * @brief Configure SDADCx clock source
- * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
- * @param SDADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
-}
-#endif /* RCC_CFGR_SDPRE */
-
-/**
- * @brief Get USARTx clock source
- * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
- * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
- * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
- * @param USARTx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE
- * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
- * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
-}
-
-#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
-/**
- * @brief Get UARTx clock source
- * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
- * CFGR3 UART5SW LL_RCC_GetUARTClockSource
- * @param UARTx This parameter can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE
- * @arg @ref LL_RCC_UART5_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
- * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
- * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
- * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
- * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
-}
-#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
-
-/**
- * @brief Get I2Cx clock source
- * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
- * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
- * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
- * @param I2Cx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
- * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
-}
-
-#if defined(RCC_CFGR_I2SSRC)
-/**
- * @brief Get I2Sx clock source
- * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
-}
-#endif /* RCC_CFGR_I2SSRC */
-
-#if defined(RCC_CFGR3_TIMSW)
-/**
- * @brief Get TIMx clock source
- * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
- * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
- * @param TIMx This parameter can be one of the following values:
- * @arg @ref LL_RCC_TIM1_CLKSOURCE
- * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
- * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
-}
-#endif /* RCC_CFGR3_TIMSW */
-
-#if defined(HRTIM1)
-/**
- * @brief Get HRTIMx clock source
- * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
- * @param HRTIMx This parameter can be one of the following values:
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
-}
-#endif /* HRTIM1 */
-
-#if defined(CEC)
-/**
- * @brief Get CEC clock source
- * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
- * @param CECx This parameter can be one of the following values:
- * @arg @ref LL_RCC_CEC_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
- * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
- */
-__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
-}
-#endif /* CEC */
-
-#if defined(USB)
-/**
- * @brief Get USBx clock source
- * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
- * @param USBx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
-}
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE)
-/**
- * @brief Get ADCx clock source
- * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
-}
-
-#elif defined(RCC_CFGR2_ADC1PRES)
-/**
- * @brief Get ADCx clock source
- * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC1_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
- * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
-}
-
-#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-/**
- * @brief Get ADCx clock source
- * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
- * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSOURCE
- * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
- * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
- * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
- * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
-#if defined(RCC_CFGR2_ADCPRE34)
- return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
-#else
- return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
-#endif /*RCC_CFGR2_ADCPRE34*/
-}
-#endif /* RCC_CFGR_ADCPRE */
-
-#if defined(RCC_CFGR_SDPRE)
-/**
- * @brief Get SDADCx clock source
- * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
- * @param SDADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_SDADC_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
- * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
-}
-#endif /* RCC_CFGR_SDPRE */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_RTC RTC
- * @{
- */
-
-/**
- * @brief Set RTC Clock Source
- * @note Once the RTC clock source has been selected, it cannot be changed any more unless
- * the Backup domain is reset. The BDRST bit can be used to reset them.
- * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
- * @brief Get RTC Clock Source
- * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
- * @brief Enable RTC
- * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Disable RTC
- * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Check if RTC has been enabled or not
- * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
-}
-
-/**
- * @brief Force the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Release the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLL PLL
- * @{
- */
-
-/**
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Disable PLL
- * @note Cannot be disabled if the PLL clock is used as the system clock
- * @rmtoll CR PLLON LL_RCC_PLL_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
-}
-
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLMul This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @param PLLDiv This parameter can be one of the following values:
- * @arg @ref LL_RCC_PREDIV_DIV_1
- * @arg @ref LL_RCC_PREDIV_DIV_2
- * @arg @ref LL_RCC_PREDIV_DIV_3
- * @arg @ref LL_RCC_PREDIV_DIV_4
- * @arg @ref LL_RCC_PREDIV_DIV_5
- * @arg @ref LL_RCC_PREDIV_DIV_6
- * @arg @ref LL_RCC_PREDIV_DIV_7
- * @arg @ref LL_RCC_PREDIV_DIV_8
- * @arg @ref LL_RCC_PREDIV_DIV_9
- * @arg @ref LL_RCC_PREDIV_DIV_10
- * @arg @ref LL_RCC_PREDIV_DIV_11
- * @arg @ref LL_RCC_PREDIV_DIV_12
- * @arg @ref LL_RCC_PREDIV_DIV_13
- * @arg @ref LL_RCC_PREDIV_DIV_14
- * @arg @ref LL_RCC_PREDIV_DIV_15
- * @arg @ref LL_RCC_PREDIV_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
-}
-
-#else
-
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
- * @param PLLMul This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
-}
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-
-/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
-}
-
-/**
- * @brief Get PLL multiplication Factor
- * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
-}
-
-/**
- * @brief Get PREDIV division factor for the main PLL
- * @note They can be written only when the PLL is disabled
- * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PREDIV_DIV_1
- * @arg @ref LL_RCC_PREDIV_DIV_2
- * @arg @ref LL_RCC_PREDIV_DIV_3
- * @arg @ref LL_RCC_PREDIV_DIV_4
- * @arg @ref LL_RCC_PREDIV_DIV_5
- * @arg @ref LL_RCC_PREDIV_DIV_6
- * @arg @ref LL_RCC_PREDIV_DIV_7
- * @arg @ref LL_RCC_PREDIV_DIV_8
- * @arg @ref LL_RCC_PREDIV_DIV_9
- * @arg @ref LL_RCC_PREDIV_DIV_10
- * @arg @ref LL_RCC_PREDIV_DIV_11
- * @arg @ref LL_RCC_PREDIV_DIV_12
- * @arg @ref LL_RCC_PREDIV_DIV_13
- * @arg @ref LL_RCC_PREDIV_DIV_14
- * @arg @ref LL_RCC_PREDIV_DIV_15
- * @arg @ref LL_RCC_PREDIV_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Clear LSI ready interrupt flag
- * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
- * @brief Clear LSE ready interrupt flag
- * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
- * @brief Clear HSI ready interrupt flag
- * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
- * @brief Clear HSE ready interrupt flag
- * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
- * @brief Clear PLL ready interrupt flag
- * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-/**
- * @brief Clear Clock security system interrupt flag
- * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-/**
- * @brief Check if LSI ready interrupt occurred or not
- * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
-}
-
-/**
- * @brief Check if LSE ready interrupt occurred or not
- * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
-}
-
-/**
- * @brief Check if HSI ready interrupt occurred or not
- * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
-}
-
-/**
- * @brief Check if HSE ready interrupt occurred or not
- * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
-}
-
-#if defined(RCC_CFGR_MCOF)
-/**
- * @brief Check if switch to new MCO source is effective or not
- * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
-{
- return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
-}
-#endif /* RCC_CFGR_MCOF */
-
-/**
- * @brief Check if PLL ready interrupt occurred or not
- * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
-}
-
-/**
- * @brief Check if Clock security system interrupt occurred or not
- * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
-}
-
-/**
- * @brief Check if RCC flag Independent Watchdog reset is set or not.
- * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
-}
-
-/**
- * @brief Check if RCC flag Low Power reset is set or not.
- * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
-}
-
-/**
- * @brief Check if RCC flag is set or not.
- * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
-}
-
-/**
- * @brief Check if RCC flag Pin reset is set or not.
- * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
-}
-
-/**
- * @brief Check if RCC flag POR/PDR reset is set or not.
- * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
-}
-
-/**
- * @brief Check if RCC flag Software reset is set or not.
- * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
-}
-
-/**
- * @brief Check if RCC flag Window Watchdog reset is set or not.
- * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
-}
-
-#if defined(RCC_CSR_V18PWRRSTF)
-/**
- * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
- * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
-}
-#endif /* RCC_CSR_V18PWRRSTF */
-
-/**
- * @brief Set RMVF bit to clear the reset flags.
- * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Enable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Enable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Enable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Enable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-/**
- * @brief Disable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Disable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Disable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Disable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Disable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-/**
- * @brief Checks if LSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
-}
-
-/**
- * @brief Checks if LSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
-}
-
-/**
- * @brief Checks if HSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
-}
-
-/**
- * @brief Checks if HSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
-}
-
-/**
- * @brief Checks if PLL ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_RCC_DeInit(void);
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
- * @{
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
-#if defined(UART4) || defined(UART5)
-uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
-#endif /* UART4 || UART5 */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
-#if defined(RCC_CFGR_I2SSRC)
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#endif /* RCC_CFGR_I2SSRC */
-#if defined(USB_OTG_FS) || defined(USB)
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* USB_OTG_FS || USB */
-#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-#if defined(RCC_CFGR_SDPRE)
-uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
-#endif /*RCC_CFGR_SDPRE */
-#if defined(CEC)
-uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
-#endif /* CEC */
-#if defined(RCC_CFGR3_TIMSW)
-uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
-#endif /*RCC_CFGR3_TIMSW*/
-uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* RCC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h
deleted file mode 100644
index e0d43c6ca90..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rtc.h
+++ /dev/null
@@ -1,3794 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_RTC_H
-#define __STM32F3xx_LL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(RTC)
-
-/** @defgroup RTC_LL RTC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_LL_Private_Constants RTC Private Constants
- * @{
- */
-/* Masks Definition */
-#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-
-/* Write protection defines */
-#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
-#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
-#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
-
-/* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY 24U
-#define RTC_OFFSET_DAY 16U
-#define RTC_OFFSET_MONTH 8U
-#define RTC_OFFSET_HOUR 16U
-#define RTC_OFFSET_MINUTE 8U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_Private_Macros RTC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
- * @{
- */
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
- This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetHourFormat(). */
-
- uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetAsynchPrescaler(). */
-
- uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetSynchPrescaler(). */
-} LL_RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
-
- uint8_t Hours; /*!< Specifies the RTC Time Hours.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
-} LL_RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
-
- uint8_t Month; /*!< Specifies the RTC Date Month.
- This parameter can be a value of @ref RTC_LL_EC_MONTH
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
-
- uint8_t Day; /*!< Specifies the RTC Date Day.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
-} LL_RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
- or @ref LL_RTC_ALMB_SetMask() for ALARM B
- */
-
- uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
- for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
- */
-
- uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
- If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
- for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
-
- If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
- for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
- */
-} LL_RTC_AlarmTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
- * @{
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EC_FORMAT FORMAT
- * @{
- */
-#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
- * @{
- */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
- * @{
- */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RTC_ReadReg function
- * @{
- */
-#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
-#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
-#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
-#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
-#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
-#define LL_RTC_ISR_TSF RTC_ISR_TSF
-#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
-#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
-#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
-#define LL_RTC_ISR_INITF RTC_ISR_INITF
-#define LL_RTC_ISR_RSF RTC_ISR_RSF
-#define LL_RTC_ISR_INITS RTC_ISR_INITS
-#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
-#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
-#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
-#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
- * @{
- */
-#define LL_RTC_CR_TSIE RTC_CR_TSIE
-#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
-#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
-#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
-#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
- * @{
- */
-#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */
-#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
-#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */
-#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */
-#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */
-#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
-#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_MONTH MONTH
- * @{
- */
-#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */
-#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */
-#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */
-#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */
-#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */
-#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */
-#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */
-#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */
-#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */
-#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */
-#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */
-#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
- * @{
- */
-#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
-#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
- * @{
- */
-#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
-#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
-#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
-#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
- * @{
- */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
-#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_PIN PIN
- * @{
- */
-#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */
-#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */
-#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
- * @{
- */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
-#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
- * @{
- */
-#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
- * @{
- */
-#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
-#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
- * @{
- */
-#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
-#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
- * @{
- */
-#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
- * @{
- */
-#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
-#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
- * @{
- */
-#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
- * @{
- */
-#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
- * @{
- */
-#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER TAMPER
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
- * @{
- */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
-#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
- * @{
- */
-#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
- * @{
- */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
- * @{
- */
-#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
-/**
- * @}
- */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EC_BKP BACKUP
- * @{
- */
-#define LL_RTC_BKP_DR0 0x00000000U
-#define LL_RTC_BKP_DR1 0x00000001U
-#define LL_RTC_BKP_DR2 0x00000002U
-#define LL_RTC_BKP_DR3 0x00000003U
-#define LL_RTC_BKP_DR4 0x00000004U
-#if RTC_BKP_NUMBER > 5
-#define LL_RTC_BKP_DR5 0x00000005U
-#define LL_RTC_BKP_DR6 0x00000006U
-#define LL_RTC_BKP_DR7 0x00000007U
-#define LL_RTC_BKP_DR8 0x00000008U
-#define LL_RTC_BKP_DR9 0x00000009U
-#define LL_RTC_BKP_DR10 0x0000000AU
-#define LL_RTC_BKP_DR11 0x0000000BU
-#define LL_RTC_BKP_DR12 0x0000000CU
-#define LL_RTC_BKP_DR13 0x0000000DU
-#define LL_RTC_BKP_DR14 0x0000000EU
-#define LL_RTC_BKP_DR15 0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5 */
-
-#if RTC_BKP_NUMBER > 16
-#define LL_RTC_BKP_DR16 0x00000010U
-#define LL_RTC_BKP_DR17 0x00000011U
-#define LL_RTC_BKP_DR18 0x00000012U
-#define LL_RTC_BKP_DR19 0x00000013U
-#endif /* RTC_BKP_NUMBER > 16 */
-
-#if RTC_BKP_NUMBER > 20
-#define LL_RTC_BKP_DR20 0x00000014U
-#define LL_RTC_BKP_DR21 0x00000015U
-#define LL_RTC_BKP_DR22 0x00000016U
-#define LL_RTC_BKP_DR23 0x00000017U
-#define LL_RTC_BKP_DR24 0x00000018U
-#define LL_RTC_BKP_DR25 0x00000019U
-#define LL_RTC_BKP_DR26 0x0000001AU
-#define LL_RTC_BKP_DR27 0x0000001BU
-#define LL_RTC_BKP_DR28 0x0000001CU
-#define LL_RTC_BKP_DR29 0x0000001DU
-#define LL_RTC_BKP_DR30 0x0000001EU
-#define LL_RTC_BKP_DR31 0x0000001FU
-#endif /* RTC_BKP_NUMBER > 20 */
-/**
- * @}
- */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
- * @{
- */
-#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
-#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
- * @{
- */
-#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
-#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
- * @{
- */
-#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Convert Convert helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
- * @param __VALUE__ Byte to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
-
-/**
- * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
- * @param __VALUE__ BCD value to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Date Date helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to retrieve weekday.
- * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Year in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Year in BCD format (0x00 . . . 0x99)
- */
-#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Month in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Day in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Day in BCD format (0x01 . . . 0x31)
- */
-#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Time Time helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to retrieve hour in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
- */
-#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve minute in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Minutes in BCD format (0x00. . .0x59)
- */
-#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve second in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Seconds in format (0x00. . .0x59)
- */
-#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Set Hours format (24 hour/day or AM/PM hour format)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR FMT LL_RTC_SetHourFormat
- * @param RTCx RTC Instance
- * @param HourFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_HOURFORMAT_24HOUR
- * @arg @ref LL_RTC_HOURFORMAT_AMPM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
-}
-
-/**
- * @brief Get Hours format (24 hour/day or AM/PM hour format)
- * @rmtoll CR FMT LL_RTC_GetHourFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_HOURFORMAT_24HOUR
- * @arg @ref LL_RTC_HOURFORMAT_AMPM
- */
-__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
-}
-
-/**
- * @brief Select the flag to be routed to RTC_ALARM output
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent
- * @param RTCx RTC Instance
- * @param AlarmOutput This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALARMOUT_DISABLE
- * @arg @ref LL_RTC_ALARMOUT_ALMA
- * @arg @ref LL_RTC_ALARMOUT_ALMB
- * @arg @ref LL_RTC_ALARMOUT_WAKEUP
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
-}
-
-/**
- * @brief Get the flag to be routed to RTC_ALARM output
- * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALARMOUT_DISABLE
- * @arg @ref LL_RTC_ALARMOUT_ALMA
- * @arg @ref LL_RTC_ALARMOUT_ALMB
- * @arg @ref LL_RTC_ALARMOUT_WAKEUP
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
-}
-
-/**
- * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
- * @note Used only when RTC_ALARM is mapped on PC13
- * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
- * PC13 output data
- * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
- * @param RTCx RTC Instance
- * @param Output This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
-}
-
-/**
- * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
- * @note used only when RTC_ALARM is mapped on PC13
- * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
- * PC13 output data
- * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
-}
-
-/**
- * @brief Enable push-pull output on PC13, PC14 and/or PC15
- * @note PC13 forced to push-pull output if all RTC alternate functions are disabled
- * @note PC14 and PC15 forced to push-pull output if LSE is disabled
- * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
- * @param RTCx RTC Instance
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_PIN_PC13
- * @arg @ref LL_RTC_PIN_PC14
- * @arg @ref LL_RTC_PIN_PC15
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
-{
- SET_BIT(RTCx->TAFCR, PinMask);
-}
-
-/**
- * @brief Disable push-pull output on PC13, PC14 and/or PC15
- * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers.
- * Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
- * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n
- * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n
- * TAFCR PC15MODE LL_RTC_DisablePushPullMode
- * @param RTCx RTC Instance
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_PIN_PC13
- * @arg @ref LL_RTC_PIN_PC14
- * @arg @ref LL_RTC_PIN_PC15
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
-{
- CLEAR_BIT(RTCx->TAFCR, PinMask);
-}
-
-/**
- * @brief Set PC14 and/or PC15 to high level.
- * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
- * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n
- * TAFCR PC15VALUE LL_RTC_SetOutputPin
- * @param RTCx RTC Instance
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_PIN_PC14
- * @arg @ref LL_RTC_PIN_PC15
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
-{
- SET_BIT(RTCx->TAFCR, (PinMask >> 1));
-}
-
-/**
- * @brief Set PC14 and/or PC15 to low level.
- * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
- * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n
- * TAFCR PC15VALUE LL_RTC_ResetOutputPin
- * @param RTCx RTC Instance
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_PIN_PC14
- * @arg @ref LL_RTC_PIN_PC15
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
-{
- CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
-}
-
-/**
- * @brief Enable initialization mode
- * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
- * and prescaler register (RTC_PRER).
- * Counters are stopped and start counting from the new value when INIT is reset.
- * @rmtoll ISR INIT LL_RTC_EnableInitMode
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
-{
- /* Set the Initialization mode */
- WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
-}
-
-/**
- * @brief Disable initialization mode (Free running mode)
- * @rmtoll ISR INIT LL_RTC_DisableInitMode
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
-{
- /* Exit Initialization mode */
- WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
-}
-
-/**
- * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR POL LL_RTC_SetOutputPolarity
- * @param RTCx RTC Instance
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
-}
-
-/**
- * @brief Get Output polarity
- * @rmtoll CR POL LL_RTC_GetOutputPolarity
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
- */
-__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
-}
-
-/**
- * @brief Enable Bypass the shadow registers
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
- * @brief Disable Bypass the shadow registers
- * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
- * @brief Check if Shadow registers bypass is enabled or not.
- * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
-}
-
-/**
- * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR REFCKON LL_RTC_EnableRefClock
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
- * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR REFCKON LL_RTC_DisableRefClock
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
- * @brief Set Asynchronous prescaler factor
- * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler
- * @param RTCx RTC Instance
- * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
-{
- MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
- * @brief Set Synchronous prescaler factor
- * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler
- * @param RTCx RTC Instance
- * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
-{
- MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
-}
-
-/**
- * @brief Get Asynchronous prescaler factor
- * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0x7F
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
- * @brief Get Synchronous prescaler factor
- * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
- */
-__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
-}
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @rmtoll WPR KEY LL_RTC_EnableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
-}
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @rmtoll WPR KEY LL_RTC_DisableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Time Time
- * @{
- */
-
-/**
- * @brief Set time format (AM/24-hour or PM notation)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll TR PM LL_RTC_TIME_SetFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
-}
-
-/**
- * @brief Get time format (AM or PM notation)
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @rmtoll TR PM LL_RTC_TIME_GetFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
-}
-
-/**
- * @brief Set Hours in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
- * @rmtoll TR HT LL_RTC_TIME_SetHour\n
- * TR HU LL_RTC_TIME_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
-}
-
-/**
- * @brief Get Hours in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
- * Binary format
- * @rmtoll TR HT LL_RTC_TIME_GetHour\n
- * TR HU LL_RTC_TIME_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
- return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
-}
-
-/**
- * @brief Set Minutes in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n
- * TR MNU LL_RTC_TIME_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
- (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
-}
-
-/**
- * @brief Get Minutes in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
- * to Binary format
- * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n
- * TR MNU LL_RTC_TIME_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
- return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
-}
-
-/**
- * @brief Set Seconds in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll TR ST LL_RTC_TIME_SetSecond\n
- * TR SU LL_RTC_TIME_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
-}
-
-/**
- * @brief Get Seconds in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
- * to Binary format
- * @rmtoll TR ST LL_RTC_TIME_GetSecond\n
- * TR SU LL_RTC_TIME_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
-}
-
-/**
- * @brief Set time (hour, minute and second) in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note TimeFormat and Hours should follow the same format
- * @rmtoll TR PM LL_RTC_TIME_Config\n
- * TR HT LL_RTC_TIME_Config\n
- * TR HU LL_RTC_TIME_Config\n
- * TR MNT LL_RTC_TIME_Config\n
- * TR MNU LL_RTC_TIME_Config\n
- * TR ST LL_RTC_TIME_Config\n
- * TR SU LL_RTC_TIME_Config
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | \
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
- MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
-}
-
-/**
- * @brief Get time (hour, minute and second) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll TR HT LL_RTC_TIME_Get\n
- * TR HU LL_RTC_TIME_Get\n
- * TR MNT LL_RTC_TIME_Get\n
- * TR MNU LL_RTC_TIME_Get\n
- * TR ST LL_RTC_TIME_Get\n
- * TR SU LL_RTC_TIME_Get
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
- (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
- ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
-}
-
-/**
- * @brief Memorize whether the daylight saving time change has been performed
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
- * @brief Disable memorization whether the daylight saving time change has been performed.
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
- * @brief Check if RTC Day Light Saving stored operation has been enabled or not
- * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
-}
-
-/**
- * @brief Subtract 1 hour (winter time change)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR SUB1H LL_RTC_TIME_DecHour
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_SUB1H);
-}
-
-/**
- * @brief Add 1 hour (summer time change)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ADD1H LL_RTC_TIME_IncHour
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ADD1H);
-}
-
-/**
- * @brief Get Sub second value in the synchronous prescaler counter.
- * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
- * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
- * SubSeconds value in second fraction ratio with time unit following
- * generic formula:
- * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
- * This conversion can be performed only if no shift operation is pending
- * (ie. SHFP=0) when PREDIV_S >= SS.
- * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
- * @param RTCx RTC Instance
- * @retval Sub second value (number between 0 and 65535)
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
-}
-
-/**
- * @brief Synchronize to a remote clock with a high degree of precision.
- * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note When REFCKON is set, firmware must not write to Shift control register.
- * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
- * SHIFTR SUBFS LL_RTC_TIME_Synchronize
- * @param RTCx RTC Instance
- * @param ShiftSecond This parameter can be one of the following values:
- * @arg @ref LL_RTC_SHIFT_SECOND_DELAY
- * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
- * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
-{
- WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Date Date
- * @{
- */
-
-/**
- * @brief Set Year in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
- * @rmtoll DR YT LL_RTC_DATE_SetYear\n
- * DR YU LL_RTC_DATE_SetYear
- * @param RTCx RTC Instance
- * @param Year Value between Min_Data=0x00 and Max_Data=0x99
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
-}
-
-/**
- * @brief Get Year in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
- * @rmtoll DR YT LL_RTC_DATE_GetYear\n
- * DR YU LL_RTC_DATE_GetYear
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x99
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
-}
-
-/**
- * @brief Set Week day
- * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
-}
-
-/**
- * @brief Get Week day
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
-}
-
-/**
- * @brief Set Month in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
- * @rmtoll DR MT LL_RTC_DATE_SetMonth\n
- * DR MU LL_RTC_DATE_SetMonth
- * @param RTCx RTC Instance
- * @param Month This parameter can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
- (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
-}
-
-/**
- * @brief Get Month in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
- * @rmtoll DR MT LL_RTC_DATE_GetMonth\n
- * DR MU LL_RTC_DATE_GetMonth
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
- return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
-}
-
-/**
- * @brief Set Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll DR DT LL_RTC_DATE_SetDay\n
- * DR DU LL_RTC_DATE_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
-}
-
-/**
- * @brief Get Day in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll DR DT LL_RTC_DATE_GetDay\n
- * DR DU LL_RTC_DATE_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
- return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
-}
-
-/**
- * @brief Set date (WeekDay, Day, Month and Year) in BCD format
- * @rmtoll DR WDU LL_RTC_DATE_Config\n
- * DR MT LL_RTC_DATE_Config\n
- * DR MU LL_RTC_DATE_Config\n
- * DR DT LL_RTC_DATE_Config\n
- * DR DU LL_RTC_DATE_Config\n
- * DR YT LL_RTC_DATE_Config\n
- * DR YU LL_RTC_DATE_Config
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @param Month This parameter can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- * @param Year Value between Min_Data=0x00 and Max_Data=0x99
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
-{
- register uint32_t temp = 0U;
-
- temp = (WeekDay << RTC_DR_WDU_Pos) | \
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
- (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
-
- MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
-}
-
-/**
- * @brief Get date (WeekDay, Day, Month and Year) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
- * and __LL_RTC_GET_DAY are available to get independently each parameter.
- * @rmtoll DR WDU LL_RTC_DATE_Get\n
- * DR MT LL_RTC_DATE_Get\n
- * DR MU LL_RTC_DATE_Get\n
- * DR DT LL_RTC_DATE_Get\n
- * DR DU LL_RTC_DATE_Get\n
- * DR YT LL_RTC_DATE_Get\n
- * DR YU LL_RTC_DATE_Get
- * @param RTCx RTC Instance
- * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
- (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
- (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
- ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_ALARMA ALARMA
- * @{
- */
-
-/**
- * @brief Enable Alarm A
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAE LL_RTC_ALMA_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
- * @brief Disable Alarm A
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAE LL_RTC_ALMA_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
- * @brief Specify the Alarm A masks.
- * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK1 LL_RTC_ALMA_SetMask
- * @param RTCx RTC Instance
- * @param Mask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_ALMA_MASK_NONE
- * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMA_MASK_HOURS
- * @arg @ref LL_RTC_ALMA_MASK_MINUTES
- * @arg @ref LL_RTC_ALMA_MASK_SECONDS
- * @arg @ref LL_RTC_ALMA_MASK_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
-}
-
-/**
- * @brief Get the Alarm A masks.
- * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK1 LL_RTC_ALMA_GetMask
- * @param RTCx RTC Instance
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_RTC_ALMA_MASK_NONE
- * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMA_MASK_HOURS
- * @arg @ref LL_RTC_ALMA_MASK_MINUTES
- * @arg @ref LL_RTC_ALMA_MASK_SECONDS
- * @arg @ref LL_RTC_ALMA_MASK_ALL
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
-}
-
-/**
- * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
- * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
- * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
- * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
- * @brief Set ALARM A Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n
- * ALRMAR DU LL_RTC_ALMA_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
- (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n
- * ALRMAR DU LL_RTC_ALMA_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
- return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
-}
-
-/**
- * @brief Set ALARM A Weekday
- * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
-}
-
-/**
- * @brief Get ALARM A Weekday
- * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
- * @brief Set Alarm A time format (AM/24-hour or PM notation)
- * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
-}
-
-/**
- * @brief Get Alarm A time format (AM or PM notation)
- * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
-}
-
-/**
- * @brief Set ALARM A Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
- * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n
- * ALRMAR HU LL_RTC_ALMA_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
- (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n
- * ALRMAR HU LL_RTC_ALMA_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
- return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
-}
-
-/**
- * @brief Set ALARM A Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n
- * ALRMAR MNU LL_RTC_ALMA_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
- (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n
- * ALRMAR MNU LL_RTC_ALMA_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
- return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
-}
-
-/**
- * @brief Set ALARM A Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n
- * ALRMAR SU LL_RTC_ALMA_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n
- * ALRMAR SU LL_RTC_ALMA_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
-}
-
-/**
- * @brief Set Alarm A Time (hour, minute and second) in BCD format
- * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n
- * ALRMAR HT LL_RTC_ALMA_ConfigTime\n
- * ALRMAR HU LL_RTC_ALMA_ConfigTime\n
- * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
- * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
- * ALRMAR ST LL_RTC_ALMA_ConfigTime\n
- * ALRMAR SU LL_RTC_ALMA_ConfigTime
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
-
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
-}
-
-/**
- * @brief Get Alarm B Time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n
- * ALRMAR HU LL_RTC_ALMA_GetTime\n
- * ALRMAR MNT LL_RTC_ALMA_GetTime\n
- * ALRMAR MNU LL_RTC_ALMA_GetTime\n
- * ALRMAR ST LL_RTC_ALMA_GetTime\n
- * ALRMAR SU LL_RTC_ALMA_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
-}
-
-/**
- * @brief Set Alarm A Mask the most-significant bits starting at this bit
- * @note This register can be written only when ALRAE is reset in RTC_CR register,
- * or in initialization mode.
- * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
- * @param RTCx RTC Instance
- * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
- * @brief Get Alarm A Mask the most-significant bits starting at this bit
- * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
- * @brief Set Alarm A Sub seconds value
- * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
- * @param RTCx RTC Instance
- * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
- MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
-}
-
-/**
- * @brief Get Alarm A Sub seconds value
- * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_ALARMB ALARMB
- * @{
- */
-
-/**
- * @brief Enable Alarm B
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBE LL_RTC_ALMB_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
- * @brief Disable Alarm B
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBE LL_RTC_ALMB_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
- * @brief Specify the Alarm B masks.
- * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK1 LL_RTC_ALMB_SetMask
- * @param RTCx RTC Instance
- * @param Mask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_ALMB_MASK_NONE
- * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMB_MASK_HOURS
- * @arg @ref LL_RTC_ALMB_MASK_MINUTES
- * @arg @ref LL_RTC_ALMB_MASK_SECONDS
- * @arg @ref LL_RTC_ALMB_MASK_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
-}
-
-/**
- * @brief Get the Alarm B masks.
- * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK1 LL_RTC_ALMB_GetMask
- * @param RTCx RTC Instance
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_RTC_ALMB_MASK_NONE
- * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMB_MASK_HOURS
- * @arg @ref LL_RTC_ALMB_MASK_MINUTES
- * @arg @ref LL_RTC_ALMB_MASK_SECONDS
- * @arg @ref LL_RTC_ALMB_MASK_ALL
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
-}
-
-/**
- * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
- * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
- * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
- * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
- * @brief Set ALARM B Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n
- * ALRMBR DU LL_RTC_ALMB_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
- (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n
- * ALRMBR DU LL_RTC_ALMB_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
- return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
-}
-
-/**
- * @brief Set ALARM B Weekday
- * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
-}
-
-/**
- * @brief Get ALARM B Weekday
- * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
- * @brief Set ALARM B time format (AM/24-hour or PM notation)
- * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
-}
-
-/**
- * @brief Get ALARM B time format (AM or PM notation)
- * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
-}
-
-/**
- * @brief Set ALARM B Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
- * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n
- * ALRMBR HU LL_RTC_ALMB_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
- (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n
- * ALRMBR HU LL_RTC_ALMB_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
- return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
-}
-
-/**
- * @brief Set ALARM B Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n
- * ALRMBR MNU LL_RTC_ALMB_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
- (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n
- * ALRMBR MNU LL_RTC_ALMB_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
- return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
-}
-
-/**
- * @brief Set ALARM B Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n
- * ALRMBR SU LL_RTC_ALMB_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
- (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n
- * ALRMBR SU LL_RTC_ALMB_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
- return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
-}
-
-/**
- * @brief Set Alarm B Time (hour, minute and second) in BCD format
- * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n
- * ALRMBR HT LL_RTC_ALMB_ConfigTime\n
- * ALRMBR HU LL_RTC_ALMB_ConfigTime\n
- * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
- * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
- * ALRMBR ST LL_RTC_ALMB_ConfigTime\n
- * ALRMBR SU LL_RTC_ALMB_ConfigTime
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
-
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
-}
-
-/**
- * @brief Get Alarm B Time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n
- * ALRMBR HU LL_RTC_ALMB_GetTime\n
- * ALRMBR MNT LL_RTC_ALMB_GetTime\n
- * ALRMBR MNU LL_RTC_ALMB_GetTime\n
- * ALRMBR ST LL_RTC_ALMB_GetTime\n
- * ALRMBR SU LL_RTC_ALMB_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
-}
-
-/**
- * @brief Set Alarm B Mask the most-significant bits starting at this bit
- * @note This register can be written only when ALRBE is reset in RTC_CR register,
- * or in initialization mode.
- * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
- * @param RTCx RTC Instance
- * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
- * @brief Get Alarm B Mask the most-significant bits starting at this bit
- * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xF
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
- * @brief Set Alarm B Sub seconds value
- * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
- * @param RTCx RTC Instance
- * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
- MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
-}
-
-/**
- * @brief Get Alarm B Sub seconds value
- * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Timestamp Timestamp
- * @{
- */
-
-/**
- * @brief Enable Timestamp
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSE LL_RTC_TS_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
- * @brief Disable Timestamp
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSE LL_RTC_TS_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
- * @brief Set Time-stamp event active edge
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
- * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge
- * @param RTCx RTC Instance
- * @param Edge This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
-}
-
-/**
- * @brief Get Time-stamp event active edge
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
-}
-
-/**
- * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
- * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
- * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
-}
-
-/**
- * @brief Get Timestamp Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll TSTR HT LL_RTC_TS_GetHour\n
- * TSTR HU LL_RTC_TS_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
-}
-
-/**
- * @brief Get Timestamp Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n
- * TSTR MNU LL_RTC_TS_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
-}
-
-/**
- * @brief Get Timestamp Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n
- * TSTR SU LL_RTC_TS_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
- * @brief Get Timestamp time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll TSTR HT LL_RTC_TS_GetTime\n
- * TSTR HU LL_RTC_TS_GetTime\n
- * TSTR MNT LL_RTC_TS_GetTime\n
- * TSTR MNU LL_RTC_TS_GetTime\n
- * TSTR ST LL_RTC_TS_GetTime\n
- * TSTR SU LL_RTC_TS_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR,
- RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
- * @brief Get Timestamp Week day
- * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
-}
-
-/**
- * @brief Get Timestamp Month in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
- * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n
- * TSDR MU LL_RTC_TS_GetMonth
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
-}
-
-/**
- * @brief Get Timestamp Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll TSDR DT LL_RTC_TS_GetDay\n
- * TSDR DU LL_RTC_TS_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
- * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
- * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
- * and __LL_RTC_GET_DAY are available to get independently each parameter.
- * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n
- * TSDR MT LL_RTC_TS_GetDate\n
- * TSDR MU LL_RTC_TS_GetDate\n
- * TSDR DT LL_RTC_TS_GetDate\n
- * TSDR DU LL_RTC_TS_GetDate
- * @param RTCx RTC Instance
- * @retval Combination of Weekday, Day and Month
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
- * @brief Get time-stamp sub second value
- * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
-}
-
-#if defined(RTC_TAFCR_TAMPTS)
-/**
- * @brief Activate timestamp on tamper detection event
- * @rmtoll TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-
-/**
- * @brief Disable timestamp on tamper detection event
- * @rmtoll TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-#endif /* RTC_TAFCR_TAMPTS */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Tamper Tamper
- * @{
- */
-
-/**
- * @brief Enable RTC_TAMPx input detection
- * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Enable\n
- * TAFCR TAMP2E LL_RTC_TAMPER_Enable\n
- * TAFCR TAMP3E LL_RTC_TAMPER_Enable
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- * @arg @ref LL_RTC_TAMPER_2
- * @arg @ref LL_RTC_TAMPER_3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @brief Clear RTC_TAMPx input detection
- * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Disable\n
- * TAFCR TAMP2E LL_RTC_TAMPER_Disable\n
- * TAFCR TAMP3E LL_RTC_TAMPER_Disable
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- * @arg @ref LL_RTC_TAMPER_2
- * @arg @ref LL_RTC_TAMPER_3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-#if defined(RTC_TAFCR_TAMPPUDIS)
-/**
- * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
- * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-
-/**
- * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
- * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-#endif /* RTC_TAFCR_TAMPPUDIS */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/**
- * @brief Set RTC_TAMPx precharge duration
- * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
- * @param RTCx RTC Instance
- * @param Duration This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
-}
-
-/**
- * @brief Get RTC_TAMPx precharge duration
- * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
-}
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/**
- * @brief Set RTC_TAMPx filter count
- * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
- * @param RTCx RTC Instance
- * @param FilterCount This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
- * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
-}
-
-/**
- * @brief Get RTC_TAMPx filter count
- * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
- * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
-}
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/**
- * @brief Set Tamper sampling frequency
- * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
- * @param RTCx RTC Instance
- * @param SamplingFreq This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
-}
-
-/**
- * @brief Get Tamper sampling frequency
- * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
-}
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/**
- * @brief Enable Active level for Tamper input
- * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
- * TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n
- * TAFCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @brief Disable Active level for Tamper input
- * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
- * TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n
- * TAFCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @}
- */
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Wakeup Wakeup
- * @{
- */
-
-/**
- * @brief Enable Wakeup timer
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
- * @brief Disable Wakeup timer
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
- * @brief Check if Wakeup timer is enabled or not
- * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
-}
-
-/**
- * @brief Select Wakeup clock
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
- * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
- * @param RTCx RTC Instance
- * @param WakeupClock This parameter can be one of the following values:
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
-}
-
-/**
- * @brief Get Wakeup clock
- * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
-}
-
-/**
- * @brief Set Wakeup auto-reload value
- * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
- * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
- * @param RTCx RTC Instance
- * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
-{
- MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
-}
-
-/**
- * @brief Get Wakeup auto-reload value
- * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
-}
-
-/**
- * @}
- */
-#endif /* RTC_WAKEUP_SUPPORT */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister
- * @param RTCx RTC Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR0
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5 (*)
- * @arg @ref LL_RTC_BKP_DR6 (*)
- * @arg @ref LL_RTC_BKP_DR7 (*)
- * @arg @ref LL_RTC_BKP_DR8 (*)
- * @arg @ref LL_RTC_BKP_DR9 (*)
- * @arg @ref LL_RTC_BKP_DR10 (*)
- * @arg @ref LL_RTC_BKP_DR11 (*)
- * @arg @ref LL_RTC_BKP_DR12 (*)
- * @arg @ref LL_RTC_BKP_DR13 (*)
- * @arg @ref LL_RTC_BKP_DR14 (*)
- * @arg @ref LL_RTC_BKP_DR15 (*)
- * @arg @ref LL_RTC_BKP_DR16 (*)
- * @arg @ref LL_RTC_BKP_DR17 (*)
- * @arg @ref LL_RTC_BKP_DR18 (*)
- * @arg @ref LL_RTC_BKP_DR19 (*)
- * @arg @ref LL_RTC_BKP_DR20 (*)
- * @arg @ref LL_RTC_BKP_DR21 (*)
- * @arg @ref LL_RTC_BKP_DR22 (*)
- * @arg @ref LL_RTC_BKP_DR23 (*)
- * @arg @ref LL_RTC_BKP_DR24 (*)
- * @arg @ref LL_RTC_BKP_DR25 (*)
- * @arg @ref LL_RTC_BKP_DR26 (*)
- * @arg @ref LL_RTC_BKP_DR27 (*)
- * @arg @ref LL_RTC_BKP_DR28 (*)
- * @arg @ref LL_RTC_BKP_DR29 (*)
- * @arg @ref LL_RTC_BKP_DR30 (*)
- * @arg @ref LL_RTC_BKP_DR31 (*)
- *
- * (*) value not defined in all devices.
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister
- * @param RTCx RTC Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR0
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5 (*)
- * @arg @ref LL_RTC_BKP_DR6 (*)
- * @arg @ref LL_RTC_BKP_DR7 (*)
- * @arg @ref LL_RTC_BKP_DR8 (*)
- * @arg @ref LL_RTC_BKP_DR9 (*)
- * @arg @ref LL_RTC_BKP_DR10 (*)
- * @arg @ref LL_RTC_BKP_DR11 (*)
- * @arg @ref LL_RTC_BKP_DR12 (*)
- * @arg @ref LL_RTC_BKP_DR13 (*)
- * @arg @ref LL_RTC_BKP_DR14 (*)
- * @arg @ref LL_RTC_BKP_DR15 (*)
- * @arg @ref LL_RTC_BKP_DR16 (*)
- * @arg @ref LL_RTC_BKP_DR17 (*)
- * @arg @ref LL_RTC_BKP_DR18 (*)
- * @arg @ref LL_RTC_BKP_DR19 (*)
- * @arg @ref LL_RTC_BKP_DR20 (*)
- * @arg @ref LL_RTC_BKP_DR21 (*)
- * @arg @ref LL_RTC_BKP_DR22 (*)
- * @arg @ref LL_RTC_BKP_DR23 (*)
- * @arg @ref LL_RTC_BKP_DR24 (*)
- * @arg @ref LL_RTC_BKP_DR25 (*)
- * @arg @ref LL_RTC_BKP_DR26 (*)
- * @arg @ref LL_RTC_BKP_DR27 (*)
- * @arg @ref LL_RTC_BKP_DR28 (*)
- * @arg @ref LL_RTC_BKP_DR29 (*)
- * @arg @ref LL_RTC_BKP_DR30 (*)
- * @arg @ref LL_RTC_BKP_DR31 (*)
- *
- * (*) value not defined in all devices.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EF_Calibration Calibration
- * @{
- */
-
-/**
- * @brief Set Calibration output frequency (1 Hz or 512 Hz)
- * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n
- * CR COSEL LL_RTC_CAL_SetOutputFreq
- * @param RTCx RTC Instance
- * @param Frequency This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
- * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
-}
-
-/**
- * @brief Get Calibration output frequency (1 Hz or 512 Hz)
- * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n
- * CR COSEL LL_RTC_CAL_GetOutputFreq
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
- * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
-}
-
-/**
- * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
- * @rmtoll CALR CALP LL_RTC_CAL_SetPulse
- * @param RTCx RTC Instance
- * @param Pulse This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
- * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
-{
- MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
-}
-
-/**
- * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
- * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
-}
-
-/**
- * @brief Set the calibration cycle period
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
- * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
- * CALR CALW16 LL_RTC_CAL_SetPeriod
- * @param RTCx RTC Instance
- * @param Period This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
- * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
- * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
-{
- MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
-}
-
-/**
- * @brief Get the calibration cycle period
- * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
- * CALR CALW16 LL_RTC_CAL_GetPeriod
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
- * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
- * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
-}
-
-/**
- * @brief Set Calibration minus
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
- * @rmtoll CALR CALM LL_RTC_CAL_SetMinus
- * @param RTCx RTC Instance
- * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
-{
- MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
-}
-
-/**
- * @brief Get Calibration minus
- * @rmtoll CALR CALM LL_RTC_CAL_GetMinus
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Recalibration pending Flag
- * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
- * @brief Get RTC_TAMP3 detection flag
- * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
- * @brief Get RTC_TAMP2 detection flag
- * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
- * @brief Get RTC_TAMP1 detection flag
- * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
- * @brief Get Time-stamp overflow flag
- * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
-}
-
-/**
- * @brief Get Time-stamp flag
- * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
- * @brief Get Wakeup timer flag
- * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
- * @brief Get Alarm B flag
- * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
-}
-
-/**
- * @brief Get Alarm A flag
- * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
- * @brief Clear RTC_TAMP3 detection flag
- * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
- * @brief Clear RTC_TAMP2 detection flag
- * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
- * @brief Clear RTC_TAMP1 detection flag
- * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
- * @brief Clear Time-stamp overflow flag
- * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Time-stamp flag
- * @rmtoll ISR TSF LL_RTC_ClearFlag_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
- * @brief Clear Wakeup timer flag
- * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
- * @brief Clear Alarm B flag
- * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Alarm A flag
- * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Get Initialization flag
- * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
-}
-
-/**
- * @brief Get Registers synchronization flag
- * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
-}
-
-/**
- * @brief Clear Registers synchronization flag
- * @rmtoll ISR RSF LL_RTC_ClearFlag_RS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Get Initialization status flag
- * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
-}
-
-/**
- * @brief Get Shift operation pending flag
- * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
- * @brief Get Wakeup timer write flag
- * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
- * @brief Get Alarm B write flag
- * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
-}
-
-/**
- * @brief Get Alarm A write flag
- * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Time-stamp interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSIE LL_RTC_EnableIT_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-/**
- * @brief Disable Time-stamp interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSIE LL_RTC_DisableIT_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
- * @brief Enable Wakeup timer interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-
-/**
- * @brief Disable Wakeup timer interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
- * @brief Enable Alarm B interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
- * @brief Disable Alarm B interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
- * @brief Enable Alarm A interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
- * @brief Disable Alarm A interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
- * @brief Enable all Tamper Interrupt
- * @rmtoll TAFCR TAMPIE LL_RTC_EnableIT_TAMP
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
- * @brief Disable all Tamper Interrupt
- * @rmtoll TAFCR TAMPIE LL_RTC_DisableIT_TAMP
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
- * @brief Check if Time-stamp interrupt is enabled or not
- * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
- * @brief Check if Wakeup timer interrupt is enabled or not
- * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
- * @brief Check if Alarm B interrupt is enabled or not
- * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
-}
-
-/**
- * @brief Check if Alarm A interrupt is enabled or not
- * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
-}
-
-/**
- * @brief Check if all the TAMPER interrupts are enabled or not
- * @rmtoll TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->TAFCR,
- RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
-void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RTC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h
deleted file mode 100644
index a9641465cd0..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h
+++ /dev/null
@@ -1,2261 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_SPI_H
-#define __STM32F3xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
-
-/** @defgroup SPI_LL SPI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
- * @{
- */
-
-/**
- * @brief SPI Init structures definition
- */
-typedef struct
-{
- uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
- uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_LL_EC_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
- uint32_t DataWidth; /*!< Specifies the SPI data width.
- This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
- uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
- uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
- uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
- uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_SPI_ReadReg function
- * @{
- */
-#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
-#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
-#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
-#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
- * @{
- */
-#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
-#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
-#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
- * @{
- */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
- * @{
- */
-#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
- * @{
- */
-#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
-#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
-#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
- * @{
- */
-#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
-#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
-#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
-#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
-#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
-#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
-#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
-#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
-#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
-#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
-#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
-#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
-#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
-#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
- * @{
- */
-#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
- * @{
- */
-#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
-#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
- * @{
- */
-#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
-#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
- * @{
- */
-#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
-#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
-#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
-#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
- * @{
- */
-#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
-#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
-#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
-#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
- * @{
- */
-#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
-#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable SPI peripheral
- * @rmtoll CR1 SPE LL_SPI_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Disable SPI peripheral
- * @note When disabling the SPI, follow the procedure described in the Reference Manual.
- * @rmtoll CR1 SPE LL_SPI_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Check if SPI peripheral is enabled
- * @rmtoll CR1 SPE LL_SPI_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
-}
-
-/**
- * @brief Set SPI operation mode to Master or Slave
- * @note This bit should not be changed when communication is ongoing.
- * @rmtoll CR1 MSTR LL_SPI_SetMode\n
- * CR1 SSI LL_SPI_SetMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
- * @brief Get SPI operation mode (Master or Slave)
- * @rmtoll CR1 MSTR LL_SPI_GetMode\n
- * CR1 SSI LL_SPI_GetMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-/**
- * @brief Set serial protocol used
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR2 FRF LL_SPI_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
- * @brief Get serial protocol used
- * @rmtoll CR2 FRF LL_SPI_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-
-/**
- * @brief Set clock phase
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
- * @param SPIx SPI Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
- * @brief Get clock phase
- * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
- * @brief Set clock polarity
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Get clock polarity
- * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
- * @brief Set baud rate prescaler
- * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
- * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @param BaudRate This parameter can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
- * @brief Get baud rate prescaler
- * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
- * @brief Set transfer bit order
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
- * @param SPIx SPI Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
- * @brief Get transfer bit order
- * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
- * @brief Set transfer direction mode
- * @note For Half-Duplex mode, Rx Direction is set by default.
- * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
- * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
- * CR1 BIDIOE LL_SPI_SetTransferDirection
- * @param SPIx SPI Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
- * @brief Get transfer direction mode
- * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
- * CR1 BIDIOE LL_SPI_GetTransferDirection
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
- * @brief Set frame data width
- * @rmtoll CR2 DS LL_SPI_SetDataWidth
- * @param SPIx SPI Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_4BIT
- * @arg @ref LL_SPI_DATAWIDTH_5BIT
- * @arg @ref LL_SPI_DATAWIDTH_6BIT
- * @arg @ref LL_SPI_DATAWIDTH_7BIT
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_9BIT
- * @arg @ref LL_SPI_DATAWIDTH_10BIT
- * @arg @ref LL_SPI_DATAWIDTH_11BIT
- * @arg @ref LL_SPI_DATAWIDTH_12BIT
- * @arg @ref LL_SPI_DATAWIDTH_13BIT
- * @arg @ref LL_SPI_DATAWIDTH_14BIT
- * @arg @ref LL_SPI_DATAWIDTH_15BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
-}
-
-/**
- * @brief Get frame data width
- * @rmtoll CR2 DS LL_SPI_GetDataWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_4BIT
- * @arg @ref LL_SPI_DATAWIDTH_5BIT
- * @arg @ref LL_SPI_DATAWIDTH_6BIT
- * @arg @ref LL_SPI_DATAWIDTH_7BIT
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_9BIT
- * @arg @ref LL_SPI_DATAWIDTH_10BIT
- * @arg @ref LL_SPI_DATAWIDTH_11BIT
- * @arg @ref LL_SPI_DATAWIDTH_12BIT
- * @arg @ref LL_SPI_DATAWIDTH_13BIT
- * @arg @ref LL_SPI_DATAWIDTH_14BIT
- * @arg @ref LL_SPI_DATAWIDTH_15BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
-}
-
-/**
- * @brief Set threshold of RXFIFO that triggers an RXNE event
- * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
- * @param SPIx SPI Instance
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_TH_HALF
- * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
-}
-
-/**
- * @brief Get threshold of RXFIFO that triggers an RXNE event
- * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_TH_HALF
- * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
- * @{
- */
-
-/**
- * @brief Enable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Disable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Check if CRC is enabled
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
-}
-
-/**
- * @brief Set CRC Length
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
- * @param SPIx SPI Instance
- * @param CRCLength This parameter can be one of the following values:
- * @arg @ref LL_SPI_CRC_8BIT
- * @arg @ref LL_SPI_CRC_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
-}
-
-/**
- * @brief Get CRC Length
- * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_CRC_8BIT
- * @arg @ref LL_SPI_CRC_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
-}
-
-/**
- * @brief Set CRCNext to transfer CRC on the line
- * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
- * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
- * @brief Set polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
- * @param SPIx SPI Instance
- * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
- WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
- * @brief Get polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
- * @brief Get Rx CRC
- * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
- * @brief Get Tx CRC
- * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
- * @{
- */
-
-/**
- * @brief Set NSS mode
- * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
- * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
- * @param SPIx SPI Instance
- * @param NSS This parameter can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
- * @brief Get NSS mode
- * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
- register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
- return (Ssm | Ssoe);
-}
-
-/**
- * @brief Enable NSS pulse management
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
- * @brief Disable NSS pulse management
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
- * @brief Check if NSS pulse is enabled
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
-}
-
-/**
- * @brief Get CRC error flag
- * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
-}
-
-/**
- * @brief Get mode fault error flag
- * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
-}
-
-/**
- * @brief Get busy flag
- * @note The BSY flag is cleared under any one of the following conditions:
- * -When the SPI is correctly disabled
- * -When a fault is detected in Master mode (MODF bit set to 1)
- * -In Master mode, when it finishes a data transmission and no new data is ready to be
- * sent
- * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
- * each data transfer.
- * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
-}
-
-/**
- * @brief Get FIFO reception Level
- * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_RX_FIFO_EMPTY
- * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
- * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
- * @arg @ref LL_SPI_RX_FIFO_FULL
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
-}
-
-/**
- * @brief Get FIFO Transmission Level
- * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_TX_FIFO_EMPTY
- * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
- * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
- * @arg @ref LL_SPI_TX_FIFO_FULL
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
-}
-
-/**
- * @brief Clear CRC error flag
- * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
- * @brief Clear mode fault error flag
- * @note Clearing this flag is done by a read access to the SPIx_SR
- * register followed by a write access to the SPIx_CR1 register
- * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
-}
-
-/**
- * @brief Clear overrun error flag
- * @note Clearing this flag is done by a read access to the SPIx_DR
- * register followed by a read access to the SPIx_SR register
- * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->DR;
- (void) tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @note Clearing this flag is done by reading SPIx_SR register
- * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Enable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Enable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Disable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Disable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Check if error interrupt is enabled
- * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
-}
-
-/**
- * @brief Check if Rx buffer not empty interrupt is enabled
- * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
-}
-
-/**
- * @brief Check if Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
-}
-
-/**
- * @brief Set parity of Last DMA reception
- * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
- * @param SPIx SPI Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
-}
-
-/**
- * @brief Get parity configuration for Last DMA reception
- * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
-}
-
-/**
- * @brief Set parity of Last DMA transmission
- * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
- * @param SPIx SPI Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
-}
-
-/**
- * @brief Get parity configuration for Last DMA transmission
- * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DMA_PARITY_ODD
- * @arg @ref LL_SPI_DMA_PARITY_EVEN
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
- * @param SPIx SPI Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
- return (uint32_t) & (SPIx->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
- * @{
- */
-
-/**
- * @brief Read 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData8
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
- return (uint8_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Read 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Write 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData8
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
- *((__IO uint8_t *)&SPIx->DR) = TxData;
-}
-
-/**
- * @brief Write 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- *((__IO uint16_t *)&SPIx->DR) = TxData;
-}
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
- * @{
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_LL_EC_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
- This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
- Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
- and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
- uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2S_ReadReg function
- * @{
- */
-#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
-#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
-#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
- * @{
- */
-#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
-#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
- * @{
- */
-#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
-#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
-#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
-#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
-#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
-#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
- * @{
- */
-#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
- * @{
- */
-#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
- * @{
- */
-
-#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Select I2S mode and Enable I2S peripheral
- * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
- * I2SCFGR I2SE LL_I2S_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Disable I2S peripheral
- * @rmtoll I2SCFGR I2SE LL_I2S_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Check if I2S peripheral is enabled
- * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
-}
-
-/**
- * @brief Set I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_SetDataFormat
- * @param SPIx SPI Instance
- * @param DataFormat This parameter can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
- * @brief Get I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_GetDataFormat
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
- * @brief Set I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
- * @brief Get I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
- * @brief Set I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
- * @brief Get I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
- * @brief Set I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
- * @brief Get I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
- * @brief Set I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
- * @param SPIx SPI Instance
- * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
- * @brief Get I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
- * @param SPIx SPI Instance
- * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
- * @brief Set I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
- * @param SPIx SPI Instance
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
- * @brief Get I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
- * @brief Enable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Disable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Check if the master clock ouput (Pin MCK) is enabled
- * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
- * @brief Get busy flag
- * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
- * @brief Get underrun error flag
- * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-
-/**
- * @brief Get channel side flag.
- * @note 0: Channel Left has to be transmitted or has been received\n
- * 1: Channel Right has to be transmitted or has been received\n
- * It has no significance in PCM mode.
- * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
-}
-
-/**
- * @brief Clear overrun error flag
- * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
- * @brief Clear underrun error flag
- * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
- * @brief Enable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Enable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
- * @brief Disable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
- * @brief Disable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Disable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
- * @brief Check if ERR IT is enabled
- * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
- * @brief Check if RXNE IT is enabled
- * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
- * @brief Check if TXE IT is enabled
- * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
- * @{
- */
-
-/**
- * @brief Read 16-Bits in data register
- * @rmtoll DR DR LL_I2S_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
- * @brief Write 16-Bits in data register
- * @rmtoll DR DR LL_I2S_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h
deleted file mode 100644
index eaad3d3d4cb..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h
+++ /dev/null
@@ -1,1740 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_system.h
- * @author MCD Application Team
- * @brief Header file of SYSTEM LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL SYSTEM driver contains a set of generic APIs that can be
- used by user:
- (+) Some of the FLASH features need to be handled in the SYSTEM file.
- (+) Access to DBGCMU registers
- (+) Access to SYSCFG registers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_SYSTEM_H
-#define __STM32F3xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- * @{
- */
-
-/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
-#define SYSCFG_OFFSET_CFGR1 0x00000000U
-#define SYSCFG_OFFSET_CFGR3 0x00000050U
-
-/* Mask used for TIM breaks functions */
-#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
-#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
-#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
-#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
-#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
-#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
-#else
-#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
-#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- * @{
- */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
- * @{
- */
-#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
-#if defined(FMC_BANK1)
-#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
-}
-
-/**
- * @brief Get memory mapping at address 0x00000000
- * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_REMAP_FLASH
- * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
- * @arg @ref LL_SYSCFG_REMAP_SRAM
- * @arg @ref LL_SYSCFG_REMAP_FMC (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
- return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
-}
-
-#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
-/**
- * @brief Set DMA request remapping bits for SPI
- * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
- * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
- * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
- * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
- * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
- * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
- * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
-}
-#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
-
-#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
-/**
- * @brief Set DMA request remapping bits for I2C
- * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
- * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
- * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
- * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
- * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
- * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
- * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
-}
-#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
-
-#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
-/**
- * @brief Set DMA request remapping bits for ADC
- * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
- * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
- * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
- * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
- * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
- * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
- * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
-{
- __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
- MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
-}
-#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
-
-/**
- * @brief Set DMA request remapping bits for DAC
- * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
- * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
- * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
- * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
- * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
- * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
- * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
- * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
- * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
-}
-
-/**
- * @brief Set DMA request remapping bits for TIM
- * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
- * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
- * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
- * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
- * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
- * @param Remap This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
- * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
- * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
- * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
- * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
-}
-
-#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
-/**
- * @brief Set Timer input remap
- * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
- * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
- * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
- * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
- * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
- * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
- * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
-}
-#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
-
-#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
-/**
- * @brief Set ADC Trigger remap
- * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
- * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
- * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
- * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
- * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
- * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
- * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
- * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
- * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
- * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
- * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
- * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
- * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
- * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
- * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
- * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
- * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
- * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
- * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
- * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
- * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
- * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
- * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
- * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
- * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
- * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
- * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
- * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
- * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
-{
- MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
-}
-#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
-
-#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
-/**
- * @brief Set DAC Trigger remap
- * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
- * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
- * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
- * @param Remap This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
- * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
- * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
- * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
- * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
- * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
-{
- __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
- MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
-}
-#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
-
-#if defined(SYSCFG_CFGR1_USB_IT_RMP)
-/**
- * @brief Enable USB interrupt remap
- * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
- * respectively
- * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
-}
-
-/**
- * @brief Disable USB interrupt remap
- * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
-}
-#endif /* SYSCFG_CFGR1_USB_IT_RMP */
-
-#if defined(SYSCFG_CFGR1_VBAT)
-/**
- * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
- * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
-}
-
-/**
- * @brief Disable VBAT monitoring
- * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
-}
-#endif /* SYSCFG_CFGR1_VBAT */
-
-/**
- * @brief Enable the I2C fast mode plus driving capability.
- * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
- * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
- * @param ConfigFastModePlus This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
- SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-/**
- * @brief Disable the I2C fast mode plus driving capability.
- * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
- * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
- * @param ConfigFastModePlus This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
- * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
- CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-/**
- * @brief Enable Floating Point Unit Invalid operation Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
-}
-
-/**
- * @brief Enable Floating Point Unit Divide-by-zero Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
-}
-
-/**
- * @brief Enable Floating Point Unit Underflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
-}
-
-/**
- * @brief Enable Floating Point Unit Overflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
-}
-
-/**
- * @brief Enable Floating Point Unit Input denormal Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
-}
-
-/**
- * @brief Enable Floating Point Unit Inexact Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
-{
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
-}
-
-/**
- * @brief Disable Floating Point Unit Invalid operation Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
-}
-
-/**
- * @brief Disable Floating Point Unit Divide-by-zero Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
-}
-
-/**
- * @brief Disable Floating Point Unit Underflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
-}
-
-/**
- * @brief Disable Floating Point Unit Overflow Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
-}
-
-/**
- * @brief Disable Floating Point Unit Input denormal Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
-}
-
-/**
- * @brief Disable Floating Point Unit Inexact Interrupt
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
-{
- CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
-}
-
-/**
- * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
-}
-
-/**
- * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
-}
-
-/**
- * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
-}
-
-/**
- * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
-}
-
-/**
- * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
-}
-
-/**
- * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
- * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
-{
- return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
-}
-
-/**
- * @brief Configure source input for the EXTI external interrupt.
- * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
- * @param Port This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTF
- * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
- *
- * (*) value not defined in all devices.
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
- MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
-}
-
-/**
- * @brief Get the configured defined for specific EXTI Line
- * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTF
- * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
-}
-
-/**
- * @brief Set connections to TIMx Break inputs
- * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
- * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
- * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
- * @param Break This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
- * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
-{
- MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
-}
-
-/**
- * @brief Get connections to TIMx Break inputs
- * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
- * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
- * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
- * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
- *
- * (*) value not defined in all devices.
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
-{
- return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
-}
-
-#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
-/**
- * @brief Disable RAM Parity Check Disable
- * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
-{
- SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
-}
-#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
-
-#if defined(SYSCFG_CFGR2_SRAM_PE)
-/**
- * @brief Check if SRAM parity error detected
- * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
-{
- return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
-}
-
-/**
- * @brief Clear SRAM parity error flag
- * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
-{
- SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
-}
-#endif /* SYSCFG_CFGR2_SRAM_PE */
-
-#if defined(SYSCFG_RCR_PAGE0)
-/**
- * @brief Enable CCM SRAM page write protection
- * @note Write protection is cleared only by a system reset
- * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
- * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
- * @param PageWRP This parameter can be a combination of the following values:
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
- * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
-{
- SET_BIT(SYSCFG->RCR, PageWRP);
-}
-#endif /* SYSCFG_RCR_PAGE0 */
-
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- * @{
- */
-
-/**
- * @brief Return the device identifier
- * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
- * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
- * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
- * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
- * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
- * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
- * @brief Return the device revision identifier
- * @note This field indicates the revision of the device.
- * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Set Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- * @param PinAssignment This parameter can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
- * @brief Get Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
- * @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
- * @brief Freeze APB2 peripherals
- * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
- * @brief Unfreeze APB2 peripherals
- * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
- * @{
- */
-
-/**
- * @brief Set FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- * @param Latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
- * @brief Get FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
- * @brief Enable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
-}
-
-/**
- * @brief Disable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
-}
-
-/**
- * @brief Check if Prefetch buffer is enabled
- * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
-}
-
-#if defined(FLASH_ACR_HLFCYA)
-/**
- * @brief Enable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Disable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Check if Flash Half Cycle Access is enabled or not
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
-}
-#endif /* FLASH_ACR_HLFCYA */
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h
deleted file mode 100644
index 61ad5cb80da..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h
+++ /dev/null
@@ -1,4961 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_TIM_H
-#define __STM32F3xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
-
-/** @defgroup TIM_LL TIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
- * @{
- */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
- 0x00U, /* 0: TIMx_CH1 */
- 0x00U, /* 1: TIMx_CH1N */
- 0x00U, /* 2: TIMx_CH2 */
- 0x00U, /* 3: TIMx_CH2N */
- 0x04U, /* 4: TIMx_CH3 */
- 0x04U, /* 5: TIMx_CH3N */
- 0x04U, /* 6: TIMx_CH4 */
- 0x3CU, /* 7: TIMx_CH5 */
- 0x3CU /* 8: TIMx_CH6 */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
- 0U, /* 0: OC1M, OC1FE, OC1PE */
- 0U, /* 1: - NA */
- 8U, /* 2: OC2M, OC2FE, OC2PE */
- 0U, /* 3: - NA */
- 0U, /* 4: OC3M, OC3FE, OC3PE */
- 0U, /* 5: - NA */
- 8U, /* 6: OC4M, OC4FE, OC4PE */
- 0U, /* 7: OC5M, OC5FE, OC5PE */
- 8U /* 8: OC6M, OC6FE, OC6PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
- 0U, /* 0: CC1S, IC1PSC, IC1F */
- 0U, /* 1: - NA */
- 8U, /* 2: CC2S, IC2PSC, IC2F */
- 0U, /* 3: - NA */
- 0U, /* 4: CC3S, IC3PSC, IC3F */
- 0U, /* 5: - NA */
- 8U, /* 6: CC4S, IC4PSC, IC4F */
- 0U, /* 7: - NA */
- 0U /* 8: - NA */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
- 0U, /* 0: CC1P */
- 2U, /* 1: CC1NP */
- 4U, /* 2: CC2P */
- 6U, /* 3: CC2NP */
- 8U, /* 4: CC3P */
- 10U, /* 5: CC3NP */
- 12U, /* 6: CC4P */
- 16U, /* 7: CC5P */
- 20U /* 8: CC6P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
- 0U, /* 0: OIS1 */
- 1U, /* 1: OIS1N */
- 2U, /* 2: OIS2 */
- 3U, /* 3: OIS2N */
- 4U, /* 4: OIS3 */
- 5U, /* 5: OIS3N */
- 6U, /* 6: OIS4 */
- 8U, /* 7: OIS5 */
- 10U /* 8: OIS6 */
-};
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
- * @{
- */
-
-
-#define TIMx_OR_RMP_SHIFT 16U
-#define TIMx_OR_RMP_MASK 0x0000FFFFU
-#if defined(TIM1)
-#define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
-#endif /* TIM1 */
-#if defined (TIM8)
-#define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
-#endif /* TIM8 */
-#if defined(TIM14)
-#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
-#endif /* TIM14 */
-#if defined(TIM16)
-#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
-#endif /* TIM16 */
-#if defined(TIM20)
-#define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
-#endif /* TIM20 */
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7FU)
-#define DT_DELAY_2 ((uint8_t)0x3FU)
-#define DT_DELAY_3 ((uint8_t)0x1FU)
-#define DT_DELAY_4 ((uint8_t)0x1FU)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00U)
-#define DT_RANGE_2 ((uint8_t)0x80U)
-#define DT_RANGE_3 ((uint8_t)0xC0U)
-#define DT_RANGE_4 ((uint8_t)0xE0U)
-
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
- * @{
- */
-/** @brief Convert channel id into channel index.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @note CH5 and CH6 channels are not available for all F3 devices
- * @retval none
- */
-#if defined(TIM_CCR5_CCR5)
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
-#else
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
-#endif
-
-/** @brief Calculate the deadtime sampling period(in ps).
- * @param __TIMCLK__ timer input clock frequency (in Hz).
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval none
- */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- * @{
- */
-
-/**
- * @brief TIM Time Base configuration structure definition.
- */
-typedef struct
-{
- uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
-
- uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
-
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
- * @brief TIM Output Compare configuration structure definition.
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the output mode.
- This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
-
- uint32_t OCState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM Input Capture configuration structure definition.
- */
-
-typedef struct
-{
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t ICActiveInput; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
- * @brief TIM Encoder interface configuration structure definition.
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
- * @brief TIM Hall sensor interface configuration structure definition.
- */
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- Prescaler must be set to get a maximum counter period longer than the
- time interval between 2 consecutive changes on the Hall inputs.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
- A positive pulse (TRGO event) is generated with a programmable delay every time
- a change occurs on the Hall inputs.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
- * @brief BDTR (Break and Dead Time) structure definition
- */
-typedef struct
-{
- uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_LL_EC_OSSR
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OSSI
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
- has been written, their content is frozen until the next reset.*/
-
- uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
-
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
-
- uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
-#if defined(TIM_BDTR_BKF)
- uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
-#endif /* TIM_BDTR_BKF */
-#if defined(TIM_BDTR_BK2E)
- uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
- This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
- This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
-#endif /* TIM_BDTR_BK2E */
- uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- * @{
- */
-#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
-#if defined(TIM_CCMR1_OC1M_3)
-#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
-#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
-#endif /* TIM_CCMR1_OC1M_3 */
-#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
-#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
-#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- * @{
- */
-#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
-/**
- * @}
- */
-#if defined(TIM_BDTR_BK2E)
-
-/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
- * @{
- */
-#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
-#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
-/**
- * @}
- */
-#endif /* TIM_BDTR_BK2E */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- * @{
- */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
- * @{
- */
-#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- * @{
- */
-#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- * @{
- */
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- * @{
- */
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_USART_H
-#define __STM32F3xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @defgroup USART_LL USART
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
- * @{
- */
-
-/**
- * @brief LL USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
-
- uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_LL_EC_PARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
-
- uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
- uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
- This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
- * @brief LL USART Clock Init Structure definition
- */
-typedef struct
-{
- uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
- USART HW configuration can be modified afterwards using unitary functions
- @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
- For more details, refer to description of this function. */
-
- uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
- For more details, refer to description of this function. */
-
- uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_LL_EC_PHASE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
- For more details, refer to description of this function. */
-
- uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
- For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_USART_WriteReg function
- * @{
- */
-#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
-#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
-#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
-#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
-#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_USART_ReadReg function
- * @{
- */
-#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
-#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
-#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
-#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
-#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
-#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
-#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
-#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
-#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
-#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
- * @{
- */
-#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
-#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
-#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
-#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
- * @{
- */
-#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
- * @{
- */
-#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
- * @{
- */
-#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#if defined(USART_7BITS_SUPPORT)
-#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-#else
-#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-#endif
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
- * @{
- */
-#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
- * @{
- */
-
-#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
- * @{
- */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
- * @{
- */
-#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
- * @{
- */
-#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
- * @{
- */
-#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
- * @{
- */
-#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
- * @{
- */
-#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_BITORDER Bit Order
- * @{
- */
-#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
- * @{
- */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
-#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
-#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
-#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
- * @{
- */
-#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
- * @{
- */
-#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
- * @{
- */
-#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
-#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
- * @{
- */
-#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
- * @{
- */
-#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
- * @{
- */
-#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
-#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
- * @{
- */
-#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
- */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
- */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
- * @{
- */
-
-/**
- * @brief USART Enable
- * @rmtoll CR1 UE LL_USART_Enable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief USART Disable (all USART prescalers and outputs are disabled)
- * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
- * and current operations are discarded. The configuration of the USART is kept, but all the status
- * flags, in the USARTx_ISR are set to their default values.
- * @rmtoll CR1 UE LL_USART_Disable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief Indicate if USART is enabled
- * @rmtoll CR1 UE LL_USART_IsEnabled
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
-}
-
-/**
- * @brief USART enabled in STOP Mode.
- * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
- * USART clock selection is HSI or LSE in RCC.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR1 UESM LL_USART_EnableInStopMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief USART disabled in STOP Mode.
- * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR1 UESM LL_USART_DisableInStopMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
- * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
-}
-
-/**
- * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
- * @rmtoll CR1 RE LL_USART_EnableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Receiver Disable
- * @rmtoll CR1 RE LL_USART_DisableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Transmitter Enable
- * @rmtoll CR1 TE LL_USART_EnableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Transmitter Disable
- * @rmtoll CR1 TE LL_USART_DisableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Configure simultaneously enabled/disabled states
- * of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
- * CR1 TE LL_USART_SetTransferDirection
- * @param USARTx USART Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
- * @brief Return enabled/disabled states of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
- * CR1 TE LL_USART_GetTransferDirection
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
- * @brief Configure Parity (enabled/disabled and parity mode if enabled).
- * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
- * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
- * (9th or 8th bit depending on data width) and parity is checked on the received data.
- * @rmtoll CR1 PS LL_USART_SetParity\n
- * CR1 PCE LL_USART_SetParity
- * @param USARTx USART Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
- * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
- * @rmtoll CR1 PS LL_USART_GetParity\n
- * CR1 PCE LL_USART_GetParity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
- * @brief Set Receiver Wake Up method from Mute mode.
- * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
- * @param USARTx USART Instance
- * @param Method This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
- * @brief Return Receiver Wake Up method from Mute mode
- * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
- * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
- * CR1 M1 LL_USART_SetDataWidth
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B (*)
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- *
- * (*) Values not available on all devices
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
- * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
- * CR1 M1 LL_USART_GetDataWidth
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B (*)
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- *
- * (*) Values not available on all devices
- */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
- * @brief Allow switch between Mute Mode and Active mode
- * @rmtoll CR1 MME LL_USART_EnableMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
- * @rmtoll CR1 MME LL_USART_DisableMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
- * @brief Indicate if switch between Mute Mode and Active mode is allowed
- * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
-}
-
-/**
- * @brief Set Oversampling to 8-bit or 16-bit mode
- * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
- * @param USARTx USART Instance
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
- * @brief Return Oversampling mode
- * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
- * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
- * @param USARTx USART Instance
- * @param LastBitClockPulse This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
- * @brief Retrieve Clock pulse of the last data bit output configuration
- * (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
- * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_SetClockPhase
- * @param USARTx USART Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
- * @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_GetClockPhase
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
- * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
- * @param USARTx USART Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
- * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
- * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
- * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
- * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
- * CR2 CPOL LL_USART_ConfigClock\n
- * CR2 LBCL LL_USART_ConfigClock
- * @param USARTx USART Instance
- * @param Phase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @param LBCPOutput This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
- * @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
-}
-
-/**
- * @brief Set the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
- * @param USARTx USART Instance
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Retrieve the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
- * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
- * @note Call of this function is equivalent to following function call sequence :
- * - Data Width configuration using @ref LL_USART_SetDataWidth() function
- * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
- * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
- * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
- * CR1 PCE LL_USART_ConfigCharacter\n
- * CR1 M0 LL_USART_ConfigCharacter\n
- * CR1 M1 LL_USART_ConfigCharacter\n
- * CR2 STOP LL_USART_ConfigCharacter
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_7B (*)
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- *
- * (*) Values not available on all devices
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
- uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Configure TX/RX pins swapping setting.
- * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
- * @param USARTx USART Instance
- * @param SwapConfig This parameter can be one of the following values:
- * @arg @ref LL_USART_TXRX_STANDARD
- * @arg @ref LL_USART_TXRX_SWAPPED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
- * @brief Retrieve TX/RX pins swapping configuration.
- * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_TXRX_STANDARD
- * @arg @ref LL_USART_TXRX_SWAPPED
- */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
- * @brief Configure RX pin active level logic
- * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
- * @param USARTx USART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve RX pin active level logic configuration
- * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
- * @brief Configure TX pin active level logic
- * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
- * @param USARTx USART Instance
- * @param PinInvMethod This parameter can be one of the following values:
- * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
- * @brief Retrieve TX pin active level logic configuration
- * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
- * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
- */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
- * @brief Configure Binary data logic.
- * @note Allow to define how Logical data from the data register are send/received :
- * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
- * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
- * @param USARTx USART Instance
- * @param DataLogic This parameter can be one of the following values:
- * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
- * @brief Retrieve Binary data configuration
- * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
- * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
- */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
- * @brief Configure transfer bit order (either Less or Most Significant Bit First)
- * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
- * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
- * @param USARTx USART Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_USART_BITORDER_LSBFIRST
- * @arg @ref LL_USART_BITORDER_MSBFIRST
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
- * @brief Return transfer bit order (either Less or Most Significant Bit First)
- * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
- * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
- * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_BITORDER_LSBFIRST
- * @arg @ref LL_USART_BITORDER_MSBFIRST
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
- * @brief Enable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
- * @brief Disable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
- * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
-}
-
-/**
- * @brief Set Auto Baud-Rate mode bits
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
- * @param USARTx USART Instance
- * @param AutoBaudRateMode This parameter can be one of the following values:
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
-}
-
-/**
- * @brief Return Auto Baud-Rate mode
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
- * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
- */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
-}
-
-/**
- * @brief Enable Receiver Timeout
- * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
- * @brief Disable Receiver Timeout
- * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
- * @brief Indicate if Receiver Timeout feature is enabled
- * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
-}
-
-/**
- * @brief Set Address of the USART node.
- * @note This is used in multiprocessor communication during Mute mode or Stop mode,
- * for wake up with address mark detection.
- * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
- * (b7-b4 should be set to 0)
- * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
- * (This is used in multiprocessor communication during Mute mode or Stop mode,
- * for wake up with 7-bit address mark detection.
- * The MSB of the character sent by the transmitter should be equal to 1.
- * It may also be used for character detection during normal reception,
- * Mute mode inactive (for example, end of block detection in ModBus protocol).
- * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
- * value and CMF flag is set on match)
- * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
- * CR2 ADDM7 LL_USART_ConfigNodeAddress
- * @param USARTx USART Instance
- * @param AddressLen This parameter can be one of the following values:
- * @arg @ref LL_USART_ADDRESS_DETECT_4B
- * @arg @ref LL_USART_ADDRESS_DETECT_7B
- * @param NodeAddress 4 or 7 bit Address of the USART node.
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
- (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
- * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
- * @note If 4-bit Address Detection is selected in ADDM7,
- * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
- * If 7-bit Address Detection is selected in ADDM7,
- * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
- * @rmtoll CR2 ADD LL_USART_GetNodeAddress
- * @param USARTx USART Instance
- * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
- * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
- * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_ADDRESS_DETECT_4B
- * @arg @ref LL_USART_ADDRESS_DETECT_7B
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
- * @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
- * CR3 CTSE LL_USART_SetHWFlowCtrl
- * @param USARTx USART Instance
- * @param HardwareFlowControl This parameter can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
- * @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
- * CR3 CTSE LL_USART_GetHWFlowCtrl
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
- * @brief Enable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Disable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Indicate if One bit sampling method is enabled
- * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
-}
-
-/**
- * @brief Enable Overrun detection
- * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Disable Overrun detection
- * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Indicate if Overrun detection is enabled
- * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
-}
-
-/**
- * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR3 WUS LL_USART_SetWKUPType
- * @param USARTx USART Instance
- * @param Type This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_USART_WAKEUP_ON_RXNE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
- * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR3 WUS LL_USART_GetWKUPType
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
- * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
- * @arg @ref LL_USART_WAKEUP_ON_RXNE
- */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
-}
-
-/**
- * @brief Configure USART BRR register for achieving expected Baud Rate value.
- * @note Compute and set USARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
- * @note Peripheral clock and Baud rate values provided as function parameters should be valid
- * (Baud rate value != 0)
- * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
- * @rmtoll BRR BRR LL_USART_SetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
- uint32_t BaudRate)
-{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrtemp = 0x0U;
-
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- USARTx->BRR = brrtemp;
- }
- else
- {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
- }
-}
-
-/**
- * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
- * (full BRR content), and to used Peripheral Clock and Oversampling mode values
- * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
- * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
- * @rmtoll BRR BRR LL_USART_GetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrresult = 0x0U;
-
- usartdiv = USARTx->BRR;
-
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- if ((usartdiv & 0xFFF7U) != 0U)
- {
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
- brrresult = (PeriphClk * 2U) / usartdiv;
- }
- }
- else
- {
- if ((usartdiv & 0xFFFFU) != 0U)
- {
- brrresult = PeriphClk / usartdiv;
- }
- }
- return (brrresult);
-}
-
-/**
- * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
- * @rmtoll RTOR RTO LL_USART_SetRxTimeout
- * @param USARTx USART Instance
- * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
-{
- MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
-}
-
-/**
- * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
- * @rmtoll RTOR RTO LL_USART_GetRxTimeout
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
- */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
-}
-
-/**
- * @brief Set Block Length value in reception
- * @rmtoll RTOR BLEN LL_USART_SetBlockLength
- * @param USARTx USART Instance
- * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
-{
- MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
-}
-
-/**
- * @brief Get Block Length value in reception
- * @rmtoll RTOR BLEN LL_USART_GetBlockLength
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
- * @{
- */
-
-/**
- * @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_EnableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_DisableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
-}
-
-/**
- * @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
- * @param USARTx USART Instance
- * @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_IRDA_POWER_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
- * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
- * @brief Set Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
- * @param USARTx USART Instance
- * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
- * @{
- */
-
-/**
- * @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
-}
-
-/**
- * @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
-}
-
-/**
- * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
- * In transmission mode, it specifies the number of automatic retransmission retries, before
- * generating a transmission error (FE bit set).
- * In reception mode, it specifies the number or erroneous reception trials, before generating a
- * reception error (RXNE and PE bits set)
- * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
- * @param USARTx USART Instance
- * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
-}
-
-/**
- * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
- * @param USARTx USART Instance
- * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
-}
-
-/**
- * @brief Set Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
- * @param USARTx USART Instance
- * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
- * @param USARTx USART Instance
- * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
-}
-
-/**
- * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
- * @param USARTx USART Instance
- * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
- * @{
- */
-
-/**
- * @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
- * @{
- */
-
-/**
- * @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @param LINBDLength This parameter can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
- * @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
- * @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_EnableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_DisableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
- * @{
- */
-
-/**
- * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
- * @param USARTx USART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Return DEDT (Driver Enable De-Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
- * @param USARTx USART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
- */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
- * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
- * @param USARTx USART Instance
- * @param Time Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Return DEAT (Driver Enable Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
- * @param USARTx USART Instance
- * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
- */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
- * @brief Enable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_EnableDEMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Disable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_DisableDEMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
- * @brief Indicate if Driver Enable (DE) Mode is enabled
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
-}
-
-/**
- * @brief Select Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
- * @param USARTx USART Instance
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_DE_POLARITY_HIGH
- * @arg @ref LL_USART_DE_POLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
- * @brief Return Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
- * Driver Enable feature is supported by the USARTx instance.
- * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DE_POLARITY_HIGH
- * @arg @ref LL_USART_DE_POLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
- * @{
- */
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
- * @note In UART mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Asynchronous Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
- * CR2 CLKEN LL_USART_ConfigAsyncMode\n
- * CR3 SCEN LL_USART_ConfigAsyncMode\n
- * CR3 IREN LL_USART_ConfigAsyncMode\n
- * CR3 HDSEL LL_USART_ConfigAsyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
- /* In Asynchronous mode, the following bits must be kept cleared:
- - LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
- * @note In Synchronous mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * @note Other remaining configurations items related to Synchronous Mode
- * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
- * CR2 CLKEN LL_USART_ConfigSyncMode\n
- * CR3 SCEN LL_USART_ConfigSyncMode\n
- * CR3 IREN LL_USART_ConfigSyncMode\n
- * CR3 HDSEL LL_USART_ConfigSyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
- /* set the UART/USART in Synchronous mode */
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in LIN Mode
- * @note In LIN mode, the following bits must be kept cleared:
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
- * @note Other remaining configurations items related to LIN Mode
- * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
- * CR2 STOP LL_USART_ConfigLINMode\n
- * CR2 LINEN LL_USART_ConfigLINMode\n
- * CR3 IREN LL_USART_ConfigLINMode\n
- * CR3 SCEN LL_USART_ConfigLINMode\n
- * CR3 HDSEL LL_USART_ConfigLINMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
- /* In LIN mode, the following bits must be kept cleared:
- - STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
- /* Set the UART/USART in LIN mode */
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
- * @note In Half Duplex mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
- * @note Other remaining configurations items related to Half Duplex Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
- * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
- * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 IREN LL_USART_ConfigHalfDuplexMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
- /* In Half Duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
- /* set the UART/USART in Half Duplex mode */
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
- * @note In Smartcard mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also configures Stop bits to 1.5 bits and
- * sets the USART in Smartcard mode (SCEN bit).
- * Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
- * @note Other remaining configurations items related to Smartcard Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
- * CR2 STOP LL_USART_ConfigSmartcardMode\n
- * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
- * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
- * CR3 SCEN LL_USART_ConfigSmartcardMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
- /* In Smartcard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
- /* Configure Stop bits to 1.5 bits */
- /* Synchronous mode is activated by default */
- SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
- /* set the UART/USART in Smartcard mode */
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Irda Mode
- * @note In IRDA mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
- * @note Other remaining configurations items related to Irda Mode
- * (as Baud Rate, Word length, Power mode, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
- * CR2 CLKEN LL_USART_ConfigIrdaMode\n
- * CR2 STOP LL_USART_ConfigIrdaMode\n
- * CR3 SCEN LL_USART_ConfigIrdaMode\n
- * CR3 HDSEL LL_USART_ConfigIrdaMode\n
- * CR3 IREN LL_USART_ConfigIrdaMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
- /* set the UART/USART in IRDA mode */
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
- * (several USARTs connected in a network, one of the USARTs can be the master,
- * its TX output connected to the RX inputs of the other slaves USARTs).
- * @note In MultiProcessor mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Multi processor Mode
- * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
- * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
- * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
- * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
- * CR3 IREN LL_USART_ConfigMultiProcessMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
- /* In Multi Processor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if the USART Parity Error Flag is set or not
- * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
-}
-
-/**
- * @brief Check if the USART Framing Error Flag is set or not
- * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
-}
-
-/**
- * @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll ISR NF LL_USART_IsActiveFlag_NE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
-}
-
-/**
- * @brief Check if the USART OverRun Error Flag is set or not
- * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
-}
-
-/**
- * @brief Check if the USART IDLE line detected Flag is set or not
- * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
-}
-
-/**
- * @brief Check if the USART Read Data Register Not Empty Flag is set or not
- * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Flag is set or not
- * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
-}
-
-/**
- * @brief Check if the USART Transmit Data Register Empty Flag is set or not
- * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
-}
-
-/**
- * @brief Check if the USART CTS interrupt Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
-}
-
-/**
- * @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
-}
-
-/**
- * @brief Check if the USART Receiver Time Out Flag is set or not
- * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
-}
-
-/**
- * @brief Check if the USART End Of Block Flag is set or not
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
-}
-
-/**
- * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
-}
-
-/**
- * @brief Check if the USART Auto-Baud Rate Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
-}
-
-/**
- * @brief Check if the USART Busy Flag is set or not
- * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
-}
-
-/**
- * @brief Check if the USART Character Match Flag is set or not
- * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
-}
-
-/**
- * @brief Check if the USART Send Break Flag is set or not
- * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
-}
-
-/**
- * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
- * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
-}
-
-/**
- * @brief Check if the USART Wake Up from stop mode Flag is set or not
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
-}
-
-/**
- * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
- * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
-}
-
-/**
- * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
- * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
-}
-
-
-/**
- * @brief Clear Parity Error Flag
- * @rmtoll ICR PECF LL_USART_ClearFlag_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_PECF);
-}
-
-/**
- * @brief Clear Framing Error Flag
- * @rmtoll ICR FECF LL_USART_ClearFlag_FE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_FECF);
-}
-
-/**
- * @brief Clear Noise detected Flag
- * @rmtoll ICR NCF LL_USART_ClearFlag_NE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_NCF);
-}
-
-/**
- * @brief Clear OverRun Error Flag
- * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
- * @brief Clear IDLE line detected Flag
- * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
- * @brief Clear Transmission Complete Flag
- * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
-}
-
-
-/**
- * @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
-}
-
-/**
- * @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
- * @brief Clear Receiver Time Out Flag
- * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
-}
-
-/**
- * @brief Clear End Of Block Flag
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
-}
-
-/**
- * @brief Clear Character Match Flag
- * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
- * @brief Clear Wake Up from stop mode Flag
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Enable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Enable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Enable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Enable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Enable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Enable Receiver Timeout Interrupt
- * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
- * @brief Enable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
- * @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Enable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
- * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Enable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-
-/**
- * @brief Disable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Disable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Disable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Disable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Disable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Disable Character Match Interrupt
- * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
- * @brief Disable Receiver Timeout Interrupt
- * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
- * @brief Disable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
- * @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Disable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
- * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Disable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-
-/**
- * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
- * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
-}
-
-/**
- * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
- * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
-}
-
-/**
- * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
-}
-
-/**
- * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
- * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
-}
-
-/**
- * @brief Check if the USART Character Match Interrupt is enabled or disabled.
- * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
-}
-
-/**
- * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
- * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
-}
-
-/**
- * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
-}
-
-/**
- * @brief Check if the USART Error Interrupt is enabled or disabled.
- * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
-}
-
-/**
- * @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
-}
-
-/**
- * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
- * Wake-up from Stop mode feature is supported by the USARTx instance.
- * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
- * @{
- */
-
-/**
- * @brief Enable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Disable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for reception
- * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
-}
-
-/**
- * @brief Enable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Disable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for transmission
- * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
-}
-
-/**
- * @brief Enable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Disable DMA Disabling on Reception Error
- * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
- * @brief Indicate if DMA Disabling on Reception Error is disabled
- * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
- * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
- * @param USARTx USART Instance
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
- * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
-{
- register uint32_t data_reg_addr = 0U;
-
- if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
- {
- /* return address of TDR register */
- data_reg_addr = (uint32_t) &(USARTx->TDR);
- }
- else
- {
- /* return address of RDR register */
- data_reg_addr = (uint32_t) &(USARTx->RDR);
- }
-
- return data_reg_addr;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 8 bits)
- * @rmtoll RDR RDR LL_USART_ReceiveData8
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
- return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 9 bits)
- * @rmtoll RDR RDR LL_USART_ReceiveData9
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
- */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
- return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
- * @rmtoll TDR TDR LL_USART_TransmitData8
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
- USARTx->TDR = Value;
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
- * @rmtoll TDR TDR LL_USART_TransmitData9
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
- USARTx->TDR = Value & 0x1FFU;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Execution Execution
- * @{
- */
-
-/**
- * @brief Request an Automatic Baud Rate measurement on next received data frame
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
- * Auto Baud Rate detection feature is supported by the USARTx instance.
- * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
-}
-
-/**
- * @brief Request Break sending
- * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
-}
-
-/**
- * @brief Put USART in mute mode and set the RWU flag
- * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
-}
-
-/**
- * @brief Request a Receive Data flush
- * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
-}
-
-/**
- * @brief Request a Transmit data flush
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h
deleted file mode 100644
index 0d15f65ce6e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_utils.h
- * @author MCD Application Team
- * @brief Header file of UTILS LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL UTILS driver contains a set of generic APIs that can be
- used by user:
- (+) Device electronic signature
- (+) Timing functions
- (+) PLL configuration functions
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_UTILS_H
-#define __STM32F3xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/** @defgroup UTILS_LL UTILS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
- * @{
- */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY 0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
-
-/**
- * @brief Package data register base address
- */
-#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
- * @{
- */
-/**
- * @brief UTILS PLL structure definition
- */
-typedef struct
-{
- uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
- This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
- This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-#else
- uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
- This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
- * @brief UTILS System, AHB and APB buses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAHBPrescaler(). */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB1Prescaler(). */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
- * @{
- */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
- * @{
- */
-#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
-#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
- * @{
- */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
- * @{
- */
-
-/**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed in
- * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
- return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source of the time base.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @note When a RTOS is used, it is recommended to avoid changing the SysTick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
-}
-
-void LL_Init1msTick(uint32_t HCLKFrequency);
-void LL_mDelay(uint32_t Delay);
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
- * @{
- */
-
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_wwdg.h b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_wwdg.h
deleted file mode 100644
index df52fd187d0..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_wwdg.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG LL module.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_WWDG_H
-#define __STM32F3xx_LL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (WWDG)
-
-/** @defgroup WWDG_LL WWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-
-/** @defgroup WWDG_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
- * @{
- */
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
-#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
- * @{
- */
-/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
- * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
- * then it cannot be disabled again except by a reset.
- * This bit is set by software and only cleared by hardware after a reset.
- * When WDGA = 1, the watchdog can generate a reset.
- * @rmtoll CR WDGA LL_WWDG_Enable
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
-}
-
-/**
- * @brief Checks if Window Watchdog is enabled
- * @rmtoll CR WDGA LL_WWDG_IsEnabled
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
-}
-
-/**
- * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
- * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
- * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
- * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
- * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
- * @rmtoll CR T LL_WWDG_SetCounter
- * @param WWDGx WWDG Instance
- * @param Counter 0..0x7F (7 bit counter value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
-{
- MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
-}
-
-/**
- * @brief Return current Watchdog Counter Value (7 bits counter value)
- * @rmtoll CR T LL_WWDG_GetCounter
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Counter value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
-}
-
-/**
- * @brief Set the time base of the prescaler (WDGTB).
- * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
- * is decremented every (4096 x 2expWDGTB) PCLK cycles
- * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
- * @param WWDGx WWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
-}
-
-/**
- * @brief Return current Watchdog Prescaler Value
- * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
- * @param WWDGx WWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
-}
-
-/**
- * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
- * @note This window value defines when write in the WWDG_CR register
- * to program Watchdog counter is allowed.
- * Watchdog counter value update must occur only when the counter value
- * is lower than the Watchdog window register value.
- * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
- * (in the control register) is refreshed before the downcounter has reached
- * the watchdog window register value.
- * Physically is possible to set the Window lower then 0x40 but it is not recommended.
- * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
- * @rmtoll CFR W LL_WWDG_SetWindow
- * @param WWDGx WWDG Instance
- * @param Window 0x00..0x7F (7 bit Window value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
-}
-
-/**
- * @brief Return current Watchdog Window Value (7 bits value)
- * @rmtoll CFR W LL_WWDG_GetWindow
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Window value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-/**
- * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
- * @note This bit is set by hardware when the counter has reached the value 0x40.
- * It must be cleared by software by writing 0.
- * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
- * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
-}
-
-/**
- * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
- * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_IT_Management IT_Management
- * @{
- */
-/**
- * @brief Enable the Early Wakeup Interrupt.
- * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
- * This interrupt is only cleared by hardware after a reset
- * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
-}
-
-/**
- * @brief Check if Early Wakeup Interrupt is enabled
- * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* WWDG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html
deleted file mode 100644
index 496a79a1f9a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html
+++ /dev/null
@@ -1,1095 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
deleted file mode 100644
index 1c3eb9ed4fe..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal.c
- * @author MCD Application Team
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs categories:
- (+) HAL Initialization and de-initialization functions
- (+) HAL Control functions
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- *
-
-
-
-
-
-
-
|
-
© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver.
- * @{
- */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup HAL_Private Constants
- * @{
- */
-/**
- * @brief STM32F3xx HAL Driver version number V1.5.0
- */
-#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
-#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
-#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
- |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
- |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\
- |(__STM32F3xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK (0x00000FFFU)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-__IO uint32_t uwTick;
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initializes the Flash interface, the NVIC allocation and initial clock
- configuration. It initializes the source of time base also when timeout
- is needed and the backup domain when enabled.
- (+) de-Initializes common part of the HAL.
- (+) Configure The time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) Systick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general purpose
- timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
- handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called automatically
- at the beginning of the program after reset by HAL_Init() or at any time
- when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at regular
- time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher priority
- (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __Weak
- to make override possible in case of other implementations in user file.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function configures the Flash prefetch,
- * Configures time base source, NVIC and Low level hardware
- * @note This function is called at the beginning of program after reset and before
- * the clock configuration
- *
- * @note The Systick configuration is based on HSI clock, as HSI is the clock
- * used after a system Reset and the NVIC configuration is set to Priority group 4
- *
- * @note The time base configuration is based on MSI clock when exting from Reset.
- * Once done, time base tick start incrementing.
- * In the default implementation,Systick is used as source of time base.
- * The tick variable is incremented each 1ms in its ISR.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- /* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
-
- /* Init the low level hardware */
- HAL_MspInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function de-Initializes common part of the HAL and stops the source
- * of time base.
- * @note This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
- /* Reset of all peripherals */
- __HAL_RCC_APB1_FORCE_RESET();
- __HAL_RCC_APB1_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
- __HAL_RCC_AHB_FORCE_RESET();
- __HAL_RCC_AHB_RELEASE_RESET();
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals.
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __Weak to be overwritten in case of other
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- /*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(SystemCoreClock / 1000U);
-
- /*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
- (+) Enable/Disable Debug module during Sleep mode
- (+) Enable/Disable Debug module during STOP mode
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- uwTick++;
-}
-
-/**
- * @brief Povides a tick value in millisecond.
- * @note The function is declared as __Weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- return uwTick;
-}
-
-/**
- * @brief This function provides accurate delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals where uwTick
- * is incremented.
- * The function is declared as __Weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(__IO uint32_t Delay)
-{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a period to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait++;
- }
-
- while((HAL_GetTick() - tickstart) < wait)
- {
- }
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-
-{
- /* Disable SysTick Interrupt */
- SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * The function is declared as __Weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
-
-}
-
-/**
- * @brief This function returns the HAL revision
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32F3xx_HAL_VERSION;
-}
-
-/**
- * @brief Returns the device revision identifier.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void)
-{
- return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
- * @brief Returns the device identifier.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void)
-{
- return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Returns first word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw0(void)
-{
- return(READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
- * @brief Returns second word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw1(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
-}
-
-/**
- * @brief Returns third word of the unique device identifier (UID based on 96 bits)
- * @retval Device identifier
- */
-uint32_t HAL_GetUIDw2(void)
-{
- return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
deleted file mode 100644
index 14e733eafeb..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_adc.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Channels configuration on injected group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
- * Other functions (extended functions) are available in file
- * "stm32f3xx_hal_adc_ex.c".
- *
- @verbatim
- ==============================================================================
- ##### ADC peripheral features #####
- ==============================================================================
- [..]
- (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
- STM32F30xxC devices).
-
- (+) Interrupt generation at the end of regular conversion, end of injected
- conversion, and in case of analog watchdog or overrun events.
-
- (+) Single and continuous conversion modes.
-
- (+) Scan mode for conversion of several channels sequentially.
-
- (+) Data alignment with in-built data coherency.
-
- (+) Programmable sampling time (channel wise)
-
- (+) ADC conversion of regular group and injected group.
-
- (+) External trigger (timer or EXTI) with configurable polarity
- for both regular and injected groups.
-
- (+) DMA request generation for transfer of conversions data of regular group.
-
- (+) Multimode dual mode (available on devices with 2 ADCs or more).
-
- (+) Configurable DMA data storage in Multimode Dual mode (available on devices
- with 2 DCs or more).
-
- (+) Configurable delay between conversions in Dual interleaved mode (available
- on devices with 2 DCs or more).
-
- (+) ADC calibration
-
- (+) ADC channels selectable single/differential input (available only on
- STM32F30xxC devices)
-
- (+) ADC Injected sequencer&channels configuration context queue (available
- only on STM32F30xxC devices)
-
- (+) ADC offset on injected and regular groups (offset on regular group
- available only on STM32F30xxC devices)
-
- (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
- slower speed.
-
- (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
- Vdda or to an external voltage reference).
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- *** Configuration of top level parameters related to ADC ***
- ============================================================
- [..]
-
- (#) Enable the ADC interface
- (++) As prerequisite, ADC clock must be configured at RCC top level.
-
- (++) For STM32F30x/STM32F33x devices:
- Two possible clock sources: synchronous clock derived from AHB clock
- or asynchronous clock derived from ADC dedicated PLL 72MHz.
- - Synchronous clock is mandatory since used as ADC core clock.
- Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
- Synchronous clock is configured using macro __ADCx_CLK_ENABLE().
- - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
- Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig().
- (+++) For example, in case of device with a single ADC:
- Into HAL_ADC_MspInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) __HAL_RCC_ADC1_CLK_ENABLE() (mandatory)
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
- (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
-
- (+++) For example, in case of device with 4 ADCs:
-
- (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- (+++) {
- (+++) __HAL_RCC_ADC12_CLK_ENABLE() (mandatory)
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
- (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
- (+++) }
- (+++) else
- (+++) {
- (+++) __HAL_RCC_ADC34_CLK_ENABLE() (mandatory)
- (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure); (optional, if ADC conversion from asynchronous clock)
- (+++) }
-
- (++) For STM32F37x devices:
- One clock setting is mandatory:
- ADC clock (core and conversion clock) from APB2 clock.
- (+++) Example:
- Into HAL_ADC_MspInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Configure these ADC pins in analog mode
- using function HAL_GPIO_Init()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Configure the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding ADC interruption vector
- ADCx_IRQHandler().
-
- (#) Optionally, in case of usage of DMA:
- (++) Configure the DMA (DMA channel, mode normal or circular, ...)
- using function HAL_DMA_Init().
- (++) Configure the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding DMA interruption vector
- DMAx_Channelx_IRQHandler().
-
- *** Configuration of ADC, groups regular/injected, channels parameters ***
- ==========================================================================
- [..]
-
- (#) Configure the ADC parameters (resolution, data alignment, ...)
- and regular group parameters (conversion trigger, sequencer, ...)
- using function HAL_ADC_Init().
-
- (#) Configure the channels for regular group parameters (channel number,
- channel rank into sequencer, ..., into regular group)
- using function HAL_ADC_ConfigChannel().
-
- (#) Optionally, configure the injected group parameters (conversion trigger,
- sequencer, ..., of injected group)
- and the channels for injected group parameters (channel number,
- channel rank into sequencer, ..., into injected group)
- using function HAL_ADCEx_InjectedConfigChannel().
-
- (#) Optionally, configure the analog watchdog parameters (channels
- monitored, thresholds, ...)
- using function HAL_ADC_AnalogWDGConfig().
-
- (#) Optionally, for devices with several ADC instances: configure the
- multimode parameters
- using function HAL_ADCEx_MultiModeConfigChannel().
-
- *** Execution of ADC conversions ***
- ====================================
- [..]
-
- (#) Optionally, perform an automatic ADC calibration to improve the
- conversion accuracy
- using function HAL_ADCEx_Calibration_Start().
-
- (#) ADC driver can be used among three modes: polling, interruption,
- transfer by DMA.
-
- (++) ADC conversion by polling:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start()
- (+++) Wait for ADC conversion completion
- using function HAL_ADC_PollForConversion()
- (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (or for injected group: HAL_ADCEx_InjectedGetValue() )
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop()
-
- (++) ADC conversion by interruption:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_IT()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback()
- (this function must be implemented in user program)
- (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (or for injected group: HAL_ADCEx_InjectedGetValue() )
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_IT()
-
- (++) ADC conversion with transfer by DMA:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_DMA()
-
- (++) For devices with several ADCs: ADC multimode conversion
- with transfer by DMA:
- (+++) Activate the ADC peripheral (slave)
- using function HAL_ADC_Start()
- (conversion start pending ADC master)
- (+++) Activate the ADC peripheral (master) and start conversions
- using function HAL_ADCEx_MultiModeStart_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral (master)
- using function HAL_ADCEx_MultiModeStop_DMA()
- (+++) Stop conversion and disable the ADC peripheral (slave)
- using function HAL_ADC_Stop_IT()
-
- [..]
-
- (@) Callback functions must be implemented in user program:
- (+@) HAL_ADC_ErrorCallback()
- (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
- (+@) HAL_ADC_ConvCpltCallback()
- (+@) HAL_ADC_ConvHalfCpltCallback
- (+@) HAL_ADCEx_InjectedConvCpltCallback()
- (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices)
-
- *** Deinitialization of ADC ***
- ============================================================
- [..]
-
- (#) Disable the ADC interface
- (++) ADC clock can be hard reset and disabled at RCC top level.
- (++) Hard reset of ADC peripherals
- using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
- (++) ADC clock disable
- using the equivalent macro/functions as configuration step.
-
- (++) For STM32F30x/STM32F33x devices:
- Caution: For devices with several ADCs:
- These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4
- if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
-
- (+++) For example, in case of device with a single ADC:
- Into HAL_ADC_MspDeInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) __HAL_RCC_ADC1_FORCE_RESET() (optional)
- (+++) __HAL_RCC_ADC1_RELEASE_RESET() (optional)
- (+++) __HAL_RCC_ADC1_CLK_DISABLE() (mandatory)
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
- (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF (optional, if configured before)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
-
- (+++) For example, in case of device with 4 ADCs:
- (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
- (+++) {
- (+++) __HAL_RCC_ADC12_FORCE_RESET() (optional)
- (+++) __HAL_RCC_ADC12_RELEASE_RESET() (optional)
- (+++) __HAL_RCC_ADC12_CLK_DISABLE() (mandatory)
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
- (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF (optional, if configured before)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
- (+++) }
- (+++) else
- (+++) {
- (+++) __HAL_RCC_ADC32_FORCE_RESET() (optional)
- (+++) __HAL_RCC_ADC32_RELEASE_RESET() (optional)
- (+++) __HAL_RCC_ADC34_CLK_DISABLE() (mandatory)
- (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF (optional, if configured before)
- (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
- (+++) }
-
- (++) For STM32F37x devices:
- (+++) Example:
- Into HAL_ADC_MspDeInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
-
- (#) ADC pins configuration
- (++) Disable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Disable the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
- (#) Optionally, in case of usage of DMA:
- (++) Deinitialize the DMA
- using function HAL_DMA_Init().
- (++) Disable the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADC ADC
- * @brief ADC HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC.
- (+) De-initialize the ADC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * depending on both possible clock sources: PLL clock or AHB clock.
- * See commented example code below that can be copied and uncommented
- * into HAL_ADC_MspInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @note For devices with several ADCs: parameters related to common ADC
- * registers (ADC clock mode) are set only if all ADCs sharing the
- * same common group are disabled.
- * If this is not the case, these common parameters setting are
- * bypassed without error reporting: it can be the intended behaviour in
- * case of update of a parameter of ADC_InitTypeDef on the fly,
- * without disabling the other ADCs sharing the same common group.
- * @param hadc ADC handle
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Deinitialize the ADC peripheral registers to their default reset
- * values, with deinitialization of the ADC MSP.
- * @note For devices with several ADCs: reset of ADC common registers is done
- * only if all ADCs sharing the same common group are disabled.
- * If this is not the case, reset of these common parameters reset is
- * bypassed without error reporting: it can be the intended behaviour in
- * case of reset of a single ADC while the other ADCs sharing the same
- * common group is still running.
- * @note For devices with several ADCs: Global reset of all ADCs sharing a
- * common group is possible.
- * As this function is intended to reset a single ADC, to not impact
- * other ADCs, instructions for global reset of multiple ADCs have been
- * let commented below.
- * If needed, the example code can be copied and uncommented into
- * function HAL_ADC_MspDeInit().
- * @param hadc ADC handle
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Initializes the ADC MSP.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspInit must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitializes the ADC MSP.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspDeInit must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular group.
- (+) Stop conversion of regular group.
- (+) Poll for conversion complete on regular group.
- (+) Poll for conversion event.
- (+) Get result of regular channel conversion.
- (+) Start conversion of regular group and enable interruptions.
- (+) Stop conversion of regular group and disable interruptions.
- (+) Handle ADC interrupt request
- (+) Start conversion of regular group and enable DMA transfer.
- (+) Stop conversion of regular group and disable ADC DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables ADC, starts conversion of regular group.
- * Interruptions enabled in this function: None.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC slave first, then ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC master first, then ADC slave.
- * For ADC master, converson is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @param hadc ADC handle
- * @retval HAL status.
- */
-__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Wait for regular group conversion to be completed.
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- UNUSED(Timeout);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Poll for conversion event.
- * @param hadc ADC handle
- * @param EventType the ADC event type.
- * This parameter can be one of the following values:
- * @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
- * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
- * @arg ADC_OVR_EVENT: ADC Overrun event
- * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- UNUSED(EventType);
- UNUSED(Timeout);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Enables ADC, starts conversion of regular group with interruption.
- * Interruptions enabled in this function:
- * - EOC (end of conversion of regular group) or EOS (end of
- * sequence of regular group) depending on ADC initialization
- * parameter "EOCSelection" (if available)
- * - overrun (if available)
- * Each of these interruptions has its dedicated callback function.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC slave first, then ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable interruption of
- * end-of-conversion, disable ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC master first, then ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @param hadc ADC handle
- * @retval HAL status.
- */
-__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun (if available)
- * Each of these interruptions has its dedicated callback function.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function is for single-ADC mode only. For multimode, use the
- * dedicated MultimodeStart function.
- * @param hadc ADC handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- UNUSED(pData);
- UNUSED(Length);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note: Case of multimode enabled (for devices with several ADCs): This
- * function is for single-ADC mode only. For multimode, use the
- * dedicated MultimodeStop function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading DR register automatically clears EOC (end of conversion of
- * regular group) flag.
- * Additionally, this functions clears EOS (end of sequence of
- * regular group) flag, in case of the end of the sequence is reached.
- * @param hadc ADC handle
- * @retval Converted value
- */
-__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-
-/**
- * @brief Handles ADC interrupt request.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-}
-
-/**
- * @brief Conversion complete callback in non blocking mode
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Conversion DMA half-transfer callback in non blocking mode
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog callback in non blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief ADC error callback in non blocking mode
- * (ADC conversion with interruption or transfer by DMA)
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ErrorCallback must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on regular group
- (+) Configure the analog watchdog
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the the selected channel to be linked to the regular
- * group.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * The recommended sampling time is at least:
- * - For devices STM32F37x: 17.1us for temperature sensor
- * - For the other STM32F3 devices: 2.2us for each of channels
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into regular group, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_ChannelConfTypeDef".
- * @param hadc ADC handle
- * @param sConfig Structure of ADC channel for regular group.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- UNUSED(sConfig);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Configures the analog watchdog.
- * @note Possibility to update parameters on the fly:
- * This function initializes the selected analog watchdog, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_AnalogWDGConfTypeDef".
- * @param hadc ADC handle
- * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- UNUSED(AnalogWDGConfig);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_adc_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- * @brief ADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral state and errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions to get in run-time the status of the
- peripheral.
- (+) Check the ADC state
- (+) Check the ADC error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the ADC state
- * @note ADC state machine is managed by bitfield, state must be compared
- * with bit by bit.
- * For example:
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
- * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
- * @param hadc ADC handle
- * @retval HAL state
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Return ADC state */
- return hadc->State;
-}
-
-/**
- * @brief Return the ADC error code
- * @param hadc ADC handle
- * @retval ADC Error Code
- */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
- return hadc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
deleted file mode 100644
index cd93581c544..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
+++ /dev/null
@@ -1,7474 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_adc_ex.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of injected
- * group, using 2 possible modes: polling, interruption.
- * ++ Multimode feature (available on devices with 2 ADCs or more)
- * ++ Calibration (ADC automatic self-calibration)
- * + Control functions
- * ++ Channels configuration on injected group
- * Other functions (generic functions) are available in file
- * "stm32f3xx_hal_adc.c".
- *
- @verbatim
- [..]
- (@) Sections "ADC peripheral features" and "How to use this driver" are
- available in file of generic functions "stm32f3xx_hal_adc.c".
- [..]
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADCEx ADCEx
- * @brief ADC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
- /* Fixed timeout values for ADC calibration, enable settling time, disable */
- /* settling time. */
- /* Values defined to be higher than worst cases: low clock frequency, */
- /* maximum prescalers. */
- /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
- /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
- /* resolution 12 bits. */
- /* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT ( 10U)
- #define ADC_ENABLE_TIMEOUT ( 2U)
- #define ADC_DISABLE_TIMEOUT ( 2U)
- #define ADC_STOP_CONVERSION_TIMEOUT ( 11U)
-
- /* Timeout to wait for current conversion on going to be completed. */
- /* Timeout fixed to worst case, for 1 channel. */
- /* - maximum sampling time (601.5 adc_clk) */
- /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
- /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
- /* Unit: cycles of CPU clock. */
- #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U)
-
- /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
- /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
- /* Unit: us */
- #define ADC_STAB_DELAY_US ( 10U)
-
- /* Delay for temperature sensor stabilization time. */
- /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
- /* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ( 10U)
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
- /* Timeout values for ADC enable and disable settling time. */
- /* Values defined to be higher than worst cases: low clocks freq, */
- /* maximum prescaler. */
- /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
- /* Unit: ms */
- #define ADC_ENABLE_TIMEOUT ( 2U)
- #define ADC_DISABLE_TIMEOUT ( 2U)
-
- /* Delay for ADC calibration: */
- /* Hardware prerequisite before starting a calibration: the ADC must have */
- /* been in power-on state for at least two ADC clock cycles. */
- /* Unit: ADC clock cycles */
- #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
-
- /* Timeout value for ADC calibration */
- /* Value defined to be higher than worst cases: low clocks freq, */
- /* maximum prescaler. */
- /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
- /* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT ( 10U)
-
- /* Delay for ADC stabilization time. */
- /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
- /* Unit: us */
- #define ADC_STAB_DELAY_US ( 1U)
-
- /* Delay for temperature sensor stabilization time. */
- /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
- /* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ( 10U)
-
- /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
- /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
- /* minimum frequency */
- /* - AHB prescaler: 16 */
- /* - ADC prescaler: 8 */
- /* Unit: cycles of CPU clock. */
- #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
-
- /* ADC conversion cycles (unit: ADC clock cycles) */
- /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
- /* resolution 12 bits) */
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)
-#endif /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
-#endif /* STM32F373xC || STM32F378xx */
-
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
- * @{
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
- * @brief ADC Extended Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC.
- (+) De-initialize the ADC.
-
-@endverbatim
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Initializes the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * depending on possible clock sources: AHB clock or PLL clock.
- * See commented example code below that can be copied and uncommented
- * into HAL_ADC_MspInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned by ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @note For devices with several ADCs: parameters related to common ADC
- * registers (ADC clock mode) are set only if all ADCs sharing the
- * same common group are disabled.
- * If this is not the case, these common parameters setting are
- * bypassed without error reporting: it can be the intended behaviour in
- * case of update of a parameter of ADC_InitTypeDef on the fly,
- * without disabling the other ADCs sharing the same common group.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
- uint32_t tmpCFGR = 0U;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
- assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
- assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
- assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
- assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
- if(hadc->Init.DiscontinuousConvMode != DISABLE)
- {
- assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
- }
- }
-
- /* Configuration of ADC core parameters and ADC MSP related parameters */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
- /* at RCC top level. */
- /* Refer to header of this file for more details on clock enabling */
- /* procedure. */
-
- /* Actions performed only if ADC is coming from state reset: */
- /* - Initialization of ADC MSP */
- /* - ADC voltage regulator enable */
- if (hadc->State == HAL_ADC_STATE_RESET)
- {
- /* Initialize ADC error code */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Initialize HAL ADC API internal variables */
- hadc->InjectionConfig.ChannelCount = 0U;
- hadc->InjectionConfig.ContextQueue = 0U;
-
- /* Allocate lock resource and initialize it */
- hadc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
-
- /* Enable voltage regulator (if disabled at this step) */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
- {
- /* Note: The software must wait for the startup time of the ADC */
- /* voltage regulator before launching a calibration or */
- /* enabling the ADC. This temporization must be implemented by */
- /* software and is equal to 10 us in the worst case */
- /* process/temperature/power supply. */
-
- /* Disable the ADC (if not already disabled) */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- /* Configuration of ADC parameters if previous preliminary actions */
- /* are correctly completed. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- (tmp_hal_status == HAL_OK) )
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Set the intermediate state before moving the ADC voltage */
- /* regulator to state enable. */
- CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
- /* Set ADVREGEN bits to 0x01U */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
-
- /* Delay for ADC stabilization time. */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- }
- }
-
- /* Verification that ADC voltage regulator is correctly enabled, whether */
- /* or not ADC is coming from state reset (if any potential problem of */
- /* clocking, voltage regulator would not be enabled). */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
- HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed and if there is no conversion on going on regular */
- /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
- /* called to update a parameter on the fly). */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- (tmp_hal_status == HAL_OK) &&
- (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Configuration of common ADC parameters */
-
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* Set handle of the other ADC sharing the same common register */
- ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode clock configuration */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- ((tmphadcSharingSameCommonRegister.Instance == NULL) ||
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
- {
- /* Reset configuration of ADC common register CCR: */
- /* - ADC clock mode: CKMODE */
- /* Some parameters of this register are not reset, since they are set */
- /* by other functions and must be kept in case of usage of this */
- /* function on the fly (update of a parameter of ADC_InitTypeDef */
- /* without needing to reconfigure all other ADC groups/channels */
- /* parameters): */
- /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
- /* into HAL_ADCEx_MultiModeConfigChannel() ) */
- /* - internal measurement paths: Vbat, temperature sensor, Vref */
- /* (set into HAL_ADC_ConfigChannel() or */
- /* HAL_ADCEx_InjectedConfigChannel() ) */
-
- MODIFY_REG(tmpADC_Common->CCR ,
- ADC_CCR_CKMODE ,
- hadc->Init.ClockPrescaler );
- }
-
-
- /* Configuration of ADC: */
- /* - resolution */
- /* - data alignment */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
- /* - continuous conversion mode */
- /* - overrun */
- /* - discontinuous mode */
- SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
- ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
- hadc->Init.DataAlign |
- hadc->Init.Resolution );
-
- /* Enable discontinuous mode only if continuous mode is disabled */
- if (hadc->Init.DiscontinuousConvMode == ENABLE)
- {
- if (hadc->Init.ContinuousConvMode == DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- /* Set the number of channels to be converted in discontinuous mode */
- SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
- ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
- }
- else
- {
- /* ADC regular group discontinuous was intended to be enabled, */
- /* but ADC regular group modes continuous and sequencer discontinuous */
- /* cannot be enabled simultaneously. */
-
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
-
- /* Enable external trigger if trigger selection is different of software */
- /* start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
- {
- SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
- hadc->Init.ExternalTrigConvEdge );
- }
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - DMA continuous request */
- /* - LowPowerAutoWait feature */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
- ADC_CFGR_DMACFG );
-
- SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
- ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
- }
-
- /* Update ADC configuration register with previous settings */
- MODIFY_REG(hadc->Instance->CFGR,
- ADC_CFGR_DISCNUM |
- ADC_CFGR_DISCEN |
- ADC_CFGR_CONT |
- ADC_CFGR_OVRMOD |
- ADC_CFGR_EXTSEL |
- ADC_CFGR_EXTEN |
- ADC_CFGR_ALIGN |
- ADC_CFGR_RES ,
- tmpCFGR );
-
-
- /* Configuration of regular group sequencer: */
- /* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1U) */
- /* Parameter "NbrOfConversion" is discarded. */
- /* Note: Scan mode is not present by hardware on this device, but */
- /* emulated by software for alignment over all STM32 devices. */
- /* - if scan mode is enabled, regular channels sequence length is set to */
- /* parameter "NbrOfConversion" */
- if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
- {
- /* Set number of ranks in regular group sequencer */
- MODIFY_REG(hadc->Instance->SQR1 ,
- ADC_SQR1_L ,
- (hadc->Init.NbrOfConversion - (uint8_t)1U) );
- }
- else
- {
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
- }
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set the ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Initializes the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * (clock source APB2).
- * See commented example code below that can be copied and uncommented
- * into HAL_ADC_MspInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmp_cr1 = 0U;
- uint32_t tmp_cr2 = 0U;
- uint32_t tmp_sqr1 = 0U;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
- assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
- if(hadc->Init.DiscontinuousConvMode != DISABLE)
- {
- assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
- }
- }
-
- /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
- /* at RCC top level. */
- /* Refer to header of this file for more details on clock enabling */
- /* procedure. */
-
- /* Actions performed only if ADC is coming from state reset: */
- /* - Initialization of ADC MSP */
- if (hadc->State == HAL_ADC_STATE_RESET)
- {
- /* Initialize ADC error code */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Allocate lock resource and initialize it */
- hadc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
- }
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- /* Note: In case of ADC already enabled, precaution to not launch an */
- /* unwanted conversion while modifying register CR2 by writing 1 to */
- /* bit ADON. */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- (tmp_hal_status == HAL_OK) )
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Set ADC parameters */
-
- /* Configuration of ADC: */
- /* - data alignment */
- /* - external trigger to start conversion */
- /* - external trigger polarity (always set to 1U, because needed for all */
- /* triggers: external trigger of SW start) */
- /* - continuous conversion mode */
- /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
- /* HAL_ADC_Start_xxx functions because if set in this function, */
- /* a conversion on injected group would start a conversion also on */
- /* regular group after ADC enabling. */
- tmp_cr2 |= (hadc->Init.DataAlign |
- hadc->Init.ExternalTrigConv |
- ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
-
- /* Configuration of ADC: */
- /* - scan mode */
- /* - discontinuous mode disable/enable */
- /* - discontinuous mode number of conversions */
- tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
-
- /* Enable discontinuous mode only if continuous mode is disabled */
- /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
- /* discontinuous is set anyway, but will have no effect on ADC HW. */
- if (hadc->Init.DiscontinuousConvMode == ENABLE)
- {
- if (hadc->Init.ContinuousConvMode == DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- /* Set the number of channels to be converted in discontinuous mode */
- tmp_cr1 |= (ADC_CR1_DISCEN |
- ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
- }
- else
- {
- /* ADC regular group discontinuous was intended to be enabled, */
- /* but ADC regular group modes continuous and sequencer discontinuous */
- /* cannot be enabled simultaneously. */
-
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
-
- /* Update ADC configuration register CR1 with previous settings */
- MODIFY_REG(hadc->Instance->CR1,
- ADC_CR1_SCAN |
- ADC_CR1_DISCEN |
- ADC_CR1_DISCNUM ,
- tmp_cr1 );
-
- /* Update ADC configuration register CR2 with previous settings */
- MODIFY_REG(hadc->Instance->CR2,
- ADC_CR2_ALIGN |
- ADC_CR2_EXTSEL |
- ADC_CR2_EXTTRIG |
- ADC_CR2_CONT ,
- tmp_cr2 );
-
- /* Configuration of regular group sequencer: */
- /* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1U) */
- /* Parameter "NbrOfConversion" is discarded. */
- /* Note: Scan mode is present by hardware on this device and, if */
- /* disabled, discards automatically nb of conversions. Anyway, nb of */
- /* conversions is forced to 0x00 for alignment over all STM32 devices. */
- /* - if scan mode is enabled, regular channels sequence length is set to */
- /* parameter "NbrOfConversion" */
- if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
- {
- tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
- }
-
- MODIFY_REG(hadc->Instance->SQR1,
- ADC_SQR1_L ,
- tmp_sqr1 );
-
- /* Check back that ADC registers have effectively been configured to */
- /* ensure of no potential problem of ADC core IP clocking. */
- /* Check through register CR2 (excluding bits set in other functions: */
- /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
- /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
- /* measurement path bit (TSVREFE). */
- if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
- ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
- ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
- ADC_CR2_TSVREFE ))
- == tmp_cr2)
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set the ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Deinitialize the ADC peripheral registers to their default reset
- * values, with deinitialization of the ADC MSP.
- * @note For devices with several ADCs: reset of ADC common registers is done
- * only if all ADCs sharing the same common group are disabled.
- * If this is not the case, reset of these common parameters reset is
- * bypassed without error reporting: it can be the intended behaviour in
- * case of reset of a single ADC while the other ADCs sharing the same
- * common group is still running.
- * @note For devices with several ADCs: Global reset of all ADCs sharing a
- * common group is possible.
- * As this function is intended to reset a single ADC, to not impact
- * other ADCs, instructions for global reset of multiple ADCs have been
- * let commented below.
- * If needed, the example code can be copied and uncommented into
- * function HAL_ADC_MspDeInit().
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Stop potential conversion on going, on regular and injected groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Flush register JSQR: queue sequencer reset when injected queue */
- /* sequencer is enabled and ADC disabled. */
- /* Enable injected queue sequencer after injected conversion stop */
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
-
- /* Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
- }
- else
- {
- tmp_hal_status = HAL_ERROR;
- }
- }
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed. */
- if (tmp_hal_status == HAL_OK)
- {
- /* ========== Reset ADC registers ========== */
- /* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_JQOVF | ADC_IT_OVR |
- ADC_IT_JEOS | ADC_IT_JEOC |
- ADC_IT_EOS | ADC_IT_EOC |
- ADC_IT_EOSMP | ADC_IT_RDY ) );
-
- /* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_JQOVF | ADC_FLAG_OVR |
- ADC_FLAG_JEOS | ADC_FLAG_JEOC |
- ADC_FLAG_EOS | ADC_FLAG_EOC |
- ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
-
- /* Reset register CR */
- /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
- /* in access mode "read-set": no direct reset applicable. */
- /* Reset Calibration mode to default setting (single ended): */
- /* Disable voltage regulator: */
- /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
- /* already done above. */
- /* Note: Voltage regulator disable is intended for power saving. */
- /* Sequence to disable voltage regulator: */
- /* 1. Set the intermediate state before moving the ADC voltage regulator */
- /* to disable state. */
- CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
- /* 2. Set ADVREGEN bits to 0x10U */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
-
- /* Reset register CFGR */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
- ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
- ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
- ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
- ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
-
- /* Reset register SMPR1 */
- CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
- ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
- ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
-
- /* Reset register SMPR2 */
- CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
- ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
- ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
-
- /* Reset register TR1 */
- CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
-
- /* Reset register TR2 */
- CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
-
- /* Reset register TR3 */
- CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
- ADC_SQR1_SQ1 | ADC_SQR1_L);
-
- /* Reset register SQR2 */
- CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
- ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
-
- /* Reset register SQR3 */
- CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
- ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
-
- /* Reset register SQR4 */
- CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register OFR1 */
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
- /* Reset register OFR2 */
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
- /* Reset register OFR3 */
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
- /* Reset register OFR4 */
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset register AWD2CR */
- CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
-
- /* Reset register AWD3CR */
- CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
-
- /* Reset register DIFSEL */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
-
- /* Reset register CALFACT */
- CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
-
-
-
-
-
- /* ========== Reset common ADC registers ========== */
-
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* Set handle of the other ADC sharing the same common register */
- ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
-
- /* Software is allowed to change common parameters only when all ADCs of */
- /* the common group are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
- {
- /* Reset configuration of ADC common register CCR:
- - clock mode: CKMODE
- - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
- HAL_ADCEx_MultiModeConfigChannel() )
- - internal measurement paths: Vbat, temperature sensor, Vref (set into
- HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
- */
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
- ADC_CCR_VBATEN |
- ADC_CCR_TSEN |
- ADC_CCR_VREFEN |
- ADC_CCR_MDMA |
- ADC_CCR_DMACFG |
- ADC_CCR_DELAY |
- ADC_CCR_MULTI );
-
- /* Other ADC common registers (CSR, CDR) are in access mode read only,
- no direct reset applicable */
- }
-
-
- /* ========== Hard reset and clock disable of ADC peripheral ========== */
- /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */
- /* at RCC top level. */
- /* Refer to header of this file for more details on clock disabling */
- /* procedure. */
-
-
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Deinitialize the ADC peripheral registers to its default reset values.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed. */
- if (tmp_hal_status == HAL_OK)
- {
- /* ========== Reset ADC registers ========== */
- /* Reset register SR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
- ADC_FLAG_JSTRT | ADC_FLAG_STRT));
-
- /* Reset register CR1 */
- CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
- ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
- ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
- ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
-
- /* Reset register CR2 */
- CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
- ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
- ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
- ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
- ADC_CR2_ADON ));
-
- /* Reset register SMPR1 */
- CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
- ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
- ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
-
- /* Reset register SMPR2 */
- CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
- ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
- ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
- ADC_SMPR2_SMP0 ));
-
- /* Reset register JOFR1 */
- CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
- /* Reset register JOFR2 */
- CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
- /* Reset register JOFR3 */
- CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
- /* Reset register JOFR4 */
- CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
-
- /* Reset register HTR */
- CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
- /* Reset register LTR */
- CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
- ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
- ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
- ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
- ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
-
- /* Reset register SQR2 */
- CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
- ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
-
- /* Reset register SQR3 */
- CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
- ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
-
- /* Reset register JSQR */
- CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
- ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
-
- /* Reset register JSQR */
- CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
- ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset VBAT measurement path, in case of enabled before by selecting */
- /* channel ADC_CHANNEL_VBAT. */
- SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
-
-
- /* ========== Hard reset ADC peripheral ========== */
- /* Performs a global reset of the entire ADC peripheral: ADC state is */
- /* forced to a similar state after device power-on. */
- /* If needed, copy-paste and uncomment the following reset code into */
- /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
- /* */
- /* __HAL_RCC_ADC1_FORCE_RESET() */
- /* __HAL_RCC_ADC1_RELEASE_RESET() */
-
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
- * @brief ADC Extended IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular group.
- (+) Stop conversion of regular group.
- (+) Poll for conversion complete on regular group.
- (+) Poll for conversion event.
- (+) Get result of regular channel conversion.
- (+) Start conversion of regular group and enable interruptions.
- (+) Stop conversion of regular group and disable interruptions.
- (+) Handle ADC interrupt request
- (+) Start conversion of regular group and enable DMA transfer.
- (+) Stop conversion of regular group and disable ADC DMA transfer.
-
- (+) Start conversion of injected group.
- (+) Stop conversion of injected group.
- (+) Poll for conversion complete on injected group.
- (+) Get result of injected channel conversion.
- (+) Start conversion of injected group and enable interruptions.
- (+) Stop conversion of injected group and disable interruptions.
-
- (+) Start multimode and enable DMA transfer.
- (+) Stop multimode and disable ADC DMA transfer.
- (+) Get result of multimode conversion.
-
- (+) Perform the ADC self-calibration for single or differential ending.
- (+) Get calibration factors for single or differential ending.
- (+) Set calibration factors for single or differential ending.
-
-@endverbatim
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enables ADC, starts conversion of regular group.
- * Interruptions enabled in this function: None.
- * @note Case of multimode enabled (for devices with several ADCs):
- * if ADC is slave, ADC is enabled only (conversion is not started).
- * if ADC is master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular*/
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (for devices with several ADCs): */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enables ADC, starts conversion of regular group.
- * Interruptions enabled in this function: None.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) */
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Note: Alternate trigger for single conversion could be to force an */
- /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC conversion of both groups regular and injected,
- * disable ADC peripheral.
- * @note ADC peripheral disable is forcing interruption of potential
- * conversion on injected group. If injected group is under use,
- * it should be preliminarily stopped using function
- * @ref HAL_ADCEx_InjectedStop().
- * To stop ADC conversion only on ADC group regular
- * while letting ADC group injected conversions running,
- * use function @ref HAL_ADCEx_RegularStop().
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on regular and injected groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral.
- * @note ADC peripheral disable is forcing interruption of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Wait for regular group conversion to be completed.
- * @note ADC conversion flags EOS (end of sequence) and EOC (end of
- * conversion) are cleared by this function, with an exception:
- * if low power feature "LowPowerAutoWait" is enabled, flags are
- * not cleared to not interfere with this feature until data register
- * is read using function HAL_ADC_GetValue().
- * @note This function cannot be used in a particular setup: ADC configured
- * in DMA mode and polling for end of each conversion (ADC init
- * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
- * In this case, DMA resets the flag EOC and polling cannot be
- * performed on each conversion. Nevertheless, polling can still
- * be performed on the complete sequence (ADC init
- * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @note Depending on init parameter "EOCSelection", flags EOS or EOC is
- * checked and cleared depending on autodelay status (bit AUTDLY).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t tmp_Flag_EOC;
- ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmp_cfgr = 0x0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-/* If end of conversion selected to end of sequence */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- tmp_Flag_EOC = ADC_FLAG_EOS;
- }
- /* If end of conversion selected to end of each conversion */
- else /* ADC_EOC_SINGLE_CONV */
- {
- /* Verification that ADC configuration is compliant with polling for */
- /* each conversion: */
- /* Particular case is ADC configured in DMA mode and ADC sequencer with */
- /* several ranks and polling for end of each conversion. */
- /* For code simplicity sake, this particular case is generalized to */
- /* ADC configured in DMA mode and and polling for end of each conversion. */
-
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* Check DMA configuration, depending on MultiMode set or not */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
- {
- if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
- else
- {
- /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
-
- }
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
- if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait until End of Conversion or End of Sequence flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) )
- {
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
- {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
- /* ADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Change ADC state to error state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- }
-
- /* Clear end of conversion flag of regular group if low power feature */
- /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
- /* until data register is read using function HAL_ADC_GetValue(). */
- if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
- {
- /* Clear regular group conversion flag */
- /* (EOC or EOS depending on HAL ADC initialization parameter) */
- __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Wait for regular group conversion to be completed.
- * @note This function cannot be used in a particular setup: ADC configured
- * in DMA mode.
- * In this case, DMA resets the flag EOC and polling cannot be
- * performed on each conversion.
- * @note On STM32F37x devices, limitation in case of sequencer enabled
- * (several ranks selected): polling cannot be done on each
- * conversion inside the sequence. In this case, polling is replaced by
- * wait for maximum conversion time.
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Variables for polling in case of scan mode enabled */
- uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
- uint32_t Conversion_Timeout_CPU_cycles = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Verification that ADC configuration is compliant with polling for */
- /* each conversion: */
- /* Particular case is ADC configured in DMA mode */
- if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Polling for end of conversion: differentiation if single/sequence */
- /* conversion. */
- /* - If single conversion for regular group (Scan mode disabled or enabled */
- /* with NbrOfConversion =1U), flag EOC is used to determine the */
- /* conversion completion. */
- /* - If sequence conversion for regular group (scan mode enabled and */
- /* NbrOfConversion >=2U), flag EOC is set only at the end of the */
- /* sequence. */
- /* To poll for each conversion, the maximum conversion time is computed */
- /* from ADC conversion time (selected sampling time + conversion time of */
- /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
- /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
- /* As flag EOC is not set after each conversion, no timeout status can */
- /* be set. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
- HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
- {
- /* Wait until End of Conversion flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* Replace polling by wait for maximum conversion time */
- /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
- /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
- /* channels. */
- Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
- Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
-
- /* Poll with maximum conversion time */
- while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- Conversion_Timeout_CPU_cycles ++;
- }
- }
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F37x devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Poll for conversion event.
- * @param hadc ADC handle
- * @param EventType the ADC event type.
- * This parameter can be one of the following values:
- * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
- * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
- * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
- * @arg ADC_OVR_EVENT: ADC Overrun event
- * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- /* Get start tick count */
- tickstart = HAL_GetTick();
-
- /* Check selected event flag */
- while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
-
- switch(EventType)
- {
- /* Analog watchdog (level out of window) event */
- /* Note: In case of several analog watchdog enabled, if needed to know */
- /* which one triggered and on which ADCx, test ADC state of analog watchdog */
- /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */
- /* For example: */
- /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
- /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
- /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */
- /* Check analog watchdog 1 flag */
- case ADC_AWD_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
- break;
-
- /* Check analog watchdog 2 flag */
- case ADC_AWD2_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
- break;
-
- /* Check analog watchdog 3 flag */
- case ADC_AWD3_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
- break;
-
- /* Injected context queue overflow event */
- case ADC_JQOVF_EVENT:
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to Injected context queue overflow */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear ADC Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
- break;
-
- /* Overrun event */
- default: /* Case ADC_OVR_EVENT */
- /* If overrun is set to overwrite previous data, overrun event is not */
- /* considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and without */
- /* overrun ") */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to overrun */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- }
-
- /* Clear ADC Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- break;
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Poll for conversion event.
- * @param hadc ADC handle
- * @param EventType the ADC event type.
- * This parameter can be one of the following values:
- * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- tickstart = HAL_GetTick();
-
- /* Check selected event flag */
- while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Analog watchdog (level out of window) event */
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enables ADC, starts conversion of regular group with interruption.
- * Interruptions enabled in this function:
- * - EOC (end of conversion of regular group) or EOS (end of
- * sequence of regular group) depending on ADC initialization
- * parameter "EOCSelection"
- * - overrun, depending on ADC initialization parameter "Overrun"
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC slave first, then ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular*/
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable ADC end of conversion interrupt */
- /* Enable ADC overrun interrupt */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
- __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
- break;
- }
-
- /* If overrun is set to overwrite previous data (default setting), */
- /* overrun interrupt is not activated (overrun event is not considered */
- /* as an error). */
- /* (cf ref manual "Managing conversions without using the DMA and */
- /* without overrun ") */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- }
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (for devices with several ADCs): */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enables ADC, starts conversion of regular group with interruption.
- * Interruptions enabled in this function:
- * - EOC (end of conversion of regular group)
- * Each of these interruptions has its dedicated callback function.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) */
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable end of conversion interrupt for regular group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC conversion of both groups regular and injected,
- * disable ADC peripheral.
- * Interruptions disabled in this function:
- * - EOC (end of conversion of regular group) and EOS (end of
- * sequence of regular group)
- * - overrun
- * @note ADC peripheral disable is forcing interruption of potential
- * conversion on injected group. If injected group is under use,
- * it should be preliminarily stopped using function
- * @ref HAL_ADCEx_InjectedStop().
- * To stop ADC conversion only on ADC group regular
- * while letting ADC group injected conversions running,
- * use function @ref HAL_ADCEx_RegularStop_IT().
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on regular and injected groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for regular group */
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable interrution of
- * end-of-conversion, disable ADC peripheral.
- * @param hadc ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function is for single-ADC mode only. For multimode, use the
- * dedicated MultimodeStart function.
- * @param hadc ADC handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Verification if multimode is disabled (for devices with several ADC) */
- /* If multimode is enabled, dedicated function multimode conversion */
- /* start DMA must be used. */
- if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
- {
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected,*/
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular*/
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Enable ADC DMA mode */
- SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately.*/
- /* If external trigger has been selected, conversion will start at */
- /* next trigger event. */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * Each of these interruptions has its dedicated callback function.
- * @note For devices with several ADCs: This function is for single-ADC mode
- * only. For multimode, use the dedicated MultimodeStart function.
- * @param hadc ADC handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) */
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable ADC DMA mode */
- hadc->Instance->CR2 |= ADC_CR2_DMA;
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Note: Alternate trigger for single conversion could be to force an */
- /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC conversion of both groups regular and injected,
- * disable ADC DMA transfer, disable ADC peripheral.
- * Interruptions disabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * @note ADC peripheral disable is forcing interruption of potential
- * conversion on injected group. If injected group is under use,
- * it should be preliminarily stopped using function
- * @ref HAL_ADCEx_InjectedStop().
- * To stop ADC conversion only on ADC group regular
- * while letting ADC group injected conversions running,
- * use function @ref HAL_ADCEx_RegularStop_DMA().
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function is for single-ADC mode only. For multimode, use the
- * dedicated MultimodeStop function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential conversion on going, on regular and injected groups */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to retain a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Disable(hadc);
- }
- else
- {
- ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note ADC peripheral disable is forcing interruption of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note For devices with several ADCs: This function is for single-ADC mode
- * only. For multimode, use the dedicated MultimodeStop function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC DMA mode */
- hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading register DR automatically clears ADC flag EOC
- * (ADC group regular end of unitary conversion).
- * @note This function does not clear ADC flag EOS
- * (ADC group regular end of sequence conversion).
- * Occurrence of flag EOS rising:
- * - If sequencer is composed of 1 rank, flag EOS is equivalent
- * to flag EOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag EOC only is raised, at the end of the scan sequence
- * both flags EOC and EOS are raised.
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADC_PollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc ADC handle
- * @retval ADC group regular conversion data
- */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: ADC flag EOC is not cleared here by software because */
- /* automatically cleared by hardware when reading register DR. */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading register DR automatically clears ADC flag EOC
- * (ADC group regular end of unitary conversion).
- * @note This function does not clear ADC flag EOS
- * (ADC group regular end of sequence conversion).
- * Occurrence of flag EOS rising:
- * - If sequencer is composed of 1 rank, flag EOS is equivalent
- * to flag EOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag EOC only is raised, at the end of the scan sequence
- * both flags EOC and EOS are raised.
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADC_PollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc ADC handle
- * @retval ADC group regular conversion data
- */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: EOC flag is not cleared here by software because automatically */
- /* cleared by hardware when reading register DR. */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Handles ADC interrupt request.
- * @param hadc ADC handle
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
- ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmp_cfgr = 0x0U;
- uint32_t tmp_cfgr_jqm = 0x0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-
- /* ========== Check End of Conversion flag for regular group ========== */
- if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
- (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- }
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
- if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
- {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
- }
-
- /* Disable interruption if no further conversion upcoming by regular */
- /* external trigger or by continuous mode, */
- /* and if scan sequence if completed. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
- {
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
- {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
- /* ADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Disable ADC end of sequence conversion interrupt */
- /* Note: Overrun interrupt was enabled with EOC interrupt in */
- /* HAL_Start_IT(), but is not disabled here because can be used */
- /* by overrun IRQ process below. */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- }
-
- /* Conversion complete callback */
- /* Note: into callback, to determine if conversion has been triggered */
- /* from EOC or EOS, possibility to use: */
- /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
- HAL_ADC_ConvCpltCallback(hadc);
-
-
- /* Clear regular group conversion flag */
- /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
- /* conversion flags clear induces the release of the preserved */
- /* data. */
- /* Therefore, if the preserved data value is needed, it must be */
- /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
- }
-
-
- /* ========== Check End of Conversion flag for injected group ========== */
- if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
- (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) )
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
- if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
- {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
- }
-
- /* Disable interruption if no further conversion upcoming by injected */
- /* external trigger or by automatic injected conversion with regular */
- /* group having no further conversion upcoming (same conditions as */
- /* regular group interruption disabling above), */
- /* and if injected scan sequence is completed. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
- {
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
- {
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
- if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
- {
- tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
- }
-
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
- {
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
- }
- }
-
- /* Conversion complete callback */
- /* Note: into callback, to determine if conversion has been triggered */
- /* from JEOC or JEOS, possibility to use: */
- /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
-
- /* Clear injected group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
- }
-
- /* ========== Check analog watchdog 1 flag ========== */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Level out of window 1 callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
- }
-
- /* ========== Check analog watchdog 2 flag ========== */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
-
- /* Level out of window 2 callback */
- HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
- }
-
- /* ========== Check analog watchdog 3 flag ========== */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
-
- /* Level out of window 3 callback */
- HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
- }
-
- /* ========== Check Overrun flag ========== */
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
- {
- /* If overrun is set to overwrite previous data (default setting), */
- /* overrun event is not considered as an error. */
- /* (cf ref manual "Managing conversions without using the DMA and */
- /* without overrun ") */
- /* Exception for usage with DMA overrun event always considered as an */
- /* error. */
- if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
- {
- overrun_error = 1U;
- }
- else
- {
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* Check DMA configuration, depending on MultiMode set or not */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
- {
- if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
- {
- overrun_error = 1U;
- }
- }
- else
- {
- /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
- if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
- {
- overrun_error = 1U;
- }
- }
- }
-
- if (overrun_error == 1U)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
- }
-
- /* Clear the Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-
- }
-
-
- /* ========== Check Injected context queue overflow flag ========== */
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
-
- /* Clear the Injected context queue overflow flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
-
- /* Error callback */
- HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
- }
-
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Handles ADC interrupt request
- * @param hadc ADC handle
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-
-
- /* ========== Check End of Conversion flag for regular group ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- }
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F37x devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Disable ADC end of single conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
- }
- }
-
- /* ========== Check End of Conversion flag for injected group ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
- }
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger, scan sequence on going or by automatic injected */
- /* conversion from group regular (same conditions as group regular */
- /* interruption disabling above). */
- /* Note: On STM32F37x devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
- {
- /* Disable ADC end of single conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
-
- /* Clear injected group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
- }
- }
-
- /* ========== Check Analog watchdog flags ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Level out of window callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
-
- /* Clear the ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
- }
- }
-
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Perform an ADC automatic self-calibration
- * Calibration prerequisite: ADC must be disabled (execute this
- * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * @param hadc ADC handle
- * @param SingleDiff Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
- * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Calibration prerequisite: ADC must be disabled. */
-
- /* Disable the ADC (if not already disabled) */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
-
- /* Select calibration mode single ended or differential ended */
- hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
- if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
- {
- hadc->Instance->CR |= ADC_CR_ADCALDIF;
- }
-
- /* Start ADC calibration */
- hadc->Instance->CR |= ADC_CR_ADCAL;
-
- tickstart = HAL_GetTick();
-
- /* Wait for calibration completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
- {
- if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Perform an ADC automatic self-calibration
- * Calibration prerequisite: ADC must be disabled (execute this
- * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * During calibration process, ADC is enabled. ADC is let enabled at
- * the completion of this function.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Calibration prerequisite: */
- /* - ADC must be disabled for at least two ADC clock cycles in disable */
- /* mode before ADC enable */
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Wait two ADC clock cycles */
- while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U)
- {
- wait_loop_index++;
- }
-
- /* 2. Enable the ADC peripheral */
- ADC_Enable(hadc);
-
-
- /* 3. Resets ADC calibration registers */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
-
- tickstart = HAL_GetTick();
-
- /* Wait for calibration reset completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
- {
- if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
-
- /* 4. Start ADC calibration */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
-
- tickstart = HAL_GetTick();
-
- /* Wait for calibration completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
- {
- if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Get the calibration factor from automatic conversion result
- * @param hadc ADC handle
- * @param SingleDiff Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
- * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
- * @retval Converted value
- */
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
-
- /* Return the selected ADC calibration value */
- if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
- {
- return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
- }
- else
- {
- return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
- }
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
- * @param hadc ADC handle
- * @param SingleDiff Selection of single-ended or differential input
- * This parameter can be one of the following values:
- * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
- * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
- * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
- assert_param(IS_ADC_CALFACT(CalibrationFactor));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Verification of hardware constraints before modifying the calibration */
- /* factors register: ADC must be enabled, no conversion on going. */
- if ( (ADC_IS_ENABLE(hadc) != RESET) &&
- (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
- {
- /* Set the selected ADC calibration value */
- if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
- {
- MODIFY_REG(hadc->Instance->CALFACT ,
- ADC_CALFACT_CALFACT_D ,
- ADC_CALFACT_DIFF_SET(CalibrationFactor) );
- }
- else
- {
- MODIFY_REG(hadc->Instance->CALFACT,
- ADC_CALFACT_CALFACT_S ,
- CalibrationFactor );
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enables ADC, starts conversion of injected group.
- * Interruptions enabled in this function: None.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC slave first, then ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Case of independent mode or multimode(for devices with several ADCs):*/
- /* Set multimode state. */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Enable conversion of injected group, if automatic injected */
- /* conversion is disabled. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (for devices with several ADCs): */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
- ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enables ADC, starts conversion of injected group.
- * Interruptions enabled in this function: None.
- * @param hadc ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
- /* Enable conversion of injected group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If automatic injected conversion is enabled, conversion will start */
- /* after next regular group conversion. */
- if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Start ADC conversion on injected group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
- }
- else
- {
- /* Start ADC conversion on injected group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
- }
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC group injected conversion (potential conversion on going
- * on ADC group regular is not impacted), disable ADC peripheral
- * if no conversion is on going on group regular.
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
- * use function @ref HAL_ADC_Stop().
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC master first, then ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- /* - For ADC injected group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group regular) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group regular) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
- if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
- {
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group injected is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group regular) is intended to continue. */
- if (tmp_hal_status == HAL_OK)
- {
- if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on ADC group injected group is stopped, but ADC is not */
- /* disabled since conversion on ADC group regular is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Stop conversion of injected channels. Disable ADC peripheral if
- * no regular conversion is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion and disable ADC peripheral */
- /* Conditioned to: */
- /* - No conversion on the other group (regular group) is intended to */
- /* continue (injected and regular groups stop conversion and ADC disable */
- /* are common) */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Wait for injected group conversion to be completed.
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t tmp_Flag_EOC;
- uint32_t tmp_cfgr = 0x00000000U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* If end of conversion selected to end of sequence */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- tmp_Flag_EOC = ADC_FLAG_JEOS;
- }
- /* If end of conversion selected to end of each conversion */
- else /* ADC_EOC_SINGLE_CONV */
- {
- tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
- }
-
- /* Get relevant register CFGR in ADC instance of ADC master or slave */
- /* in function of multimode state (for devices with multimode */
- /* available). */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- tmp_cfgr = READ_REG(hadc->Instance->CFGR);
- }
- else
- {
- tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait until End of Conversion flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger or by automatic injected conversion */
- /* from group regular. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Clear end of conversion flag of injected group if low power feature */
- /* "Auto Wait" is disabled, to not interfere with this feature until data */
- /* register is read using function HAL_ADC_GetValue(). */
- if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
- {
- /* Clear injected group conversion flag */
- /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
- __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Wait for injected group conversion to be completed.
- * @param hadc ADC handle
- * @param Timeout Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Variables for polling in case of scan mode enabled */
- uint32_t Conversion_Timeout_CPU_cycles_max =0U;
- uint32_t Conversion_Timeout_CPU_cycles =0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Polling for end of conversion: differentiation if single/sequence */
- /* conversion. */
- /* For injected group, flag JEOC is set only at the end of the sequence, */
- /* not for each conversion within the sequence. */
- /* - If single conversion for injected group (scan mode disabled or */
- /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */
- /* conversion completion. */
- /* - If sequence conversion for injected group (scan mode enabled and */
- /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */
- /* sequence. */
- /* To poll for each conversion, the maximum conversion time is computed */
- /* from ADC conversion time (selected sampling time + conversion time of */
- /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
- /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
- /* As flag JEOC is not set after each conversion, no timeout status can */
- /* be set. */
- if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
- {
- /* Wait until End of Conversion flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* Replace polling by wait for maximum conversion time */
- /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
- /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
- /* channels. */
- Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
- Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
-
- /* Poll with maximum conversion time */
- while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- Conversion_Timeout_CPU_cycles ++;
- }
- }
-
-
- /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger or by automatic injected conversion */
- /* from group regular. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enables ADC, starts conversion of injected group with interruption.
- * Interruptions enabled in this function:
- * - JEOC (end of conversion of injected group) or JEOS (end of
- * sequence of injected group) depending on ADC initialization
- * parameter "EOCSelection"
- * Each of these interruptions has its dedicated callback function.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC slave first, then ADC master.
- * For ADC slave, ADC is enabled only (conversion is not started).
- * For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Case of independent mode or multimode(for devices with several ADCs):*/
- /* Set multimode state. */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
-
- /* Enable ADC Injected context queue overflow interrupt if this feature */
- /* is enabled. */
- if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
- {
- __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
- }
-
- /* Enable ADC end of conversion interrupt */
- switch(hadc->Init.EOCSelection)
- {
- case ADC_EOC_SEQ_CONV:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
- break;
- /* case ADC_EOC_SINGLE_CONV */
- default:
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- break;
- }
-
- /* Enable conversion of injected group, if automatic injected */
- /* conversion is disabled. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled (for devices with several ADCs): */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
- ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
- {
- SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enables ADC, starts conversion of injected group with interruption.
- * Interruptions enabled in this function:
- * - JEOC (end of conversion of injected group)
- * Each of these interruptions has its dedicated callback function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
- /* Enable end of conversion interrupt for injected channels */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Enable conversion of injected group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If automatic injected conversion is enabled, conversion will start */
- /* after next regular group conversion. */
- if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Start ADC conversion on injected group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
- }
- else
- {
- /* Start ADC conversion on injected group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
- }
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC group injected conversion (potential conversion on going
- * on ADC group regular is not impacted), disable ADC peripheral
- * if no conversion is on going on group regular.
- * Interruptions disabled in this function:
- * - JEOC (end of conversion of injected group) and JEOS (end of
- * sequence of injected group)
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
- * use function @ref HAL_ADC_Stop().
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function must be called for ADC master first, then ADC slave.
- * For ADC master, conversion is stopped and ADC is disabled.
- * For ADC slave, ADC is disabled only (conversion stop of ADC master
- * has already stopped conversion of ADC slave).
- * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- /* - For ADC injected group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group regular) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group regular) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
- if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
- {
- /* 1. Stop potential conversion on going on injected group only. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group injected is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group regular) is intended to continue. */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for injected channels */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
-
- if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on ADC group injected group is stopped, but ADC is not */
- /* disabled since conversion on ADC group regular is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Stop conversion of injected channels, disable interruption of
- * end-of-conversion. Disable ADC peripheral if no regular conversion
- * is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @param hadc ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion and disable ADC peripheral */
- /* Conditioned to: */
- /* - No conversion on the other group (regular group) is intended to */
- /* continue (injected and regular groups stop conversion and ADC disable */
- /* are common) */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for injected channels */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/**
- * @brief With ADC configured in multimode, for ADC master:
- * Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Multimode must have been previously configured using
- * HAL_ADCEx_MultiModeConfigChannel() function.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * Each of these interruptions has its dedicated callback function.
- * @note ADC slave must be preliminarily enabled using single-mode
- * HAL_ADC_Start() function.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_HandleTypeDef tmphadcSlave;
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Perform ADC enable and conversion start if no conversion is on going */
- /* (check on ADC master only) */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
-
- /* Enable the ADC peripherals: master and slave (in case if not already */
- /* enabled previously) */
- tmp_hal_status = ADC_Enable(hadc);
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Enable(&tmphadcSlave);
- }
-
- /* Start conversion all ADCs of multimode are effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state (ADC master) */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
- HAL_ADC_STATE_REG_BUSY);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
-
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
-
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_BUSY;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief With ADC configured in multimode, for ADC master:
- * Stop ADC group regular conversion (potential conversion on going
- * on ADC group injected is not impacted),
- * disable ADC DMA transfer, disable ADC peripheral
- * if no conversion is on going on group injected.
- * Interruptions disabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * @note In case of auto-injection mode, this function also stop conversion
- * on ADC group injected.
- * @note Multimode is kept enabled after this function. To disable multimode
- * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
- * @note In case of DMA configured in circular mode, function
- * HAL_ADC_Stop_DMA must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel of ADC slave.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Stop potential multimode conversion on going, on regular and */
- /* injected groups. */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
-
- /* Disable ADC peripheral if conversions are effectively stopped */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
- tickstart = HAL_GetTick();
-
- while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
- ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
- {
- if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- /* Note: In case of ADC slave using its own DMA channel (multimode */
- /* parameter "DMAAccessMode" set to disabled): */
- /* DMA channel of ADC slave should stopped after this function with */
- /* function HAL_ADC_Stop_DMA. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-
-
- /* 2. Disable the ADC peripherals: master and slave */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to retain a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- /* Check if ADC are effectively disabled */
- if ((ADC_Disable(hadc) != HAL_ERROR) &&
- (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
- {
- tmp_hal_status = HAL_OK;
-
- /* Change ADC state (ADC master) */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* In case of error, attempt to disable ADC instances anyway */
- ADC_Disable(hadc);
- ADC_Disable(&tmphadcSlave);
-
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- }
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Returns the last ADC Master&Slave regular conversions results data
- * in the selected multi mode.
- * @note Reading register CDR does not clear flag ADC flag EOC
- * (ADC group regular end of unitary conversion),
- * as it is the case for independent mode data register.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval The converted data value.
- */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
- ADC_Common_TypeDef *tmpADC_Common;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* Return the multi mode conversion value */
- return tmpADC_Common->CDR;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Get ADC injected group conversion result.
- * @note Reading register JDRx automatically clears ADC flag JEOC
- * (ADC group injected end of unitary conversion).
- * @note This function does not clear ADC flag JEOS
- * (ADC group injected end of sequence conversion)
- * Occurrence of flag JEOS rising:
- * - If sequencer is composed of 1 rank, flag JEOS is equivalent
- * to flag JEOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag JEOC only is raised, at the end of the scan sequence
- * both flags JEOC and EOS are raised.
- * Flag JEOS must not be cleared by this function because
- * it would not be compliant with low power features
- * (feature low power auto-wait, not available on all STM32 families).
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc ADC handle
- * @param InjectedRank the converted ADC injected rank.
- * This parameter can be one of the following values:
- * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
- * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
- * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
- * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
- * @retval ADC group injected conversion data
- */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
- uint32_t tmp_jdr = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
- /* Note: ADC flag JEOC is not cleared here by software because */
- /* automatically cleared by hardware when reading register JDRx. */
-
- /* Get ADC converted value */
- switch(InjectedRank)
- {
- case ADC_INJECTED_RANK_4:
- tmp_jdr = hadc->Instance->JDR4;
- break;
- case ADC_INJECTED_RANK_3:
- tmp_jdr = hadc->Instance->JDR3;
- break;
- case ADC_INJECTED_RANK_2:
- tmp_jdr = hadc->Instance->JDR2;
- break;
- case ADC_INJECTED_RANK_1:
- default:
- tmp_jdr = hadc->Instance->JDR1;
- break;
- }
-
- /* Return ADC converted value */
- return tmp_jdr;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Get ADC injected group conversion result.
- * @note Reading register JDRx automatically clears ADC flag JEOC
- * (ADC group injected end of unitary conversion).
- * @note This function does not clear ADC flag JEOS
- * (ADC group injected end of sequence conversion)
- * Occurrence of flag JEOS rising:
- * - If sequencer is composed of 1 rank, flag JEOS is equivalent
- * to flag JEOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag JEOC only is raised, at the end of the scan sequence
- * both flags JEOC and EOS are raised.
- * Flag JEOS must not be cleared by this function because
- * it would not be compliant with low power features
- * (feature low power auto-wait, not available on all STM32 families).
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc ADC handle
- * @param InjectedRank the converted ADC injected rank.
- * This parameter can be one of the following values:
- * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
- * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
- * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
- * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
- * @retval ADC group injected conversion data
- */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
- uint32_t tmp_jdr = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
- /* Get ADC converted value */
- switch(InjectedRank)
- {
- case ADC_INJECTED_RANK_4:
- tmp_jdr = hadc->Instance->JDR4;
- break;
- case ADC_INJECTED_RANK_3:
- tmp_jdr = hadc->Instance->JDR3;
- break;
- case ADC_INJECTED_RANK_2:
- tmp_jdr = hadc->Instance->JDR2;
- break;
- case ADC_INJECTED_RANK_1:
- default:
- tmp_jdr = hadc->Instance->JDR1;
- break;
- }
-
- /* Return ADC converted value */
- return tmp_jdr;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Stop ADC group regular conversion (potential conversion on going
- * on ADC group injected is not impacted), disable ADC peripheral
- * if no conversion is on going on group injected.
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
- * use function @ref HAL_ADC_Stop().
- * @note In case of auto-injection mode, this function also stop conversion
- * on ADC group injected.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - For ADC regular group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group injected) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group injected) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
-
- /* 1. Stop potential conversion on going, on regular group only */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group regular is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group injected) is intended to continue. */
- if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
- {
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on ADC group regular group is stopped, but ADC is not */
- /* disabled since conversion on ADC group injected is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC group regular conversion (potential conversion on going
- * on ADC group injected is not impacted), disable ADC peripheral
- * if no conversion is on going on group injected.
- * Interruptions disabled in this function:
- * - EOC (end of conversion of regular group) and EOS (end of
- * sequence of regular group)
- * - overrun
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
- * use function @ref HAL_ADC_Stop().
- * @note In case of auto-injection mode, this function also stop conversion
- * on ADC group injected.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - For ADC regular group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group injected) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group injected) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
-
- /* 1. Stop potential conversion on going, on regular group only */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group regular is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group injected) is intended to continue. */
- if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
- {
- /* Disable ADC end of conversion interrupt for regular group */
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
-
- /* 2. Disable the ADC peripheral */
- tmp_hal_status = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on ADC group regular group is stopped, but ADC is not */
- /* disabled since conversion on ADC group injected is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC group regular conversion (potential conversion on going
- * on ADC group injected is not impacted),
- * disable ADC DMA transfer, disable ADC peripheral
- * if no conversion is on going on group injected.
- * Interruptions disabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
- * use function @ref HAL_ADC_Stop().
- * @note Case of multimode enabled (for devices with several ADCs): This
- * function is for single-ADC mode only. For multimode, use the
- * dedicated MultimodeStop function.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - For ADC regular group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group injected) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group injected) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
-
- /* 1. Stop potential conversion on going, on regular group only */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group regular is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group injected) is intended to continue. */
- if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
- {
- /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
- /* 2. Disable the ADC peripheral */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to retain a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Disable(hadc);
- }
- else
- {
- ADC_Disable(hadc);
- }
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- /* Conversion on ADC group regular group is stopped, but ADC is not */
- /* disabled since conversion on ADC group injected is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/**
- * @brief With ADC configured in multimode, for ADC master:
- * Stop ADC group regular conversion (potential conversion on going
- * on ADC group injected is not impacted),
- * disable ADC DMA transfer, disable ADC peripheral
- * if no conversion is on going on group injected.
- * Interruptions disabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * - overrun
- * @note To stop ADC conversion of both groups regular and injected and to
- * to disable ADC peripheral, instead of using 2 functions
- * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
- * @ref HAL_ADCEx_InjectedStop(), use function
- * @ref HAL_ADCEx_MultiModeStop_DMA.
- * @note In case of auto-injection mode, this function also stop conversion
- * on ADC group injected.
- * @note Multimode is kept enabled after this function. To disable multimode
- * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
- * @note In case of DMA configured in circular mode, function
- * HAL_ADC_Stop_DMA must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel of ADC slave.
- * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential ADC conversion on going and disable ADC peripheral */
- /* conditioned to: */
- /* - For ADC regular group conversion stop: */
- /* On this STM32 family, conversion on the other group */
- /* (group injected) can continue (groups regular and injected */
- /* conversion stop commands are independent) */
- /* - For ADC disable: */
- /* No conversion on the other group (group injected) must be intended to */
- /* continue (groups regular and injected are both impacted by */
- /* ADC disable) */
-
- /* 1. Stop potential conversion on going, on regular group only */
- tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
-
- /* Disable ADC peripheral if conversion on ADC group regular is */
- /* effectively stopped and if no conversion on the other group */
- /* (ADC group injected) is intended to continue. */
- if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
- ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
- {
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- if (tmphadcSlave.Instance == NULL)
- {
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped (ADC master and ADC slave), then disable ADC */
-
- /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
- tickstart = HAL_GetTick();
-
- while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
- ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
- {
- if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- /* Note: In case of ADC slave using its own DMA channel (multimode */
- /* parameter "DMAAccessMode" set to disabled): */
- /* DMA channel of ADC slave should stopped after this function with */
- /* function HAL_ADC_Stop_DMA. */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
-
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-
-
-
- /* 2. Disable the ADC peripherals: master and slave */
- /* Update "tmp_hal_status" only if DMA channel disabling passed, */
- /* to retain a potential failing status. */
- if (tmp_hal_status == HAL_OK)
- {
- /* Check if ADC are effectively disabled */
- if ((ADC_Disable(hadc) != HAL_ERROR) &&
- (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
- {
- tmp_hal_status = HAL_OK;
-
- /* Change ADC state (ADC master) */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* In case of error, attempt to disable ADC instances anyway */
- ADC_Disable(hadc);
- ADC_Disable(&tmphadcSlave);
-
- /* Update ADC state machine (ADC master) to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- }
-
- }
- /* Conversion on ADC group regular group is stopped, but ADC is not */
- /* disabled since conversion on ADC group injected is still on going. */
- else
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Injected conversion complete callback in non blocking mode
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
- */
-}
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Injected context queue overflow flag callback.
- * @note This callback is called if injected context queue is enabled
- (parameter "QueueInjectedContext" in injected channel configuration)
- and if a new injected context is set when queue is full (maximum 2
- contexts).
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
- in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 2 callback in non blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog 3 callback in non blocking mode.
- * @param hadc ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
-
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
- */
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
- * @brief ADC Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on regular group
- (+) Configure channels on injected group
- (+) Configure multimode
- (+) Configure the analog watchdog
-
-@endverbatim
- * @{
- */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the the selected channel to be linked to the regular
- * group.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * The recommended sampling time is at least:
- * - For devices STM32F37x: 17.1us for temperature sensor
- * - For the other STM32F3 devices: 2.2us for each of channels
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into regular group, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_ChannelConfTypeDef".
- * @param hadc ADC handle
- * @param sConfig Structure ADC channel for regular group.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
- uint32_t tmpOffsetShifted;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
-
-
- /* Verification of channel number: Channels 1 to 14 are available in */
- /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
- /* single-ended mode. */
- if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- assert_param(IS_ADC_CHANNEL(sConfig->Channel));
- }
- else
- {
- assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel number */
- /* - Channel rank */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- {
- /* Regular sequence configuration */
- /* For Rank 1 to 4U */
- if (sConfig->Rank < 5U)
- {
- MODIFY_REG(hadc->Instance->SQR1,
- ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
- ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 5 to 9U */
- else if (sConfig->Rank < 10U)
- {
- MODIFY_REG(hadc->Instance->SQR2,
- ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
- ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 10 to 14U */
- else if (sConfig->Rank < 15U)
- {
- MODIFY_REG(hadc->Instance->SQR3 ,
- ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
- ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 15 to 16U */
- else
- {
- MODIFY_REG(hadc->Instance->SQR4 ,
- ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) ,
- ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Channel sampling time */
- /* - Channel offset */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- /* Channel sampling time configuration */
- /* For channels 10 to 18U */
- if (sConfig->Channel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR2 ,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
- }
- else /* For channels 1 to 9U */
- {
- MODIFY_REG(hadc->Instance->SMPR1 ,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
- }
-
-
- /* Configure the offset: offset enable/disable, channel, offset value */
-
- /* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
- /* to 0. */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
-
- /* Configure the selected offset register: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- switch (sConfig->OffsetNumber)
- {
- case ADC_OFFSET_1:
- /* Configure offset register 1U */
- MODIFY_REG(hadc->Instance->OFR1 ,
- ADC_OFR1_OFFSET1_CH |
- ADC_OFR1_OFFSET1 ,
- ADC_OFR1_OFFSET1_EN |
- ADC_OFR_CHANNEL(sConfig->Channel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_2:
- /* Configure offset register 2U */
- MODIFY_REG(hadc->Instance->OFR2 ,
- ADC_OFR2_OFFSET2_CH |
- ADC_OFR2_OFFSET2 ,
- ADC_OFR2_OFFSET2_EN |
- ADC_OFR_CHANNEL(sConfig->Channel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_3:
- /* Configure offset register 3U */
- MODIFY_REG(hadc->Instance->OFR3 ,
- ADC_OFR3_OFFSET3_CH |
- ADC_OFR3_OFFSET3 ,
- ADC_OFR3_OFFSET3_EN |
- ADC_OFR_CHANNEL(sConfig->Channel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_4:
- /* Configure offset register 4U */
- MODIFY_REG(hadc->Instance->OFR4 ,
- ADC_OFR4_OFFSET4_CH |
- ADC_OFR4_OFFSET4 ,
- ADC_OFR4_OFFSET4_EN |
- ADC_OFR_CHANNEL(sConfig->Channel) |
- tmpOffsetShifted );
- break;
-
- /* Case ADC_OFFSET_NONE */
- default :
- /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
- /* enabled. If this is the case, offset OFRx is disabled. */
- if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- /* Disable offset OFR1*/
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
- }
- if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- /* Disable offset OFR2*/
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
- }
- if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- /* Disable offset OFR3*/
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
- }
- if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
- {
- /* Disable offset OFR4*/
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
- }
- break;
- }
-
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Configuration of differential mode */
- if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- /* Disable differential mode (default mode: single-ended) */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
- }
- else
- {
- /* Enable differential mode */
- SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
-
- /* Channel sampling time configuration (channel ADC_INx +1 */
- /* corresponding to differential negative input). */
- /* For channels 10 to 18U */
- if (sConfig->Channel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
- }
- else /* For channels 1 to 9U */
- {
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) ,
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) );
- }
- }
-
-
- /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
- /* internal measurement paths enable: If internal channel selected, */
- /* enable dedicated internal buffers and path. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_DeInit(). */
-
- /* Configuration of common ADC parameters */
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
- ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
- ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
- )
- {
- /* Configuration of common ADC parameters (continuation) */
- /* Set handle of the other ADC sharing the same common register */
- ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
-
- /* Software is allowed to change common parameters only when all ADCs */
- /* of the common group are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
- {
- /* If Channel_16 is selected, enable Temp. sensor measurement path */
- /* Note: Temp. sensor internal channels available on ADC1 only */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- /* If Channel_17 is selected, enable VBAT measurement path */
- /* Note: VBAT internal channels available on ADC1 only */
- else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
- }
- /* If Channel_18 is selected, enable VREFINT measurement path */
- /* Note: VrefInt internal channels available on all ADCs, but only */
- /* one ADC is allowed to be connected to VrefInt at the same */
- /* time. */
- else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
- }
- }
- /* If the requested internal measurement path has already been */
- /* enabled and other ADC of the common group are enabled, internal */
- /* measurement paths cannot be enabled. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- }
-
- }
- /* If a conversion is on going on regular group, no update on regular */
- /* channel could be done on neither of the channel configuration structure */
- /* parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Configures the the selected channel to be linked to the regular
- * group.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * The recommended sampling time is at least:
- * - For devices STM32F37x: 17.1us for temperature sensor
- * - For the other STM32F3 devices: 2.2us for each of channels
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into regular group, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_ChannelConfTypeDef".
- * @param hadc ADC handle
- * @param sConfig Structure of ADC channel for regular group.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CHANNEL(sConfig->Channel));
- assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* Regular sequence configuration */
- /* For Rank 1 to 6U */
- if (sConfig->Rank < 7U)
- {
- MODIFY_REG(hadc->Instance->SQR3 ,
- ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
- ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 7 to 12U */
- else if (sConfig->Rank < 13U)
- {
- MODIFY_REG(hadc->Instance->SQR2 ,
- ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
- ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 13 to 16U */
- else
- {
- MODIFY_REG(hadc->Instance->SQR1 ,
- ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
- ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
- }
-
-
- /* Channel sampling time configuration */
- /* For channels 10 to 18U */
- if (sConfig->Channel > ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR1 ,
- ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
- }
- else /* For channels 0 to 9U */
- {
- MODIFY_REG(hadc->Instance->SMPR2 ,
- ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
- }
-
- /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
- /* and VREFINT measurement path. */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
- (sConfig->Channel == ADC_CHANNEL_VREFINT) )
- {
- SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
-
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
- {
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- }
- /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
- else if (sConfig->Channel == ADC_CHANNEL_VBAT)
- {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the ADC injected group and the selected channel to be
- * linked to the injected group.
- * @note Possibility to update parameters on the fly:
- * This function initializes injected group, following calls to this
- * function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InjectionConfTypeDef".
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * The recommended sampling time is at least:
- * - For devices STM32F37x: 17.1us for temperature sensor
- * - For the other STM32F3 devices: 2.2us for each of channels
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
- * be used.
- * @note Caution: For Injected Context Queue use: a context must be fully
- * defined before start of injected conversion: all channels configured
- * consecutively for the same ADC instance. Therefore, Number of calls of
- * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
- * InjectedNbrOfConversion for each context.
- * - Example 1: If 1 context intended to be used (or not use of this feature:
- * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
- * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
- * called once for each channel (3 times) before launching a conversion.
- * This function must not be called to configure the 4th injected channel:
- * it would start a new context into context queue.
- * - Example 2: If 2 contexts intended to be used and usage of the 3 first
- * injected ranks (InjectedNbrOfConversion=3),
- * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
- * for each context (3 channels x 2 contexts = 6 calls). Conversion can
- * start once the 1st context is set. The 2nd context can be set on the fly.
- * @param hadc ADC handle
- * @param sConfigInjected Structure of ADC injected group and ADC channel for
- * injected group.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
- uint32_t tmpOffsetShifted;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Injected context queue feature: temporary JSQR variables defined in */
- /* static to be passed over calls of this function */
- uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
- assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
- assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- }
-
- /* Verification of channel number: Channels 1 to 14 are available in */
- /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
- /* single-ended mode. */
- if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else
- {
- assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Configuration of Injected group sequencer. */
- /* Hardware constraint: Must fully define injected context register JSQR */
- /* before make it entering into injected sequencer queue. */
- /* */
- /* - if scan mode is disabled: */
- /* * Injected channels sequence length is set to 0x00: 1 channel */
- /* converted (channel on injected rank 1U) */
- /* Parameter "InjectedNbrOfConversion" is discarded. */
- /* * Injected context register JSQR setting is simple: register is fully */
- /* defined on one call of this function (for injected rank 1U) and can */
- /* be entered into queue directly. */
- /* - if scan mode is enabled: */
- /* * Injected channels sequence length is set to parameter */
- /* "InjectedNbrOfConversion". */
- /* * Injected context register JSQR setting more complex: register is */
- /* fully defined over successive calls of this function, for each */
- /* injected channel rank. It is entered into queue only when all */
- /* injected ranks have been set. */
- /* Note: Scan mode is not present by hardware on this device, but used */
- /* by software for alignment over all STM32 devices. */
-
- if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
- (sConfigInjected->InjectedNbrOfConversion == 1U) )
- {
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer: fixed to 1st rank */
- /* (scan mode disabled, only rank 1 used) */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
- /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
-
- if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
- {
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
- {
- SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
- ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
- sConfigInjected->ExternalTrigInjecConvEdge );
- }
- else
- {
- SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
- }
-
- /* Update ADC register JSQR */
- MODIFY_REG(hadc->Instance->JSQR ,
- ADC_JSQR_JSQ4 |
- ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 |
- ADC_JSQR_JSQ1 |
- ADC_JSQR_JEXTEN |
- ADC_JSQR_JEXTSEL |
- ADC_JSQR_JL ,
- tmp_JSQR_ContextQueueBeingBuilt );
-
- /* For debug and informative reasons, hadc handle saves JSQR setting */
- hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
- }
- /* If another injected rank than rank1 was intended to be set, and could */
- /* not due to ScanConvMode disabled, error is reported. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- }
- else
- {
- /* Case of scan mode enabled, several channels to set into injected group */
- /* sequencer. */
- /* Procedure to define injected context register JSQR over successive */
- /* calls of this function, for each injected channel rank: */
-
- /* 1. Start new context and set parameters related to all injected */
- /* channels: injected sequence length and trigger */
- if (hadc->InjectionConfig.ChannelCount == 0U)
- {
- /* Initialize number of channels that will be configured on the context */
- /* being built */
- hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
- /* Initialize value that will be set into register JSQR */
- hadc->InjectionConfig.ContextQueue = 0x00000000U;
-
- /* Configuration of context register JSQR: */
- /* - number of ranks in injected group sequencer */
- /* - external trigger to start conversion */
- /* - external trigger polarity */
-
- /* Enable external trigger if trigger selection is different of */
- /* software start. */
- /* Note: This configuration keeps the hardware feature of parameter */
- /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
- /* software start. */
- if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
- {
- SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) |
- ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
- sConfigInjected->ExternalTrigInjecConvEdge );
- }
- else
- {
- SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) );
- }
-
- }
-
- /* 2. Continue setting of context under definition with parameter */
- /* related to each channel: channel rank sequence */
-
- /* Set the JSQx bits for the selected rank */
- MODIFY_REG(hadc->InjectionConfig.ContextQueue ,
- ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) ,
- ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
-
- /* Decrease channel count after setting into temporary JSQR variable */
- hadc->InjectionConfig.ChannelCount --;
-
- /* 3. End of context setting: If last channel set, then write context */
- /* into register JSQR and make it enter into queue */
- if (hadc->InjectionConfig.ChannelCount == 0U)
- {
- /* Update ADC register JSQR */
- MODIFY_REG(hadc->Instance->JSQR ,
- ADC_JSQR_JSQ4 |
- ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 |
- ADC_JSQR_JSQ1 |
- ADC_JSQR_JEXTEN |
- ADC_JSQR_JEXTSEL |
- ADC_JSQR_JL ,
- hadc->InjectionConfig.ContextQueue );
- }
-
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on injected group: */
- /* - Injected context queue: Queue disable (active context is kept) or */
- /* enable (context decremented, up to 2 contexts queued) */
- /* - Injected discontinuous mode: can be enabled only if auto-injected */
- /* mode is disabled. */
- if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
- {
- /* If auto-injected mode is disabled: no constraint */
- if (sConfigInjected->AutoInjectedConv == DISABLE)
- {
- MODIFY_REG(hadc->Instance->CFGR ,
- ADC_CFGR_JQM |
- ADC_CFGR_JDISCEN ,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
- ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
- }
- /* If auto-injected mode is enabled: Injected discontinuous setting is */
- /* discarded. */
- else
- {
- MODIFY_REG(hadc->Instance->CFGR ,
- ADC_CFGR_JQM |
- ADC_CFGR_JDISCEN ,
- ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
-
- /* If injected discontinuous mode was intended to be set and could not */
- /* due to auto-injected enabled, error is reported. */
- if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Automatic injected conversion: can be enabled if injected group */
- /* external triggers are disabled. */
- /* - Channel sampling time */
- /* - Channel offset */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
- /* If injected group external triggers are disabled (set to injected */
- /* software start): no constraint */
- if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
- {
- MODIFY_REG(hadc->Instance->CFGR ,
- ADC_CFGR_JAUTO ,
- ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv) );
- }
- /* If Automatic injected conversion was intended to be set and could not */
- /* due to injected group external triggers enabled, error is reported. */
- else
- {
- /* Disable Automatic injected conversion */
- CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
-
- if (sConfigInjected->AutoInjectedConv == ENABLE)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
-
- /* Channel sampling time configuration */
- /* For channels 10 to 18U */
- if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR2 ,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
- else /* For channels 1 to 9U */
- {
- MODIFY_REG(hadc->Instance->SMPR1 ,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
-
- /* Configure the offset: offset enable/disable, channel, offset value */
-
- /* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
- /* to 0. */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
-
- /* Configure the selected offset register: */
- /* - Enable offset */
- /* - Set channel number */
- /* - Set offset value */
- switch (sConfigInjected->InjectedOffsetNumber)
- {
- case ADC_OFFSET_1:
- /* Configure offset register 1U */
- MODIFY_REG(hadc->Instance->OFR1 ,
- ADC_OFR1_OFFSET1_CH |
- ADC_OFR1_OFFSET1 ,
- ADC_OFR1_OFFSET1_EN |
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_2:
- /* Configure offset register 2U */
- MODIFY_REG(hadc->Instance->OFR2 ,
- ADC_OFR2_OFFSET2_CH |
- ADC_OFR2_OFFSET2 ,
- ADC_OFR2_OFFSET2_EN |
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_3:
- /* Configure offset register 3U */
- MODIFY_REG(hadc->Instance->OFR3 ,
- ADC_OFR3_OFFSET3_CH |
- ADC_OFR3_OFFSET3 ,
- ADC_OFR3_OFFSET3_EN |
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
- tmpOffsetShifted );
- break;
-
- case ADC_OFFSET_4:
- /* Configure offset register 4U */
- MODIFY_REG(hadc->Instance->OFR4 ,
- ADC_OFR4_OFFSET4_CH |
- ADC_OFR4_OFFSET4 ,
- ADC_OFR4_OFFSET4_EN |
- ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
- tmpOffsetShifted );
- break;
-
- /* Case ADC_OFFSET_NONE */
- default :
- /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
- /* enabled. If this is the case, offset OFRx is disabled. */
- if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
- {
- /* Disable offset OFR1*/
- CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
- }
- if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
- {
- /* Disable offset OFR2*/
- CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
- }
- if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
- {
- /* Disable offset OFR3*/
- CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
- }
- if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
- {
- /* Disable offset OFR4*/
- CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
- }
- break;
- }
-
- }
-
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Single or differential mode */
- /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Configuration of differential mode */
- if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
- {
- /* Disable differential mode (default mode: single-ended) */
- CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
- }
- else
- {
- /* Enable differential mode */
- SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
-
- /* Channel sampling time configuration (channel ADC_INx +1 */
- /* corresponding to differential negative input). */
- /* For channels 10 to 18U */
- if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U),
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
- }
- else /* For channels 1 to 9U */
- {
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U),
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
- }
- }
-
-
- /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
- /* internal measurement paths enable: If internal channel selected, */
- /* enable dedicated internal buffers and path. */
- /* Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_deInit(). */
-
- /* Configuration of common ADC parameters */
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* If the requested internal measurement path has already been enabled, */
- /* bypass the configuration processing. */
- if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
- ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
- ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
- (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
- )
- {
- /* Configuration of common ADC parameters (continuation) */
- /* Set handle of the other ADC sharing the same common register */
- ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
-
- /* Software is allowed to change common parameters only when all ADCs */
- /* of the common group are disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
- {
- /* If Channel_16 is selected, enable Temp. sensor measurement path */
- /* Note: Temp. sensor internal channels available on ADC1 only */
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
-
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- /* If Channel_17 is selected, enable VBAT measurement path */
- /* Note: VBAT internal channels available on ADC1 only */
- else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
- }
- /* If Channel_18 is selected, enable VREFINT measurement path */
- /* Note: VrefInt internal channels available on all ADCs, but only */
- /* one ADC is allowed to be connected to VrefInt at the same */
- /* time. */
- else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
- {
- SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
- }
- }
- /* If the requested internal measurement path has already been enabled */
- /* and other ADC of the common group are enabled, internal */
- /* measurement paths cannot be enabled. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Configures the ADC injected group and the selected channel to be
- * linked to the injected group.
- * @note Possibility to update parameters on the fly:
- * This function initializes injected group, following calls to this
- * function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * this function must be called when ADC is not under conversion.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * The recommended sampling time is at least:
- * - For devices STM32F37x: 17.1us for temperature sensor
- * - For the other STM32F3 devices: 2.2us for each of channels
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @param hadc ADC handle
- * @param sConfigInjected Structure of ADC injected group and ADC channel for
- * injected group.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
- assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
- assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Configuration of injected group sequencer: */
- /* - if scan mode is disabled, injected channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1U) */
- /* Parameter "InjectedNbrOfConversion" is discarded. */
- /* Note: Scan mode is present by hardware on this device and, if */
- /* disabled, discards automatically nb of conversions. Anyway, nb of */
- /* conversions is forced to 0x00 for alignment over all STM32 devices. */
- /* - if scan mode is enabled, injected channels sequence length is set to */
- /* parameter "InjectedNbrOfConversion". */
- if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
- {
- if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
- {
- /* Clear the old SQx bits for all injected ranks */
- MODIFY_REG(hadc->Instance->JSQR ,
- ADC_JSQR_JL |
- ADC_JSQR_JSQ4 |
- ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 |
- ADC_JSQR_JSQ1 ,
- ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
- ADC_INJECTED_RANK_1,
- 0x01U) );
- }
- /* If another injected rank than rank1 was intended to be set, and could */
- /* not due to ScanConvMode disabled, error is reported. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
- else
- {
- /* Since injected channels rank conv. order depends on total number of */
- /* injected conversions, selected rank must be below or equal to total */
- /* number of injected conversions to be updated. */
- if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
- {
- /* Clear the old SQx bits for the selected rank */
- /* Set the SQx bits for the selected rank */
- MODIFY_REG(hadc->Instance->JSQR ,
-
- ADC_JSQR_JL |
- ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) ,
-
- ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
- ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) );
- }
- else
- {
- /* Clear the old SQx bits for the selected rank */
- MODIFY_REG(hadc->Instance->JSQR ,
-
- ADC_JSQR_JL |
- ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) ,
-
- 0x00000000 );
- }
- }
-
- /* Configuration of injected group */
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - external trigger to start conversion */
- /* Parameters update not conditioned to ADC state: */
- /* - Automatic injected conversion */
- /* - Injected discontinuous mode */
- /* Note: In case of ADC already enabled, caution to not launch an unwanted */
- /* conversion while modifying register CR2 by writing 1 to bit ADON. */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- MODIFY_REG(hadc->Instance->CR2 ,
- ADC_CR2_JEXTSEL |
- ADC_CR2_ADON ,
- sConfigInjected->ExternalTrigInjecConv );
- }
-
- /* Configuration of injected group */
- /* - Automatic injected conversion */
- /* - Injected discontinuous mode */
-
- /* Automatic injected conversion can be enabled if injected group */
- /* external triggers are disabled. */
- if (sConfigInjected->AutoInjectedConv == ENABLE)
- {
- if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
- {
- SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- /* Injected discontinuous can be enabled only if auto-injected mode is */
- /* disabled. */
- if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
- {
- if (sConfigInjected->AutoInjectedConv == DISABLE)
- {
- SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
-
- /* InjectedChannel sampling time configuration */
- /* For channels 10 to 18 */
- if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
- else /* For channels 1 to 9 */
- {
- MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
-
-
- /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
- switch(sConfigInjected->InjectedRank)
- {
- case 1:
- /* Set injected channel 1 offset */
- MODIFY_REG(hadc->Instance->JOFR1,
- ADC_JOFR1_JOFFSET1,
- sConfigInjected->InjectedOffset);
- break;
- case 2:
- /* Set injected channel 2 offset */
- MODIFY_REG(hadc->Instance->JOFR2,
- ADC_JOFR2_JOFFSET2,
- sConfigInjected->InjectedOffset);
- break;
- case 3:
- /* Set injected channel 3 offset */
- MODIFY_REG(hadc->Instance->JOFR3,
- ADC_JOFR3_JOFFSET3,
- sConfigInjected->InjectedOffset);
- break;
- case 4:
- default:
- MODIFY_REG(hadc->Instance->JOFR4,
- ADC_JOFR4_JOFFSET4,
- sConfigInjected->InjectedOffset);
- break;
- }
-
- /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
- /* and VREFINT measurement path. */
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
- (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
- {
- if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
- {
- SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
-
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
- {
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- }
- }
- /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
- else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
- {
- SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the analog watchdog.
- * @note Possibility to update parameters on the fly:
- * This function initializes the selected analog watchdog, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_AnalogWDGConfTypeDef".
- * @param hadc ADC handle
- * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- uint32_t tmpAWDHighThresholdShifted;
- uint32_t tmpAWDLowThresholdShifted;
-
- uint32_t tmpADCFlagAWD2orAWD3;
- uint32_t tmpADCITAWD2orAWD3;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
- assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
- assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-
- /* Verify if threshold is within the selected ADC resolution */
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
-
- if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
- {
- assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular and injected groups: */
- /* - Analog watchdog channels */
- /* - Analog watchdog thresholds */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
- {
-
- /* Analog watchdogs configuration */
- if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
- {
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog enable mode: regular and/or injected */
- /* groups, one or overall group of channels. */
- /* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
- MODIFY_REG(hadc->Instance->CFGR ,
- ADC_CFGR_AWD1SGL |
- ADC_CFGR_JAWD1EN |
- ADC_CFGR_AWD1EN |
- ADC_CFGR_AWD1CH ,
- AnalogWDGConfig->WatchdogMode |
- ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
-
- /* Shift the offset in function of the selected ADC resolution: */
- /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */
- /* are set to 0 */
- tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->TR1 ,
- ADC_TR1_HT1 |
- ADC_TR1_LT1 ,
- ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
- tmpAWDLowThresholdShifted );
-
- /* Clear the ADC Analog watchdog flag (in case of left enabled by */
- /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
- /* or HAL_ADC_PollForEvent(). */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- /* Enable the ADC Analog watchdog interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
- }
- else
- {
- /* Disable the ADC Analog watchdog interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
- }
-
- }
- /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
- else
- {
- /* Shift the threshold in function of the selected ADC resolution */
- /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */
- tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
- {
- /* Set the Analog watchdog channel or group of channels. This also */
- /* enables the watchdog. */
- /* Note: Conditional register reset, because several channels can be */
- /* set by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
- {
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->TR2 ,
- ADC_TR2_HT2 |
- ADC_TR2_LT2 ,
- ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
- tmpAWDLowThresholdShifted );
-
- SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
- }
- else
- {
- CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
- CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
- }
-
- /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
- /* settings. */
- tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
- tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
- }
- /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
- else
- {
- /* Set the Analog watchdog channel or group of channels. This also */
- /* enables the watchdog. */
- /* Note: Conditionnal register reset, because several channels can be */
- /* set by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
- {
- /* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->TR3 ,
- ADC_TR3_HT3 |
- ADC_TR3_LT3 ,
- ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
- tmpAWDLowThresholdShifted );
-
- SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
- }
- else
- {
- CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
- CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
- }
-
- /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
- /* settings. */
- tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
- tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
- }
-
- /* Clear the ADC Analog watchdog flag (in case of left enabled by */
- /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
- /* or HAL_ADC_PollForEvent(). */
- __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
- }
- else
- {
- __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
- }
- }
-
- }
- /* If a conversion is on going on regular or injected groups, no update */
- /* could be done on neither of the AWD configuration structure parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Configures the analog watchdog.
- * @note Analog watchdog thresholds can be modified while ADC conversion
- * is on going.
- * In this case, some constraints must be taken into account:
- * the programmed threshold values are effective from the next
- * ADC EOC (end of unitary conversion).
- * Considering that registers write delay may happen due to
- * bus activity, this might cause an uncertainty on the
- * effective timing of the new programmed threshold values.
- * @param hadc ADC handle
- * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
- assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
- assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
-
- if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
- {
- assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Analog watchdog configuration */
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- /* Enable the ADC Analog watchdog interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
- }
- else
- {
- /* Disable the ADC Analog watchdog interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
- }
-
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog enable mode: regular and/or injected groups, */
- /* one or all channels. */
- /* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
- MODIFY_REG(hadc->Instance->CR1 ,
- ADC_CR1_AWDSGL |
- ADC_CR1_JAWDEN |
- ADC_CR1_AWDEN |
- ADC_CR1_AWDCH ,
- AnalogWDGConfig->WatchdogMode |
- AnalogWDGConfig->Channel );
-
- /* Set the high threshold */
- WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
-
- /* Set the low threshold */
- WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/**
- * @brief Enable ADC multimode and configure multimode parameters
- * @note Possibility to update parameters on the fly:
- * This function initializes multimode parameters, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
- * the ADCs (both ADCs of the common group).
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_MultiModeTypeDef".
- * @note To change back configuration from multimode to single mode, ADC must
- * be reset (using function HAL_ADC_Init() ).
- * @param hadc ADC handle
- * @param multimode Structure of ADC multimode configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_MODE(multimode->Mode));
- if(multimode->Mode != ADC_MODE_INDEPENDENT)
- {
- assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
- assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
- }
-
- /* Set handle of the other ADC sharing the same common register */
- ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
- if (tmphadcSharingSameCommonRegister.Instance == NULL)
- {
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - Multimode DMA configuration */
- /* - Multimode DMA mode */
- if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
- && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
- {
- /* Pointer to the common control register to which is belonging hadc */
- /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
- /* control registers) */
- tmpADC_Common = ADC_COMMON_REGISTER(hadc);
-
- /* If multimode is selected, configure all multimode paramaters. */
- /* Otherwise, reset multimode parameters (can be used in case of */
- /* transition from multimode to independent mode). */
- if(multimode->Mode != ADC_MODE_INDEPENDENT)
- {
- /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
- /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
- /* - DMA access mode */
- MODIFY_REG(tmpADC_Common->CCR ,
- ADC_CCR_MDMA |
- ADC_CCR_DMACFG ,
- multimode->DMAAccessMode |
- ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Set delay between two sampling phases */
- /* Note: Delay range depends on selected resolution: */
- /* from 1 to 12 clock cycles for 12 bits */
- /* from 1 to 10 clock cycles for 10 bits, */
- /* from 1 to 8 clock cycles for 8 bits */
- /* from 1 to 6 clock cycles for 6 bits */
- /* If a higher delay is selected, it will be clamped to maximum delay */
- /* range */
- /* Note: If ADC is not in the appropriate state to modify these */
- /* parameters, their setting is bypassed without error reporting */
- /* (as it can be the expected behaviour in case of intended action */
- /* to update parameter above (which fulfills the ADC state */
- /* condition: no conversion on going on group regular) */
- /* on the fly). */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
- {
- MODIFY_REG(tmpADC_Common->CCR ,
- ADC_CCR_MULTI |
- ADC_CCR_DELAY ,
- multimode->Mode |
- multimode->TwoSamplingDelay );
- }
- }
- else /* ADC_MODE_INDEPENDENT */
- {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
-
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* - Multimode delay */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
- {
- CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
- }
- }
- }
- /* If one of the ADC sharing the same common group is enabled, no update */
- /* could be done on neither of the multimode structure parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F328xx || STM32F334x8 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Private_Functions ADCEx Private Functions
- * @{
- */
-/**
- * @brief DMA transfer complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
- {
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F3 devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
- }
- else
- {
- /* Call DMA error callback */
- hadc->DMA_Handle->XferErrorCallback(hdma);
- }
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Half conversion callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Set ADC error code to DMA error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
-}
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Enable the selected ADC.
- * @note Prerequisite condition to use this function: ADC must be disabled
- * and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc ADC handle
- * @retval HAL status.
- */
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
-
- /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
- /* enabling phase not yet completed: flag ADC ready not yet set). */
- /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
- /* causes: ADC clock not running, ...). */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Check if conditions to enable the ADC are fulfilled */
- if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Enable the ADC peripheral */
- __HAL_ADC_ENABLE(hadc);
-
- /* Wait for ADC effectively enabled */
- tickstart = HAL_GetTick();
-
- while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Disable the selected ADC.
- * @note Prerequisite condition to use this function: ADC conversions must be
- * stopped.
- * @param hadc ADC handle
- * @retval HAL status.
- */
-static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
-
- /* Verification if ADC is not already disabled: */
- /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
- /* disabled. */
- if (ADC_IS_ENABLE(hadc) != RESET )
- {
- /* Check if conditions to disable the ADC are fulfilled */
- if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
- {
- /* Disable the ADC peripheral */
- __HAL_ADC_DISABLE(hadc);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
-
- /* Wait for ADC effectively disabled */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
- {
- if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Stop ADC conversion.
- * @param hadc ADC handle
- * @param ConversionGroup ADC group regular and/or injected.
- * This parameter can be one of the following values:
- * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
- * @arg ADC_INJECTED_GROUP: ADC injected conversion type.
- * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
-{
- uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U;
- uint32_t tickstart = 0U;
- uint32_t Conversion_Timeout_CPU_cycles = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
-
- /* Verification if ADC is not already stopped (on regular and injected */
- /* groups) to bypass this function if not needed. */
- if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
- {
- /* Particular case of continuous auto-injection mode combined with */
- /* auto-delay mode. */
- /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
- /* injected group stop ADC_CR_JADSTP). */
- /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */
- /* (see reference manual). */
- if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
- (hadc->Init.ContinuousConvMode==ENABLE) &&
- (hadc->Init.LowPowerAutoWait==ENABLE) )
- {
- /* Use stop of regular group */
- ConversionGroup = ADC_REGULAR_GROUP;
-
- /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
- while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
- {
- if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- Conversion_Timeout_CPU_cycles ++;
- }
-
- /* Clear JEOS */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
- }
-
- /* Stop potential conversion on going on regular group */
- if (ConversionGroup != ADC_INJECTED_GROUP)
- {
- /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
- {
- /* Stop conversions on regular group */
- hadc->Instance->CR |= ADC_CR_ADSTP;
- }
- }
-
- /* Stop potential conversion on going on injected group */
- if (ConversionGroup != ADC_REGULAR_GROUP)
- {
- /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
- {
- /* Stop conversions on injected group */
- hadc->Instance->CR |= ADC_CR_JADSTP;
- }
- }
-
- /* Selection of start and stop bits in function of regular or injected group */
- switch(ConversionGroup)
- {
- case ADC_REGULAR_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
- break;
- case ADC_INJECTED_GROUP:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
- break;
- /* Case ADC_REGULAR_GROUP */
- default:
- tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
- break;
- }
-
- /* Wait for conversion effectively stopped */
- tickstart = HAL_GetTick();
-
- while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
-
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Enable the selected ADC.
- * @note Prerequisite condition to use this function: ADC must be disabled
- * and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc ADC handle
- * @retval HAL status.
- */
-static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
- __IO uint32_t wait_loop_index = 0U;
-
- /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
- /* enabling phase not yet completed: flag ADC ready not yet set). */
- /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
- /* causes: ADC clock not running, ...). */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Enable the Peripheral */
- __HAL_ADC_ENABLE(hadc);
-
- /* Delay for ADC stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait for ADC effectively enabled */
- while(ADC_IS_ENABLE(hadc) == RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop ADC conversion and disable the selected ADC
- * @param hadc ADC handle
- * @retval HAL status.
- */
-static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
-
- /* Verification if ADC is not already disabled: */
- if (ADC_IS_ENABLE(hadc) != RESET)
- {
- /* Disable the ADC peripheral */
- __HAL_ADC_DISABLE(hadc);
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait for ADC effectively disabled */
- while(ADC_IS_ENABLE(hadc) != RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
deleted file mode 100644
index ac192d589b2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
+++ /dev/null
@@ -1,1700 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_can.c
- * @author MCD Application Team
- * @brief CAN HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (++) Connect and configure the involved CAN pins to AF9 using the
- following function HAL_GPIO_Init();
-
- (#) Initialise and configure the CAN using HAL_CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN HAL driver header file for more useful macros
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CAN CAN
- * @brief CAN driver modules
- * @{
- */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-#define CAN_TIMEOUT_VALUE 10U
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
- * @{
- */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the CAN.
- (+) De-initialize the CAN.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
-{
- uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0U;
-
- /* Check CAN handle */
- if(hcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
- assert_param(IS_CAN_MODE(hcan->Init.Mode));
- assert_param(IS_CAN_SJW(hcan->Init.SJW));
- assert_param(IS_CAN_BS1(hcan->Init.BS1));
- assert_param(IS_CAN_BS2(hcan->Init.BS2));
- assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
- if(hcan->State == HAL_CAN_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcan->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_CAN_MspInit(hcan);
- }
-
- /* Initialize the CAN state*/
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Exit from sleep mode */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
- /* Request initialisation */
- SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check acknowledge */
- if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- /* Set the time triggered communication mode */
- if (hcan->Init.TTCM == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
- }
-
- /* Set the automatic bus-off management */
- if (hcan->Init.ABOM == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
- }
-
- /* Set the automatic wake-up mode */
- if (hcan->Init.AWUM == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
- }
-
- /* Set the no automatic retransmission */
- if (hcan->Init.NART == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
- }
-
- /* Set the receive FIFO locked mode */
- if (hcan->Init.RFLM == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
- }
-
- /* Set the transmit FIFO priority */
- if (hcan->Init.TXFP == ENABLE)
- {
- SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
- }
- else
- {
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
- }
-
- /* Set the bit timing register */
- WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
- hcan->Init.SJW |
- hcan->Init.BS1 |
- hcan->Init.BS2 |
- (hcan->Init.Prescaler - 1U) ));
-
- /* Request leave initialisation */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check acknowledged */
- if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- status = CAN_INITSTATUS_SUCCESS;
- }
- }
-
- if(status == CAN_INITSTATUS_SUCCESS)
- {
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
- * contains the filter configuration information.
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
- uint32_t filternbrbitpos = 0U;
-
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-
- filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
-
- /* Initialisation mode for the filter */
- SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT);
-
- /* Filter Deactivation */
- CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
-
- /* Filter Scale */
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
- {
- /* 16-bit scale for the filter */
- CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
- }
-
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
- {
- /* 32-bit scale for the filter */
- SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
-
- /* 32-bit identifier or First 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* 32-bit mask or Second 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
- {
- /*Id/Mask mode for the filter*/
- CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
- }
-
- /* Filter FIFO assignment */
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
- }
- else
- {
- /* FIFO 1 assignation for the filter */
- SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
- }
-
- /* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
- {
- SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
- }
-
- /* Leave the initialisation mode for the filter */
- CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
-{
- /* Check CAN handle */
- if(hcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CAN_MspDeInit(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CAN MSP.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the CAN MSP.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Transmit a CAN frame message.
- (+) Receive a CAN frame message.
- (+) Enter CAN peripheral in sleep mode.
- (+) Wake up the CAN peripheral from sleep mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
-{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Select one empty transmit mailbox */
- if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
-
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
-
- /* Request transmission */
- SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check End of transmission flag */
- while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Cancel transmission */
- __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process Locked */
- __HAL_LOCK(hcan);
-
- /* Select one empty transmit mailbox */
- if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
-
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber FIFO number.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_BUSY;
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- }
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
- {
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
- }
- else
- {
- pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
- }
- pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
- /* Get the DLC */
- pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
- /* Get the FMI */
- pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
- pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
- pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
- pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
- pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
- pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
- pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
- pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
-
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
- {
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber FIFO number.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_BUSY;
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- }
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- else
- {
- /* Enable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Request Sleep mode */
- MODIFY_REG(hcan->Instance->MCR,
- CAN_MCR_INRQ ,
- CAN_MCR_SLEEP );
-
- /* Sleep mode status */
- if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
- * is in the normal mode.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Wake up request */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Sleep mode status */
- while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
-
- if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handles CAN interrupt request
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
- uint32_t errorcode = HAL_CAN_ERROR_NONE;
-
- /* Check Overrun flag for FIFO0 */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
- {
- /* Set CAN error code to FOV0 error */
- errorcode |= HAL_CAN_ERROR_FOV0;
-
- /* Clear FIFO0 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
- }
-
- /* Check Overrun flag for FIFO1 */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
- {
- /* Set CAN error code to FOV1 error */
- errorcode |= HAL_CAN_ERROR_FOV1;
-
- /* Clear FIFO1 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
- }
-
- /* Check End of transmission flag */
- if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
- {
- /* Check Transmit request completion status */
- if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
- {
- /* Check Transmit success */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
- (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
- (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
- {
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
- }
- else /* Transmit failure */
- {
- /* Set CAN error code to TXFAIL error */
- errorcode |= HAL_CAN_ERROR_TXFAIL;
- }
-
- /* Clear transmission status flags (RQCPx and TXOKx) */
- SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
- CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
- }
- }
-
- /* Check End of reception flag for FIFO0 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO0);
- }
-
- /* Check End of reception flag for FIFO1 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO1);
- }
-
- /* Set error code in handle */
- hcan->ErrorCode |= errorcode;
-
- /* Check Error Warning Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
- {
- /* Set CAN error code to EWG error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- /* No need for clear of Error Warning Flag as read-only */
- }
-
- /* Check Error Passive Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
- {
- /* Set CAN error code to EPV error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- /* No need for clear of Error Passive Flag as read-only */
- }
-
- /* Check Bus-Off Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
- {
- /* Set CAN error code to BOF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- /* No need for clear of Bus-Off Flag as read-only */
- }
-
- /* Check Last error code Flag */
- if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
- {
- switch(hcan->Instance->ESR & CAN_ESR_LEC)
- {
- case(CAN_ESR_LEC_0):
- /* Set CAN error code to STF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_STF;
- break;
- case(CAN_ESR_LEC_1):
- /* Set CAN error code to FOR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
- break;
- case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
- /* Set CAN error code to ACK error */
- hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
- break;
- case(CAN_ESR_LEC_2):
- /* Set CAN error code to BR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BR;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
- /* Set CAN error code to BD error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BD;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
- /* Set CAN error code to CRC error */
- hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
- break;
- default:
- break;
- }
-
- /* Clear Last error code Flag */
- CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
- }
-
- /* Call the Error call Back in case of Errors */
- if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
- {
- /* Clear ERRI Flag */
- SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
-
- /* Set the CAN state ready to be able to start again the process */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- /* - Disable FIFO 0 message pending Interrupt */
- /* - Disable FIFO 0 Overrun Interrupt */
- /* - Disable FIFO 1 message pending Interrupt */
- /* - Disable FIFO 1 Overrun Interrupt */
- /* - Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_FMP0|
- CAN_IT_FOV0|
- CAN_IT_FMP1|
- CAN_IT_FOV1|
- CAN_IT_TME );
-
- /* Call Error callback function */
- HAL_CAN_ErrorCallback(hcan);
- }
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Error CAN callback.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Check the CAN state.
- (+) Check CAN Errors detected during interrupt process
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the CAN state
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL state
- */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
-{
- /* Return CAN state */
- return hcan->State;
-}
-
-/**
- * @brief Return the CAN error code
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval CAN Error Code
- */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
- return hcan->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Private_Functions CAN Private Functions
- * @brief CAN Frame message Rx/Tx functions
- *
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
- /* Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR );
- }
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
-
- /* Transmission complete callback */
- HAL_CAN_TxCpltCallback(hcan);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber Specify the FIFO number
- * @retval HAL status
- * @retval None
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
- {
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
- }
- else
- {
- pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
- }
- pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
- /* Get the DLC */
- pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
- /* Get the FMI */
- pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
- pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
- pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
- pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
- pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
- pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
- pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
- pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
-
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-
- /* Disable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
- /* Disable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR );
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Receive complete callback */
- HAL_CAN_RxCpltCallback(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F302x8 || */
- /* STM32F373xC || STM32F378xx */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
deleted file mode 100644
index ec37473837f..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
+++ /dev/null
@@ -1,671 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_cec.c
- * @author MCD Application Team
- * @brief CEC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Definition Multimedia Interface
- * Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The CEC HAL driver can be used as follow:
-
- (#) Declare a CEC_HandleTypeDef handle structure.
- (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
- (##) Enable the CEC interface clock.
- (##) CEC pins configuration:
- (+) Enable the clock for the CEC GPIOs.
- (+) Configure these CEC pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
- and HAL_CEC_Receive_IT() APIs):
- (+) Configure the CEC interrupt priority.
- (+) Enable the NVIC CEC IRQ handle.
- (@) The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
-
- (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
- in case of Bit Rising Error, Error-Bit generation conditions, device logical
- address and Listen mode in the hcec Init structure.
-
- (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_CEC_MspInit() API.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup CEC CEC
- * @brief HAL CEC module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Functions CEC Exported Functions
- * @{
- */
-
-/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the CEC
- (+) The following parameters need to be configured:
- (++) SignalFreeTime
- (++) Tolerance
- (++) BRERxStop (RX stopped or not upon Bit Rising Error)
- (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
- (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
- (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
- (++) SignalFreeTimeOption (SFT Timer start definition)
- (++) OwnAddress (CEC device address)
- (++) ListenMode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CEC mode according to the specified
- * parameters in the CEC_InitTypeDef and creates the associated handle .
- * @param hcec CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
- assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
- assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
- assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
- assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
- assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
- assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
- assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
- assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
- assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
-
- if(hcec->gState == HAL_CEC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcec->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_CEC_MspInit(hcec);
- }
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- /* Write to CEC Control Register */
- hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
- hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
- hcec->Init.ListenMode;
-
- /* Enable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
- /* Enable the CEC Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->RxState = HAL_CEC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the CEC peripheral
- * @param hcec CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if(hcec == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CEC_MspDeInit(hcec);
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- /* Clear Flags */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
-
- /* Disable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_RESET;
- hcec->RxState = HAL_CEC_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the Own Address of the CEC device
- * @param hcec CEC handle
- * @param CEC_OwnAddress The CEC own address.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
-{
- /* Check the parameters */
- assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
-
- if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
- {
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
- {
- hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
- }
- else
- {
- hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
- }
-
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief CEC MSP Init
- * @param hcec CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC MSP DeInit
- * @param hcec CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the CEC data transfers.
-
- (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
-
- (#) The communication is performed using Interrupts.
- These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated CEC IRQ when using Interrupt mode.
- The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_CEC_ErrorCallback()user callback will be executed when a communication
- error is detected
-
- (#) API's with Interrupt are :
- (+) HAL_CEC_Transmit_IT()
- (+) HAL_CEC_IRQHandler()
-
- (#) A set of User Callbacks are provided:
- (+) HAL_CEC_TxCpltCallback()
- (+) HAL_CEC_RxCpltCallback()
- (+) HAL_CEC_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send data in interrupt mode
- * @param hcec CEC handle
- * @param InitiatorAddress Initiator address
- * @param DestinationAddress destination logical address
- * @param pData pointer to input byte data buffer
- * @param Size amount of data to be sent in bytes (without counting the header).
- * 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
-{
- /* if the IP isn't already busy and if there is no previous transmission
- already pending due to arbitration lost */
- if (hcec->gState == HAL_CEC_STATE_READY)
- {
- if((pData == NULL ) && (Size > 0U))
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
- assert_param(IS_CEC_ADDRESS(InitiatorAddress));
- assert_param(IS_CEC_MSGSIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hcec);
- hcec->pTxBuffPtr = pData;
- hcec->gState = HAL_CEC_STATE_BUSY_TX;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
-
- /* in case of no payload (Size = 0U), sender is only pinging the system;
- Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
- if (Size == 0U)
- {
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
-
- /* send header block */
- hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
- /* Set TX Start of Message (TXSOM) bit */
- __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Get size of the received frame.
- * @param hcec CEC handle
- * @retval Frame size
- */
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
-{
- return hcec->RxXferSize;
-}
-
-/**
- * @brief Change Rx Buffer.
- * @param hcec CEC handle
- * @param Rxbuffer Rx Buffer
- * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
- * @retval Frame size
- */
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
-{
- hcec->Init.RxBuffer = Rxbuffer;
-}
-
-/**
- * @brief This function handles CEC interrupt requests.
- * @param hcec CEC handle
- * @retval None
- */
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
-{
-
- /* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg = 0U;
- reg = hcec->Instance->ISR;
-
-
- /* ----------------------------Arbitration Lost Management----------------------------------*/
- /* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if((reg & CEC_FLAG_ARBLST) != RESET)
- {
- hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
- }
-
- /* ----------------------------Rx Management----------------------------------*/
- /* CEC RX byte received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXBR) != RESET)
- {
- /* reception is starting */
- hcec->RxState = HAL_CEC_STATE_BUSY_RX;
- hcec->RxXferSize++;
- /* read received byte */
- *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
- }
-
- /* CEC RX end received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXEND) != RESET)
- {
- /* clear IT */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
-
- /* Rx process is completed, restore hcec->RxState to Ready */
- hcec->RxState = HAL_CEC_STATE_READY;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->Init.RxBuffer -= hcec->RxXferSize;
- HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
- hcec->RxXferSize = 0U;
- }
-
- /* ----------------------------Tx Management----------------------------------*/
- /* CEC TX byte request interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXBR) != RESET)
- {
- if (hcec->TxXferCount == 0U)
- {
- /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- }
- else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- hcec->TxXferCount--;
- }
- /* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- }
-
- /* CEC TX end interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXEND) != RESET)
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
-
- /* Tx process is ended, restore hcec->gState to Ready */
- hcec->gState = HAL_CEC_STATE_READY;
- /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hcec);
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- HAL_CEC_TxCpltCallback(hcec);
- }
-
- /* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
- {
- hcec->ErrorCode = reg;
- __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
-
-
- if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
- {
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- hcec->RxXferSize = 0U;
- hcec->RxState = HAL_CEC_STATE_READY;
- }
- else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
- {
- /* Set the CEC state ready to be able to start again the process */
- hcec->gState = HAL_CEC_STATE_READY;
- }
-
- /* Error Call Back */
- HAL_CEC_ErrorCallback(hcec);
- }
-
-}
-
-/**
- * @brief Tx Transfer completed callback
- * @param hcec CEC handle
- * @retval None
- */
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback
- * @param hcec CEC handle
- * @param RxFrameSize Size of frame
- * @retval None
- */
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- UNUSED(RxFrameSize);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC error callbacks
- * @param hcec CEC handle
- * @retval None
- */
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_ErrorCallback can be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
- * @brief CEC control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CEC.
- (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
-@endverbatim
- * @{
- */
-/**
- * @brief return the CEC state
- * @param hcec pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC module.
- * @retval HAL state
- */
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
-{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
- temp1 = hcec->gState;
- temp2 = hcec->RxState;
-
- return (HAL_CEC_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the CEC error code
- * @param hcec pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC.
- * @retval CEC Error Code
- */
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
-{
- return hcec->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
-
-#endif /* HAL_CEC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
deleted file mode 100644
index c98a42e591a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
+++ /dev/null
@@ -1,832 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_comp.c
- * @author MCD Application Team
- * @brief COMP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the COMP peripheral:
- * + Initialization and de-initialization functions
- * + Start/Stop operation functions in polling mode.
- * + Start/Stop operation functions in interrupt mode.
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
-================================================================================
- ##### COMP Peripheral features #####
-================================================================================
-
- [..]
- The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
- (#) The non inverting input and inverting input can be set to GPIO pins.
- For STM32F3xx devices please refer to the COMP peripheral section in corresponding
- Reference Manual.
-
- (#) The COMP output is available using HAL_COMP_GetOutputLevel()
- and can be set on GPIO pins.
- For STM32F3xx devices please refer to the COMP peripheral section in corresponding
- Reference Manual.
-
- (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...).
- For STM32F3xx devices please refer to the COMP peripheral section in corresponding
- Reference Manual.
-
- (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
- mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input.
-
- (#) The seven comparators have interrupt capability with wake-up
- from Sleep and Stop modes (through the EXTI controller):
- (++) COMP1 is internally connected to EXTI Line 21
- (++) COMP2 is internally connected to EXTI Line 22
- (++) COMP3 is internally connected to EXTI Line 29
- (++) COMP4 is internally connected to EXTI Line 30
- (++) COMP5 is internally connected to EXTI Line 31
- (++) COMP6 is internally connected to EXTI Line 32
- (++) COMP7 is internally connected to EXTI Line 33.
-
- From the corresponding IRQ handler, the right interrupt source can be retrieved with the
- adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
-
-
- ##### How to use this driver #####
-================================================================================
- [..]
- This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
-
- To use the comparator, perform the following steps:
-
- (#) Fill in the HAL_COMP_MspInit() to
- (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
- (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
- output to the GPIO pin
- (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and
- selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
- interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions.
-
- (#) Configure the comparator using HAL_COMP_Init() function:
- (++) Select the inverting input (input minus)
- (++) Select the non-inverting input (input plus)
- (++) Select the output polarity
- (++) Select the output redirection
- (++) Select the hysteresis level
- (++) Select the power mode
- (++) Select the event/interrupt mode
-
- -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
- to enable the comparator(s).
-
- (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init(
- function with new input parameter values; HAL_COMP_MspInit() function shall be adapted
- to support multi configurations.
-
- (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions.
-
- (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
- to manage comparator outputs (events and output level).
-
- (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
- function.
-
- (#) De-initialize the comparator using HAL_COMP_DeInit() function.
-
- (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
- Only a MCU reset can reset that protection.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*
- Additional Tables:
-
- Table 1. COMP Inputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
- +------------------------------------------------------------------------------------------+
- | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |-----------------|----------------|---------------|---------------------------------------|
- | | 1U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 1U/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 3U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
- | | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
- | | IO1 | PA0 | PA2 | PD15U | PE8 | PD13U | PD10U | PC0 |
- | | IO2 | --- | --- | PB12U | PB2 | PB10U | PB15U | --- |
- |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
- | Non Inverting | IO1 | PA1 | PA7 | PB14U | PB0 | PD12U | PD11U | PA0 |
- | Input | IO2 | --- | PA3 | PD14U | PE7 | PB13U | PB11U | PC1 |
- +------------------------------------------------------------------------------------------+
-
- Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
- +-------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |-------|-------|-------|-------|-------|-------|-------|
- | PA0 | PA2 | PB1 | PC8 | PC7 | PA10U | PC2 |
- | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
- | PA6 | PA12U | --- | --- | --- | --- | --- |
- | PA11U | PB9 | --- | --- | --- | --- | --- |
- | PB8 | --- | --- | --- | --- | --- | --- |
- +-------------------------------------------------------+
-
- Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
- +----------------------------------------------------------------------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | | | | | | | |
- | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
- | | | | | | | |
- | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | + | + | + | + | + | + | + |
- | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
- | | | | | | | |
- | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
- | | | | | | | |
- | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
- | | | | | | | |
- | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
- | | | | | | | |
- | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
- | | | | | | | |
- | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
- | | | | | | | |
- | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
- +----------------------------------------------------------------------------------------------------------------------+
-
- Table 4. COMP Outputs redirection to embedded timers for the STM32F303xE devices
- +----------------------------------------------------------------------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | | | | | | | |
- | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) |
- | | | | | | | |
- | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | + | + | + | + | + | + | + |
- | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
- | | | | | | | |
- | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
- | | | | | | | |
- | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
- | | | | | | | |
- | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
- | | | | | | | |
- | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
- | | | | | | | |
- | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
- | | | | | | | |
- | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
- | | | | | | | |
- | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)|
- | | | | | | | |
- | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
- | | | | | | | |
- | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
- | + | + | + | + | + | + | + |
- | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
- | + | + | + | + | + | + | + |
- | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
- | | | | | | | |
- +----------------------------------------------------------------------------------------------------------------------+
- (1U): This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead
- of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to
- add a digital filter (3 bits) on the COMP output.
-
- Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices
- +----------------------------------------------------------------------------------------------------------------------+
- | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
- |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | -------- | TIM8 OC5 | TIM1 OC5 |
- | | | | | | | |
- | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM3 OC3 | TIM2 OC4 | TIM8 OC5 |
- | | | | | | | |
- | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 OC5 | TIM15 OC2 | TIM15 OC2 |
- | | | | | | | |
- +----------------------------------------------------------------------------------------------------------------------+
-
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup COMP COMP
- * @brief COMP HAL module driver
- * @{
- */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup COMP_Private_Constants COMP Private Constants
- * @{
- */
-#define COMP_LOCK_DISABLE (0x00000000U)
-#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Functions COMP Exported Functions
- * @{
- */
-
-/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and de-initialization functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions to initialize and de-initialize comparators.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the COMP peripheral according to the specified
- * parameters in the COMP_InitTypeDef and initialize the associated handle.
- * @note If the selected comparator is locked, initialization cannot be performed.
- * To unlock the configuration, perform a system reset.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
- assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
- assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
- assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
- assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
- assert_param(IS_COMP_OUTPUT_INSTANCE(hcomp->Instance, hcomp->Init.Output));
- assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
- assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
- assert_param(IS_COMP_MODE(hcomp->Init.Mode));
- assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
- assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
- assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
-
- if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
- {
- assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
- assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
- }
-
- /* Init SYSCFG and the low level hardware to access comparators */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- /* Init the low level hardware : SYSCFG to access comparators */
- HAL_COMP_MspInit(hcomp);
-
- if(hcomp->State == HAL_COMP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcomp->Lock = HAL_UNLOCKED;
- }
-
- /* Manage inverting input comparator inverting input connected to a GPIO */
- /* for STM32F302x, STM32F32xx, STM32F33x. */
- hcomp->Init.InvertingInput = COMP_INVERTINGINPUT_SELECTION(hcomp->Instance, hcomp->Init.InvertingInput);
-
- /* Set COMP parameters */
- /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
- /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
- /* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */
- /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
- /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
- /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
- /* Set COMPxMODE bits according to hcomp->Init.Mode value */
- COMP_INIT(hcomp);
-
- /* Initialize the COMP state*/
- hcomp->State = HAL_COMP_STATE_READY;
- }
-
- return status;
-}
-
-/**
- * @brief DeInitialize the COMP peripheral.
- * @note If the selected comparator is locked, deinitialization cannot be performed.
- * To unlock the configuration, perform a system reset.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- /* Set COMP_CSR register to reset value */
- COMP_DEINIT(hcomp);
-
- /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
- HAL_COMP_MspDeInit(hcomp);
-
- hcomp->State = HAL_COMP_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcomp);
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the COMP MSP.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the COMP MSP.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions
- * @brief Start-Stop operation functions.
- *
-@verbatim
- ===============================================================================
- ##### Start Stop operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start a comparator without interrupt generation.
- (+) Stop a comparator without interrupt generation.
- (+) Start a comparator with interrupt generation.
- (+) Stop a comparator with interrupt generation.
- (+) Handle interrupts from a comparator with associated callback function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t extiline = 0U;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if(hcomp->State == HAL_COMP_STATE_READY)
- {
- /* Get the EXTI Line output configuration */
- extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-
- /* Configure the event generation */
- if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING|COMP_TRIGGERMODE_EVENT_FALLING)) != RESET)
- {
- /* Configure the event trigger rising edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET)
- {
- COMP_EXTI_RISING_ENABLE(extiline);
- }
- else
- {
- COMP_EXTI_RISING_DISABLE(extiline);
- }
-
- /* Configure the trigger falling edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET)
- {
- COMP_EXTI_FALLING_ENABLE(extiline);
- }
- else
- {
- COMP_EXTI_FALLING_DISABLE(extiline);
- }
-
- /* Enable EXTI event generation */
- COMP_EXTI_ENABLE_EVENT(extiline);
-
- /* Clear COMP EXTI pending bit */
- COMP_EXTI_CLEAR_FLAG(extiline);
- }
-
- /* Enable the selected comparator */
- __HAL_COMP_ENABLE(hcomp);
-
- hcomp->State = HAL_COMP_STATE_BUSY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Stop the comparator.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if(hcomp->State == HAL_COMP_STATE_BUSY)
- {
- /* Disable the EXTI Line event mode if any */
- COMP_EXTI_DISABLE_EVENT(COMP_GET_EXTI_LINE(hcomp->Instance));
-
- /* Disable the selected comparator */
- __HAL_COMP_DISABLE(hcomp);
-
- hcomp->State = HAL_COMP_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Start the comparator in Interrupt mode.
- * @param hcomp COMP handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t extiline = 0U;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- if(hcomp->State == HAL_COMP_STATE_READY)
- {
- /* Configure the EXTI event generation */
- if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING|COMP_TRIGGERMODE_IT_FALLING)) != RESET)
- {
- /* Get the EXTI Line output configuration */
- extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-
- /* Configure the trigger rising edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
- {
- COMP_EXTI_RISING_ENABLE(extiline);
- }
- else
- {
- COMP_EXTI_RISING_DISABLE(extiline);
- }
- /* Configure the trigger falling edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
- {
- COMP_EXTI_FALLING_ENABLE(extiline);
- }
- else
- {
- COMP_EXTI_FALLING_DISABLE(extiline);
- }
-
- /* Clear COMP EXTI pending bit if any */
- COMP_EXTI_CLEAR_FLAG(extiline);
-
- /* Enable EXTI interrupt mode */
- COMP_EXTI_ENABLE_IT(extiline);
-
- /* Enable the selected comparator */
- __HAL_COMP_ENABLE(hcomp);
-
- hcomp->State = HAL_COMP_STATE_BUSY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Stop the comparator in Interrupt mode.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Disable the EXTI Line interrupt mode */
- COMP_EXTI_DISABLE_IT(COMP_GET_EXTI_LINE(hcomp->Instance));
-
- status = HAL_COMP_Stop(hcomp);
-
- return status;
-}
-
-/**
- * @brief Comparator IRQ Handler.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
-{
- uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-
- /* Check COMP EXTI flag */
- if(COMP_EXTI_GET_FLAG(extiline) != RESET)
- {
- /* Clear COMP EXTI pending bit */
- COMP_EXTI_CLEAR_FLAG(extiline);
-
- /* COMP trigger user callback */
- HAL_COMP_TriggerCallback(hcomp);
- }
-}
-
-/**
- * @brief Comparator callback.
- * @param hcomp COMP handle
- * @retval None
- */
-__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcomp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_COMP_TriggerCallback should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
- * @brief Management functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the comparators.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected comparator configuration.
- * @note A system reset is required to unlock the comparator configuration.
- * @param hcomp COMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the COMP handle allocation and lock status */
- if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- /* Set lock flag on state */
- switch(hcomp->State)
- {
- case HAL_COMP_STATE_BUSY:
- hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
- break;
- case HAL_COMP_STATE_READY:
- hcomp->State = HAL_COMP_STATE_READY_LOCKED;
- break;
- default:
- /* unexpected state */
- status = HAL_ERROR;
- break;
- }
- }
-
- if(status == HAL_OK)
- {
- /* Set the lock bit corresponding to selected comparator */
- __HAL_COMP_LOCK(hcomp);
- }
-
- return status;
-}
-
-/**
- * @brief Return the output level (high or low) of the selected comparator.
- * The output level depends on the selected polarity.
- * If the polarity is not inverted:
- * - Comparator output is low when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is high when the non-inverting input is at a higher
- * voltage than the inverting input
- * If the polarity is inverted:
- * - Comparator output is high when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is low when the non-inverting input is at a higher
- * voltage than the inverting input
- * @param hcomp COMP handle
- * @retval Returns the selected comparator output level:
- * @arg @ref COMP_OUTPUTLEVEL_LOW
- * @arg @ref COMP_OUTPUTLEVEL_HIGH
- *
- */
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
-{
- uint32_t level=0U;
-
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
-
- if(level != 0U)
- {
- return(COMP_OUTPUTLEVEL_HIGH);
- }
- return(COMP_OUTPUTLEVEL_LOW);
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the COMP handle state.
- * @param hcomp COMP handle
- * @retval HAL state
- */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
-{
- /* Check the COMP handle allocation */
- if(hcomp == NULL)
- {
- return HAL_COMP_STATE_RESET;
- }
-
- /* Check the parameter */
- assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
- /* Return COMP handle state */
- return hcomp->State;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
deleted file mode 100644
index c12c78bc4ff..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
+++ /dev/null
@@ -1,529 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_cortex.c
- * @author MCD Application Team
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- * @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M4 exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
-
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
-
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
-
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
- The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure Systick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base
-
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
- is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
- inside the stm32f3xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*
- Additional Tables: CORTEX_NVIC_Priority_Table
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ==========================================================================================================================
-
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX CORTEX HAL module driver
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts
- Systick functionalities
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Sets the priority grouping field (pre-emption priority and subpriority)
- * using the required unlock sequence.
- * @param PriorityGroup The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Sets the priority of an interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @param PreemptPriority The pre-emption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
- * A lower priority value indicates a higher priority
- * @param SubPriority the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enables a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiates a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void)
-{
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- * Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-
-/**
- * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
- * @retval None
- */
-void HAL_MPU_Disable(void)
-{
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU */
- MPU->CTRL = 0U;
-}
-
-/**
- * @brief Enables the MPU
- * @param MPU_Control Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-
- /**
- * @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Gets the priority of an interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @param PriorityGroup: the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
- * 0 bits for subpriority
- * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
- * @brief Sets Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC
- * and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- /* Return 1 if pending else 0U */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
- /* Return 1 if active else 0U */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param CLKSource specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
- {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }
- else
- {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief This function handles SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void)
-{
- HAL_SYSTICK_Callback();
-}
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
deleted file mode 100644
index 39c600f66a2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_crc.c
- * @author MCD Application Team
- * @brief CRC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
- (+) Initialize CRC calculator
- (++)specify generating polynomial (IP default or non-default one)
- (++)specify initialization value (IP default or non-default one)
- (++)specify input data format
- (++)specify input or output data inversion mode if any
- (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
- input data buffer starting with the previously computed CRC as
- initialization value
- (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
- input data buffer starting with the defined initialization value
- (default or non-default) to initiate CRC calculation
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRC CRC
- * @brief CRC HAL module driver.
- * @{
- */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRC according to the specified parameters
- in the CRC_InitTypeDef and create the associated handle
- (+) DeInitialize the CRC peripheral
- (+) Initialize the CRC MSP (MCU Specific Package)
- (+) DeInitialize the CRC MSP
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the CRC according to the specified
- * parameters in the CRC_InitTypeDef and initialize the associated handle.
- * @param hcrc CRC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- if(hcrc->State == HAL_CRC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcrc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_CRC_MspInit(hcrc);
- }
-
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* check whether or not non-default generating polynomial has been
- * picked up by user */
- assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
- if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
- {
- /* initialize IP with default generating polynomial */
- WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
- }
- else
- {
- /* initialize CRC IP with generating polynomial defined by user */
- if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
-
- /* check whether or not non-default CRC initial value has been
- * picked up by user */
- assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
- if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
- {
- WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
- }
- else
- {
- WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
- }
-
-
- /* set input data inversion mode */
- assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
-
- /* set output data inversion mode */
- assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
-
- /* makes sure the input data format (bytes, halfwords or words stream)
- * is properly specified by user */
- assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the CRC peripheral.
- * @param hcrc CRC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- /* Check the CRC peripheral state */
- if(hcrc->State == HAL_CRC_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC calculation unit */
- __HAL_CRC_DR_RESET(hcrc);
-
- /* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
-
- /* DeInit the low level hardware */
- HAL_CRC_MspDeInit(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_RESET;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRC MSP.
- * @param hcrc CRC handle
- * @retval None
- */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CRC_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the CRC MSP.
- * @param hcrc CRC handle
- * @retval None
- */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CRC_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
- using the combination of the previous CRC value and the new one
-
- [..] or
-
- (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
- independently of the previous CRC value.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- * starting with the previously computed CRC as initialization value.
- * @param hcrc CRC handle
- * @param pBuffer pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
- * @param BufferLength input data buffer length (number of bytes if pBuffer
- * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
- * number of words if pBuffer type is * uint32_t).
- * @note By default, the API expects a uint32_t pointer as input buffer parameter.
- * Input buffer pointers with other types simply need to be cast in uint32_t
- * and the API will internally adjust its input data processing based on the
- * handle field hcrc->InputDataFormat.
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0U; /* CRC input data buffer index */
- uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- switch (hcrc->InputDataFormat)
- {
- case CRC_INPUTDATA_FORMAT_WORDS:
- /* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
- temp = hcrc->Instance->DR;
- break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
- break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
- break;
-
- default:
- break;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return temp;
-}
-
-
-/**
- * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
- * starting with hcrc->Instance->INIT as initialization value.
- * @param hcrc CRC handle
- * @param pBuffer pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
- * @param BufferLength input data buffer length (number of bytes if pBuffer
- * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
- * number of words if pBuffer type is * uint32_t).
- * @note By default, the API expects a uint32_t pointer as input buffer parameter.
- * Input buffer pointers with other types simply need to be cast in uint32_t
- * and the API will internally adjust its input data processing based on the
- * handle field hcrc->InputDataFormat.
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0U; /* CRC input data buffer index */
- uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
- * written in hcrc->Instance->DR) */
- __HAL_CRC_DR_RESET(hcrc);
-
- switch (hcrc->InputDataFormat)
- {
- case CRC_INPUTDATA_FORMAT_WORDS:
- /* Enter 32-bit input data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
- temp = hcrc->Instance->DR;
- break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
- /* Specific 8-bit input data handling */
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
- break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
- /* Specific 16-bit input data handling */
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
- break;
-
- default:
- break;
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return temp;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the CRC handle state.
- * @param hcrc CRC handle
- * @retval HAL state
- */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
- /* Return CRC handle state */
- return hcrc->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
-
-/**
- * @brief Enter 8-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc CRC handle
- * @param pBuffer pointer to the input data buffer
- * @param BufferLength input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0U; /* input data buffer index */
-
- /* Processing time optimization: 4 bytes are entered in a row with a single word write,
- * last bytes must be carefully fed to the CRC calculator to ensure a correct type
- * handling by the IP */
- for(i = 0U; i < (BufferLength/4U); i++)
- {
- hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
- }
- /* last bytes specific handling */
- if ((BufferLength%4U) != 0U)
- {
- if (BufferLength%4U == 1U)
- {
- *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
- }
- if (BufferLength%4U == 2U)
- {
- *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
- }
- if (BufferLength%4U == 3U)
- {
- *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
- *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
- }
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-
-
-/**
- * @brief Enter 16-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc CRC handle
- * @param pBuffer pointer to the input data buffer
- * @param BufferLength input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0U; /* input data buffer index */
-
- /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
- * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
- * a correct type handling by the IP */
- for(i = 0U; i < (BufferLength/2U); i++)
- {
- hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
- }
- if ((BufferLength%2U) != 0U)
- {
- *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
deleted file mode 100644
index c89b975f62d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_crc_ex.c
- * @author MCD Application Team
- * @brief Extended CRC HAL module driver.
- * This file provides firmware functions to manage the extended
- * functionalities of the CRC peripheral.
- *
- @verbatim
-================================================================================
- ##### How to use this driver #####
-================================================================================
- [..]
- (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
- (+) Configure Input or Output data inversion
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRCEx CRCEx
- * @brief CRC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
- * @{
- */
-
-/** @defgroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
- * @brief CRC Extended Initialization and Configuration functions.
- *
-@verbatim
- ===============================================================================
- ##### Extended configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the generating polynomial
- (+) Configure the input data inversion
- (+) Configure the output data inversion
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initialize the CRC polynomial if different from default one.
- * @param hcrc CRC handle
- * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
- * This parameter is written in normal representation, e.g.
- * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
- * @param PolyLength CRC polynomial length.
- * This parameter can be one of the following values:
- * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
- * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
- * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
- * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
-{
- uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
-
- /* Check the parameters */
- assert_param(IS_CRC_POL_LENGTH(PolyLength));
-
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U)){}
-
- switch (PolyLength)
- {
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- break;
- }
-
- /* set generating polynomial */
- WRITE_REG(hcrc->Instance->POL, Pol);
-
- /* set generating polynomial size */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the Reverse Input data mode.
- * @param hcrc CRC handle
- * @param InputReverseMode Input Data inversion mode.
- * This parameter can be one of the following values:
- * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
- * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
-{
- /* Check the parameters */
- assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* set input data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the Reverse Output data mode.
- * @param hcrc CRC handle
- * @param OutputReverseMode Output Data inversion mode.
- * This parameter can be one of the following values:
- * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
- * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
-{
- /* Check the parameters */
- assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* set output data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
deleted file mode 100644
index 15941680004..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
+++ /dev/null
@@ -1,772 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_dac.c
- * @author MCD Application Team
- * @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Digital to Analog Converter (DAC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- *
- @verbatim
- ==============================================================================
- ##### DAC Peripheral features #####
- ==============================================================================
- [..]
- *** DAC Channels ***
- ====================
- [..]
- The device integrates up to 3 12-bit Digital Analog Converters that can
- be used independently or simultaneously (dual mode):
- (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
- (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
- (for STM32F3 devices having 2 channels on DAC1)
- (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
- (for STM32F3 devices having 2 DAC)
-
- *** DAC Triggers ***
- ====================
- [..]
- Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
- and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
- [..]
- Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
- The used pin (GPIOx_PIN_9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
- (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
- (#) Software using DAC_TRIGGER_SOFTWARE
-
- *** DAC Buffer mode feature ***
- ===============================
- [..]
- Each DAC channel integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
- Or
- An output switch
- (in STM32F303x4, STM32F303x6, STM32F303x8
- c, STM32F334x6, STM32F334x8
- & STM32F334xx).
- To enable, the output switch
- sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
- [..]
- (@) Refer to the device datasheet for more details about output
- impedance value with and without output buffer.
-
- *** GPIO configurations guidelines ***
- =====================
- [..]
- When a DAC channel is used (ex channel1 on PA4) and the other is not
- (ex channel2 on PA5 is configured in Analog and disabled).
- Channel1 may disturb channel2 as coupling effect.
- Note that there is no coupling on channel2 as soon as channel2 is turned on.
- Coupling on adjacent channel could be avoided as follows:
- when unused PA5 is configured as INPUT PULL-UP or DOWN.
- PA5 is configured in ANALOG just before it is turned on.
-
-
- *** DAC wave generation feature ***
- ===================================
- [..]
- Both DAC channels of DAC1 can be used to generate
- note that wave generation is not available in DAC2.
- (#) Noise wave
- (#) Triangle wave
-
- Wave generation is NOT available in DAC2.
-
- *** DAC data format ***
- =======================
- [..]
- The DAC data format can be:
- (#) 8-bit right alignment using DAC_ALIGN_8B_R
- (#) 12-bit left alignment using DAC_ALIGN_12B_L
- (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
- *** DAC data value to voltage correspondance ***
- ================================================
- [..]
- The analog output voltage on each DAC channel pin is determined
- by the following equation:
- [..]
- DAC_OUTx = VREF+ * DOR / 4095
- (+) with DOR is the Data Output Register
- [..]
- VEF+ is the input voltage reference (refer to the device datasheet)
- [..]
- e.g. To set DAC_OUT1 to 0.7V, use
- (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
-
- *** DMA requests ***
- =====================
- [..]
- A DMA1 or DMA2 request can be generated when an external trigger
- (but not a software trigger) occurs if DMA1 or DMA2 requests are
- enabled using HAL_DAC_Start_DMA().
- [..]
- DMA1 requests are mapped as following:
- (#) DAC1 channel1: mapped either on
- (++) DMA1 channel3
- (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
- which must be already configured
- (#) DAC1 channel2:
- (for STM32F3 devices having 2 channels on DAC1)
- mapped either on
- (++) DMA1 channel4
- (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
- which must be already configured
-
- (#) DAC2 channel1: mapped either on
- (for STM32F3 devices having 2 DAC)
- (++) DMA1 channel4
- (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
- which must be already configured
-
-
- (@) For Dual mode and specific signal (Triangle and noise) generation please
- refer to Extended Features Driver description
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) DAC APB clock must be enabled to get write access to DAC
- registers using HAL_DAC_Init()
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
- (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
- (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
- (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
- (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
- (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
- (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
- *** DAC HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DAC HAL driver.
-
- (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
- (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
- (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
- (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
- [..]
- (@) You can refer to the DAC HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DAC DAC
- * @brief DAC HAL module driver
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
- * @{
- */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DAC.
- (+) De-initialize the DAC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct and initialize the associated handle.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- if(hdac->State == HAL_DAC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdac->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_DAC_MspInit(hdac);
- }
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitialize the DAC peripheral registers to their default reset values.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_DAC_MspDeInit(hdac);
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_DAC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
- (+) Get result of dual mode conversion.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- UNUSED(Channel);
-
- /* Note : This function is defined into this file for library reference */
- /* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Disable the DMA channel */
- /* Channel1 is used */
- if (Channel == DAC_CHANNEL_1)
- {
- /* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
- }
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
- /* For all products including channel 2U */
- /* DAC channel 2 is available on top of DAC channel 1U */
- else /* Channel2 is used for */
- {
- /* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
- }
-#endif
-
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval The selected DAC channel data output value.
- */
-__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- UNUSED(Channel);
-
- /* Note : This function is defined into this file for library reference */
- /* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval The selected DAC channel data output value.
- */
-__weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* Note : This function is defined into this file for library reference */
- /* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Configure Triangle wave generation.
- (+) Configure Noise wave generation.
- (+) Set the specified data holding register value for DAC channel.
- (+) Set the specified data holding register value for Dual DAC channels.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig DAC configuration structure.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval HAL status
- */
-
-__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- UNUSED(sConfig);
- UNUSED(Channel);
-
- /* Return function status */
- return HAL_OK;
-}
-
-__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- UNUSED(Channel);
- UNUSED(Alignment);
- UNUSED(Data);
-
- /* Note : This function is defined into this file for library reference */
- /* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- UNUSED(Alignment);
- UNUSED(Data1);
- UNUSED(Data2);
-
- /* Note : This function is defined into this file for library reference */
- /* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief DAC Peripheral State and Error functions
- *
-@verbatim
- ==============================================================================
- ##### DAC Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DAC state.
- (+) Check the DAC Errors.
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the DAC handle state
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL state
- */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
- /* Return DAC handle state */
- return hdac->State;
-}
-
-/**
- * @brief Return the DAC error code
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval DAC Error Code
- */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
- return hdac->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-
-/**
- * @brief Conversion complete callback in non blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallback could be implemented in the user file
- */
-}
-
-
-/**
- * @brief DMA underrun DAC callback for Channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
deleted file mode 100644
index 5536cd2e28a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
+++ /dev/null
@@ -1,1144 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_dac_ex.c
- * @author MCD Application Team
- * @brief DACEx HAL module driver.
- * This file provides firmware functions to manage the extended
- * functionalities of the DAC peripheral.
- *
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
- Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
- HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
- (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
- (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/** @defgroup DACEx DACEx
- * @brief DAC HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx Private Functions
- * @{
- */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1U */
-static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
- * @{
- */
-
-/** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Set the specified data holding register value for DAC channel.
- (+) Set the specified data holding register value for dual DAC channel
- (when DAC channel 2 is present in DAC 1U)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified data holding register value for DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * @param Alignment Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data Data to be loaded in the selected data holding register.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- __IO uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t) (hdac->Instance);
-
-/* DAC 1 has 1 or 2 channels - no DAC2 */
-/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
-
- if(Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
- }
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
- else /* channel = DAC_CHANNEL_2 */
- {
- tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
- }
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is present in DAC 1U */
-/**
- * @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Alignment Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
- uint32_t data = 0U, tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (Alignment == DAC_ALIGN_8B_R)
- {
- data = ((uint32_t)Data2 << 8U) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16U) | Data1;
- }
-
- tmp = (uint32_t) (hdac->Instance);
- tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Get result of conversion.
- (+) Handle DAC IRQ's.
- (+) Generate triangular-wave
- (+) Generate noise-wave
- (+) Callback functions for DAC1 Channel2 (when supported)
-@endverbatim
- * @{
- */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
- }
- }
- else
- {
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
- }
- }
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channels 1U */
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
- }
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC 1 has 2 channels 1U & 2U */
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @param pData The destination peripheral Buffer address.
- * @param Length The length of data to be transferred from memory to DAC peripheral
- * @param Alignment Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1U */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
- }
- else
- {
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
- /* Enable the selected DAC channel2 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Case of use of channel 2U */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
- break;
- default:
- break;
- }
- }
-
- /* Enable the DMA Channel */
- if(Channel == DAC_CHANNEL_1)
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- }
- else
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channel (channel 1U) */
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @param pData The destination peripheral Buffer address.
- * @param Length The length of data to be transferred from memory to DAC peripheral
- * @param Alignment Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1U */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
-
- /* Enable the DMA Channel */
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Enable the Peripheral */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC 1 has 2 channels 1U & 2U */
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Returns the DAC channel data output register value */
- if(Channel == DAC_CHANNEL_1)
- {
- return hdac->Instance->DOR1;
- }
- else /* channel = DAC_CHANNEL_2 */
- {
- return hdac->Instance->DOR2;
- }
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channel (channel 1U) */
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
- /* Returns the DAC channel data output register value */
- return hdac->Instance->DOR1;
-}
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Return the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
- uint32_t tmp = 0U;
-
- tmp |= hdac->Instance->DOR1;
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is present in DAC 1U */
- tmp |= hdac->Instance->DOR2 << 16U;
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
- /* Returns the DAC channel data output register value */
- return tmp;
-}
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1U */
-/**
- * @brief Handles DAC interrupt request
- * This function uses the interruption of DMA
- * underrun.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
-{
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
- {
- /* Check underrun flag of DAC channel 1U */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to chanel1 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
- }
- }
-
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
- {
- /* Check underrun flag of DAC channel 1U */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to channel2 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Error callback */
- HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
- }
- }
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
-/**
- * @brief Handles DAC interrupt request
- * This function uses the interruption of DMA
- * underrun.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
-{
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
- {
- /* Check underrun flag of DAC channel 1U */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to chanel1 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
- }
- }
-}
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @brief Configures the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig DAC configuration structure.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
- uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
- if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
- {
- /* Output Buffer (BOFF1) control */
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- }
- else /* DAC1 channel 2U & DAC2 channel 1U */
- {
- /* Output Switch (OUTEN) control */
- assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
- }
-#else
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Get the DAC CR value */
- tmpreg1 = hdac->Instance->CR;
-
- /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
-
- /* Configure for the selected DAC channel: buffer output or switch output, trigger */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set BOFFx bit according to DAC_OutputBuffer value OR */
- /* Set OUTEN bit according to DAC_OutputSwitch value */
-#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
- if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
- {
- /* Output Buffer (BOFF1) control */
- tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
- tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
- }
- else /* DAC1 channel 2U & DAC2 channel 1U */
- {
- /* Output Switch (OUTEN) control */
- tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
- tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
- }
-#else
- tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
- tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
-
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << Channel;
- /* Write to DAC CR */
- hdac->Instance->CR = tmpreg1;
-
- /* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @param Amplitude Select max triangle amplitude.
- * This parameter can be one of the following values:
- * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
- * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
- * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
- * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
- * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
- * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
- * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
- * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
- * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
- * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
- * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
- * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
- * @note Wave generation is not available in DAC2.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
- circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and initialize the associated handle.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp = 0U;
-
- /* Check the DMA handle allocation */
- if(NULL == hdma)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
- tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
- DMA_CCR_DIR));
-
- /* Prepare the DMA Channel configuration */
- tmp |= hdma->Init.Direction |
- hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
- /* Initialize DmaBaseAddress and ChannelIndex parameters used
- by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
- DMA_CalcBaseAndBitshift(hdma);
-
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
- /* Initialise the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the DMA peripheral
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
- /* Check the DMA handle allocation */
- if(NULL == hdma)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* Disable the selected DMA Channelx */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Reset DMA Channel control register */
- hdma->Instance->CCR = 0U;
-
- /* Reset DMA Channel Number of Data to Transfer register */
- hdma->Instance->CNDTR = 0U;
-
- /* Reset DMA Channel peripheral address register */
- hdma->Instance->CPAR = 0U;
-
- /* Reset DMA Channel memory address register */
- hdma->Instance->CMAR = 0U;
-
- /* Get DMA Base Address */
- DMA_CalcBaseAndBitshift(hdma);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
-
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete, & transfer error interrupts */
- /* Half transfer interrupt is optional: enable it only if associated callback is available */
- if(NULL != hdma->XferHalfCpltCallback )
- {
- hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
- }
- else
- {
- hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
-
- return status;
-}
-
-/**
- * @brief Abort the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- /* Disable DMA IT */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
- /* Disable the channel */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-
- /* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- status = HAL_ERROR;
- }
- else
- {
-
- /* Disable DMA IT */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
- /* Disable the channel */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- }
- return status;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CompleteLevel Specifies the DMA level complete.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
- uint32_t temp;
- uint32_t tickstart = 0U;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
- return HAL_ERROR;
- }
-
- /* Polling mode not supported in circular mode */
- if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
- {
- /* Transfer Complete flag */
- temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
- }
- else
- {
- /* Half Transfer Complete flag */
- temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(RESET == (hdma->DmaBaseAddress->ISR & temp))
- {
- if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- }
- }
-
- if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
- {
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- hdma->State = HAL_DMA_STATE_READY;
- }
- else
- {
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle DMA interrupt request.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
- uint32_t source_it = hdma->Instance->CCR;
-
- /* Half Transfer Complete Interrupt management ******************************/
- if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* State is updated only in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
-
- /* Transfer Complete Interrupt management ***********************************/
- else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
- {
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete & transfer error interrupts */
- /* if the DMA mode is not CIRCULAR */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
-
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
-
- /* Transfer Error Interrupt management ***************************************/
- else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Then, disable all DMA interrupts */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
-}
-
-/**
- * @brief Register callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callback function which has pointer to
- * a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the DMA state.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
- return hdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Set the DMA Transfer parameters.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress The source memory Buffer address
- * @param DstAddress The destination memory Buffer address
- * @param DataLength The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-
- /* Configure DMA Channel data length */
- hdma->Instance->CNDTR = DataLength;
-
- /* Peripheral to Memory */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Channel destination address */
- hdma->Instance->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- hdma->Instance->CMAR = SrcAddress;
- }
- /* Memory to Peripheral */
- else
- {
- /* Configure DMA Channel source address */
- hdma->Instance->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- hdma->Instance->CMAR = DstAddress;
- }
-}
-
-/**
- * @brief Set the DMA base address and channel index depending on DMA instance
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval None
- */
-static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
-{
-#if defined (DMA2)
- /* calculation of the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA2;
- }
-#else
- /* calculation of the channel index */
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
- hdma->DmaBaseAddress = DMA1;
-#endif
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
deleted file mode 100644
index 430bf3f8033..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_flash.c
- * @author MCD Application Team
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory operations
- and the read and write protection mechanisms.
-
- [..] The Flash memory interface accelerates code execution with a system of instruction
- prefetch.
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Prefetch on I-Code
- (+) Option Bytes programming
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the FLASH
- memory of all STM32F3xx devices.
-
- (#) FLASH Memory I/O Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the FLASH interface
- (++) Erase function: Erase page, erase all pages
- (++) Program functions: half word, word and doubleword
- (#) FLASH Option Bytes Programming functions: this group includes all needed
- functions to manage the Option Bytes:
- (++) Lock and Unlock the Option Bytes
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user Option Bytes
- (++) Launch the Option Bytes loader
- (++) Erase Option Bytes
- (++) Program the data Option Bytes
- (++) Get the Write protection.
- (++) Get the user option bytes.
-
- (#) Interrupts and flags management functions : this group
- includes all needed functions to:
- (++) Handle FLASH interrupts
- (++) Wait for last FLASH operation according to its status
- (++) Get error flag status
-
- [..] In addition to these function, this driver includes a set of macros allowing
- to handle the following operations:
-
- (+) Set/Get the latency
- (+) Enable/Disable the prefetch buffer
- (+) Enable/Disable the half cycle access
- (+) Enable/Disable the FLASH interrupts
- (+) Monitor the FLASH flags status
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro ---------------------------- ---------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void FLASH_SetErrorCode(void);
-extern void FLASH_PageErase(uint32_t PageAddress);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program halfword, word or double word at a specified address
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @note FLASH should be previously erased before new programmation (only exception to this
- * is when 0x0000 is programmed)
- *
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address Specifie the address to be programmed.
- * @param Data Specifie the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint8_t index = 0U;
- uint8_t nbiterations = 0U;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- /* Program halfword (16-bit) at a specified address. */
- nbiterations = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- /* Program word (32-bit = 2*16-bit) at a specified address. */
- nbiterations = 2U;
- }
- else
- {
- /* Program double word (64-bit = 4*16-bit) at a specified address. */
- nbiterations = 4U;
- }
-
- for (index = 0U; index < nbiterations; index++)
- {
- FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
- /* In case of error, stop programation procedure */
- if (status != HAL_OK)
- {
- break;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Program halfword, word or double word at a specified address with interrupt enabled.
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param TypeProgram Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address Specifie the address to be programmed.
- * @param Data Specifie the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
- pFlash.Address = Address;
- pFlash.Data = Data;
-
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
- /* Program halfword (16-bit) at a specified address. */
- pFlash.DataRemaining = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
- /* Program word (32-bit : 2*16-bit) at a specified address. */
- pFlash.DataRemaining = 2U;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
- /* Program double word (64-bit : 4*16-bit) at a specified address. */
- pFlash.DataRemaining = 4U;
- }
-
- /* Program halfword (16-bit) at a specified address. */
- FLASH_Program_HalfWord(Address, (uint16_t)Data);
-
- return status;
-}
-
-/**
- * @brief This function handles FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void)
-{
- uint32_t addresstmp = 0U;
-
- /* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
- {
- /* Return the faulty address */
- addresstmp = pFlash.Address;
- /* Reset address */
- pFlash.Address = 0xFFFFFFFFU;
-
- /* Save the Error code */
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(addresstmp);
-
- /* Stop the procedure ongoing */
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH End of Operation flag */
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
- /* Process can continue only if no error detected */
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still pages to erase */
- if(pFlash.DataRemaining != 0U)
- {
- addresstmp = pFlash.Address;
- /*Indicate user which sector has been erased */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
-
- /*Increment sector number*/
- addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
- pFlash.Address = addresstmp;
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /* No more pages to Erase, user callback can be called. */
- /* Reset Sector and stop Erase pages procedure */
- pFlash.Address = addresstmp = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
- }
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /* Operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
-
- /* MassErase ended. Return the selected bank */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0U);
-
- /* Stop Mass Erase procedure*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0U)
- {
- /* Increment address to 16-bit */
- pFlash.Address += 2U;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16U);
-
- /* Operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /* Program ended. Return the selected address */
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
- }
- else
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
- }
-
- /* Reset Address and stop Program procedure */
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- }
- }
-
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
- {
- /* Operation is completed, disable the PG, PER and MER Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
-
- /* Disable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-}
-
-/**
- * @brief FLASH end of operation interrupt callback
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which returned an error
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
- if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
- {
- /* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
- {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Lock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
- /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @note This function will reset automatically the MCU.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
- /* Set the OBL_Launch bit to launch the option byte loading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
-
- /* Wait for last operation to be completed */
- return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
- * @brief Peripheral errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode The returned value can be:
- * @ref FLASH_Error_Codes
- */
-uint32_t HAL_FLASH_GetError(void)
-{
- return pFlash.ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Program a half-word (16-bit) at a specified address.
- * @param Address specify the address to be programmed.
- * @param Data specify the data to be programmed.
- * @retval None
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-
- /* Write data in the address */
- *(__IO uint16_t*)Address = Data;
-}
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
- {
- /*Save the error code*/
- FLASH_SetErrorCode();
- return HAL_ERROR;
- }
-
- /* There is no error flag set */
- return HAL_OK;
-}
-
-
-/**
- * @brief Set the specific FLASH error flag.
- * @retval None
- */
-static void FLASH_SetErrorCode(void)
-{
- uint32_t flags = 0U;
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
- flags |= FLASH_FLAG_WRPERR;
- }
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
- flags |= FLASH_FLAG_PGERR;
- }
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(flags);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
deleted file mode 100644
index f0a42842939..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_flash_ex.c
- * @author MCD Application Team
- * @brief Extended FLASH HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * + Extended Initialization/de-initialization functions
- * + Extended I/O operation functions
- * + Extended Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### Flash peripheral extended features #####
- ==============================================================================
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32F3xxx devices. It includes
-
- (++) Set/Reset the write protection
- (++) Program the user Option Bytes
- (++) Get the Read protection Level
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
- * @{
- */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH HAL Extension module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
- * @{
- */
-#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
-#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
-#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-/* Erase operations */
-static void FLASH_MassErase(void);
-void FLASH_PageErase(uint32_t PageAddress);
-
-/* Option bytes control */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
-static uint32_t FLASH_OB_GetWRP(void);
-static uint32_t FLASH_OB_GetRDP(void);
-static uint8_t FLASH_OB_GetUser(void);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
- * @{
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
- * @brief FLASH Memory Erasing functions
- *
-@verbatim
- ==============================================================================
- ##### FLASH Erasing Programming functions #####
- ==============================================================================
-
- [..] The FLASH Memory Erasing functions, includes the following functions:
- (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
- (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
- is called with parameter 0xFFFFFFFF
-
- [..] Any operation of erase should follow these steps:
- (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
- program memory access.
- (#) Call the desired function to erase page.
- (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
- (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @param[out] PageError pointer to variable that
- * contains the configuration information on faulty page in case of error
- * (0xFFFFFFFF means that all the pages have been correctly erased)
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t address = 0U;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /* Mass Erase requested for Bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Mass erase to be done*/
- FLASH_MassErase();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- }
- }
- else
- {
- /* Page Erase is requested */
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
- /* Page Erase requested on address located on bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- /* Erase page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
- address += FLASH_PAGE_SIZE)
- {
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* If procedure already ongoing, reject the next one */
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
- FLASH_MassErase();
- }
- else
- {
- /* Erase by page to be done*/
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
- pFlash.DataRemaining = pEraseInit->NbPages;
- pFlash.Address = pEraseInit->PageAddress;
-
- /*Erase 1st page and wait for IT*/
- FLASH_PageErase(pEraseInit->PageAddress);
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ==============================================================================
- ##### Option Bytes Programming functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- option bytes operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
-{
- uint8_t rdptmp = OB_RDP_LEVEL_0;
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Get the actual read protection Option Byte value */
- rdptmp = FLASH_OB_GetRDP();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Restore the last read protection Option Byte value */
- status = FLASH_OB_RDP_LevelConfig(rdptmp);
- }
- }
-
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Program option bytes
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- *
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- /* Write protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
- {
- assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
- {
- /* Enable of Write protection on the selected page */
- status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
- }
- else
- {
- /* Disable of Write protection on the selected page */
- status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
- }
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Read protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
- {
- status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* USER configuration */
- if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
- {
- status = FLASH_OB_UserConfig(pOBInit->USERConfig);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* DATA configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
- {
- status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option byte configuration
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
-
- /*Get WRP*/
- pOBInit->WRPPage = FLASH_OB_GetWRP();
-
- /*Get RDP Level*/
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /*Get USER*/
- pOBInit->USERConfig = FLASH_OB_GetUser();
-}
-
-/**
- * @brief Get the Option byte user data
- * @param DATAAdress Address of the option byte DATA
- * This parameter can be one of the following values:
- * @arg @ref OB_DATA_ADDRESS_DATA0
- * @arg @ref OB_DATA_ADDRESS_DATA1
- * @retval Value programmed in USER data
- */
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
-{
- uint32_t value = 0U;
-
- if (DATAAdress == OB_DATA_ADDRESS_DATA0)
- {
- /* Get value programmed in OB USER Data0 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
- }
- else
- {
- /* Get value programmed in OB USER Data1 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
- }
-
- return value;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Full erase of FLASH memory Bank
- *
- * @retval None
- */
-static void FLASH_MassErase(void)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Only bank1 will be erased*/
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @brief Enable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write protected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFFU;
-#if defined(OB_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFFU;
-#endif /* OB_WRP1_WRP1 */
-#if defined(OB_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFFU;
-#endif /* OB_WRP2_WRP2 */
-#if defined(OB_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFFU;
-#endif /* OB_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be protected ******/
- WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#endif /* OB_WRP_PAGES48TO63MASK */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- /* Enable write protection */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(OB_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 &= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP0_WRP0 */
-
-#if defined(OB_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 &= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP1_WRP1 */
-
-#if defined(OB_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 &= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP2_WRP2 */
-
-#if defined(OB_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 &= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write unprotected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFFU;
-#if defined(OB_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFFU;
-#endif /* OB_WRP1_WRP1 */
-#if defined(OB_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFFU;
-#endif /* OB_WRP2_WRP2 */
-#if defined(OB_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFFU;
-#endif /* OB_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be unprotected ******/
- WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#endif /* OB_WRP_PAGES48TO63MASK */
-
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(OB_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 |= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP0_WRP0 */
-
-#if defined(OB_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 |= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP1_WRP1 */
-
-#if defined(OB_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 |= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP2_WRP2 */
-
-#if defined(OB_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 |= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* OB_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
- return status;
-}
-
-/**
- * @brief Set the read protection level.
- * @param ReadProtectLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- * @arg @ref OB_RDP_LEVEL_2 Full chip protection
- * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
- WRITE_REG(OB->RDP, ReadProtectLevel);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Program the FLASH User Option Byte.
- * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
- * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
- * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
- assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
- assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
- assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
- assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
- assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
-#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
- assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
-#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
- OB->USER = (UserConfig | 0x08U);
-#else
- OB->USER = (UserConfig | 0x88U);
-#endif
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
-
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param Address specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data specifies the data to be programmed.
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enables the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- * @retval The FLASH Write Protection Option Bytes value
- */
-static uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(READ_REG(FLASH->WRPR));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @retval FLASH RDP level
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- * @arg @ref OB_RDP_LEVEL_2 Full chip protection
- */
-static uint32_t FLASH_OB_GetRDP(void)
-{
- uint32_t tmp_reg = 0U;
-
- /* Read RDP level bits */
-#if defined(FLASH_OBR_RDPRT)
- tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
-#endif
-#if defined(FLASH_OBR_LEVEL1_PROT)
- tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT));
-#endif /* FLASH_OBR_LEVEL1_PROT */
-
-#if defined(FLASH_OBR_RDPRT)
- if (tmp_reg == FLASH_OBR_RDPRT_1)
-#endif
-#if defined(FLASH_OBR_LEVEL1_PROT)
- if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
-#endif /* FLASH_OBR_LEVEL1_PROT */
- {
- return OB_RDP_LEVEL_1;
- }
-#if defined(FLASH_OBR_RDPRT)
- else if (tmp_reg == FLASH_OBR_RDPRT_2)
-#elif defined(FLASH_OBR_LEVEL2_PROT)
- else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
-#endif
- {
- return OB_RDP_LEVEL_2;
- }
- else
- {
- return OB_RDP_LEVEL_0;
- }
-}
-
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
- * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
- * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
- */
-static uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Erase the specified FLASH memory page
- * @param PageAddress FLASH page to erase
- * The value of this parameter depend on device used within the same series
- *
- * @retval None
- */
-void FLASH_PageErase(uint32_t PageAddress)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- WRITE_REG(FLASH->AR, PageAddress);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
deleted file mode 100644
index d205d19c2a4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
+++ /dev/null
@@ -1,547 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_gpio.c
- * @author MCD Application Team
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
- configured by software in several modes:
- (++) Input mode
- (++) Analog mode
- (++) Output mode
- (++) Alternate function mode
- (++) External interrupt/event lines
-
- (+) During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
-
- (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
- multiplexer that allows only one peripheral alternate function (AF) connected
- to an IO pin at a time. In this way, there can be no conflict between peripherals
- sharing the same IO pin.
-
- (+) All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- (+) The external interrupt/event controller consists of up to 23 edge detectors
- (16 lines are connected to GPIO) for generating event/interrupt requests (each
- input line can be independently configured to select the type (interrupt or event)
- and the corresponding trigger event (rising or falling or both). Each line can
- also be masked independently.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
- structure.
- (++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure.
- (++) In alternate mode is selection, the alternate function connected to the IO
- is configured through "Alternate" member from GPIO_InitTypeDef structure.
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member from
- GPIO_InitTypeDef structure select the type (interrupt or event) and
- the corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
- HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup GPIO_Private_Defines GPIO Private Defines
- * @{
- */
-#define GPIO_MODE (0x00000003U)
-#define EXTI_MODE (0x10000000U)
-#define GPIO_MODE_IT (0x00010000U)
-#define GPIO_MODE_EVT (0x00020000U)
-#define RISING_EDGE (0x00100000U)
-#define FALLING_EDGE (0x00200000U)
-#define GPIO_OUTPUT_TYPE (0x00000010U)
-
-#define GPIO_NUMBER (16U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- uint32_t position = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t temp = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- while (((GPIO_Init->Pin) >> position) != RESET)
- {
- /* Get current io position */
- iocurrent = (GPIO_Init->Pin) & (1U << position);
-
- if(iocurrent)
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
- temp |= (GPIO_Init->Speed << (position * 2U));
- GPIOx->OSPEEDR = temp;
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
- GPIOx->OTYPER = temp;
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
- temp |= ((GPIO_Init->Pull) << (position * 2U));
- GPIOx->PUPDR = temp;
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- temp = SYSCFG->EXTICR[position >> 2];
- temp &= ~((0x0FU) << (4U * (position & 0x03U)));
- temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
- SYSCFG->EXTICR[position >> 2] = temp;
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- temp |= iocurrent;
- }
- EXTI->IMR = temp;
-
- temp = EXTI->EMR;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- temp |= iocurrent;
- }
- EXTI->EMR = temp;
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- {
- temp |= iocurrent;
- }
- EXTI->RTSR = temp;
-
- temp = EXTI->FTSR;
- temp &= ~((uint32_t)iocurrent);
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- {
- temp |= iocurrent;
- }
- EXTI->FTSR = temp;
- }
- }
-
- position++;
- }
-}
-
-/**
- * @brief De-initialize the GPIOx peripheral registers to their default reset values.
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
-{
- uint32_t position = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t tmp = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Configure the port pins */
- while ((GPIO_Pin >> position) != RESET)
- {
- /* Get current io position */
- iocurrent = GPIO_Pin & (1U << position);
-
- if (iocurrent)
- {
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floting Mode */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-
-
- /*------------------------- EXTI Mode Configuration --------------------*/
- /* Clear the External Interrupt or Event for the current IO */
-
- tmp = SYSCFG->EXTICR[position >> 2];
- tmp &= ((0x0FU) << (4U * (position & 0x03U)));
- if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
- {
- tmp = (0x0FU) << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
- }
- }
-
- position++;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the specified input port pin.
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin specifies the port bit to read.
- * This parameter can be GPIO_PIN_x where x can be (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
- {
- bitstatus = GPIO_PIN_SET;
- }
- else
- {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Set or clear the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- *
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @param PinState specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = (uint32_t)GPIO_Pin;
- }
-}
-
-/**
- * @brief Toggle the specified GPIO pin.
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin specifies the pin to be toggled.
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-* @brief Lock GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next reset.
- * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- tmp |= GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Handle EXTI interrupt request.
- * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-}
-
-/**
- * @brief EXTI line detection callback.
- * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
deleted file mode 100644
index e3a0039f627..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
+++ /dev/null
@@ -1,8219 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_hrtim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Resolution Timer (HRTIM) peripheral:
- * + HRTIM Initialization
- * + DLL Calibration Start
- * + Timer Time Base Unit Configuration
- * + Simple Time Base Start/Stop
- * + Simple Time Base Start/Stop Interrupt
- * + Simple Time Base Start/Stop DMA Request
- * + Simple Output Compare/PWM Channel Configuration
- * + Simple Output Compare/PWM Channel Start/Stop Interrupt
- * + Simple Output Compare/PWM Channel Start/Stop DMA Request
- * + Simple Input Capture Channel Configuration
- * + Simple Input Capture Channel Start/Stop Interrupt
- * + Simple Input Capture Channel Start/Stop DMA Request
- * + Simple One Pulse Channel Configuration
- * + Simple One Pulse Channel Start/Stop Interrupt
- * + HRTIM External Synchronization Configuration
- * + HRTIM Burst Mode Controller Configuration
- * + HRTIM Burst Mode Controller Enabling
- * + HRTIM External Events Conditioning Configuration
- * + HRTIM Faults Conditioning Configuration
- * + HRTIM Faults Enabling
- * + HRTIM ADC trigger Configuration
- * + Waveform Timer Configuration
- * + Waveform Event Filtering Configuration
- * + Waveform Dead Time Insertion Configuration
- * + Waveform Chopper Mode Configuration
- * + Waveform Compare Unit Configuration
- * + Waveform Capture Unit Configuration
- * + Waveform Output Configuration
- * + Waveform Counter Start/Stop
- * + Waveform Counter Start/Stop Interrupt
- * + Waveform Counter Start/Stop DMA Request
- * + Waveform Output Enabling
- * + Waveform Output Level Set/Get
- * + Waveform Output State Get
- * + Waveform Burst DMA Operation Configuration
- * + Waveform Burst DMA Operation Start
- * + Waveform Timer Counter Software Reset
- * + Waveform Capture Software Trigger
- * + Waveform Burst Mode Controller Software Trigger
- * + Waveform Timer Pre-loadable Registers Update Enabling
- * + Waveform Timer Pre-loadable Registers Software Update
- * + Waveform Timer Delayed Protection Status Get
- * + Waveform Timer Burst Status Get
- * + Waveform Timer Push-Pull Status Get
- * + Peripheral State Get
- @verbatim
-==============================================================================
- ##### Simple mode v.s. waveform mode #####
-==============================================================================
- [..] The HRTIM HAL API is split into 2 categories:
- (#)Simple functions: these functions allow for using a HRTIM timer as a
- general purpose timer with high resolution capabilities.
- HRTIM simple modes are managed through the set of functions named
- HAL_HRTIM_Simple© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
-
-#if defined(STM32F334x8)
-
-/** @defgroup HRTIM HRTIM
- * @brief HRTIM HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup HRTIM_Private_Defines HRTIM Private Define
- * @{
- */
-#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
- HRTIM_FLTR_FLT2EN |\
- HRTIM_FLTR_FLT3EN |\
- HRTIM_FLTR_FLT4EN | \
- HRTIM_FLTR_FLT5EN)
-
-#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
- HRTIM_TIMUPDATETRIGGER_TIMER_A |\
- HRTIM_TIMUPDATETRIGGER_TIMER_B |\
- HRTIM_TIMUPDATETRIGGER_TIMER_C |\
- HRTIM_TIMUPDATETRIGGER_TIMER_D |\
- HRTIM_TIMUPDATETRIGGER_TIMER_E)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HRTIM_Private_Variables HRTIM Private Variables
- * @{
- */
-static uint32_t TimerIdxToTimerId[] =
-{
- HRTIM_TIMERID_TIMER_A,
- HRTIM_TIMERID_TIMER_B,
- HRTIM_TIMERID_TIMER_C,
- HRTIM_TIMERID_TIMER_D,
- HRTIM_TIMERID_TIMER_E,
- HRTIM_TIMERID_MASTER,
-};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HRTIM_Private_Functions HRTIM Private Functions
- * @{
- */
-static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
-
-static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg);
-
-static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * pCompareCfg);
-
-static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event);
-
-static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg);
-
-static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef * pEventCfg);
-
-static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event);
-
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel);
-
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
-
-static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
-
-static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx);
-
-static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
-
-static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
- * @{
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
-@verbatim
- ===============================================================================
- ##### Initialization and Time Base Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize a HRTIM instance
- (+) De-initialize a HRTIM instance
- (+) Initialize the HRTIM MSP
- (+) De-initialize the HRTIM MSP
- (+) Start the high-resolution unit (start DLL calibration)
- (+) Check that the high resolution unit is ready (DLL calibration done)
- (+) Configure the time base unit of a HRTIM timer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes a HRTIM instance
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
-{
- uint8_t timer_idx;
- uint32_t hrtim_mcr;
-
- /* Check the HRTIM handle allocation */
- if(hhrtim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
- assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Initialize the DMA handles */
- hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
- hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
-
- /* HRTIM output synchronization configuration (if required) */
- if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
- assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
-
- /* The synchronization output initialization procedure must be done prior
- to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
- */
- if (hhrtim->Instance == HRTIM1)
- {
- /* Enable the HRTIM peripheral clock */
- __HAL_RCC_HRTIM1_CLK_ENABLE();
- }
-
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the event to be sent on the synchronization output */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
- hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
-
- /* Set the polarity of the synchronization output */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
- hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- }
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_HRTIM_MspInit(hhrtim);
-
- /* HRTIM input synchronization configuration (if required) */
- if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
-
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the synchronization input source */
- hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
- hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- }
-
- /* Initialize the HRTIM state*/
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Initialize the lock status of the HRTIM HAL API */
- __HAL_UNLOCK(hhrtim);
-
- /* Tnitialize timer related parameters */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx <= HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
- hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
- hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
- hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
- hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
- hhrtim->TimerParam[timer_idx].DMASize = 0U;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-initializes a HRTIM instance
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
-{
- /* Check the HRTIM handle allocation */
- if(hhrtim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_HRTIM_MspDeInit(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief MSP initialization for a HRTIM instance
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_HRTIM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief MSP de-initialization for a for a HRTIM instance
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_HRTIM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the DLL calibration
- * @param hhrtim pointer to HAL HRTIM handle
- * @param CalibrationRate DLL calibration period
- * This parameter can be one of the following values:
- * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
- * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
- * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
- * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
- * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
- * @retval HAL status
- * @note This function locks the HRTIM instance. HRTIM instance is unlocked
- * within the HAL_HRTIM_PollForDLLCalibration function, just before
- * exiting the function.
- */
-HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t CalibrationRate)
-{
- uint32_t hrtim_dllcr;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure DLL Calibration */
- hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
-
- if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
- {
- /* One shot DLL calibration */
- hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
- hrtim_dllcr |= HRTIM_DLLCR_CAL;
- }
- else
- {
- /* Periodic DLL calibration */
- hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
- hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
- }
-
- /* Update HRTIM register */
- hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the DLL calibration.
- * DLL ready interrupt is enabled
- * @param hhrtim pointer to HAL HRTIM handle
- * @param CalibrationRate DLL calibration period
- * This parameter can be one of the following values:
- * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
- * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
- * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
- * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
- * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
- * @retval HAL status
- * @note This function locks the HRTIM instance. HRTIM instance is unlocked
- * within the IRQ processing function when processing the DLL ready
- * interrupt.
- * @note If this function is called for periodic calibration, the DLLRDY
- * interrupt is generated every time the calibration completes which
- * will significantly increases the overall interrupt rate.
- */
-HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t CalibrationRate)
-{
- uint32_t hrtim_dllcr;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable DLL Ready interrupt flag */
- __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
-
- /* Configure DLL Calibration */
- hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
-
- if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
- {
- /* One shot DLL calibration */
- hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
- hrtim_dllcr |= HRTIM_DLLCR_CAL;
- }
- else
- {
- /* Periodic DLL calibration */
- hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
- hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
- }
-
- /* Update HRTIM register */
- hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
-
- return HAL_OK;
-}
-
-/**
- * @brief Polls the DLL calibration ready flag and returns when the flag is
- * set (DLL calibration completed) or upon timeout expiration
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timeout Timeout duration in millisecond
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timeout)
-{
- uint32_t tickstart=0U;
-
- tickstart = HAL_GetTick();
-
- /* Check End of conversion flag */
- while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set HRTIM State */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the time base unit of a timer
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimeBaseCfg pointer to the time base configuration structure
- * @note This function must be called prior starting the timer
- * @note The time-base unit initialization parameters specify:
- * The timer counter operating mode (continuous, one shot),
- * The timer clock prescaler,
- * The timer period ,
- * The timer repetition counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
- assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Set the HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure master timer time base unit */
- HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
- }
- else
- {
- /* Configure timing unit time base unit */
- HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
- }
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
- * @brief Simple time base mode functions.
-@verbatim
- ===============================================================================
- ##### Simple time base mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start simple time base
- (+) Stop simple time base
- (+) Start simple time base and enable interrupt
- (+) Stop simple time base and disable interrupt
- (+) Start simple time base and enable DMA transfer
- (+) Stop simple time base and disable DMA transfer
- -@- When a HRTIM timer operates in simple time base mode, the timer
- counter counts from 0 to the period value.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the counter of a timer operating in simple time base mode.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in simple time base mode.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of a timer operating in simple time base mode
- * (Timer repetition interrupt is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the repetition interrupt */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in simple time base mode
- * (Timer repetition interrupt is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the repetition interrupt */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of a timer operating in simple time base mode
- * (Timer repetition DMA request is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param SrcAddr DMA transfer source address
- * @param DestAddr DMA transfer destination address
- * @param Length The length of data items (data size) to be transferred
- * from source to destination
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
- /* Set the DMA transfer completed callback */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
- }
- else
- {
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer repetition DMA request */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
- }
- else
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of a timer operating in simple time base mode
- * (Timer repetition DMA request is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index.
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Disable the DMA */
- HAL_DMA_Abort(hhrtim->hdmaMaster);
-
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
- }
- else
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
- if (hdma == NULL)
- {
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
- else
- {
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
- }
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
- * @brief Simple output compare functions
-@verbatim
- ===============================================================================
- ##### Simple output compare functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple output channel
- (+) Start simple output compare
- (+) Stop simple output compare
- (+) Start simple output compare and enable interrupt
- (+) Stop simple output compare and disable interrupt
- (+) Start simple output compare and enable DMA transfer
- (+) Stop simple output compare and disable DMA transfer
- -@- When a HRTIM timer operates in simple output compare mode
- the output level is set to a programmable value when a match
- is found between the compare register and the counter.
- Compare unit 1 is automatically associated to output 1
- Compare unit 2 is automatically associated to output 2
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output in simple output compare mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
- * @note When the timer operates in simple output compare mode:
- * Output 1 is implicitly controlled by the compare unit 1
- * Output 2 is implicitly controlled by the compare unit 2
- * Output Set/Reset crossbar is set according to the selected output compare mode:
- * Toggle: SETxyR = RSTxyR = CMPy
- * Active: SETxyR = CMPy, RSTxyR = 0
- * Inactive: SETxy =0, RSTxy = CMPy
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg = {0};
- HRTIM_OutputCfgTypeDef OutputCfg = {0};
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
- assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0U;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
- OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- switch (pSimpleOCChannelCfg->Mode)
- {
- case HRTIM_BASICOCMODE_TOGGLE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = OutputCfg.SetSource;
- }
- break;
- case HRTIM_BASICOCMODE_ACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
- }
- break;
- case HRTIM_BASICOCMODE_INACTIVE:
- {
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
- }
- else
- {
- OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
- }
- OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
- }
- break;
- default:
- break;
- }
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- OCChannel,
- &OutputCfg);
-
- /* Set HRTIM state */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * (Interrupt is enabled (see note note below)).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @note Interrupt enabling depends on the chosen output compare mode
- * Output toggle: compare match interrupt is enabled
- * Output set active: output set interrupt is enabled
- * Output set inactive: output reset interrupt is enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t interrupt;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the interrupt to enable (depends on the output compare mode) */
- interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Enable the timer interrupt (depends on the output compare mode) */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * (Interrupt is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t interrupt;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Get the interrupt to disable (depends on the output compare mode) */
- interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Disable the timer interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the output compare signal generation on the designed timer output
- * (DMA request is enabled (see note below)).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr DMA transfer source address
- * @param DestAddr DMA transfer destination address
- * @param Length The length of data items (data size) to be transferred
- * from source to destination
- * @note DMA request enabling depends on the chosen output compare mode
- * Output toggle: compare match DMA request is enabled
- * Output set active: output set DMA request is enabled
- * Output set inactive: output reset DMA request is enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
- uint32_t dma_request;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
-
- /* Get the DMA request to enable */
- dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the output compare signal generation on the designed timer output
- * (DMA request is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- DMA_HandleTypeDef * hdma;
- uint32_t dma_request;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Get the DMA request to disable */
- dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
-
- /* Disable the timer DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
- * @brief Simple PWM output functions
-@verbatim
- ===============================================================================
- ##### Simple PWM output functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple PWM output channel
- (+) Start simple PWM output
- (+) Stop simple PWM output
- (+) Start simple PWM output and enable interrupt
- (+) Stop simple PWM output and disable interrupt
- (+) Start simple PWM output and enable DMA transfer
- (+) Stop simple PWM output and disable DMA transfer
- -@- When a HRTIM timer operates in simple PWM output mode
- the output level is set to a programmable value when a match is
- found between the compare register and the counter and reset when
- the timer period is reached. Duty cycle is determined by the
- comparison value.
- Compare unit 1 is automatically associated to output 1
- Compare unit 2 is automatically associated to output 2
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output in simple PWM mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
- * @note When the timer operates in simple PWM output mode:
- * Output 1 is implicitly controlled by the compare unit 1
- * Output 2 is implicitly controlled by the compare unit 2
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * @note When Simple PWM mode is used the registers preload mechanism is
- * enabled (otherwise the behavior is not guaranteed).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
- uint32_t hrtim_timcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0U;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
- OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- PWMChannel,
- &OutputCfg);
-
- /* Enable the registers preload mechanism */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
- hrtim_timcr |= HRTIM_TIMCR_PREEN;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * (The compare interrupt is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Enable the timer interrupt (depends on the PWM output) */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * (The compare interrupt is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Disable the timer interrupt (depends on the PWM output) */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM output signal generation on the designed timer output
- * (The compare DMA request is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr DMA transfer source address
- * @param DestAddr DMA transfer destination address
- * @param Length The length of data items (data size) to be transferred
- * from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- /* Enable the timer DMA request */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM output signal generation on the designed timer output
- * (The compare DMA request is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t PWMChannel)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the timer DMA request */
- switch (PWMChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
- * @brief Simple input capture functions
-@verbatim
- ===============================================================================
- ##### Simple input capture functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure simple input capture channel
- (+) Start simple input capture
- (+) Stop simple input capture
- (+) Start simple input capture and enable interrupt
- (+) Stop simple input capture and disable interrupt
- (+) Start simple input capture and enable DMA transfer
- (+) Stop simple input capture and disable DMA transfer
- -@- When a HRTIM timer operates in simple input capture mode
- the Capture Register (HRTIM_CPT1/2xR) is used to latch the
- value of the timer counter counter after a transition detected
- on a given external event input.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures a simple capture
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Capture unit
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
- * @note When the timer operates in simple capture mode the capture is trigerred
- * by the designated external event and GPIO input is implicitly used as event source.
- * The cature can be triggered by a rising edge, a falling edge or both
- * edges on event channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
-{
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
- assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
- pSimpleCaptureChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
- pSimpleCaptureChannelCfg->EventFilter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
- EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_EventConfig(hhrtim,
- pSimpleCaptureChannelCfg->Event,
- &EventCfg);
-
- /* Memorize capture trigger (will be configured when the capture is started */
- HRTIM_CaptureUnitConfig(hhrtim,
- TimerIdx,
- CaptureChannel,
- pSimpleCaptureChannelCfg->Event);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a simple capture on the designed capture unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- * @note The external event triggering the capture is available for all timing
- * units. It can be used directly and is active as soon as the timing
- * unit counter is enabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a simple capture on the designed capture unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a simple capture on the designed capture unit
- * (Capture interrupt is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
-
- /* Enable the capture unit 1 interrupt */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
-
- /* Enable the capture unit 2 interrupt */
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a simple capture on the designed capture unit
- * (Capture interrupt is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the capture unit trigger */
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 1 interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 2 interrupt */
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables a simple capture on the designed capture unit
- * (Capture DMA request is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param SrcAddr DMA transfer source address
- * @param DestAddr DMA transfer destination address
- * @param Length The length of data items (data size) to be transferred
- * from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel,
- uint32_t SrcAddr,
- uint32_t DestAddr,
- uint32_t Length)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
-
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- /* Set the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
-
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- /* Set the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables a simple capture on the designed capture unit
- * (Capture DMA request is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureChannel)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- switch (CaptureChannel)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- /* Reset the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 1 DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- /* Reset the capture unit trigger */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
-
- /* Disable the capture unit 2 DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
- (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
- {
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
- * @brief Simple one pulse functions
-@verbatim
- ===============================================================================
- ##### Simple one pulse functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure one pulse channel
- (+) Start one pulse generation
- (+) Stop one pulse generation
- (+) Start one pulse generation and enable interrupt
- (+) Stop one pulse generation and disable interrupt
- -@- When a HRTIM timer operates in simple one pulse mode
- the timer counter is started in response to transition detected
- on a given external event input to generate a pulse with a
- programmable length after a programmable delay.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures an output simple one pulse mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
- * @note When the timer operates in simple one pulse mode:
- * the timer counter is implicitly started by the reset event,
- * the reset of the timer counter is triggered by the designated external event
- * GPIO input is implicitly used as event source,
- * Output 1 is implicitly controlled by the compare unit 1,
- * Output 2 is implicitly controlled by the compare unit 2.
- * Output Set/Reset crossbar is set as follows:
- * Output 1: SETx1R = CMP1, RSTx1R = PER
- * Output 2: SETx2R = CMP2, RST2R = PER
- * @retval HAL status
- * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
- * outputs, the reset event related configuration data provided in the
- * second call will override the reset event related configuration data
- * provided in the first call.
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel,
- HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
-{
- uint32_t CompareUnit = 0xFFFFFFFFU;
- HRTIM_CompareCfgTypeDef CompareCfg;
- HRTIM_OutputCfgTypeDef OutputCfg;
- HRTIM_EventCfgTypeDef EventCfg;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
- assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
- assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
- pSimpleOnePulseChannelCfg->EventPolarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
- assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
- pSimpleOnePulseChannelCfg->EventFilter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer compare unit */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- CompareUnit = HRTIM_COMPAREUNIT_1;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- CompareUnit = HRTIM_COMPAREUNIT_2;
- }
- break;
- default:
- break;
- }
-
- CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
- CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0U;
-
- HRTIM_CompareUnitConfig(hhrtim,
- TimerIdx,
- CompareUnit,
- &CompareCfg);
-
- /* Configure timer output */
- OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
- OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
- OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
- OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
- OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
- OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
-
- if (CompareUnit == HRTIM_COMPAREUNIT_1)
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
- }
- else
- {
- OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
- }
- OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
-
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- OnePulseChannel,
- &OutputCfg);
-
- /* Configure external event channel */
- EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
- EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
- EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
- EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
- EventCfg.Source = HRTIM_EVENTSRC_1;
-
- HRTIM_EventConfig(hhrtim,
- pSimpleOnePulseChannelCfg->Event,
- &EventCfg);
-
- /* Configure the timer reset register */
- HRTIM_TIM_ResetConfig(hhrtim,
- TimerIdx,
- pSimpleOnePulseChannelCfg->Event);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the simple one pulse signal generation on the designed output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the simple one pulse signal generation on the designed output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the simple one pulse signal generation on the designed output
- * (The compare interrupt is enabled (pulse start)).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the timer output */
- hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
-
- /* Enable the timer interrupt (depends on the OnePulse output) */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the simple one pulse signal generation on the designed output
- * (The compare interrupt is disabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OnePulseChannel)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable the timer output */
- hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
-
- /* Disable the timer interrupt (depends on the OnePulse output) */
- switch (OnePulseChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
- }
- break;
- default:
- break;
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
- * @brief HRTIM configuration functions
-@verbatim
- ===============================================================================
- ##### HRTIM configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the HRTIM
- resources shared by all the HRTIM timers operating in waveform mode:
- (+) Configure the burst mode controller
- (+) Configure an external event conditionning
- (+) Configure the external events sampling clock
- (+) Configure a fault conditionning
- (+) Enable or disable fault inputs
- (+) Configure the faults sampling clock
- (+) Configure an ADC trigger
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the burst mode feature of the HRTIM
- * @param hhrtim pointer to HAL HRTIM handle
- * @param pBurstModeCfg pointer to the burst mode configuration structure
- * @retval HAL status
- * @note This function must be called before starting the burst mode
- * controller
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
-{
- uint32_t hrtim_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
- assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
- assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
- assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
- assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Set the burst mode operating mode */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
- hrtim_bmcr |= pBurstModeCfg->Mode;
-
- /* Set the burst mode clock source */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
- hrtim_bmcr |= pBurstModeCfg->ClockSource;
-
- /* Set the burst mode prescaler */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
- hrtim_bmcr |= pBurstModeCfg->Prescaler;
-
- /* Enable/disable burst mode registers preload */
- hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
- hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
-
- /* Set the burst mode trigger */
- hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
-
- /* Set the burst mode compare value */
- hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
-
- /* Set the burst mode period */
- hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the conditioning of an external event
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Event external event to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pEventCfg pointer to the event conditioning configuration structure
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef* pEventCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
- assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
- assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
- assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
- assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the event channel */
- HRTIM_EventConfig(hhrtim, Event, pEventCfg);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the external event conditioning block prescaler
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Prescaler Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
- * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
- * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
- * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Prescaler)
-{
- uint32_t hrtim_eecr3;
-
- /* Check parameters */
- assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the external event prescaler */
- hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
- hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
- hrtim_eecr3 |= Prescaler;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the conditioning of fault input
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Fault fault input to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param pFaultCfg pointer to the fault conditioning configuration structure
- * @note This function must be called before starting the timer and before
- * enabling faults inputs
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Fault,
- HRTIM_FaultCfgTypeDef* pFaultCfg)
-{
- uint32_t hrtim_fltinr1;
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Fault));
- assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
- assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
- assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
- assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure fault channel */
- hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
-
- switch (Fault)
- {
- case HRTIM_FAULT_1:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
- hrtim_fltinr1 |= pFaultCfg->Polarity;
- hrtim_fltinr1 |= pFaultCfg->Source;
- hrtim_fltinr1 |= pFaultCfg->Filter;
- hrtim_fltinr1 |= pFaultCfg->Lock;
- }
- break;
- case HRTIM_FAULT_2:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U);
- hrtim_fltinr1 |= (pFaultCfg->Source << 8U);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 8U);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 8U);
- }
- break;
- case HRTIM_FAULT_3:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U);
- hrtim_fltinr1 |= (pFaultCfg->Source << 16U);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 16U);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 16U);
- }
- break;
- case HRTIM_FAULT_4:
- {
- hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U);
- hrtim_fltinr1 |= (pFaultCfg->Source << 24U);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 24U);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 24U);
- }
- break;
- case HRTIM_FAULT_5:
- {
- hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
- hrtim_fltinr2 |= pFaultCfg->Polarity;
- hrtim_fltinr2 |= pFaultCfg->Source;
- hrtim_fltinr2 |= pFaultCfg->Filter;
- hrtim_fltinr2 |= pFaultCfg->Lock;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the fault conditioning block prescaler
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Prescaler Prescaler value
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
- * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
- * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
- * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
- * @retval HAL status
- * @note This function must be called before starting the timer and before
- * enabling faults inputs
- */
-HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Prescaler)
-{
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the external event prescaler */
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
- hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
- hrtim_fltinr2 |= Prescaler;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the HRTIMx Fault mode.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Faults fault input(s) to enable or disable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_FAULT_1: Fault input 1
- * @arg HRTIM_FAULT_2: Fault input 2
- * @arg HRTIM_FAULT_3: Fault input 3
- * @arg HRTIM_FAULT_4: Fault input 4
- * @arg HRTIM_FAULT_5: Fault input 5
- * @param Enable Fault(s) enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
- * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
- * @retval None
- */
-void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Faults,
- uint32_t Enable)
-{
- uint32_t hrtim_fltinr1;
- uint32_t hrtim_fltinr2;
-
- /* Check parameters */
- assert_param(IS_HRTIM_FAULT(Faults));
- assert_param(IS_HRTIM_FAULTMODECTL(Enable));
-
- /* Configure fault channel */
- hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
- hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
-
- if ((Faults & HRTIM_FAULT_1) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
- hrtim_fltinr1 |= Enable;
- }
- if ((Faults & HRTIM_FAULT_2) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
- hrtim_fltinr1 |= (Enable << 8U);
- }
- if ((Faults & HRTIM_FAULT_3) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
- hrtim_fltinr1 |= (Enable << 16U);
- }
- if ((Faults & HRTIM_FAULT_4) != RESET)
- {
- hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
- hrtim_fltinr1 |= (Enable << 24U);
- }
- if ((Faults & HRTIM_FAULT_5) != RESET)
- {
- hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
- hrtim_fltinr2 |= Enable;
- }
-
- /* Update the HRTIMx registers */
- hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
- hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
-}
-
-/**
- * @brief Configures both the ADC trigger register update source and the ADC
- * trigger source.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param ADCTrigger ADC trigger to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
- * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
- * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
- * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
- * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t ADCTrigger,
- HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
-{
- uint32_t hrtim_cr1;
-
- /* Check parameters */
- assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
- assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the ADC trigger update source */
- hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
-
- switch (ADCTrigger)
- {
- case HRTIM_ADCTRIGGER_1:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
- hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
-
- /* Set the ADC trigger 1 source */
- hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_2:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
-
- /* Set the ADC trigger 2 source */
- hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_3:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
-
- /* Set the ADC trigger 3 source */
- hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
- }
- break;
- case HRTIM_ADCTRIGGER_4:
- {
- hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
-
- /* Set the ADC trigger 4 source */
- hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
- * @brief HRTIM timer configuration and control functions
-@verbatim
- ===============================================================================
- ##### HRTIM timer configuration and control functions #####
- ===============================================================================
- [..] This section provides functions used to configure and control a
- HRTIM timer operating in waveform mode:
- (+) Configure HRTIM timer general behavior
- (+) Configure HRTIM timer event filtering
- (+) Configure HRTIM timer deadtime insertion
- (+) Configure HRTIM timer chopper mode
- (+) Configure HRTIM timer burst DMA
- (+) Configure HRTIM timer compare unit
- (+) Configure HRTIM timer capture unit
- (+) Configure HRTIM timer output
- (+) Set HRTIM timer output level
- (+) Enable HRTIM timer output
- (+) Disable HRTIM timer output
- (+) Start HRTIM timer
- (+) Stop HRTIM timer
- (+) Start HRTIM timer and enable interrupt
- (+) Stop HRTIM timer and disable interrupt
- (+) Start HRTIM timer and enable DMA transfer
- (+) Stop HRTIM timer and disable DMA transfer
- (+) Enable or disable the burst mode controller
- (+) Start the burst mode controller (by software)
- (+) Trigger a Capture (by software)
- (+) Update the HRTIM timer preloadable registers (by software)
- (+) Reset the HRTIM timer counter (by software)
- (+) Start a burst DMA transfer
- (+) Enable timer register update
- (+) Disable timer register update
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the general behavior of a timer operating in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimerCfg pointer to the timer configuration structure
- * @note When the timer operates in waveform mode, all the features supported by
- * the HRTIM are available without any limitation.
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- /* Relevant for all HRTIM timers, including the master */
- assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
- assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
- assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
- assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
- assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
- assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
- assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
- assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
- assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
-
- /* Configure master timer */
- HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
- }
- else
- {
- /* Check parameters */
- assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
- assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
- assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
- assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
- assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
- assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
- assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
- pTimerCfg->DeadTimeInsertion));
- assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
- pTimerCfg->DelayedProtectionMode));
- assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
- assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
- assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
-
- /* Configure timing unit */
- HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
- }
-
- /* Update timer parameters */
- hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
- hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
- hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
- hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
- hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
-
- /* Force a software update */
- HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Event external event for which timer event filtering must be configured
- * This parameter can be one of the following values:
- * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
- * @arg HRTIM_EVENT_1: External event 1
- * @arg HRTIM_EVENT_2: External event 2
- * @arg HRTIM_EVENT_3: External event 3
- * @arg HRTIM_EVENT_4: External event 4
- * @arg HRTIM_EVENT_5: External event 5
- * @arg HRTIM_EVENT_6: External event 6
- * @arg HRTIM_EVENT_7: External event 7
- * @arg HRTIM_EVENT_8: External event 8
- * @arg HRTIM_EVENT_9: External event 9
- * @arg HRTIM_EVENT_10: External event 10
- * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
- * @note This function must be called before starting the timer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event,
- HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
-{
- uint32_t hrtim_eefr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_EVENT(Event));
- assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
- assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure timer event filtering capabilities */
- switch (Event)
- {
- case HRTIM_EVENT_NONE:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U;
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U;
- }
- break;
- case HRTIM_EVENT_1:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
- hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
- hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
- hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
- hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
- }
- break;
- default:
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the deadtime insertion feature for a timer
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
-{
- uint32_t hrtim_dtr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
- assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
-
- /* Clear timer deadtime configuration */
- hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
- HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
- HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
-
- /* Set timer deadtime configuration */
- hrtim_dtr |= pDeadTimeCfg->Prescaler;
- hrtim_dtr |= pDeadTimeCfg->RisingValue;
- hrtim_dtr |= pDeadTimeCfg->RisingSign;
- hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
- hrtim_dtr |= pDeadTimeCfg->RisingLock;
- hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U);
- hrtim_dtr |= pDeadTimeCfg->FallingSign;
- hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
- hrtim_dtr |= pDeadTimeCfg->FallingLock;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the chopper mode feature for a timer
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pChopperModeCfg pointer to the chopper mode configuration structure
- * @retval HAL status
- * @note This function must be called before configuring the timer output(s)
- */
-HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
-{
- uint32_t hrtim_chpr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
- assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
- assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
-
- /* Clear timer chopper mode configuration */
- hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
-
- /* Set timer choppe mode configuration */
- hrtim_chpr |= pChopperModeCfg->CarrierFreq;
- hrtim_chpr |= (pChopperModeCfg->DutyCycle);
- hrtim_chpr |= (pChopperModeCfg->StartPulse);
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the burst DMA controller for a timer
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param RegistersToUpdate registers to be written by DMA
- * This parameter can be any combination of the following values:
- * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
- * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
- * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
- * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
- * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
- * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
- * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
- * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
- * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
- * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
- * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
- * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
- * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
- * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
- * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
- * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
- * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
- * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
- * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
- * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
- * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t RegistersToUpdate)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Set the burst DMA timer update register */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
- }
- break;
- case HRTIM_TIMERINDEX_MASTER:
- {
- hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
- }
- break;
- default:
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the compare unit of a timer operating in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CompareUnit Compare unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
- * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
- * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
- * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param pCompareCfg pointer to the compare unit configuration structure
- * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
- * application has to configure separately the capture unit. Capture unit
- * to configure in that case depends on the compare unit auto delayed mode
- * is applied to (see below):
- * Auto delayed on output compare 2: capture unit 1 must be configured
- * Auto delayed on output compare 4: capture unit 2 must be configured
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef* pCompareCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the compare unit */
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
- }
- break;
- default:
- break;
- }
- }
- else
- {
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
-
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- /* DELCMP2 bitfield must be reset when reprogrammed from one value */
- /* to the other to reinitialize properly the auto-delayed mechanism */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- /* Check parameters */
- assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
-
- /* Set the compare value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
-
- if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
- {
- /* Configure auto-delayed mode */
- /* DELCMP4 bitfield must be reset when reprogrammed from one value */
- /* to the other to reinitialize properly the auto-delayed mechanism */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
-
- /* Set the compare value for timeout compare unit (if any) */
- if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
- }
- else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
- }
- }
- }
- break;
- default:
- break;
- }
- }
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the capture unit of a timer operating in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit Capture unit to configure
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pCaptureCfg pointer to the compare unit configuration structure
- * @retval HAL status
- * @note This function must be called before starting the timer
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- HRTIM_CaptureCfgTypeDef* pCaptureCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
- }
- break;
- default:
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the output of a timer operating in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pOutputCfg pointer to the timer output configuration structure
- * @retval HAL status
- * @note This function must be called before configuring the timer and after
- * configuring the deadtime insertion feature (if required).
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
- assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
- assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
- assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
- assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
- assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Configure the timer output */
- HRTIM_OutputConfig(hhrtim,
- TimerIdx,
- Output,
- pOutputCfg);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Forces the timer output to its active or inactive state
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param OutputLevel indicates whether the output is forced to its active or inactive level
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
- * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
- * @retval HAL status
- * @note The 'software set/reset trigger' bit in the output set/reset registers
- * is automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- uint32_t OutputLevel)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
- assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
- {
- /* Force output to its active state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
- }
- else
- {
- /* Force output to its inactive state */
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
- }
- }
- break;
- default:
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output enabling.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param OutputsToStart Timer output(s) to enable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t OutputsToStart)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the HRTIM outputs */
- hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables the generation of the waveform signal on the designated output(s)
- * Outputs can be combined (ORed) to allow for simultaneous output disabling.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param OutputsToStop Timer output(s) to disable
- * This parameter can be any combination of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t OutputsToStop)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable the HRTIM outputs */
- hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_TIMER_A
- * @arg HRTIM_TIMERID_TIMER_B
- * @arg HRTIM_TIMERID_TIMER_C
- * @arg HRTIM_TIMERID_TIMER_D
- * @arg HRTIM_TIMERID_TIMER_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
- * to the timers to start are enabled within this function.
- * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
- * function.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable HRTIM interrupts (if required) */
- __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
-
- /* Enable master timer related interrupts (if required) */
- if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
- {
- __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
- }
-
- /* Enable timing unit related interrupts (if required) */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
- {
- __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].InterruptRequests);
- }
- }
-
- /* Enable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- * @note All enabled timer related interrupts are disabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* ++ WA */
- __IO uint32_t delai = (uint32_t)(0x17FU);
- /* -- WA */
-
- uint8_t timer_idx;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Disable HRTIM interrupts (if required) */
- __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
-
- /* Disable master timer related interrupts (if required) */
- if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
- {
- /* Interrupts enable flag must be cleared one by one */
- __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
- }
-
- /* Disable timing unit related interrupts (if required) */
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
- {
- __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
- }
- }
-
- /* ++ WA */
- do { delai--; } while (delai != 0U);
- /* -- WA */
-
- /* Disable timer(s) counter */
- hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to start
- * This parameter can be any combination of the following values:
- * HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @retval HAL status
- * @note This function enables the dma request(s) mentionned in the timer
- * configuration data structure for every timers to start.
- * @note The source memory address, the destination memory address and the
- * size of each DMA transfer are specified at timer configuration time
- * (see HAL_HRTIM_WaveformTimerConfig)
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
- {
- /* Set the DMA error callback */
- hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hhrtim->hdmaMaster,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
- }
-
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma,
- hhrtim->TimerParam[timer_idx].DMASrcAddress,
- hhrtim->TimerParam[timer_idx].DMADstAddress,
- hhrtim->TimerParam[timer_idx].DMASize);
-
- /* Enable the timer DMA request */
- __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].DMARequests);
- }
- }
-
- /* Enable the timer counter */
- __HAL_HRTIM_ENABLE(hhrtim, Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the counter of the designated timer(s) operating in waveform mode
- * Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer counter(s) to stop
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
- * @retval HAL status
- * @note The counter of a timer is stopped only if all timer outputs are disabled
- * @note All enabled timer related DMA requests are disabled.
- */
-HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- uint8_t timer_idx;
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERID(Timers));
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
- {
- /* Disable the DMA */
- HAL_DMA_Abort(hhrtim->hdmaMaster);
-
- /* Disable the DMA request(s) */
- __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
- hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
- }
-
- for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
- timer_idx < HRTIM_TIMERINDEX_MASTER ;
- timer_idx++)
- {
- if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
- {
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
- if (hdma == NULL)
- {
- /* Disable the DMA request(s) */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].DMARequests);
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the DMA request(s) */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
- timer_idx,
- hhrtim->TimerParam[timer_idx].DMARequests);
- }
- }
-
- /* Disable the timer counter */
- __HAL_HRTIM_DISABLE(hhrtim, Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the HRTIM burst mode controller.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Enable Burst mode controller enabling
- * This parameter can be one of the following values:
- * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
- * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
- * @retval HAL status
- * @note This function must be called after starting the timer(s)
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Enable)
-{
- uint32_t hrtim_bmcr;
-
- /* Check parameters */
- assert_param(IS_HRTIM_BURSTMODECTL(Enable));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable/Disable the burst mode controller */
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
- hrtim_bmcr &= ~(HRTIM_BMCR_BME);
- hrtim_bmcr |= Enable;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the burst mode operation.
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
-{
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Software trigger of the burst mode controller */
- hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers a software capture on the designed capture unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval HAL status
- * @note The 'software capture' bit in the capure configuration register is
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force a software capture on concerned capture unit */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
- }
- break;
- default:
- break;
- }
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the update of the registers of one or several timers
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers timers concerned with the software register update
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- * @note The 'software update' bits in the HRTIM conrol register 2 register are
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR2 |= Timers;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Triggers the reset of one or several timers
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers timers concerned with the software counter reset
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERRESET_MASTER
- * @arg HRTIM_TIMERRESET_TIMER_A
- * @arg HRTIM_TIMERRESET_TIMER_B
- * @arg HRTIM_TIMERRESET_TIMER_C
- * @arg HRTIM_TIMERRESET_TIMER_D
- * @arg HRTIM_TIMERRESET_TIMER_E
- * @retval HAL status
- * @note The 'software reset' bits in the HRTIM conrol register 2 are
- * automatically reset by hardware
- */
-HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Timers)
-{
- /* Check parameters */
- assert_param(IS_HRTIM_TIMERRESET(Timers));
-
- if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Force timer(s) registers reset */
- hhrtim->Instance->sCommonRegs.CR2 = Timers;
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Starts a burst DMA operation to update HRTIM control registers content
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param BurstBufferAddress address of the buffer the HRTIM control registers
- * content will be updated from.
- * @param BurstBufferLength size (in WORDS) of the burst buffer.
- * @retval HAL status
- * @note The TimerIdx parameter determines the dma channel to be used by the
- * DMA burst controller (see below)
- * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
- * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
- */
-HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
- uint32_t TimerIdx,
- uint32_t BurstBufferAddress,
- uint32_t BurstBufferLength)
-{
- DMA_HandleTypeDef * hdma;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
-
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
- {
- if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- /* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
- if (hdma == NULL)
- {
- hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_ERROR;
- }
-
- /* Set the DMA transfer completed callback */
- hdma->XferCpltCallback = HRTIM_BurstDMACplt;
-
- /* Set the DMA error callback */
- hdma->XferErrorCallback = HRTIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdma,
- BurstBufferAddress,
- (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
- BurstBufferLength);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the transfer from preload to active registers for one
- * or several timing units (including master timer).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer(s) concerned by the register preload enabling command
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
- }
-
-/**
- * @brief Disables the transfer from preload to active registers for one
- * or several timing units (including master timer).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Timers Timer(s) concerned by the register preload disabling command
- * This parameter can be any combination of the following values:
- * @arg HRTIM_TIMERUPDATE_MASTER
- * @arg HRTIM_TIMERUPDATE_A
- * @arg HRTIM_TIMERUPDATE_B
- * @arg HRTIM_TIMERUPDATE_C
- * @arg HRTIM_TIMERUPDATE_D
- * @arg HRTIM_TIMERUPDATE_E
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
- uint32_t Timers)
-{
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMERUPDATE(Timers));
-
- /* Process Locked */
- __HAL_LOCK(hhrtim);
-
- hhrtim->State = HAL_HRTIM_STATE_BUSY;
-
- /* Enable timer(s) registers update */
- hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
-
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhrtim);
-
- return HAL_OK;
- }
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
- * @brief Peripheral State functions
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..] This section provides functions used to get HRTIM or HRTIM timer
- specific information:
- (+) Get HRTIM HAL state
- (+) Get captured value
- (+) Get HRTIM timer output level
- (+) Get HRTIM timer output state
- (+) Get delayed protection status
- (+) Get burst status
- (+) Get current push-pull status
- (+) Get idle push-pull status
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the HRTIM HAL state
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval HAL state
- */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
-{
- /* Return ADC state */
- return hhrtim->State;
-}
-
-/**
- * @brief Returns actual value of the capture register of the designated capture unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit Capture unit to trig
- * This parameter can be one of the following values:
- * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
- * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @retval Captured value
- */
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit)
-{
- uint32_t captured_value = 0U;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
- assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
-
- /* Read captured value */
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
- }
- break;
- default:
- break;
- }
-
- return captured_value;
-}
-
-/**
- * @brief Returns actual level (active or inactive) of the designated output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output level
- * @note Returned output level is taken before the output stage (chopper,
- * polarity).
- */
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the output level */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
- {
- output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- default:
- break;
- }
-
- return output_level;
-}
-
-/**
- * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Output state
- */
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t output_bit = 0U;
- uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Set output state according to output control status and output disable status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- {
- output_bit = HRTIM_OENR_TA1OEN;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- {
- output_bit = HRTIM_OENR_TA2OEN;
- }
- break;
- case HRTIM_OUTPUT_TB1:
- {
- output_bit = HRTIM_OENR_TB1OEN;
- }
- break;
- case HRTIM_OUTPUT_TB2:
- {
- output_bit = HRTIM_OENR_TB2OEN;
- }
- break;
- case HRTIM_OUTPUT_TC1:
- {
- output_bit = HRTIM_OENR_TC1OEN;
- }
- break;
- case HRTIM_OUTPUT_TC2:
- {
- output_bit = HRTIM_OENR_TC2OEN;
- }
- break;
- case HRTIM_OUTPUT_TD1:
- {
- output_bit = HRTIM_OENR_TD1OEN;
- }
- break;
- case HRTIM_OUTPUT_TD2:
- {
- output_bit = HRTIM_OENR_TD2OEN;
- }
- break;
- case HRTIM_OUTPUT_TE1:
- {
- output_bit = HRTIM_OENR_TE1OEN;
- }
- break;
- case HRTIM_OUTPUT_TE2:
- {
- output_bit = HRTIM_OENR_TE2OEN;
- }
- break;
- default:
- break;
- }
-
- if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
- {
- /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
- output_state = HRTIM_OUTPUTSTATE_RUN;
- }
- else
- {
- if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
- {
- /* Output is disabled: output in FAULT state */
- output_state = HRTIM_OUTPUTSTATE_FAULT;
- }
- else
- {
- /* Output is disabled: output in IDLE state */
- output_state = HRTIM_OUTPUTSTATE_IDLE;
- }
- }
-
- return(output_state);
-}
-
-/**
- * @brief Returns the level (active or inactive) of the designated output
- * when the delayed protection was triggered.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
- * @retval Delayed protection status
- */
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output)
-{
- uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
-
- /* Check parameters */
- assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
-
- /* Read the delayed protection status */
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
- {
- /* Output 1 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 1 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
- {
- /* Output 2 was active when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
- }
- else
- {
- /* Output 2 was inactive when the delayed idle protection was triggered */
- delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
- }
- }
- break;
- default:
- break;
- }
-
- return delayed_protection_status;
-}
-
-/**
- * @brief Returns the actual status (active or inactive) of the burst mode controller
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval Burst mode controller status
- */
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
-{
- uint32_t burst_mode_status;
-
- /* Read burst mode status */
- burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
-
- return burst_mode_status;
-}
-
-/**
- * @brief Indicates on which output the signal is currently active (when the
- * push pull mode is enabled).
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval Burst mode controller status
- */
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- uint32_t current_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
-
- return current_pushpull_status;
-}
-
-
-/**
- * @brief Indicates on which output the signal was applied, in push-pull mode,
- balanced fault mode or delayed idle mode, when the protection was triggered.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval Idle Push Pull Status
- */
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- uint32_t idle_pushpull_status;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
-
- /* Read current push pull status */
- idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
-
- return idle_pushpull_status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
- * @brief Functions called when HRTIM generates an interrupt
- * 7 interrupts can be generated by the master timer:
- * - Master timer registers update
- * - Synchronization event received
- * - Master timer repetition event
- * - Master Compare 1 to 4 event
- * 14 interrupts can be generated by each timing unit:
- * - Delayed protection triggered
- * - Counter reset or roll-over event
- * - Output 1 and output 2 reset (transition active to inactive)
- * - Output 1 and output 2 set (transition inactive to active)
- * - Capture 1 and 2 events
- * - Timing unit registers update
- * - Repetition event
- * - Compare 1 to 4 event
- * 8 global interrupts are generated for the whole HRTIM:
- * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
- * - DLL calibration done
- * - Burst mode period completed
-@verbatim
- ===============================================================================
- ##### HRTIM interrupts handling #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the HRTIM
- interrupts:
- (+) HRTIM interrupt handler
- (+) Callback function called when Fault1 interrupt occurs
- (+) Callback function called when Fault2 interrupt occurs
- (+) Callback function called when Fault3 interrupt occurs
- (+) Callback function called when Fault4 interrupt occurs
- (+) Callback function called when Fault5 interrupt occurs
- (+) Callback function called when system Fault interrupt occurs
- (+) Callback function called when DLL ready interrupt occurs
- (+) Callback function called when burst mode period interrupt occurs
- (+) Callback function called when synchronization input interrupt occurs
- (+) Callback function called when a timer register update interrupt occurs
- (+) Callback function called when a timer repetition interrupt occurs
- (+) Callback function called when a compare 1 match interrupt occurs
- (+) Callback function called when a compare 2 match interrupt occurs
- (+) Callback function called when a compare 3 match interrupt occurs
- (+) Callback function called when a compare 4 match interrupt occurs
- (+) Callback function called when a capture 1 interrupt occurs
- (+) Callback function called when a capture 2 interrupt occurs
- (+) Callback function called when a delayed protection interrupt occurs
- (+) Callback function called when a timer counter reset interrupt occurs
- (+) Callback function called when a timer output 1 set interrupt occurs
- (+) Callback function called when a timer output 1 reset interrupt occurs
- (+) Callback function called when a timer output 2 set interrupt occurs
- (+) Callback function called when a timer output 2 reset interrupt occurs
- (+) Callback function called when a timer output 2 reset interrupt occurs
- (+) Callback function called upon completion of a burst DMA transfer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles HRTIM interrupt request.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be any value of @ref HRTIM_Timer_Index
- * @retval None
- */
-void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* HRTIM interrupts handling */
- if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
- {
- HRTIM_HRTIM_ISR(hhrtim);
- }
- else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Master related interrupts handling */
- HRTIM_Master_ISR(hhrtim);
- }
- else
- {
- /* Timing unit related interrupts handling */
- HRTIM_Timer_ISR(hhrtim, TimerIdx);
- }
-
-}
-
-/**
- * @brief Callback function invoked when a fault 1 interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle * @retval None
- * @retval None
- */
-__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault1Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 2 interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault2Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 3 interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault3Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 4 interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault4Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a fault 5 interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Fault5Callback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a system fault interrupt occured
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the DLL calibration is completed
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the end of the burst mode period is reached
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a synchronization input event is received
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when timer registers are updated
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when timer repetition period has elapsed
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 1 register
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 2 register
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- */
-__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 3 register
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer counter matches the value
- * programmed in the compare 4 register.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x capture 1 event occurs
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x capture 2 event occurs
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the delayed idle or balanced idle mode is
- * entered.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x counter reset/roll-over
- * event occurs.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 1 is set
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 1 is reset
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 2 is set
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when the timer x output 2 is reset
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a DMA burst transfer is completed
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_MASTER for master timer
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
- */
-__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
- UNUSED(TimerIdx);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Callback function invoked when a DMA error occurs
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhrtim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_HRTIM_ErrorCallback could be implenetd in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
- * @{
- */
-
-/**
- * @brief Configures the master timer time base
- * @param hhrtim pointer to HAL HRTIM handle
- * @param pTimeBaseCfg pointer to the time base configuration structure
- * @retval None
- */
-static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- uint32_t hrtim_mcr;
-
- /* Configure master timer */
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
-
- /* Set the prescaler ratio */
- hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
- hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
-
- /* Set the operating mode */
- hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
- hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
- hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) time base
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param pTimeBaseCfg pointer to the time base configuration structure
- * @retval None
- */
-static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx ,
- HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
-{
- uint32_t hrtim_timcr;
-
- /* Configure master timing unit */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
-
- /* Set the prescaler ratio */
- hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
- hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
-
- /* Set the operating mode */
- hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
- hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
- hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
-}
-
-/**
- * @brief Configures the master timer in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param pTimerCfg pointer to the timer configuration data structure
- * @retval None
- */
-static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- uint32_t hrtim_mcr;
- uint32_t hrtim_bmcr;
-
- /* Configure master timer */
- hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Enable/Disable the half mode */
- hrtim_mcr &= ~(HRTIM_MCR_HALF);
- hrtim_mcr |= pTimerCfg->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
- hrtim_mcr |= pTimerCfg->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
- hrtim_mcr |= pTimerCfg->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
- hrtim_mcr |= pTimerCfg->DACSynchro;
-
- /* Enable/Disable preload meachanism for timer registers */
- hrtim_mcr &= ~(HRTIM_MCR_PREEN);
- hrtim_mcr |= pTimerCfg->PreloadEnable;
-
- /* Master timer registers update handling */
- hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
- hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
-
- /* Enable/Disable registers update on repetition */
- hrtim_mcr &= ~(HRTIM_MCR_MREPU);
- hrtim_mcr |= pTimerCfg->RepetitionUpdate;
-
- /* Set the timer burst mode */
- hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
- hrtim_bmcr |= pTimerCfg->BurstMode;
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-}
-
-/**
- * @brief Configures timing unit (timer A to timer E) in waveform mode
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param pTimerCfg pointer to the timer configuration data structure
- * @retval None
- */
-static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- HRTIM_TimerCfgTypeDef * pTimerCfg)
-{
- uint32_t hrtim_timcr;
- uint32_t hrtim_timfltr;
- uint32_t hrtim_timoutr;
- uint32_t hrtim_timrstr;
- uint32_t hrtim_bmcr;
-
- /* UPDGAT bitfield must be reset before programming a new value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
-
- /* Configure timing unit (Timer A to Timer E) */
- hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
- hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
- hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
- hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
- hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
-
- /* Enable/Disable the half mode */
- hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
- hrtim_timcr |= pTimerCfg->HalfModeEnable;
-
- /* Enable/Disable the timer start upon synchronization event reception */
- hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
- hrtim_timcr |= pTimerCfg->StartOnSync;
-
- /* Enable/Disable the timer reset upon synchronization event reception */
- hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
- hrtim_timcr |= pTimerCfg->ResetOnSync;
-
- /* Enable/Disable the DAC synchronization event generation */
- hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
- hrtim_timcr |= pTimerCfg->DACSynchro;
-
- /* Enable/Disable preload meachanism for timer registers */
- hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
- hrtim_timcr |= pTimerCfg->PreloadEnable;
-
- /* Timing unit registers update handling */
- hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
- hrtim_timcr |= pTimerCfg->UpdateGating;
-
- /* Enable/Disable registers update on repetition */
- hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
- if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
- {
- hrtim_timcr |= HRTIM_TIMCR_TREPU;
- }
-
- /* Set the push-pull mode */
- hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
- hrtim_timcr |= pTimerCfg->PushPull;
-
- /* Enable/Disable registers update on timer counter reset */
- hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
- hrtim_timcr |= pTimerCfg->ResetUpdate;
-
- /* Set the timer update trigger */
- hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
- hrtim_timcr |= pTimerCfg->UpdateTrigger;
-
-
- /* Enable/Disable the fault channel at timer level */
- hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
- hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
-
- /* Lock/Unlock fault sources at timer level */
- hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
- hrtim_timfltr |= pTimerCfg->FaultLock;
-
- /* The deadtime cannot be used simultaneously with the push-pull mode */
- if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
- {
- /* Enable/Disable dead time insertion at timer level */
- hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
- hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
- }
-
- /* Enable/Disable delayed protection at timer level
- Delayed Idle is available whatever the timer operating mode (regular, push-pull)
- Balanced Idle is only available in push-pull mode
- */
- if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
- && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
- || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
- {
- hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
- hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
- }
-
- /* Set the timer counter reset trigger */
- hrtim_timrstr = pTimerCfg->ResetTrigger;
-
- /* Set the timer burst mode */
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
- }
- break;
- default:
- break;
- }
-
- /* Update the HRTIM registers */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
- hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
-}
-
-/**
- * @brief Configures a compare unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param CompareUnit Compare unit identifier
- * @param pCompareCfg pointer to the compare unit configuration data structure
- * @retval None
- */
-static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CompareUnit,
- HRTIM_CompareCfgTypeDef * pCompareCfg)
-{
- if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
- {
- /* Configure the compare unit of the master timer */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
- }
- break;
- default:
- break;
- }
- }
- else
- {
- /* Configure the compare unit of the timing unit */
- switch (CompareUnit)
- {
- case HRTIM_COMPAREUNIT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_3:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
- }
- break;
- case HRTIM_COMPAREUNIT_4:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
- }
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * @brief Configures a capture unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param CaptureUnit Capture unit identifier
- * @param Event Event reference
- * @retval None
- */
-static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t CaptureUnit,
- uint32_t Event)
-{
- uint32_t CaptureTrigger = 0xFFFFFFFFU;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
- }
- break;
- default:
- break;
- }
-
- switch (CaptureUnit)
- {
- case HRTIM_CAPTUREUNIT_1:
- {
- hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
- }
- break;
- case HRTIM_CAPTUREUNIT_2:
- {
- hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the output of a timing unit
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param Output timing unit output identifier
- * @param pOutputCfg pointer to the output configuration data structure
- * @retval None
- */
-static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Output,
- HRTIM_OutputCfgTypeDef * pOutputCfg)
-{
- uint32_t hrtim_outr;
- uint32_t hrtim_dtr;
-
- uint32_t shift = 0xFFFFFFFFU;
-
- hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
- hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
-
- switch (Output)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Set the output set/reset crossbar */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
-
- shift = 0U;
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Set the output set/reset crossbar */
- hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
-
- shift = 16U;
- }
- break;
- default:
- break;
- }
-
- /* Clear output config */
- hrtim_outr &= ~((HRTIM_OUTR_POL1 |
- HRTIM_OUTR_IDLM1 |
- HRTIM_OUTR_IDLES1|
- HRTIM_OUTR_FAULT1|
- HRTIM_OUTR_CHP1 |
- HRTIM_OUTR_DIDL1) << shift);
-
- /* Set the polarity */
- hrtim_outr |= (pOutputCfg->Polarity << shift);
-
- /* Set the IDLE mode */
- hrtim_outr |= (pOutputCfg->IdleMode << shift);
-
- /* Set the IDLE state */
- hrtim_outr |= (pOutputCfg->IdleLevel << shift);
-
- /* Set the FAULT state */
- hrtim_outr |= (pOutputCfg->FaultLevel << shift);
-
- /* Set the chopper mode */
- hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
-
- /* Set the burst mode entry mode : deadtime insertion when entering the idle
- state during a burst mode operation is allowed only under the following
- conditions:
- - the outputs is active during the burst mode (IDLES=1U)
- - positive deadtimes (SDTR/SDTF set to 0U)
- */
- if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
- ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
- ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
- {
- hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
- }
-
- /* Update HRTIM register */
- hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
-}
-
-/**
- * @brief Configures an external event channel
- * @param hhrtim pointer to HAL HRTIM handle
- * @param Event Event channel identifier
- * @param pEventCfg pointer to the event channel configuration data structure
- * @retval None
- */
-static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t Event,
- HRTIM_EventCfgTypeDef *pEventCfg)
-{
- uint32_t hrtim_eecr1;
- uint32_t hrtim_eecr2;
- uint32_t hrtim_eecr3;
-
- /* Configure external event channel */
- hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
- hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
- hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
-
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
- hrtim_eecr1 |= pEventCfg->Source;
- hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
- hrtim_eecr1 |= pEventCfg->Sensitivity;
- /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE1FAST bit) */
- hrtim_eecr1 |= pEventCfg->FastMode;
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 6U);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U);
- /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE2FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 6U);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 12U);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U);
- /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE3FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 12U);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 18U);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U);
- /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE4FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 18U);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 24U);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U);
- /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- /* Update the HRTIM registers (EE5FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 24U);
- hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
- hrtim_eecr2 |= pEventCfg->Source;
- hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
- hrtim_eecr2 |= pEventCfg->Sensitivity;
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
- hrtim_eecr3 |= pEventCfg->Filter;
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 6U);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
- hrtim_eecr3 |= (pEventCfg->Filter << 6U);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 12U);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
- hrtim_eecr3 |= (pEventCfg->Filter << 12U);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 18U);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
- hrtim_eecr3 |= (pEventCfg->Filter << 18U);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 24U);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U);
- hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
- hrtim_eecr3 |= (pEventCfg->Filter << 24U);
- /* Update the HRTIM registers */
- hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
- hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Configures the timer counter reset
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param Event Event channel identifier
- * @retval None
- */
-static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t Event)
-{
- switch (Event)
- {
- case HRTIM_EVENT_1:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
- }
- break;
- case HRTIM_EVENT_2:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
- }
- break;
- case HRTIM_EVENT_3:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
- }
- break;
- case HRTIM_EVENT_4:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
- }
- break;
- case HRTIM_EVENT_5:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
- }
- break;
- case HRTIM_EVENT_6:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
- }
- break;
- case HRTIM_EVENT_7:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
- }
- break;
- case HRTIM_EVENT_8:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
- }
- break;
- case HRTIM_EVENT_9:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
- }
- break;
- case HRTIM_EVENT_10:
- {
- hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Returns the interrupt to enable or disable according to the
- * OC mode.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval Interrupt to enable or disable
- */
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t hrtim_set;
- uint32_t hrtim_reset;
- uint32_t interrupt = 0U;
-
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Retreives actual OC mode and set interrupt accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- interrupt = HRTIM_TIM_IT_CMP1;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0U))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- interrupt = HRTIM_TIM_IT_SET1;
- }
- else if ((hrtim_set == 0U) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- interrupt = HRTIM_TIM_IT_RST1;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Retreives actual OC mode and set interrupt accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- interrupt = HRTIM_TIM_IT_CMP2;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0U))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- interrupt = HRTIM_TIM_IT_SET2;
- }
- else if ((hrtim_set == 0U) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- interrupt = HRTIM_TIM_IT_RST2;
- }
- }
- break;
- default:
- break;
- }
-
- return interrupt;
-}
-
-/**
- * @brief Returns the DMA request to enable or disable according to the
- * OC mode.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @param OCChannel Timer output
- * This parameter can be one of the following values:
- * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
- * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
- * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
- * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
- * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
- * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
- * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
- * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
- * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
- * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @retval DMA request to enable or disable
- */
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx,
- uint32_t OCChannel)
-{
- uint32_t hrtim_set;
- uint32_t hrtim_reset;
- uint32_t dma_request = 0U;
-
- switch (OCChannel)
- {
- case HRTIM_OUTPUT_TA1:
- case HRTIM_OUTPUT_TB1:
- case HRTIM_OUTPUT_TC1:
- case HRTIM_OUTPUT_TD1:
- case HRTIM_OUTPUT_TE1:
- {
- /* Retreives actual OC mode and set dma_request accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- dma_request = HRTIM_TIM_DMA_CMP1;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0U))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- dma_request = HRTIM_TIM_DMA_SET1;
- }
- else if ((hrtim_set == 0U) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- dma_request = HRTIM_TIM_DMA_RST1;
- }
- }
- break;
- case HRTIM_OUTPUT_TA2:
- case HRTIM_OUTPUT_TB2:
- case HRTIM_OUTPUT_TC2:
- case HRTIM_OUTPUT_TD2:
- case HRTIM_OUTPUT_TE2:
- {
- /* Retreives actual OC mode and set dma_request accordingly */
- hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
- hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
-
- if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
- dma_request = HRTIM_TIM_DMA_CMP2;
- }
- else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0U))
- {
- /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
- dma_request = HRTIM_TIM_DMA_SET2;
- }
- else if ((hrtim_set == 0U) &&
- ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
- {
- /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
- dma_request = HRTIM_TIM_DMA_RST2;
- }
- }
- break;
- default:
- break;
- }
-
- return dma_request;
-}
-
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
-
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- hdma = hhrtim->hdmaMaster;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hdma = hhrtim->hdmaTimerA;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hdma = hhrtim->hdmaTimerB;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hdma = hhrtim->hdmaTimerC;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hdma = hhrtim->hdmaTimerD;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hdma = hhrtim->hdmaTimerE;
- }
- break;
- default:
- break;
- }
-
- return hdma;
-}
-
-static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
-{
- uint32_t timed_idx = 0xFFFFFFFFU;
-
- if (hdma->Instance == DMA1_Channel2)
- {
- timed_idx = HRTIM_TIMERINDEX_MASTER;
- }
- else if (hdma->Instance == DMA1_Channel3)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_A;
- }
- else if (hdma->Instance == DMA1_Channel4)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_B;
- }
- else if (hdma->Instance == DMA1_Channel5)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_C;
- }
- else if (hdma->Instance == DMA1_Channel6)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_D;
- }
- else if (hdma->Instance == DMA1_Channel7)
- {
- timed_idx = HRTIM_TIMERINDEX_TIMER_E;
- }
-
- return timed_idx;
-}
-
-/**
- * @brief Forces an immediate transfer from the preload to the active
- * registers.
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * @retval None
- */
-static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- switch (TimerIdx)
- {
- case HRTIM_TIMERINDEX_MASTER:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_A:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_B:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_C:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_D:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
- }
- break;
- case HRTIM_TIMERINDEX_TIMER_E:
- {
- hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
- }
- break;
- default:
- break;
- }
-}
-
-
-/**
- * @brief HRTIM interrupts service routine
- * @param hhrtim pointer to HAL HRTIM handle
- * @retval None
- */
-static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
-{
- /* Fault 1 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
-
- /* Invoke Fault 1 event callback */
- HAL_HRTIM_Fault1Callback(hhrtim);
- }
- }
-
- /* Fault 2 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
-
- /* Invoke Fault 2 event callback */
- HAL_HRTIM_Fault2Callback(hhrtim);
- }
- }
-
- /* Fault 3 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
-
- /* Invoke Fault 3 event callback */
- HAL_HRTIM_Fault3Callback(hhrtim);
- }
- }
-
- /* Fault 4 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
-
- /* Invoke Fault 4 event callback */
- HAL_HRTIM_Fault4Callback(hhrtim);
- }
- }
-
- /* Fault 5 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
-
- /* Invoke Fault 5 event callback */
- HAL_HRTIM_Fault5Callback(hhrtim);
- }
- }
-
- /* System fault event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
-
- /* Invoke System fault event callback */
- HAL_HRTIM_SystemFaultCallback(hhrtim);
- }
- }
-}
-
-/**
-* @brief Master timer interrupts service routine
-* @param hhrtim pointer to HAL HRTIM handle
-* @retval None
-*/
-static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
-{
- /* DLL calibration ready event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
-
- /* Set HRTIM State */
- hhrtim->State = HAL_HRTIM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hhrtim);
-
- /* Invoke System fault event callback */
- HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
- }
- }
-
- /* Burst mode period event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
- {
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
- {
- __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
-
- /* Invoke Burst mode period event callback */
- HAL_HRTIM_BurstModePeriodCallback(hhrtim);
- }
- }
-
- /* Master timer compare 1 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
-
- /* Invoke compare 1 event callback */
- HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 2 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
-
- /* Invoke compare 2 event callback */
- HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 3 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
-
- /* Invoke compare 3 event callback */
- HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer compare 4 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
-
- /* Invoke compare 4 event callback */
- HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Master timer repetition event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
-
- /* Invoke repetition event callback */
- HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-
- /* Synchronization input event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
-
- /* Invoke synchronization event callback */
- HAL_HRTIM_SynchronizationEventCallback(hhrtim);
- }
- }
-
- /* Master timer registers update event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
- {
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
- {
- __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
-
- /* Invoke registers update event callback */
- HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
- }
- }
-}
-
-/**
- * @brief Timer interrupts service routine
- * @param hhrtim pointer to HAL HRTIM handle
- * @param TimerIdx Timer index
- * This parameter can be one of the following values:
- * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
- * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
- * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
- * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
- * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @retval None
-*/
-static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
- uint32_t TimerIdx)
-{
- /* Timer compare 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
-
- /* Invoke compare 1 event callback */
- HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
-
- /* Invoke compare 2 event callback */
- HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 3 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
-
- /* Invoke compare 3 event callback */
- HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer compare 4 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
-
- /* Invoke compare 4 event callback */
- HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer repetition event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
-
- /* Invoke repetition event callback */
- HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer registers update event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
-
- /* Invoke registers update event callback */
- HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer capture 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
-
- /* Invoke capture 1 event callback */
- HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer capture 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
-
- /* Invoke capture 2 event callback */
- HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 1 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
-
- /* Invoke ouput 1 set event callback */
- HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 1 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
-
- /* Invoke ouput 1 reset event callback */
- HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 2 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
-
- /* Invoke ouput 2 set event callback */
- HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer ouput 2 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
-
- /* Invoke ouput 2 reset event callback */
- HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Timer reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
-
- /* Invoke timer reset callback */
- HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
- }
- }
-
- /* Delayed protection event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
- {
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
- {
- __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
-
- /* Invoke delayed protection callback */
- HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
- }
- }
-}
-
-/**
- * @brief DMA callback invoked upon master timer related DMA request completion
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
- {
- HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
- {
- HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
- {
- HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
- {
- HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
- {
- HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
- {
- HAL_HRTIM_SynchronizationEventCallback(hrtim);
- }
- else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
- {
- HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
- }
-}
-
-/**
- * @brief DMA callback invoked upon timer A..E related DMA request completion
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
-{
- uint8_t timer_idx;
-
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- timer_idx = GetTimerIdxFromDMAHandle(hdma);
-
- if (IS_HRTIM_TIMING_UNIT( timer_idx))
- {
- if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
- {
- HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
- {
- HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
- {
- HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
- {
- HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
- {
- HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
- {
- HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
- {
- HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
- {
- HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
- {
- HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
- {
- HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
- {
- HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
- {
- HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
- {
- HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
- {
- HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
- }
- }
-}
-
-/**
-* @brief DMA error callback
-* @param hdma pointer to DMA handle.
-* @retval None
-*/
-static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_HRTIM_ErrorCallback(hrtim);
-}
-
-/**
- * @brief DMA callback invoked upon burst DMA transfer completion
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
-{
- HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F334x8 */
-
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
deleted file mode 100644
index 82e59e74204..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
+++ /dev/null
@@ -1,4868 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2c.c
- * @author MCD Application Team
- * @brief I2C HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Inter Integrated Circuit (I2C) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The I2C HAL driver can be used as follows:
-
- (#) Declare a I2C_HandleTypeDef handle structure, for example:
- I2C_HandleTypeDef hi2c;
-
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
- (##) Enable the I2Cx interface clock
- (##) I2C pins configuration
- (+++) Enable the clock for the I2C GPIOs
- (+++) Configure I2C pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the I2Cx interrupt priority
- (+++) Enable the NVIC I2C IRQ Channel
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
- (+++) Enable the DMAx interface clock using
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
- (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx channel
-
- (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
- Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
-
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
- (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
- *** Polling mode IO MEM operation ***
- =====================================
- [..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
-
- *** Interrupt mode IO sequential operation ***
- ==============================================
- [..]
- (@) These interfaces allow to manage a sequential transfer with a repeated start condition
- when a direction change during transfer
- [..]
- (+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
- (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition
- (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
- (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and without a final stop condition in both cases
- (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and with a final stop condition in both cases
-
- (+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** Interrupt mode IO MEM operation ***
- =======================================
- [..]
- (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
- This action will inform Master to generate a Stop condition to discard the communication.
-
- *** DMA mode IO MEM operation ***
- =================================
- [..]
- (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
-
- *** I2C HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in I2C HAL driver.
-
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
- [..]
- (@) You can refer to the I2C HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2C I2C
- * @brief I2C HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Define I2C Private Define
- * @{
- */
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
-#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
-#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
-#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE 255U
-#define SlaveAddr_SHIFT 7U
-#define SlaveAddr_MSK 0x06U
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
-
-
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
-
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
-
-/* Private define Sequential Transfer Options default/reset value */
-#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
- ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-/* Private functions to handle IT transfer */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
-
-/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-
-/* Private functions to flush TXDR register */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-
-/* Private functions to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- deinitialize the I2Cx peripheral:
-
- (+) User must Implement HAL_I2C_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2C_Init() to configure the selected device with
- the selected configuration:
- (++) Clock Timing
- (++) Own Address 1
- (++) Addressing mode (Master, Slave)
- (++) Dual Addressing mode
- (++) Own Address 2
- (++) Own Address 2 Mask
- (++) General call mode
- (++) Nostretch mode
-
- (+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and initialize the associated handle.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if (hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
- assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
- assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
- assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
- assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
- assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
- if (hi2c->State == HAL_I2C_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2c->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2C_MspInit(hi2c);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
- /* Configure I2Cx: Frequency range */
- hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Disable Own Address1 before set the Own Address1 configuration */
- hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- /* Configure I2Cx: Own Address1 and ack own address1 mode */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
-
- /*---------------------------- I2Cx CR2 Configuration ----------------------*/
- /* Configure I2Cx: Addressing Master mode */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
- }
- /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
- hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
- /* Disable Own Address2 before set the Own Address2 configuration */
- hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
-
- /* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
-
- /*---------------------------- I2Cx CR1 Configuration ----------------------*/
- /* Configure I2Cx: Generalcall and NoStretch mode */
- hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
- /* Enable the selected I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the I2C peripheral.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if (hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the I2C Peripheral Clock */
- __HAL_I2C_DISABLE(hi2c);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_I2C_MspDeInit(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2C data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2C_Master_Transmit()
- (++) HAL_I2C_Master_Receive()
- (++) HAL_I2C_Slave_Transmit()
- (++) HAL_I2C_Slave_Receive()
- (++) HAL_I2C_Mem_Write()
- (++) HAL_I2C_Mem_Read()
- (++) HAL_I2C_IsDeviceReady()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2C_Master_Transmit_IT()
- (++) HAL_I2C_Master_Receive_IT()
- (++) HAL_I2C_Slave_Transmit_IT()
- (++) HAL_I2C_Slave_Receive_IT()
- (++) HAL_I2C_Mem_Write_IT()
- (++) HAL_I2C_Mem_Read_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2C_Master_Transmit_DMA()
- (++) HAL_I2C_Master_Receive_DMA()
- (++) HAL_I2C_Slave_Transmit_DMA()
- (++) HAL_I2C_Slave_Receive_DMA()
- (++) HAL_I2C_Mem_Write_DMA()
- (++) HAL_I2C_Mem_Read_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
- (++) HAL_I2C_MasterTxCpltCallback()
- (++) HAL_I2C_MasterRxCpltCallback()
- (++) HAL_I2C_SlaveTxCpltCallback()
- (++) HAL_I2C_SlaveRxCpltCallback()
- (++) HAL_I2C_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* If 10bit addressing mode is selected */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Wait until DIR flag is set Transmitter mode */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Wait until DIR flag is reset Receiver mode */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- while (hi2c->XferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Store Last receive data if any */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferCount--;
- }
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferCount--;
- }
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if (hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- uint32_t xfermode = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- if (hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- /* Update Transfer ISR function pointer */
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* Send Slave Address */
- /* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Slave_ISR_DMA;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
-
- do
- {
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
-
- }
- while (hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferISR = NULL;
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
-
- do
- {
- /* Wait until RXNE flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
- while (hi2c->XferCount > 0U);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- /* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Checks if target device is ready for communication.
- * @note This function is used with Memory devices
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param Trials Number of trials
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- __IO uint32_t I2C_Trials = 0U;
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- do
- {
- /* Generate Start */
- hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set or a NACK flag is set*/
- tickstart = HAL_GetTick();
- while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Device is ready */
- hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check if the NACKF flag has not been set */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
- {
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Device is ready */
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Clear STOP Flag, auto generated with autoend*/
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials++ == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
- }
- while (I2C_Trials < Trials);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = I2C_GENERATE_START_WRITE;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If size > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
-
- /* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = I2C_GENERATE_START_READ;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
-
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
- }
-
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
- {
- xferrequest = I2C_NO_STARTSTOP;
- }
-
- /* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave TX state to RX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
- {
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->XferISR = I2C_Slave_ISR_IT;
-
- /* Enable the Address Match interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
- /* Disable Address listen mode only if a transfer is not ongoing */
- if (hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Disable the Address Match interrupt */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Set State at HAL_I2C_STATE_ABORT */
- hi2c->State = HAL_I2C_STATE_ABORT;
-
- /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
- /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- return HAL_OK;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief This function handles I2C event interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- /* Get current IT Flags and IT sources value */
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
- /* I2C events treatment -------------------------------------*/
- if (hi2c->XferISR != NULL)
- {
- hi2c->XferISR(hi2c, itflags, itsources);
- }
-}
-
-/**
- * @brief This function handles I2C error interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- uint32_t itflags = READ_REG(hi2c->Instance->ISR);
- uint32_t itsources = READ_REG(hi2c->Instance->CR1);
-
- /* I2C Bus error interrupt occurred ------------------------------------*/
- if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
- }
-
- /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
- }
-
- /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
- }
-
- /* Call the Error Callback in case of Error detected */
- if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
- {
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
- * @param AddrMatchCode Address Match Code
- * @retval None
- */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AddrCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ListenCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemTxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C error callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C abort callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State, Mode and Error functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2C handle state.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL state
- */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
- /* Return I2C handle state */
- return hi2c->State;
-}
-
-/**
- * @brief Returns the I2C Master, Slave, Memory or no mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL mode
- */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->Mode;
-}
-
-/**
-* @brief Return the I2C error code.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- uint16_t devaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- /* No need to generate STOP, it is automatically done */
- /* Error callback will be send during stop flag treatment */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
- {
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
- }
- }
- else
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- }
- else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- if (hi2c->XferCount == 0U)
- {
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate a stop condition in case of no transfer option */
- if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
- }
- }
- }
- else
- {
- /* Wrong size Status regarding TC flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
-
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if (hi2c->XferCount == 0U)
- {
- if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
- }
- else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- else
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
- {
- if (hi2c->XferCount > 0U)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
-
- if ((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
- {
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- }
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
- {
- I2C_ITAddrCplt(hi2c, ITFlags);
- }
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
- /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if (hi2c->XferCount > 0U)
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
- else
- {
- if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
- {
- /* Last Byte is Transmitted */
- /* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
- }
- }
- }
-
- /* Check if STOPF is set */
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- uint16_t devaddress = 0U;
- uint32_t xfermode = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set corresponding Error Code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* No need to generate STOP, it is automatically done */
- /* But enable STOP interrupt, to treat it */
- /* Error callback will be send during stop flag treatment */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
- }
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
- {
- /* Disable TC interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
- if (hi2c->XferCount != 0U)
- {
- /* Recover Slave address */
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- /* Prepare the new XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
-
- /* Set the new XferSize in Nbytes register */
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
-
- /* Enable DMA Request */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- else
- {
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- }
- else
- {
- /* Wrong size Status regarding TCR flag event */
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
- }
- }
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param ITFlags Interrupt flags to handle.
- * @param ITSources Interrupt sources enabled.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
-{
- /* Process locked */
- __HAL_LOCK(hi2c);
-
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
- {
- /* Check that I2C transfer finished */
- /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0 */
- /* So clear Flag NACKF only */
- if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- else
- {
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TCR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXIS flag is set */
- if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TC flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief I2C Address complete process callback.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- uint8_t transferdirection = 0U;
- uint16_t slaveaddrcode = 0U;
- uint16_t ownadd1code = 0U;
- uint16_t ownadd2code = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ITFlags);
-
- /* In case of Listen state, need to inform upper layer of address match code event */
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
- {
- transferdirection = I2C_GET_DIR(hi2c);
- slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
- ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
- ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
-
- /* If 10bits addressing mode is selected */
- if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
- {
- slaveaddrcode = ownadd1code;
- hi2c->AddrEventCount++;
- if (hi2c->AddrEventCount == 2U)
- {
- /* Reset Address Event counter */
- hi2c->AddrEventCount = 0U;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- else
- {
- slaveaddrcode = ownadd2code;
-
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- /* else 7 bits addressing mode is selected */
- else
- {
- /* Disable ADDR Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
- }
- }
- /* Else clear address flag only */
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
-}
-
-/**
- * @brief I2C Master sequential complete process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* No Generate Stop, to permit restart mode */
- /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
- hi2c->XferISR = NULL;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Slave sequential complete process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
-{
- /* Reset I2C handle mode */
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
-
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
- {
- /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Master complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = NULL;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- if ((ITFlags & I2C_FLAG_AF) != RESET)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set acknowledge error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- }
- /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- if (hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
- }
-}
-
-/**
- * @brief I2C Slave complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* If a DMA is ongoing, Update handle size context */
- if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
- {
- hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
- }
-
- /* All data are not transferred, so set error code accordingly */
- if (hi2c->XferCount != 0U)
- {
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- /* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
- if ((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, hi2c->ErrorCode);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if (hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- /* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
- }
- }
- else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
- }
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Slave Rx Complete callback */
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Slave Tx Complete callback */
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Listen complete process.
- * @param hi2c I2C handle.
- * @param ITFlags Interrupt flags to handle.
- * @retval None
- */
-static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
-{
- /* Reset handle parameters */
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferISR = NULL;
-
- /* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
- if ((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
- /* Disable all Interrupts*/
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
-}
-
-/**
- * @brief I2C interrupts error process.
- * @param hi2c I2C handle.
- * @param ErrorCode Error code to handle.
- * @retval None
- */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
-{
- /* Reset handle parameters */
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferCount = 0U;
-
- /* Set new error code */
- hi2c->ErrorCode |= ErrorCode;
-
- /* Disable Interrupts */
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- /* Disable all interrupts, except interrupts related to LISTEN state */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* keep HAL_I2C_STATE_LISTEN if set */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = I2C_Slave_ISR_IT;
- }
- else
- {
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
- /* If state is an abort treatment on goind, don't change state */
- /* This change will be do later */
- if (hi2c->State != HAL_I2C_STATE_ABORT)
- {
- /* Set HAL_I2C_STATE_READY */
- hi2c->State = HAL_I2C_STATE_READY;
- }
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->XferISR = NULL;
- }
-
- /* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- /* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
- {
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_ErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Tx data register flush process.
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
-{
- /* If a pending TXIS flag is set */
- /* Write a dummy data in TXDR to clear it */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
- {
- hi2c->Instance->TXDR = 0x00U;
- }
-
- /* Flush TX register if not empty */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
- }
-}
-
-/**
- * @brief DMA I2C master transmit process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if (hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
-}
-
-/**
- * @brief DMA I2C slave transmit process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
- * @brief DMA I2C master receive process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
-
- /* If last transfer, enable STOP interrupt */
- if (hi2c->XferCount == 0U)
- {
- /* Enable STOP interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- }
- /* else prepare a new DMA transfer and enable TCReload interrupt */
- else
- {
- /* Update Buffer pointer */
- hi2c->pBuffPtr += hi2c->XferSize;
-
- /* Set the XferSize to transfer */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
- {
- hi2c->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
- }
-}
-
-/**
- * @brief DMA I2C slave receive process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
-}
-
-/**
- * @brief DMA I2C communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
-}
-
-/**
- * @brief DMA I2C communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma DMA handle.
- * @retval None
- */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_ErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief This function handles I2C Communication Timeout.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag Specifies the I2C flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
- {
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- {
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check if a STOPF is detected */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles Acknowledge failed detection during an I2C Communication.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- /* Wait until STOP Flag is reset */
- /* AutoEnd should be initiate after AF */
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param hi2c I2C handle.
- * @param DevAddress Specifies the slave address to be programmed.
- * @param Size Specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param Mode New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
- * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
- * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
- * @param Request New state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
- * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
- * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
- * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
- * @retval None
- */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_TRANSFER_MODE(Mode));
- assert_param(IS_TRANSFER_REQUEST(Request));
-
- /* Get the CR2 register value */
- tmpreg = hi2c->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
- /* update CR2 register */
- hi2c->Instance->CR2 = tmpreg;
-}
-
-/**
- * @brief Manage the enabling of Interrupts.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
-
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and RXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
- }
-
- if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Enable ERR, TC, STOP, NACK and TXI interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
- }
-
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
- }
-
- /* Enable interrupts only at the end */
- /* to avoid the risk of I2C interrupt handle execution before */
- /* all interrupts requested done */
- __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
-}
-
-/**
- * @brief Manage the disabling of Interrupts.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
- {
- /* Disable TC and TXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
-
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
- {
- /* Disable TC and RXI interrupts */
- tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
-
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
- {
- /* Disable NACK and STOP interrupts */
- tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
- }
-
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Disable ADDR, NACK and STOP interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
- }
-
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
-
- /* Disable interrupts only at the end */
- /* to avoid a breaking situation like at "t" time */
- /* all disable interrupts request are not done */
- __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
deleted file mode 100644
index e4b25f5286f..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2c_ex.c
- * @author MCD Application Team
- * @brief I2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2C Extended peripheral:
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### I2C peripheral Extended features #####
- ==============================================================================
-
- [..] Comparing to other previous devices, the I2C interface for STM32F3xx
- devices contains the following additional features
-
- (+) Possibility to disable or enable Analog Noise Filter
- (+) Use of a configured Digital Noise Filter
- (+) Disable or enable wakeup from Stop mode
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure Noise Filter and Wake Up Feature
- (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
- (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
- (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
- (++) HAL_I2CEx_EnableWakeUp()
- (++) HAL_I2CEx_DisableWakeUp()
- (#) Configure the enable or disable of fast mode plus driving capability using the functions :
- (++) HAL_I2CEx_EnableFastModePlus()
- (++) HAL_I2CEx_DisableFastModePlus()
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2CEx I2CEx
- * @brief I2C Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure Noise Filters
- (+) Configure Wake Up Feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure I2C Analog noise filter.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param AnalogFilter New state of the Analog filter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Reset I2Cx ANOFF bit */
- hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
- /* Set analog filter bit*/
- hi2c->Instance->CR1 |= AnalogFilter;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure I2C Digital noise filter.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Get the old register value */
- tmpreg = hi2c->Instance->CR1;
-
- /* Reset I2Cx DNF bits [11:8] */
- tmpreg &= ~(I2C_CR1_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= DigitalFilter << 8U;
-
- /* Store the new register value */
- hi2c->Instance->CR1 = tmpreg;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable I2C wakeup from stop mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable I2C wakeup from stop mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2Cx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
-{
- /* Check the parameters */
- assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
- if (hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Enable wakeup from stop mode */
- hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
- * @note For all I2C3 pins fast mode plus driving capability can be enabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
- * @retval None
- */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Enable fast mode plus driving capability for selected pin */
- SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-
-/**
- * @brief Disable the I2C fast mode plus driving capability.
- * @param ConfigFastModePlus Selects the pin.
- * This parameter can be one of the @ref I2CEx_FastModePlus values
- * @note For I2C1, fast mode plus driving capability can be disabled on all selected
- * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C2 parameter.
- * @note For all I2C3 pins fast mode plus driving capability can be disabled
- * only by using I2C_FASTMODEPLUS_I2C3 parameter.
- * @retval None
- */
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
- /* Check the parameter */
- assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
- /* Enable SYSCFG clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- /* Disable fast mode plus driving capability for selected pin */
- CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
deleted file mode 100644
index bdfb602441a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2s.c
- * @author MCD Application Team
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Integrated Interchip Sound (I2S) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The I2S HAL driver can be used as follows:
-
- (#) Declare a I2S_HandleTypeDef handle structure.
- (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
- (##) I2S pins configuration:
- (+++) Enable the clock for the I2S GPIOs.
- (+++) Configure these I2S pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
- and HAL_I2S_Receive_IT() APIs).
- (+++) Configure the I2Sx interrupt priority.
- (+++) Enable the NVIC I2S IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
- and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Channel.
- (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Channel.
-
- (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
- using HAL_I2S_Init() function.
-
- -@- The specific I2S interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
- -@- Make sure that either:
- (+@) I2S clock is configured based on SYSCLK or
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
-
- (#) Three mode of operations are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
- *** I2S HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in I2S HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
- (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
- (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
- [..]
- (@) You can refer to the I2S HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2S I2S
- * @brief I2S HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
-
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2S_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Standard
- (++) Data Format
- (++) MCLK Output
- (++) Audio frequency
- (++) Polarity
- (++) Full duplex mode
-
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2S according to the specified parameters
- * in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f3xx_hal_i2s_ex.c to */
- /* handle the possible I2S interfaces defined in STM32F3xx devices */
-
- /* Return error status as not implemented here */
- return HAL_ERROR;
-}
-
-/**
- * @brief DeInitializes the I2S peripheral
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_I2S_MspDeInit(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief I2S MSP Init
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S MSP DeInit
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2S_Transmit()
- (++) HAL_I2S_Receive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2S_Transmit_IT()
- (++) HAL_I2S_Receive_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2S_Transmit_DMA()
- (++) HAL_I2S_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2S_TxCpltCallback()
- (++) HAL_I2S_RxCpltCallback()
- (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- while(hi2s->TxXferCount > 0U)
- {
- hi2s->Instance->DR = (*pData++);
- hi2s->TxXferCount--;
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
- }
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Receive data */
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- (*pData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pTxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
- * between Master and Slave otherwise the I2S interrupt should be optimized.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pRxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Transmit data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
- /* Enable the Tx DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Enable Tx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pRxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Rx DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Enable Rx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Disable the I2S DMA Tx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA Rx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Enable the I2S DMA Tx request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Enable the I2S DMA Rx request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
- }
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- /* Disable the I2S Tx/Rx DMA requests */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- /* Abort the I2S DMA tx channel */
- if(hi2s->hdmatx != NULL)
- {
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmatx);
- }
- /* Abort the I2S DMA rx channel */
- if(hi2s->hdmarx != NULL)
- {
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmarx);
- HAL_DMA_Abort(hi2s->hdmarx);
- }
-
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- __IO uint32_t i2ssr = hi2s->Instance->SR;
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* I2S in mode Receiver ----------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- I2S_Receive_IT(hi2s);
- }
-
- /* I2S Overrun error interrupt occured -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* I2S in mode Tramitter ---------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
- }
-
- /* I2S Underrun error interrupt occured ------------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/**
- * @brief Tx Transfer Half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S error callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2S state
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL state
- */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->State;
-}
-
-/**
- * @brief Return the I2S error code
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval I2S Error Code
- */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- hi2s->TxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S transmit process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable Rx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- HAL_I2S_RxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_RxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Rx and Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
- HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxCpltCallback(hi2s);
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
- * @retval None
- */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_RxCpltCallback(hi2s);
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(State == RESET)
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
deleted file mode 100644
index d6b53f788e4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
+++ /dev/null
@@ -1,1600 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_i2s_ex.c
- * @author MCD Application Team
- * @brief I2S Extended HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of I2S Extended peripheral:
- * + Extended features Functions
- *
- @verbatim
- ==============================================================================
- ##### I2S Extended features #####
- ==============================================================================
- [..]
- (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
- data simultaneously using two data lines. Each SPI peripheral has an extended block
- called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
- (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
- implement full duplex mode. The Extended block uses the same clock sources
- as its master.
-
- (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
-
- -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
- I2Sx can be I2S2 or I2S3.
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- Three mode of operations are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*
- Additional Figure: The Extended block uses the same clock sources as its master.
-
- +-----------------------+
- I2Sx_SCK | |
- ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
- +--|-->| |
- | | +-----------------------+
- | |
- I2S_WS | |
- ------>| |
- | | +-----------------------+
- | +-->| |
- | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
- +----->| |
- +-----------------------+
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2SEx I2SEx
- * @brief I2S Extended HAL module driver
- * @{
- */
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-
-/* Private typedef -----------------------------------------------------------*/
-/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
- * @{
- */
-typedef enum
-{
- I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
- I2S_USE_I2SEXT = 0x01 /*!< I2Sx_ext should be used */
-}I2S_UseTypeDef;
-/**
- * @}
- */
-
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
-static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
-static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
-static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
-static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup I2S I2S
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
-
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2S_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Standard
- (++) Data Format
- (++) MCLK Output
- (++) Audio frequency
- (++) Polarity
-
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2S according to the specified parameters
- * in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: I2S handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
- uint16_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U, i2sclk = 0U;
-#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
- RCC_PeriphCLKInitTypeDef rccperiphclkinit;
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
- assert_param(IS_I2S_MODE(hi2s->Init.Mode));
- assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
- assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
- assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
- assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
- assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
-
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- hi2s->Instance->I2SPR = 0x0002U;
-
- /* Get the I2SCFGR register value */
- tmpreg = hi2s->Instance->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
- {
- i2sodd = (uint16_t)0U;
- i2sdiv = (uint16_t)2U;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
- {
- /* Packet length is 16 bits */
- packetlength = 1U;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2U;
- }
-
- /* Get I2S source Clock frequency ****************************************/
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;
-
- /* If an external I2S clock has to be used, the specific define should be set
- in the project configuration or in the stm32f3xx_conf.h file */
- if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
- {
- /* Set external clock as I2S clock source */
- rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_EXT;
- HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
-
- /* Set the I2S clock to the external clock value */
- i2sclk = EXTERNAL_CLOCK_VALUE;
- }
- else
- {
- /* Set SYSCLK as I2S clock source */
- rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_SYSCLK;
- HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
-
- /* Get the I2S source clock value */
- i2sclk = HAL_RCC_GetSysClockFreq();
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-#if defined (STM32F373xC) || defined (STM32F378xx)
- if(hi2s->Instance == SPI1)
- {
- i2sclk = HAL_RCC_GetPCLK2Freq();
- }
- else if((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
- {
- i2sclk = HAL_RCC_GetPCLK1Freq();
- }
-#endif /* STM32F373xC || STM32F378xx */
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFFU */
- if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
-
- /* Configure the I2S with the I2S_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
- (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
-
- /* Write to SPIx I2SCFGR */
- hi2s->Instance->I2SCFGR = tmpreg;
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
- {
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- I2SxEXT(hi2s->Instance)->I2SPR = 0x0002U;
-
- /* Get the I2SCFGR register value */
- tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
-
- /* Get the mode to be configured for the extended I2S */
- if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
- {
- tmp = I2S_MODE_SLAVE_RX;
- }
- else
- {
- if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
- {
- tmp = I2S_MODE_SLAVE_TX;
- }
- }
-
- /* Configure the I2S Slave with the I2S Master parameter values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
- (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
-
- /* Write to SPIx I2SCFGR */
- I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State= HAL_I2S_STATE_READY;
-
- return HAL_OK;
-}
-/**
- * @}
- */
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/**
- * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
- * @param hi2s: I2S handle
- * @retval HAL status
- */
-void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- __IO uint32_t i2ssr = hi2s->Instance->SR ;
- __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
-
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- /* I2S in mode Transmitter -------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
- }
-
- /* I2Sext in mode Receiver -----------------------------------------------*/
- if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
- the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
- }
-
- /* I2Sext Overrun error interrupt occured --------------------------------*/
- if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
- }
-
- /* I2S Underrun error interrupt occured ----------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Disable RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* I2Sext in mode Transmitter ----------------------------------------------*/
- if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
- }
-
- /* I2S in mode Receiver --------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
- the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
- }
-
- /* I2S Overrun error interrupt occured -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Disable TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
- }
-
- /* I2Sext Underrun error interrupt occured -------------------------------*/
- if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
-}
-
-/**
- * @brief Tx and Rx Transfer completed callbacks
- * @param hi2s: I2S handle
- * @retval None
- */
-__weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer half completed callbacks
- * @param hi2s: I2S handle
- * @retval None
- */
-__weak void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxRxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Pauses the audio stream playing from the Media.
- * @param hi2s : I2S handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hi2s : I2S handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Enable the I2S DMA request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Enable the I2S DMA request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Pause the audio file playing by disabling the I2S DMA request */
- hi2s->Instance->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
- I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
-
- /* If the I2Sext peripheral is still not enabled, enable it */
- if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
- {
- /* Enable I2Sext peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- }
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Disable the I2S DMA requests */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmatx);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA requests */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmarx);
- }
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Disable the I2S DMA requests */
- hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-
- /* Disable the I2S DMA Channels */
- HAL_DMA_Abort(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmarx);
-
- /* Disable I2Sext peripheral */
- __HAL_I2SEXT_DISABLE(hi2s);
- }
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-/** @addtogroup I2SEx
- * @brief I2S Extended HAL module driver
- * @{
- */
-
-/** @defgroup I2SEx_Exported_Functions I2S Extended Exported Functions
- * @{
- */
-
-/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features Functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There is two mode of transfer:
- (++) Blocking mode: The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2S_TransmitReceive()
-
- (#) No-Blocking mode functions with Interrupt are:
- (++) HAL_I2S_TransmitReceive_IT()
- (++) HAL_I2SFullDuplex_IRQHandler()
-
- (#) No-Blocking mode functions with DMA are:
- (++) HAL_I2S_TransmitReceive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (++) HAL_I2S_TxRxCpltCallback()
- (++) HAL_I2S_TxRxHalfCpltCallback()
- (++) HAL_I2S_TxRxErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Full-Duplex Transmit/Receive data in blocking mode.
- * @param hi2s: I2S handle
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Check the I2S State */
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- /* Set the I2S State busy TX/RX */
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- /* Prepare the First Data before enabling the I2S */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
- {
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
- }
-
- /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
- to avoid the clock de-synchronization between Master and Slave. */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2Sx peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until TXE flag is set */
- if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- if (hi2s->TxXferCount > 0U)
- {
- /* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
- }
-
- /* Wait until RXNE flag is set */
- if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an overrun occurs */
- if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* Prepare the First Data before enabling the I2S */
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral before the I2Sext*/
- __HAL_I2S_ENABLE(hi2s);
-
- /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- }
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until TXE flag is set */
- if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- if (hi2s->TxXferCount > 0U)
- {
- /* Check if an underrun occurs */
- if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
- }
-
- /* Wait until RXNE flag is set */
- if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- (*pRxData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
- }
- }
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
- * @param hi2s: I2S handle
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Enable I2Sx TXE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
- {
- /* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0U)
- {
- /* Transmit First data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable I2Sext RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
- }
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2Sx peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* Enable I2Sext TXE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0U)
- {
- /* Transmit First data */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
- /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
- * @param hi2s: I2S handle
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
-
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_TxRxDMAHalfCplt;
-
- /* Set the I2S Rx DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
-
- /* Set the I2S Tx DMA transfer callbacks as NULL because the
- communication closing is performed in DMA reception callbacks */
- hi2s->hdmatx->XferCpltCallback = NULL;
- hi2s->hdmatx->XferHalfCpltCallback = NULL;
-
- /* Set the I2S Tx DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
-
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- /* Enable the Rx DMA Channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
- /* Enable Rx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
-
- /* Enable the Tx DMA Channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
- /* Enable Tx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral after the I2Sext*/
- __HAL_I2S_ENABLE(hi2s);
- }
- }
- else
- {
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Tx DMA Channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
-
- /* Enable Tx DMA Request */
- I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
-
- /* Enable the Rx DMA Channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
- /* Enable Rx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
-
- /* Enable I2S peripheral after the I2Sext*/
- __HAL_I2S_ENABLE(hi2s);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
- * @{
- */
-
-/**
- * @brief DMA I2S transmit receive process complete callback
- * @param hdma DMA handle
- * @retval None
- */
-static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal Mode */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable Rx/Tx DMA Request */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
- else
- {
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
-
- hi2s->RxXferCount = 0U;
- hi2s->TxXferCount = 0U;
-
- hi2s->State = HAL_I2S_STATE_READY;
- }
-
- HAL_I2S_TxRxCpltCallback(hi2s);
-}
-
-static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_I2S_TxRxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma : DMA handle
- * @retval None
- */
-static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Rx and Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
- HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
- * @brief Full-Duplex IT handler transmit function
- * @param hi2s: I2S handle
- * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
- * @retval None
- */
-static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
-{
- if(i2sUsed == I2S_USE_I2S)
- {
- /* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
- else
- {
- /* Transmit data */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
-}
-
-/**
- * @brief Full-Duplex IT handler receive function
- * @param hi2s: I2S handle
- * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
- * @retval None
- */
-static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
-{
- if(i2sUsed == I2S_USE_I2S)
- {
- /* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if(hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
- else
- {
- /* Receive data */
- (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable I2Sext RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if(hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s: I2S handle
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
- * @param i2sUsed: I2S instance reference
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
-{
- uint32_t tickstart = HAL_GetTick();
-
- if(i2sUsed == I2S_USE_I2S)
- {
- if(State == RESET)
- {
- /* Wait until flag is reset */
- while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else /* State == SET */
- {
- /* Wait until flag is set */
- while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != SET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- else /* i2sUsed == I2S_USE_I2SEXT */
- {
- if(State == RESET)
- {
- /* Wait until flag is reset */
- while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else /* State == SET */
- {
- /* Wait until flag is set */
- while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != SET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
-
- return HAL_OK;
-}
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
deleted file mode 100644
index 7c84358d73c..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
+++ /dev/null
@@ -1,2294 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_irda.c
- * @author MCD Application Team
- * @brief IRDA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the IrDA (Infrared Data Association) Peripheral
- * (IRDA)
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The IRDA HAL driver can be used as follows:
-
- (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
- (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
- in setting the associated USART or UART in IRDA mode:
- (++) Enable the USARTx/UARTx interface clock.
- (++) USARTx/UARTx pins configuration:
- (+++) Enable the clock for the USARTx/UARTx GPIOs.
- (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
- (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
- (+++) Configure the USARTx/UARTx interrupt priority.
- (+++) Enable the NVIC USARTx/UARTx IRQ handle.
- (+++) The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
- (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
- and HAL_IRDA_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
- the normal or low power mode and the clock prescaler in the hirda handle Init structure.
-
- (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
- (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_IRDA_MspInit() API.
-
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
- (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
- (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
-
- *** IRDA HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IRDA HAL driver.
-
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
- (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
- (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
- (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
- (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
- (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
-
- [..]
- (@) You can refer to the IRDA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup IRDA IRDA
- * @brief IRDA HAL module driver
- * @{
- */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
- * @{
- */
-#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
-#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx
- in asynchronous IRDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Parity
- (++) Power mode
- (++) Prescaler setting
- (++) Receiver/transmitter modes
-
- [..]
- The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
- (details for the procedures are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/*
- Additional remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible IRDA frame formats are as listed in the following table:
-
- Table 1. IRDA frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | IRDA frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
-/**
- * @brief Initialize the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and initialize the associated handle.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the IRDA handle */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- if(hirda->gState == HAL_IRDA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hirda->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_IRDA_MspInit(hirda);
- }
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* Disable the Peripheral to update the configuration registers */
- __HAL_IRDA_DISABLE(hirda);
-
- /* Set the IRDA Communication parameters */
- if (IRDA_SetConfig(hirda) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-
- /* set the UART/USART in IRDA mode */
- hirda->Instance->CR3 |= USART_CR3_IREN;
-
- /* Enable the Peripheral */
- __HAL_IRDA_ENABLE(hirda);
-
- /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
- return (IRDA_CheckIdleState(hirda));
-}
-
-/**
- * @brief DeInitialize the IRDA peripheral.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the IRDA handle */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_IRDA_MspDeInit(hirda);
- /* Disable the Peripheral */
- __HAL_IRDA_DISABLE(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_RESET;
- hirda->RxState = HAL_IRDA_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the IRDA MSP.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the IRDA MSP.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit and Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the IRDA data transfers.
-
- [..]
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
-
- (#) There are two mode of transfer:
- (++) Blocking mode: the communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: the communication is performed using Interrupts
- or DMA, these API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_IRDA_Transmit()
- (++) HAL_IRDA_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_IRDA_Transmit_IT()
- (++) HAL_IRDA_Receive_IT()
- (++) HAL_IRDA_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_IRDA_Transmit_DMA()
- (++) HAL_IRDA_Receive_DMA()
- (++) HAL_IRDA_DMAPause()
- (++) HAL_IRDA_DMAResume()
- (++) HAL_IRDA_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
- (++) HAL_IRDA_TxHalfCpltCallback()
- (++) HAL_IRDA_TxCpltCallback()
- (++) HAL_IRDA_RxHalfCpltCallback()
- (++) HAL_IRDA_RxCpltCallback()
- (++) HAL_IRDA_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_IRDA_Abort()
- (++) HAL_IRDA_AbortTransmit()
- (++) HAL_IRDA_AbortReceive()
- (++) HAL_IRDA_Abort_IT()
- (++) HAL_IRDA_AbortTransmit_IT()
- (++) HAL_IRDA_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_IRDA_AbortCpltCallback()
- (++) HAL_IRDA_AbortTransmitCpltCallback()
- (++) HAL_IRDA_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Specify timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0U)
- {
- hirda->TxXferCount--;
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2U;
- }
- else
- {
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
- }
- }
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @param Timeout Specify timeout value.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
- uhMask = hirda->Mask;
-
- /* Check data remaining to be received */
- while(hirda->RxXferCount > 0U)
- {
- hirda->RxXferCount--;
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2U;
- }
- else
- {
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Transmit Data Register Empty Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
- assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the IRDA transmit DMA channel */
- HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @note When the IRDA parity is enabled (PCE = 1), the received data contains
- * the parity bit (MSB position).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
- assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the IRDA DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- /* Enable the IRDA DMA Tx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the IRDA DMA Rx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
- HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
-
- /* Stop IRDA DMA Tx request if ongoing */
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmatx);
- }
-
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmarx);
- }
-
- IRDA_EndRxTransfer(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0U;
- hirda->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
- }
- else
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
- }
- else
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
- {
- /* IRDA Tx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
- {
- /* IRDA Rx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0U;
- hirda->RxXferCount = 0U;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
- hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable IRDA Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle IRDA interrupt request.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
- uint32_t isrflags = READ_REG(hirda->Instance->ISR);
- uint32_t cr1its = READ_REG(hirda->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
- {
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(hirda->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
- {
- /* IRDA parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
- }
-
- /* IRDA frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- }
-
- /* IRDA noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- }
-
- /* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- }
-
- /* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
- {
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the IRDA state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- IRDA_EndRxTransfer(hirda);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- IRDA_Transmit_IT(hirda);
- return;
- }
-
- /* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- IRDA_EndTransmit_IT(hirda);
- return;
- }
-
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA error callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Receive Complete callback.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief IRDA State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of IrDA
- communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
- of the IRDA peripheral handle.
- (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
- communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the IRDA handle state.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL state
- */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
- /* Return IRDA handle state */
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
-
- return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the IRDA handle error code.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval IRDA Error Code
- */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
- return hirda->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @brief Configure the IRDA peripheral.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tmpreg = 0x00000000U;
- IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the communication parameters */
- assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
- assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
- assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
- assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
- assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
- assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Configure the IRDA Word Length, Parity and transfer Mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
- tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
-
- MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- IRDA_GETCLOCKSOURCE(hirda, clocksource);
- switch (clocksource)
- {
- case IRDA_CLOCKSOURCE_PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_PCLK2:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_SYSCLK:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- return ret;
-}
-
-/**
- * @brief Check the IRDA Idle State.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the IRDA ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* TEACK bits in ISR is checked only when available.
- Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature.
- */
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
- {
- /* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check if the Receiver is enabled */
- if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the IRDA state*/
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle IRDA Communication Timeout.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param Flag Specifies the IRDA flag to check.
- * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-
-/**
- * @brief DMA IRDA transmit process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- hirda->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else
- {
- HAL_IRDA_TxCpltCallback(hirda);
- }
-
-}
-
-/**
- * @brief DMA IRDA transmit process half complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- HAL_IRDA_TxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- hirda->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- HAL_IRDA_RxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication error callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- /* Stop IRDA DMA Tx request if ongoing */
- if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
- {
- hirda->TxXferCount = 0U;
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
- {
- hirda->RxXferCount = 0U;
- IRDA_EndRxTransfer(hirda);
- }
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
- hirda->RxXferCount = 0U;
- hirda->TxXferCount = 0U;
-
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
-
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
- {
- if(hirda->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0U;
- hirda->RxXferCount = 0U;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
-
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
- {
- if(hirda->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0U;
- hirda->RxXferCount = 0U;
-
- /* Reset errorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
-
- hirda->TxXferCount = 0U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Transmit_IT().
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- if(hirda->TxXferCount == 0U)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- hirda->pTxBuffPtr += 2U;
- }
- else
- {
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
- hirda->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable the IRDA Transmit Complete Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- /* Tx process is ended, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Receive_IT()
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
- uint16_t uhMask = hirda->Mask;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
- *tmp = (uint16_t)(uhdata & uhMask);
- hirda->pRxBuffPtr +=2U;
- }
- else
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
- }
-
- if(--hirda->RxXferCount == 0U)
- {
- /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
deleted file mode 100644
index 479f4d95072..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_iwdg.c
- * @author MCD Application Team
- * @brief IWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and Start functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### IWDG Generic features #####
- ==============================================================================
- [..]
- (+) The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
-
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
- disabled. The counter starts counting down from the reset value (0xFFFU).
- When it reaches the end of count value (0x000U) a reset signal is
- generated (IWDG reset).
-
- (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
-
- (+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
- reset occurs.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the IWDG counter either continues to work normally or stops, depending
- on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
-
- [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
- IWDG_WINR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
- value will be loaded in the IWDG counter each time the watchdog is
- reloaded, then the IWDG will start counting down from this value.
- (++) wait for status flags to be reset"
- (++) Depending on window parameter:
- (+++) If Window Init parameter is same as Window register value,
- nothing more is done but reload counter value in order to exit
- function withy exact time base.
- (+++) Else modify Window register. This will automatically reload
- watchdog counter.
-
- (#) Then the application program must refresh the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- HAL_IWDG_Refresh() function.
-
- *** IWDG HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IWDG HAL driver:
- (+) __HAL_IWDG_START: Enable the IWDG peripheral
- (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
- the reload register
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-/** @addtogroup IWDG
- * @brief IWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
- * @{
- */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256U), and according to HSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48u
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Start functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters in the
- IWDG_InitTypeDef of associated handle.
- (+) Manage Window option.
- (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
- is reloaded in order to exit function with correct time base.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the IWDG according to the specified parameters in the
- * IWDG_InitTypeDef and start watchdog. Before exiting function,
- * watchdog is refreshed in order to have correct time base.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
- uint32_t tickstart;
-
- /* Check the IWDG handle allocation */
- if(hiwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
- assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
- assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
- assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
-
- /* Enable IWDG. LSI is turned on automaticaly */
- __HAL_IWDG_START(hiwdg);
-
- /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
- 0x5555 in KR */
- IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
- /* Write to IWDG registers the Prescaler & Reload values to work with */
- hiwdg->Instance->PR = hiwdg->Init.Prescaler;
- hiwdg->Instance->RLR = hiwdg->Init.Reload;
-
- /* Check pending flag, if previous update not done, return timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If window parameter is different than current value, modify window
- register */
- if(hiwdg->Instance->WINR != hiwdg->Init.Window)
- {
- /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
- even if window feature is disabled, Watchdog will be reloaded by writing
- windows register */
- hiwdg->Instance->WINR = hiwdg->Init.Window;
- }
- else
- {
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Refresh the IWDG.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Refresh the IWDG.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
deleted file mode 100644
index 2772b83f007..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_msp_template.c
- * @author MCD Application Team
- * @brief HAL MSP module.
- * This file template is located in the HAL folder and should be copied
- * to the user folder.
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL_MSP HAL MSP module
- * @brief HAL MSP module.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
- * @{
- */
-
-/**
- * @brief Initializes the Global MSP.
- * @retval None
- */
-void HAL_MspInit(void)
-{
-
-}
-
-/**
- * @brief DeInitializes the Global MSP.
- * @retval None
- */
-void HAL_MspDeInit(void)
-{
-
-}
-
-/**
- * @brief Initializes the PPP MSP.
- * @retval None
- */
-void HAL_PPP_MspInit(void)
-{
-
-}
-
-/**
- * @brief DeInitializes the PPP MSP.
- * @retval None
- */
-void HAL_PPP_MspDeInit(void)
-{
-
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
deleted file mode 100644
index 23fb514fa27..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
+++ /dev/null
@@ -1,1807 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_nand.c
- * @author MCD Application Team
- * @brief NAND HAL module driver.
- * This file provides a generic firmware to drive NAND memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NAND flash memories. It uses the FMC layer functions to interface
- with NAND devices. This driver is used as follows:
-
- (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
- with control and timing parameters for both common and attribute spaces.
-
- (+) Read NAND flash memory maker and device IDs using the function
- HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NAND flash memory by read/write operations using the functions
- HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
- HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
- HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
- HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
- to read/write page(s)/spare area(s). These functions use specific device
- information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
- structure. The read/write address information is contained by the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
-
- (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
- The erase block address information is contained in the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
-
- (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
- HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
- feature or the function HAL_NAND_GetECC() to get the ECC correction code.
-
- (+) You can monitor the NAND device HAL state by calling the function
- HAL_NAND_GetState()
-
- [..]
- (@) This driver is a set of generic APIs which handle standard NAND flash operations.
- If a NAND flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-
-/** @defgroup NAND NAND
- * @brief NAND HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @}
- */
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NAND memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform NAND memory Initialization sequence
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ComSpace_Timing pointer to Common space timing structure
- * @param AttSpace_Timing pointer to Attribute space timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
-{
- /* Check the NAND handle state */
- if(hnand == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnand->State == HAL_NAND_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnand->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspInit(hnand);
- }
-
- /* Initialize NAND control Interface */
- FMC_NAND_Init(hnand->Instance, &(hnand->Init));
-
- /* Initialize NAND common space timing Interface */
- FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
-
- /* Initialize NAND attribute space timing Interface */
- FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
-
- /* Enable the NAND device */
- __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NAND memory De-Initialization sequence
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
-{
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspDeInit(hnand);
-
- /* Configure the NAND registers with their reset values */
- FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
-
- /* Reset the NAND controller state */
- hnand->State = HAL_NAND_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND MSP Init
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NAND MSP DeInit
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief This function handles NAND device interrupt request.
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
-*/
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
-{
- /* Check NAND interrupt Rising edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Rising edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
- }
-
- /* Check NAND interrupt Level flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Level pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
- }
-
- /* Check NAND interrupt Falling edge flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Falling edge pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
- }
-
- /* Check NAND interrupt FIFO empty flag */
- if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt FIFO empty pending bit */
- __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
- }
-}
-
-/**
- * @brief NAND interrupt feature callback
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_ITCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NAND
- memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the NAND memory electronic signature
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pNAND_ID NAND ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
-{
- __IO uint32_t data = 0U;
- __IO uint32_t data1 = 0U;
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
-
- /* Read the electronic signature from NAND flash */
- if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
- {
- data = *(__IO uint32_t *)deviceaddress;
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
- }
- else
- {
- data = *(__IO uint32_t *)deviceaddress;
- data1 = *((__IO uint32_t *)deviceaddress + 4U);
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
- pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory reset
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Configure the device: Enter the physical parameters of the device
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
-{
- hnand->Config.PageSize = pDeviceConfig->PageSize;
- hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
- hnand->Config.BlockSize = pDeviceConfig->BlockSize;
- hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
- hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
- hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
- hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Page(s) from NAND memory block (8-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to destination read buffer
- * @param NumPageToRead number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- /* Check if an extra command is needed for reading pages */
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- __DSB();
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Page(s) from NAND memory block (16-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
- * @param NumPageToRead number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (8-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- __DSB();
- }
- }
-
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (16-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- __DSB();
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write
- * @param NumSpareAreaToRead Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory (16-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaToRead Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Page address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory (16-bits addressing)
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory Block erase
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t deviceaddress = 0U;
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory read status
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval NAND status
- */
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
-{
- uint32_t data = 0U;
- uint32_t deviceaddress = 0U;
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
-
- /* Read status register data */
- data = *(__IO uint8_t *)deviceaddress;
-
- /* Return the status */
- if((data & NAND_ERROR) == NAND_ERROR)
- {
- return NAND_ERROR;
- }
- else if((data & NAND_READY) == NAND_READY)
- {
- return NAND_READY;
- }
-
- return NAND_BUSY;
-}
-
-/**
- * @brief Increment the NAND memory address
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress pointer to NAND address structure
- * @retval The new status of the increment address operation. It can be:
- * - NAND_VALID_ADDRESS: When the new address is valid address
- * - NAND_INVALID_ADDRESS: When the new address is invalid address
- */
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t status = NAND_VALID_ADDRESS;
-
- /* Increment page address */
- pAddress->Page++;
-
- /* Check NAND address is valid */
- if(pAddress->Page == hnand->Config.BlockSize)
- {
- pAddress->Page = 0U;
- pAddress->Block++;
-
- if(pAddress->Block == hnand->Config.PlaneSize)
- {
- pAddress->Block = 0U;
- pAddress->Plane++;
-
- if(pAddress->Plane == (hnand->Config.PlaneNbr))
- {
- status = NAND_INVALID_ADDRESS;
- }
- }
- }
-
- return (status);
-}
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NAND interface.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables dynamically NAND ECC feature.
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Enable ECC feature */
- FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Disable ECC feature */
- FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NAND ECC feature.
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ECCval pointer to ECC value
- * @param Timeout maximum timeout to wait
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Get NAND ECC value */
- status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return status;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NAND State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NAND controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NAND state
- * @param hnand pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL state
- */
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
-{
- return hnand->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
deleted file mode 100644
index 25bf4123a91..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
+++ /dev/null
@@ -1,1057 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_nor.c
- * @author MCD Application Team
- * @brief NOR HAL module driver.
- * This file provides a generic firmware to drive NOR memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NOR flash memories. It uses the FMC layer functions to interface
- with NOR devices. This driver is used as follows:
-
- (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
- with control and timing parameters for both normal and extended mode.
-
- (+) Read NOR flash memory manufacturer code and device IDs using the function
- HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NOR flash memory by read/write data unit operations using the functions
- HAL_NOR_Read(), HAL_NOR_Program().
-
- (+) Perform NOR flash erase block/chip operations using the functions
- HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-
- (+) Read the NOR flash CFI (common flash interface) IDs using the function
- HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
- structure declared by the function caller.
-
- (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
- HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
-
- (+) You can monitor the NOR device HAL state by calling the function
- HAL_NOR_GetState()
- [..]
- (@) This driver is a set of generic APIs which handle standard NOR flash operations.
- If a NOR flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- *** NOR HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in NOR HAL driver.
-
- (+) NOR_WRITE: NOR memory write data to specified address
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-/** @defgroup NOR NOR
- * @brief NOR HAL module driver
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
- * @{
- */
-
-/* Constants to define address to set to write a command */
-#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
-#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
-
-/* Constants to define data to program a command */
-#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
-#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
-#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
-#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
-#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
-#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
-#define NOR_CMD_DATA_CFI (uint16_t)0x0098
-
-#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
-#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
-#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
-
-/* Mask on NOR STATUS REGISTER */
-#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
-#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup NOR_Private_Macros NOR Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Variables NOR Private Variables
- * @{
- */
-
-static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform the NOR memory Initialization sequence
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timing pointer to NOR control timing structure
- * @param ExtTiming pointer to NOR extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the NOR handle parameter */
- if(hnor == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnor->State == HAL_NOR_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnor->Lock = HAL_UNLOCKED;
-
- /* Initialize the low level hardware (MSP) */
- HAL_NOR_MspInit(hnor);
- }
-
- /* Initialize NOR control Interface */
- FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
-
- /* Initialize NOR timing Interface */
- FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
-
- /* Initialize NOR extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
-
- /* Initialize NOR Memory Data Width*/
- if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
- {
- uwNORMemoryDataWidth = NOR_MEMORY_8B;
- }
- else
- {
- uwNORMemoryDataWidth = NOR_MEMORY_16B;
- }
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NOR memory De-Initialization sequence
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_NOR_MspDeInit(hnor);
-
- /* Configure the NOR registers with their reset values */
- FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief NOR MSP Init
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP DeInit
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP Wait fro Ready/Busy signal
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timeout Maximum timeout value
- * @retval None
- */
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
- UNUSED(Timeout);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspWait could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read NOR flash IDs
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_ID pointer to NOR ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the NOR memory to Read mode.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read data from NOR memory
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress pointer to Device address
- * @param pData pointer to read data
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
-
- /* Read the data */
- *pData = *(__IO uint32_t *)(uint32_t)pAddress;
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Program data to NOR memory
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress Device address
- * @param pData pointer to the data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a block of data from the FMC NOR memory.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param uwAddress NOR memory internal address to read from.
- * @param pData pointer to the buffer that receives the data read from the
- * NOR memory.
- * @param uwBufferSize number of Half word to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while( uwBufferSize > 0U)
- {
- *pData++ = *(__IO uint16_t *)uwAddress;
- uwAddress += 2U;
- uwBufferSize--;
- }
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a half-word buffer to the FMC NOR memory. This function
- * must be used only with S29GL128P NOR memory.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param uwAddress NOR memory internal address from which the data
- * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
- * 64 bytes boundary for example).
- * @param pData pointer to source data buffer.
- * @param uwBufferSize number of Half words to write.
- * @note The maximum buffer size allowed is NOR memory dependent
- * (can be 64 Bytes max for example).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint16_t * p_currentaddress = (uint16_t *)NULL;
- uint16_t * p_endaddress = (uint16_t *)NULL;
- uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Initialize variables */
- p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
- p_endaddress = p_currentaddress + (uwBufferSize-1U);
- lastloadedaddress = (uint32_t)(uwAddress);
-
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
-
- /* Load Data into NOR Buffer */
- while(p_currentaddress <= p_endaddress)
- {
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
-
- NOR_WRITE(p_currentaddress, *pData++);
-
- p_currentaddress++;
- }
-
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the specified block of the NOR memory
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param BlockAddress Block to erase address
- * @param Address Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the entire NOR chip.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read NOR flash CFI IDs
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_CFI pointer to NOR CFI IDs structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
- /* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NOR Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NOR interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically NOR write operation.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NOR write operation.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Update the SRAM controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NOR State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NOR controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NOR controller state
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval NOR controller state
- */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
-{
- return hnor->State;
-}
-
-/**
- * @brief Returns the NOR operation status.
- * @param hnor pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address Device address
- * @param Timeout NOR progamming Timeout
- * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
- * or HAL_NOR_STATUS_TIMEOUT
- */
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{
- HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmp_sr1 = 0U, tmp_sr2 = 0U;
- uint32_t tickstart = 0U;
-
- /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
- HAL_NOR_MspWait(hnor, Timeout);
-
- /* Get tick */
- tickstart = HAL_GetTick();
- while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- status = HAL_NOR_STATUS_TIMEOUT;
- }
- }
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmp_sr1 = *(__IO uint16_t *)Address;
- tmp_sr2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS;
- }
-
- if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
-
- tmp_sr1 = *(__IO uint16_t *)Address;
- tmp_sr2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS;
- }
- else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- return HAL_NOR_STATUS_ERROR;
- }
- }
-
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
deleted file mode 100644
index 3a69f7fb975..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
+++ /dev/null
@@ -1,922 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_opamp.c
- * @author MCD Application Team
- * @brief OPAMP HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
- * peripheral:
- * + OPAMP Configuration
- * + OPAMP calibration
- * Thanks to
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
-================================================================================
- ##### OPAMP Peripheral Features #####
-================================================================================
-
- [..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
- OPAMP3 and OPAMP4:
-
- (#) The OPAMP(s) provides several exclusive running modes.
- (++) Standalone mode
- (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
- (++) Follower mode
-
- (#) The OPAMP(s) provide(s) calibration capabilities.
- (++) Calibration aims at correcting some offset for running mode.
- (++) The OPAMP uses either factory calibration settings OR user defined
- calibration (trimming) settings (i.e. trimming mode).
- (++) The user defined settings can be figured out using self calibration
- handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
- (++) HAL_OPAMP_SelfCalibrate:
- (++) Runs automatically the calibration in 2 steps.
- (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors).
- (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
- appropriate and enough in most cases).
- (++) Enables the user trimming mode
- (++) Updates the init structure with trimming values with fresh calibration
- results.
- The user may store the calibration results for larger
- (ex monitoring the trimming as a function of temperature
- for instance)
- (++) for STM32F3 devices having 2 or 4 OPAMPs
- HAL_OPAMPEx_SelfCalibrateAll
- runs calibration of 2 or 4 OPAMPs in parallel.
-
- (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
- mode can be set on top.
- (++) Timer-controlled Mux mode allows Automatic switching between inverting
- and non-inverting input.
- (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
- the user shall select secondary inverting and non inverting inputs.
- (++) TIM1 CC6 provides the alternate switching tempo between defaults
- (primary) and secondary inputs.
-
- (#) Running mode: Standalone mode
- (++) Gain is set externally (gain depends on external loads).
- (++) Follower mode also possible externally by connecting the inverting input to
- the output.
-
- (#) Running mode: Follower mode
- (++) No Inverting Input is connected.
-
- (#) Running mode: Programmable Gain Amplifier (PGA) mode
- (Resistor feedback output)
- (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
- output.
- (++) OPAMP gain is either 2U, 4U, 8 or 16.
-
-
- ##### How to use this driver #####
-================================================================================
- [..]
- *** Calibration ***
- ============================================
- [..]
- To run the opamp calibration self calibration:
-
- (#) Start calibration using HAL_OPAMP_SelfCalibrate.
- Store the calibration results.
-
- *** Running mode ***
- ============================================
- [..]
- To use the opamp, perform the following steps:
-
- (#) Fill in the HAL_OPAMP_MspInit() to
- (++) Configure the opamp input AND output in analog mode using
- HAL_GPIO_Init() to map the opamp output to the GPIO pin.
-
- (#) Configure the opamp using HAL_OPAMP_Init() function:
- (++) Select the mode
- (++) Select the inverting input
- (++) Select the non-inverting input
- (++) Select if the Timer controlled Mux mode is enabled/disabled
- (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
- (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
- (++) If PGA mode is enabled, Select if inverting input is connected.
- (++) Select either factory or user defined trimming mode.
- (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
- (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
-
- (#) Enable the opamp using HAL_OPAMP_Start() function.
-
- (#) Disable the opamp using HAL_OPAMP_Stop() function.
-
- (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
- can be modified
- (++) After HW reset
- (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.
-
- *** Running mode: change of configuration while OPAMP ON ***
- ============================================
- [..]
- To Re-configure OPAMP when OPAMP is ON (change on the fly)
- (#) If needed, Fill in the HAL_OPAMP_MspInit()
- (++) This is the case for instance if you wish to use new OPAMP I/O
-
- (#) Configure the opamp using HAL_OPAMP_Init() function:
- (++) As in configure case, selects first the parameters you wish to modify.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*
- Additional Tables:
- The OPAMPs non inverting input (both default and secondary) can be
- selected among the list shown by table below.
-
- The OPAMPs non inverting input (both default and secondary) can be
- selected among the list shown by table below.
-
- Table 1. OPAMPs inverting/non-inverting inputs for the STM32F3 devices:
- +--------------------------------------------------------------+
- | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
- |-----------------|--------|--------|--------|--------|--------|
- | | No conn| X | X | X | X |
- | Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
- | (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
- |-----------------|--------|--------|--------|--------|--------|
- | | VP0 | PA1 | PA7 | PB0 | PB13 |
- | Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
- | Input | VP2 | PA3 | PB0 | PA1 | PA4 |
- | | VP3 | PA5 | PB14 | PA5 | PB11 |
- +--------------------------------------------------------------+
- (1): NA in follower mode.
-
- Table 2. OPAMPs outputs for the STM32F3 devices:
- +--------------------------------------------------------------+
- | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
- |-----------------|--------|--------|--------|--------|--------|
- | Output | | PA2 | PA6 | PB1 | PB12 |
- |-----------------|--------|--------|--------|--------|--------|
-
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-/** @defgroup OPAMP OPAMP
- * @brief OPAMP HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup OPAMP_Private_Define OPAMP Private Define
- * @{
- */
-/* CSR register reset value */
-#define OPAMP_CSR_RESET_VALUE (0x00000000U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
- * @{
- */
-
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the OPAMP according to the specified
- * parameters in the OPAMP_InitTypeDef and create the associated handle.
- * @note If the selected opamp is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param hopamp OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
-
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation and lock status */
- /* Init not allowed if calibration is ongoing */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- return HAL_ERROR;
- }
- else
- {
-
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Set OPAMP parameters */
- assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
- assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
- if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
- {
- assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
- }
-
- assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
-
- if ((hopamp->Init.TimerControlledMuxmode) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE)
- {
- assert_param(IS_OPAMP_SEC_NONINVERTINGINPUT(hopamp->Init.NonInvertingInputSecondary));
- if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
- {
- assert_param(IS_OPAMP_SEC_INVERTINGINPUT(hopamp->Init.InvertingInputSecondary));
- }
- }
-
- if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
- {
- assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
- assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
- }
-
- assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
- if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
- {
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
- assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
- }
-
- /* Init SYSCFG and the low level hardware to access opamp */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
-
- if(hopamp->State == HAL_OPAMP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hopamp->Lock = HAL_UNLOCKED;
- }
-
- /* Call MSP init function */
- HAL_OPAMP_MspInit(hopamp);
-
- /* Set OPAMP parameters */
- /* Set bits according to hopamp->hopamp->Init.Mode value */
- /* Set bits according to hopamp->hopamp->Init.InvertingInput value */
- /* Set bits according to hopamp->hopamp->Init.NonInvertingInput value */
- /* Set bits according to hopamp->hopamp->Init.TimerControlledMuxmode value */
- /* Set bits according to hopamp->hopamp->Init.InvertingInputSecondary value */
- /* Set bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value */
- /* Set bits according to hopamp->hopamp->Init.PgaConnect value */
- /* Set bits according to hopamp->hopamp->Init.PgaGain value */
- /* Set bits according to hopamp->hopamp->Init.UserTrimming value */
- /* Set bits according to hopamp->hopamp->Init.TrimmingValueP value */
- /* Set bits according to hopamp->hopamp->Init.TrimmingValueN value */
-
-
- /* check if OPAMP_PGA_MODE & in Follower mode */
- /* - InvertingInput */
- /* - InvertingInputSecondary */
- /* are Not Applicable */
-
- if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
- {
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
- hopamp->Init.Mode | \
- hopamp->Init.NonInvertingInput | \
- hopamp->Init.TimerControlledMuxmode | \
- hopamp->Init.NonInvertingInputSecondary | \
- hopamp->Init.PgaConnect | \
- hopamp->Init.PgaGain | \
- hopamp->Init.UserTrimming | \
- (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
- (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
-
- }
- else /* OPAMP_STANDALONE_MODE */
- {
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
- hopamp->Init.Mode | \
- hopamp->Init.InvertingInput | \
- hopamp->Init.NonInvertingInput | \
- hopamp->Init.TimerControlledMuxmode | \
- hopamp->Init.InvertingInputSecondary | \
- hopamp->Init.NonInvertingInputSecondary | \
- hopamp->Init.PgaConnect | \
- hopamp->Init.PgaGain | \
- hopamp->Init.UserTrimming | \
- (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
- (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
- }
-
- /* Update the OPAMP state*/
- if (hopamp->State == HAL_OPAMP_STATE_RESET)
- {
- /* From RESET state to READY State */
- hopamp->State = HAL_OPAMP_STATE_READY;
- }
- /* else: remain in READY or BUSY state (no update) */
-
- return status;
- }
-}
-
-
-/**
- * @brief DeInitializes the OPAMP peripheral
- * @note Deinitialization can't be performed if the OPAMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param hopamp OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* DeInit not allowed if calibration is ongoing */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Set OPAMP_CSR register to reset value */
- WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
-
- /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
- /* When OPAMP is locked, unlocking can be achieved thanks to */
- /* __HAL_RCC_SYSCFG_CLK_DISABLE() call within HAL_OPAMP_MspDeInit */
- /* Note that __HAL_RCC_SYSCFG_CLK_DISABLE() also disables comparator */
- HAL_OPAMP_MspDeInit(hopamp);
-
- if (OPAMP_CSR_RESET_VALUE == hopamp->Instance->CSR)
- {
- /* Update the OPAMP state */
- hopamp->State = HAL_OPAMP_STATE_RESET;
- }
- else /* RESET STATE */
- {
- /* DeInit not complete */
- /* It can be the case if OPAMP was formerly locked */
- status = HAL_ERROR;
-
- /* The OPAMP state is NOT updated */
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hopamp);
- }
-
- return status;
-}
-
-/**
- * @brief Initializes the OPAMP MSP.
- * @param hopamp OPAMP handle
- * @retval None
- */
-__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hopamp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_OPAMP_MspInit could be implemented in the user file
- */
-
- /* Example */
-}
-
-/**
- * @brief DeInitializes OPAMP MSP.
- * @param hopamp OPAMP handle
- * @retval None
- */
-__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hopamp);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_OPAMP_MspDeInit could be implemented in the user file
- */
-
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the OPAMP data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the opamp
- * @param hopamp OPAMP handle
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- if(hopamp->State == HAL_OPAMP_STATE_READY)
- {
- /* Enable the selected opamp */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Update the OPAMP state*/
- /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
- hopamp->State = HAL_OPAMP_STATE_BUSY;
- }
- else
- {
- status = HAL_ERROR;
- }
-
-
- }
- return status;
-}
-
-/**
- * @brief Stop the opamp
- * @param hopamp OPAMP handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- /* Check if OPAMP calibration ongoing */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
- || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- if(hopamp->State == HAL_OPAMP_STATE_BUSY)
- {
- /* Disable the selected opamp */
- CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Update the OPAMP state*/
- /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
- hopamp->State = HAL_OPAMP_STATE_READY;
- }
- else
- {
- status = HAL_ERROR;
- }
- }
- return status;
-}
-
-/**
- * @brief Run the self calibration of one OPAMP
- * @param hopamp handle
- * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
- * @retval HAL status
- * @note Calibration runs about 25 ms.
- */
-
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
-{
-
- HAL_StatusTypeDef status = HAL_OK;
-
- uint32_t trimmingvaluen = 0U;
- uint32_t trimmingvaluep = 0U;
- uint32_t delta;
-
- /* Check the OPAMP handle allocation */
- /* Check if OPAMP locked */
- if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
- {
- status = HAL_ERROR;
- }
- else
- {
-
- /* Check if OPAMP in calibration mode and calibration not yet enable */
- if(hopamp->State == HAL_OPAMP_STATE_READY)
- {
- /* Check the parameter */
- assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Set Calibration mode */
- /* Non-inverting input connected to calibration reference voltage. */
- SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
-
- /* user trimming values are used for offset calibration */
- SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
-
- /* Enable calibration */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
-
- /* 1st calibration - N */
- /* Select 90U% VREF */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
-
- /* Enable the selected opamp */
- SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Init trimming counter */
- /* Medium value */
- trimmingvaluen = 16U;
- delta = 8U;
-
- while (delta != 0U)
- {
- /* Set candidate trimming */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCD PCD
- * @brief PCD HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup PCD_Private_Define PCD Private Define
- * @{
- */
-#define BTABLE_ADDRESS (0x000U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
- uint32_t i = 0U;
-
- uint32_t wInterrupt_Mask = 0U;
-
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
- if(hpcd->State == HAL_PCD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hpcd->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Init endpoints structures */
- for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
- {
- /* Init ep structure */
- hpcd->IN_ep[i].is_in = 1U;
- hpcd->IN_ep[i].num = i;
- /* Control until ep is actvated */
- hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0U;
- hpcd->IN_ep[i].xfer_buff = 0U;
- hpcd->IN_ep[i].xfer_len = 0U;
- }
-
- for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
- {
- hpcd->OUT_ep[i].is_in = 0U;
- hpcd->OUT_ep[i].num = i;
- /* Control until ep is activated */
- hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0U;
- hpcd->OUT_ep[i].xfer_buff = 0U;
- hpcd->OUT_ep[i].xfer_len = 0U;
- }
-
- /* Init Device */
- /*CNTR_FRES = 1U*/
- hpcd->Instance->CNTR = USB_CNTR_FRES;
-
- /*CNTR_FRES = 0U*/
- hpcd->Instance->CNTR = 0U;
-
- /*Clear pending interrupts*/
- hpcd->Instance->ISTR = 0U;
-
- /*Set Btable Adress*/
- hpcd->Instance->BTABLE = BTABLE_ADDRESS;
-
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /*Set interrupt mask*/
- hpcd->Instance->CNTR = wInterrupt_Mask;
-
- hpcd->USB_Address = 0U;
- hpcd->State= HAL_PCD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the PCD peripheral
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Stop Device */
- HAL_PCD_Stop(hpcd);
-
- /* DeInit the low level hardware */
- HAL_PCD_MspDeInit(hpcd);
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the PCD MSP.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes PCD MSP.
- * @param hpcd PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the USB device.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
- /* DP Pull-Down is external */
- HAL_PCDEx_SetConnectionState (hpcd, 1U);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the USB device.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
-
- /* disable all interrupts and force USB reset */
- hpcd->Instance->CNTR = USB_CNTR_FRES;
-
- /* clear interrupt status register */
- hpcd->Instance->ISTR = 0U;
-
- /* switch-off device */
- hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
-
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-/**
- * @brief This function handles PCD Endpoint interrupt request.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
- PCD_EPTypeDef *ep;
- uint16_t count=0U;
- uint8_t EPindex;
- __IO uint16_t wIstr;
- __IO uint16_t wEPVal = 0U;
-
- /* stay in loop while pending interrupts */
- while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
- {
- /* extract highest priority endpoint number */
- EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
- if (EPindex == 0U)
- {
- /* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
- if ((wIstr & USB_ISTR_DIR) == 0U)
- {
- /* DIR = 0U */
-
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1U) always */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- ep = &hpcd->IN_ep[0];
-
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, 0U);
-
-
- if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
- {
- hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0U;
- }
-
- }
- else
- {
- /* DIR = 1U */
-
- /* DIR = 1U & CTR_RX => SETUP or OUT int */
- /* DIR = 1U & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &hpcd->OUT_ep[0];
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
- if ((wEPVal & USB_EP_SETUP) != 0U)
- {
- /* Get SETUP Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1U*/
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
- /* Process SETUP Packet*/
- HAL_PCD_SetupStageCallback(hpcd);
- }
-
- else if ((wEPVal & USB_EP_CTR_RX) != 0U)
- {
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- /* Get Control Data OUT Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_count != 0U)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- ep->xfer_buff+=ep->xfer_count;
- }
-
- /* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0U);
-
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
- }
- }
- }
- else
- {
-
- /* Decode and service non control endpoints interrupt */
-
- /* process related endpoint register */
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
- if ((wEPVal & USB_EP_CTR_RX) != 0U)
- {
- /* clear int flag */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
- ep = &hpcd->OUT_ep[EPindex];
-
- /* OUT double Buffering*/
- if (ep->doublebuffer == 0U)
- {
- count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
- }
- }
- else
- {
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
- {
- /*read from endpoint BUF0Addr buffer*/
- count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
- }
- /*multi-packet on the NON control OUT endpoint*/
- ep->xfer_count+=count;
- ep->xfer_buff+=count;
-
- if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
- {
- /* RX COMPLETE */
- HAL_PCD_DataOutStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
-
- } /* if((wEPVal & EP_CTR_RX) */
-
- if ((wEPVal & USB_EP_CTR_TX) != 0U)
- {
- ep = &hpcd->IN_ep[EPindex];
-
- /* clear int flag */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
-
- /* IN double Buffering*/
- if (ep->doublebuffer == 0U)
- {
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- }
- }
- else
- {
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
- {
- /*read from endpoint BUF0Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
- }
- /*multi-packet on the NON control IN endpoint*/
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff+=ep->xfer_count;
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
- {
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
- }
- }
- }
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/**
- * @brief This function handles PCD interrupt request.
- * @param hpcd PCD handle
- * @retval HAL status
- */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
- {
- /* servicing of the endpoint correct transfer interrupt */
- /* clear of the CTR flag into the sub */
- PCD_EP_ISR_Handler(hpcd);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
- HAL_PCD_ResetCallback(hpcd);
- HAL_PCD_SetAddress(hpcd, 0U);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
- }
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
- {
- hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
- hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
-
- HAL_PCD_ResumeCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
- {
- /* Force low-power mode in the macrocell */
- hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
-
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
- hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
- {
- HAL_PCD_SuspendCallback(hpcd);
- }
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
- HAL_PCD_SOFCallback(hpcd);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
- {
- /* clear ESOF flag in ISTR */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
- }
-}
-
-/**
- * @brief Data out stage callbacks
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Data IN stage callbacks
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataInStageCallback could be implemented in the user file
- */
-}
-/**
- * @brief Setup stage callback
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Start Of Frame callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SOFCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Reset callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResetCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Suspend event callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SuspendCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Resume event callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResumeCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO OUT callbacks
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO IN callbacks
- * @param hpcd PCD handle
- * @param epnum endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Connection event callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ConnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disconnection event callbacks
- * @param hpcd PCD handle
- * @retval None
- */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Connect the USB device
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
-
- /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
- HAL_PCDEx_SetConnectionState(hpcd, 1U);
-
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Disconnect the USB device
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
-
- /* Disable DP Pull-Down bit*/
- HAL_PCDEx_SetConnectionState(hpcd, 0U);
-
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Set the USB Device address
- * @param hpcd PCD handle
- * @param address new device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
- __HAL_LOCK(hpcd);
-
- if(address == 0U)
- {
- /* set device address and enable function */
- hpcd->Instance->DADDR = USB_DADDR_EF;
- }
- else /* USB Address will be applied later */
- {
- hpcd->USB_Address = address;
- }
-
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-/**
- * @brief Open and configure an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param ep_mps endpoint max packet size
- * @param ep_type endpoint type
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
- HAL_StatusTypeDef ret = HAL_OK;
- PCD_EPTypeDef *ep;
-
- if ((ep_addr & 0x80U) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
- }
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
-
- __HAL_LOCK(hpcd);
-
- /* initialize Endpoint */
- switch (ep->type)
- {
- case PCD_EP_TYPE_CTRL:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
- break;
- case PCD_EP_TYPE_BULK:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
- break;
- case PCD_EP_TYPE_INTR:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
- break;
- case PCD_EP_TYPE_ISOC:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
- break;
- default:
- break;
- }
-
- PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
-
- if (ep->doublebuffer == 0U)
- {
- if (ep->is_in)
- {
- /*Set the endpoint Transmit buffer address */
- PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- /* Configure NAK status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
- }
- else
- {
- /*Set the endpoint Receive buffer address */
- PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
- /*Set the endpoint Receive buffer counter*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- /* Configure VALID status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- }
- }
- /*Double Buffer*/
- else
- {
- /*Set the endpoint as double buffered*/
- PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
- /*Set buffer address for double buffered mode*/
- PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
-
- if (ep->is_in==0U)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(hpcd->Instance, ep->num);
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_RX_DTOG(hpcd->Instance, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
-
- __HAL_UNLOCK(hpcd);
- return ret;
-}
-
-
-/**
- * @brief Deactivate an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep;
-
- if ((ep_addr & 0x80U) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
- }
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
-
- __HAL_LOCK(hpcd);
-
- if (ep->doublebuffer == 0U)
- {
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
- /*Double Buffer*/
- else
- {
- if (ep->is_in==0U)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(hpcd->Instance, ep->num);
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_RX_DTOG(hpcd->Instance, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
-
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param pBuf pointer to the reception buffer
- * @param len amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-
- PCD_EPTypeDef *ep;
-
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0U;
- ep->is_in = 0U;
- ep->num = ep_addr & 0x7FU;
-
- /* Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0U;
- }
-
- /* configure and validate Rx endpoint */
- if (ep->doublebuffer == 0U)
- {
- /*Set RX buffer count*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
- }
- else
- {
- /*Set the Double buffer counter*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
- }
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
-
- return HAL_OK;
-}
-
-/**
- * @brief Get Received Data Size
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval Data Size
- */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
-}
-/**
- * @brief Send an amount of data
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param pBuf pointer to the transmission buffer
- * @param len amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
- PCD_EPTypeDef *ep;
- uint16_t pmabuffer = 0U;
-
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0U;
- ep->is_in = 1U;
- ep->num = ep_addr & 0x7FU;
-
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0U;
- }
-
- /* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
- PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
- }
- else
- {
- /*Write the data to the USB endpoint*/
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
- {
- pmabuffer = ep->pmaaddr1;
- }
- else
- {
- pmabuffer = ep->pmaaddr0;
- }
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
- }
-
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
-
- return HAL_OK;
-}
-
-/**
- * @brief Set a STALL condition over an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep;
-
- __HAL_LOCK(hpcd);
-
- if ((0x80U & ep_addr) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 1U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- if (ep->num == 0U)
- {
- /* This macro sets STALL status for RX & TX*/
- PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
- }
- else
- {
- if (ep->is_in)
- {
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
- }
- else
- {
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
- }
- }
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear a STALL condition over in an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep;
-
- if ((0x80U & ep_addr) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 0U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- __HAL_LOCK(hpcd);
-
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
- }
- else
- {
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- }
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Flush an endpoint
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- return HAL_OK;
-}
-
-/**
- * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- hpcd->Instance->CNTR |= USB_CNTR_RESUME;
- return HAL_OK;
-}
-
-/**
- * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param hpcd PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME);
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the PCD state
- * @param hpcd PCD handle
- * @retval HAL state
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
- return hpcd->State;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
deleted file mode 100644
index e2befbff40d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pcd_ex.c
- * @author MCD Application Team
- * @brief Extended PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Configuration of the PMA for EP
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCDEx PCDEx
- * @brief PCD Extended HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief PCDEx control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Update PMA configuration
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure PMA for EP
- * @param hpcd PCD handle
- * @param ep_addr endpoint address
- * @param ep_kind endpoint Kind
- * @arg USB_SNG_BUF: Single Buffer used
- * @arg USB_DBL_BUF: Double Buffer used
- * @param pmaadress EP address in The PMA: In case of single buffer endpoint
- * this parameter is 16-bit value providing the address
- * in PMA allocated to endpoint.
- * In case of double buffer endpoint this parameter
- * is a 32-bit value providing the endpoint buffer 0 address
- * in the LSB part of 32-bit value and endpoint buffer 1 address
- * in the MSB part of 32-bit value.
- * @retval : status
- */
-
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
-
-{
- PCD_EPTypeDef *ep;
-
- /* initialize ep structure*/
- if ((0x80U & ep_addr) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- /* Here we check if the endpoint is single or double Buffer*/
- if (ep_kind == PCD_SNG_BUF)
- {
- /*Single Buffer*/
- ep->doublebuffer = 0U;
- /*Configure the PMA*/
- ep->pmaadress = (uint16_t)pmaadress;
- }
- else /*USB_DBL_BUF*/
- {
- /*Double Buffer Endpoint*/
- ep->doublebuffer = 1;
- /*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0xFFFFU;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
- }
-
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup PCDEx_Private_Functions PCD Extended Private Functions
- * @{
- */
-#if defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || \
- defined(STM32F373xC) || defined(STM32F378xx) || \
- defined(STM32F302xC)
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx: USB peripheral instance register address.
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
-
- uint32_t i, temp1, temp2;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
-
- for (i = n; i != 0; i--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
- *pdwVal++ = temp2;
- pdwVal++;
- pbUsrBuf++;
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx: USB peripheral instance register address.
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (uint32_t)wNBytes >> 1U;
- uint32_t i;
- uint16_t *pdwVal;
- uint32_t temp;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
-
- for (i = n; i != 0U; i--)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- *pbUsrBuf++ = ((temp >> 8) & 0xFF);
- pdwVal++;
- }
-
- if (wNBytes % 2)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- }
-}
-#endif /* STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302x8)
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx: USB peripheral instance register address.
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
- uint32_t i;
- uint16_t temp1, temp2;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
- for (i = n; i != 0U; i--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
- *pdwVal++ = temp2;
- pbUsrBuf++;
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx: USB peripheral instance register address.
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (uint32_t)wNBytes >> 1U;
- uint32_t i;
- uint16_t *pdwVal;
- uint32_t temp;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
-
- for (i = n; i != 0U; i--)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- *pbUsrBuf++ = ((temp >> 8) & 0xFF);
- }
-
- if (wNBytes % 2)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- }
-}
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || */
- /* STM32F302x8 */
-
-/**
- * @}
- */
-
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-
-/** @addtogroup PCDEx_Exported_Functions_Group2 Extended Initialization and de-initialization functions
- * @{
- */
-/**
- * @brief Software Device Connection
- * @param hpcd PCD handle
- * @param state Device state
- * @retval None
- */
- __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(state);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCDEx_SetConnectionState could be implenetd in the user file
- */
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
deleted file mode 100644
index 55c49a71d68..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pwr.c
- * @author MCD Application Team
- * @brief PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() macro.
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @retval None
- */
-void HAL_PWR_DeInit(void)
-{
- __HAL_RCC_PWR_FORCE_RESET();
- __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
- * @brief Enables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 32 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Disables access to the backup domain (RTC registers, RTC
- * backup data registers and backup SRAM).
- * @note If the HSE divided by 32 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- *** WakeUp pin configuration ***
- ================================
- [..]
- (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
- forced in input pull down configuration and is active on rising edges.
- (+) There are up to three WakeUp pins:
- (++)WakeUp Pin 1 on PA.00.
- (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
- (++)WakeUp Pin 3 on PE.06.
-
- *** Main and Backup Regulators configuration ***
- ================================================
- [..]
- (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
- the backup SRAM is powered from VDD which replaces the VBAT power supply to
- save battery life.
-
- (+) The backup SRAM is not mass erased by a tamper event. It is read
- protected to prevent confidential data, such as cryptographic private
- key, from being accessed. The backup SRAM can be erased only through
- the Flash interface when a protection level change from level 1 to
- level 0 is requested.
- -@- Refer to the description of Read protection (RDP) in the Flash
- programming manual.
-
- Refer to the datasheets for more details.
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The devices feature 3 low-power modes:
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator
- in low power mode
- (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
- functions with
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..]
- In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
- and the HSE RC oscillators are disabled. Internal SRAM and register contents
- are preserved.
- The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
-
- (+) Entry:
- The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
- function with:
- (++) Main regulator ON or
- (++) Low Power regulator ON.
- (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
- (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
- (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
- when programmed in wakeup mode (the peripheral must be
- programmed in wakeup mode and the corresponding interrupt vector
- must be enabled in the NVIC).
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
- The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
- the HSE oscillator are also switched off. SRAM and register contents are lost
- except for the RTC registers, RTC backup registers, backup SRAM and Standby
- circuitry.
- The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
- The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
- Wakeup event, a tamper event, a time-stamp event, or a comparator event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to configure the RTC to detect the tamper or time stamp event using the
- HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
-
- (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
- configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
-
- (+) Comparator auto-wakeup (AWU) from the Stop mode
-
- (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
- (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
- to be sensitive to to the selected edges (falling, rising or falling
- and rising) (Interrupt or Event modes) using the EXTI_Init() function.
- (+++) Configure the comparator to generate the event.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
- * This parameter can be value of :
- * @ref PWR_WakeUp_Pins
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Enable the EWUPx pin */
- SET_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
- * @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
- * This parameter can be values of :
- * @ref PWR_WakeUp_Pins
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Disable the EWUPx pin */
- CLEAR_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
- * @brief Enters Sleep mode.
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param Regulator Specifies the regulator state in SLEEP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
- * @note This parameter has no effect in F3 family and is just maintained to
- * offer full portability of other STM32 families softwares.
- * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
- * When WFI entry is used, tick interrupt have to be disabled if not desired as
- * the interrupt wake up source.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-}
-
-/**
- * @brief Enters STOP mode.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param Regulator Specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
- * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
- * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
-
- /* Clear PDDS and LPDS bits */
- tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
-
- /* Set LPDS bit according to Regulator value */
- tmpreg |= Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available),
- * - RTC alternate function pins if configured for tamper, time-stamp, RTC
- * Alarm out, or RTC clock calibration out,
- * - WKUP pins if enabled.
- * @retval None
- */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * Setting this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
- * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-
-/**
- * @brief Enables CORTEX M4 SEVONPEND bit.
- * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void)
-{
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
- * @brief Disables CORTEX M4 SEVONPEND bit.
- * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void)
-{
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
deleted file mode 100644
index ef5db43a4d1..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_pwr_ex.c
- * @author MCD Application Team
- * @brief Extended PWR HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Extended Initialization and de-initialization functions
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWREx PWREx
- * @brief PWREx HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
- * @{
- */
-#define PVD_MODE_IT (0x00010000U)
-#define PVD_MODE_EVT (0x00020000U)
-#define PVD_RISING_EDGE (0x00000001U)
-#define PVD_FALLING_EDGE (0x00000002U)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
- * @{
- */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
-
- ===============================================================================
- ##### Peripheral Extended control functions #####
- ===============================================================================
- *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
- (+) The PVD is stopped in Standby mode.
- -@- PVD is not available on STM32F3x8 Product Line
-
-
- *** Voltage regulator ***
- =========================
- [..]
- (+) The voltage regulator is always enabled after Reset. It works in three different
- modes.
- In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
- and digital peripherals).
- In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
- contents of registers and SRAM.
- In Stop mode, the regulator is powered off. The contents of the registers and SRAM
- are lost except for the Standby circuitry and the Backup Domain.
- Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
- microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.
-
-
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
- (+) The PVD is stopped in Standby mode.
-
-
- *** SDADC power configuration ***
- ================================
- [..]
- (+) On STM32F373xC/STM32F378xx devices, there are up to
- 3 SDADC instances that can be enabled/disabled.
-
-@endverbatim
- * @{
- */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || \
- defined(STM32F302xC) || defined(STM32F303xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || \
- defined(STM32F301x8) || defined(STM32F302x8) || \
- defined(STM32F373xC)
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
- * information for the PVD.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS[7:5] bits according to PVDLevel value */
- MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-}
-
-/**
- * @brief Enables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Disables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief This function handles the PWR PVD interrupt request.
- * @note This API should be called under the PVD_IRQHandler().
- * @retval None
- */
-void HAL_PWR_PVD_IRQHandler(void)
-{
- /* Check PWR exti flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PWR Exti pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
-}
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_PVDCallback could be implemented in the user file
- */
-}
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F303x8 || STM32F334x8 || */
- /* STM32F301x8 || STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
-/**
- * @brief Enables the SDADC peripheral functionaliy
- * @param Analogx specifies the SDADC peripheral instance.
- * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
- * @retval None
- */
-void HAL_PWREx_EnableSDADC(uint32_t Analogx)
-{
- /* Check the parameters */
- assert_param(IS_PWR_SDADC_ANALOG(Analogx));
-
- /* Enable PWR clock interface for SDADC use */
- __HAL_RCC_PWR_CLK_ENABLE();
-
- PWR->CR |= Analogx;
-}
-
-/**
- * @brief Disables the SDADC peripheral functionaliy
- * @param Analogx specifies the SDADC peripheral instance.
- * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
- * @retval None
- */
-void HAL_PWREx_DisableSDADC(uint32_t Analogx)
-{
- /* Check the parameters */
- assert_param(IS_PWR_SDADC_ANALOG(Analogx));
-
- PWR->CR &= ~Analogx;
-}
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
deleted file mode 100644
index dcfb2d1a003..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
+++ /dev/null
@@ -1,1171 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rcc.c
- * @author MCD Application Team
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
- and all peripherals are off except internal SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
- all peripherals mapped on these buses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..] Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB buses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals whose clocks are not
- derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
-
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-/* Bits position in in the CFGR register */
-#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
-#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
-#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-
-#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
- * @{
- */
-const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
- 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
-const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
- 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
- and APB2).
-
- [..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
- The HSI clock can be used also to clock the USART and I2C peripherals.
-
- (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 72 MHz)
- (++) The second output is used to generate the clock for the USB FS (48 MHz)
- (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
- (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
-
- (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clocks automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
- (Non-Maskable Interrupt) exception vector.
-
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
- clock (divided by 2) output on pin (such as PA8 pin).
-
- [..] System, AHB and APB buses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these buses. You can use
- "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
- (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (++) The FLASH program/erase clock which is always HSI 8MHz clock.
- (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
- (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
- (++) The I2C clock which can be derived as well from HSI 8MHz clock.
- (++) The ADC clock which is derived from PLL output.
- (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
- (HSE divided by a programmable prescaler). The System clock (SYSCLK)
- frequency must be higher or equal to the RTC clock frequency.
- (++) IWDG clock which is always the LSI clock.
-
- (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
-
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
- @endverbatim
- * @{
- */
-
-/*
- Additional consideration on the SYSCLK based on Latency settings:
- +-----------------------------------------------+
- | Latency | SYSCLK clock frequency (MHz) |
- |---------------|-------------------------------|
- |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- |---------------|-------------------------------|
- |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- |---------------|-------------------------------|
- |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- +-----------------------------------------------+
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE and PLL OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS and MCO1 OFF
- * - All interrupts disabled
- * @note This function does not modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
- */
-void HAL_RCC_DeInit(void)
-{
- /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
- SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
-
- /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
- CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
-
- /* Reset HSEON, CSSON, PLLON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Reset CFGR2 register */
- CLEAR_REG(RCC->CFGR2);
-
- /* Reset CFGR3 register */
- CLEAR_REG(RCC->CFGR3);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
-}
-
-/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
- /* Configure the HSE predivision factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Require to disable power clock if necessary */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- /* Configure the main PLL clock source, predivider and multiplication factor. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PREDIV,
- RCC_OscInitStruct->PLL.PLLMUL);
-#else
- /* Configure the main PLL clock source and multiplication factor. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLMUL);
-#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
- *
- * @note The HSI is used (enabled by hardware) as system clock source after
- * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after start-up delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) of the device. */
-
- /* Increasing the number of wait states because of higher CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
- @verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
-
- @endverbatim
- * @{
- */
-
-#if defined(RCC_CFGR_MCOPRE)
-/**
- * @brief Selects the clock source to output on MCO pin.
- * @note MCO pin should be configured in alternate function mode.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
- * @param RCC_MCODiv specifies the MCO DIV.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
- * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
- * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
- * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
- * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
- * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
- * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
- * @retval None
- */
-#else
-/**
- * @brief Selects the clock source to output on MCO pin.
- * @note MCO pin should be configured in alternate function mode.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
- * @param RCC_MCODiv specifies the MCO DIV.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @retval None
- */
-#endif
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
- GPIO_InitTypeDef gpio;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* Configure the MCO1 pin in alternate function mode */
- gpio.Mode = GPIO_MODE_AF_PP;
- gpio.Speed = GPIO_SPEED_FREQ_HIGH;
- gpio.Pull = GPIO_NOPULL;
- gpio.Pin = MCO1_PIN;
- gpio.Alternate = GPIO_AF0_MCO;
-
- /* MCO1 Clock Enable */
- MCO1_CLK_ENABLE();
-
- HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-
- /* Configure the MCO clock source */
- __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
-}
-
-/**
- * @brief Enables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the Clock Security System.
- * @retval None
- */
-void HAL_RCC_DisableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Returns the SYSCLK frequency
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**)
- * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
- * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
- uint32_t sysclockfreq = 0U;
-
- tmpreg = RCC->CFGR;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (tmpreg & RCC_CFGR_SWS)
- {
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
- {
- sysclockfreq = HSE_VALUE;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
- {
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
- if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE / prediv) * pllmul;
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (HSI_VALUE >> 1U) * pllmul;
- }
-#else
- if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE / prediv) * pllmul;
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
- pllclk = (HSI_VALUE / prediv) * pllmul;
- }
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
- sysclockfreq = pllclk;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- default: /* HSI used as system clock */
- {
- sysclockfreq = HSI_VALUE;
- break;
- }
- }
- return sysclockfreq;
-}
-
-/**
- * @brief Returns the HCLK frequency
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated within this function
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- return SystemCoreClock;
-}
-
-/**
- * @brief Returns the PCLK1 frequency
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
-}
-
-/**
- * @brief Returns the PCLK2 frequency
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
-}
-
-/**
- * @brief Configures the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
-
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-
- /* Get the HSE configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
- RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
-#endif
-
- /* Get the HSI configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-
- /* Get the LSE configuration -----------------------------------------------*/
- if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
-
- /* Get the PLL configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
-#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
- * contains the current clock configuration.
- * @param pFLatency Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
- assert_param(pFLatency != NULL);
-
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-}
-
-/**
- * @brief This function handles the RCC CSS interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void)
-{
- /* Check RCC CSSF flag */
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))
- {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CSSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback
- * @retval none
- */
-__weak void HAL_RCC_CSSCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CSSCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
deleted file mode 100644
index 7ba8cff003d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,1596 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extension peripheral:
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC Extension HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
- || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
- || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
- || defined(RCC_CFGR3_HRTIM1SW)
-/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
- * @{
- */
-static uint32_t RCC_GetPLLCLKFreq(void);
-
-/**
- * @}
- */
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
- the backup registers) are set to their reset values.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the RCC extended peripherals clocks according to the specified
- * parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains the configuration information for the Extended Peripherals clocks
- * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
- * the backup registers) and RCC_BDCR register are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t tickstart = 0U;
- uint32_t temp_reg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*---------------------------- RTC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- {
- /* check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- FlagStatus pwrclkchanged = RESET;
-
- /* As soon as function is called to change RTC clock source, activation of the
- power domain is done. */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
- temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
- if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = temp_reg;
-
- /* Wait for LSERDY if LSE was enabled */
- if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-
- /* Require to disable power clock if necessary */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*------------------------------- USART1 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- }
-
-#if defined(RCC_CFGR3_USART2SW)
- /*----------------------------- USART2 Configuration --------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- }
-#endif /* RCC_CFGR3_USART2SW */
-
-#if defined(RCC_CFGR3_USART3SW)
- /*------------------------------ USART3 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- }
-#endif /* RCC_CFGR3_USART3SW */
-
- /*------------------------------ I2C1 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- }
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
- /*------------------------------ USB Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
-
- /* Configure the USB clock source */
- __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-
- /*------------------------------ I2C2 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- /*------------------------------ I2C3 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-
- /*------------------------------ UART4 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- }
-
- /*------------------------------ UART5 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
- /*------------------------------ I2S Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure the I2S clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- /*------------------------------ ADC1 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
-
- /* Configure the ADC1 clock source */
- __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
- }
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
- /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
-
- /* Configure the ADC12 clock source */
- __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-
- /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
-
- /* Configure the ADC34 clock source */
- __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
- }
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
- /*------------------------------ ADC1 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
-
- /* Configure the ADC1 clock source */
- __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
- }
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- /*------------------------------ TIM1 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
-
- /* Configure the TIM1 clock source */
- __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-
- /*------------------------------ TIM8 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
-
- /* Configure the TIM8 clock source */
- __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
- }
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- /*------------------------------ TIM15 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
-
- /* Configure the TIM15 clock source */
- __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
- }
-
- /*------------------------------ TIM16 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
-
- /* Configure the TIM16 clock source */
- __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
- }
-
- /*------------------------------ TIM17 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
-
- /* Configure the TIM17 clock source */
- __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
- }
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F334x8)
-
- /*------------------------------ HRTIM1 clock Configuration ----------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
-
- /* Configure the HRTIM1 clock source */
- __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
- }
-
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
- /*------------------------------ SDADC clock Configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
-
- /* Configure the SDADC clock prescaler */
- __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
- }
-
- /*------------------------------ CEC clock Configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- }
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
- /*------------------------------ TIM2 clock Configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
- }
-
- /*------------------------------ TIM3 clock Configuration -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
- }
-
- /*------------------------------ TIM15 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
- }
-
- /*------------------------------ TIM16 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
- }
-
- /*------------------------------ TIM17 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
- }
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)
- /*------------------------------ TIM20 clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
- }
-#endif /* STM32F303xE || STM32F398xx */
-
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * returns the configuration information for the Extended Peripherals clocks
- * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- /* Set all possible values for the extended clock type parameter------------*/
- /* Common part first */
-#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
-#else
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
-#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
-
- /* Get the RTC configuration --------------------------------------------*/
- PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
- /* Get the USART1 clock configuration --------------------------------------------*/
- PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
-#if defined(RCC_CFGR3_USART2SW)
- /* Get the USART2 clock configuration -----------------------------------------*/
- PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
-#endif /* RCC_CFGR3_USART2SW */
-#if defined(RCC_CFGR3_USART3SW)
- /* Get the USART3 clock configuration -----------------------------------------*/
- PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
-#endif /* RCC_CFGR3_USART3SW */
- /* Get the I2C1 clock configuration -----------------------------------------*/
- PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
-
-#if defined(STM32F302xE) || defined(STM32F303xE)\
- || defined(STM32F302xC) || defined(STM32F303xC)\
- || defined(STM32F302x8) \
- || defined(STM32F373xC)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
- /* Get the USB clock configuration -----------------------------------------*/
- PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || */
- /* STM32F302xC || STM32F303xC || */
- /* STM32F302x8 || */
- /* STM32F373xC */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
- /* Get the I2C2 clock configuration -----------------------------------------*/
- PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
- /* Get the I2C3 clock configuration -----------------------------------------*/
- PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
-
- PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
- /* Get the UART4 clock configuration -----------------------------------------*/
- PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
- /* Get the UART5 clock configuration -----------------------------------------*/
- PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
- /* Get the I2S clock configuration -----------------------------------------*/
- PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
- || defined(STM32F373xC) || defined(STM32F378xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
- /* Get the ADC1 clock configuration -----------------------------------------*/
- PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
- /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
- PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
- /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
- PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
- || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
- || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
- /* Get the TIM1 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx)\
- || defined(STM32F303xC) || defined(STM32F358xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
- /* Get the TIM8 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
-
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
- PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
- /* Get the TIM15 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
- /* Get the TIM16 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
- /* Get the TIM17 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F334x8)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
- /* Get the HRTIM1 clock configuration -----------------------------------------*/
- PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
-
-#endif /* STM32F334x8 */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
- /* Get the SDADC clock configuration -----------------------------------------*/
- PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
- /* Get the CEC clock configuration -----------------------------------------*/
- PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
-
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
- /* Get the TIM2 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
- /* Get the TIM3 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
- /* Get the TIM15 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
- /* Get the TIM16 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
-
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
- /* Get the TIM17 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
-
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#if defined (STM32F303xE) || defined(STM32F398xx)
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
- /* Get the TIM20 clock configuration -----------------------------------------*/
- PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
-#endif /* STM32F303xE || STM32F398xx */
-}
-
-/**
- * @brief Returns the peripheral clock frequency
- * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
- * @param PeriphClk Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
- @if STM32F301x8
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- @endif
- @if STM32F302x8
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- @endif
- @if STM32F302xC
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- @endif
- @if STM32F302xE
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
- @endif
- @if STM32F303x8
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- @endif
- @if STM32F303xC
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
- @endif
- @if STM32F303xE
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
- @endif
- @if STM32F318xx
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- @endif
- @if STM32F328xx
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- @endif
- @if STM32F334x8
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
- @endif
- @if STM32F358xx
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
- @endif
- @if STM32F373xC
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
- * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
- @endif
- @if STM32F378xx
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
- * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
- @endif
- @if STM32F398xx
- * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
- * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
- * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
- @endif
- * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
- /* frequency == 0 : means that no available frequency for the peripheral */
- uint32_t frequency = 0U;
-
- uint32_t srcclk = 0U;
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
- uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-#if defined(RCC_CFGR_SDPRE)
- uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
-#endif /* RCC_CFGR_SDPRE */
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
- switch (PeriphClk)
- {
- case RCC_PERIPHCLK_RTC:
- {
- /* Get the current RTC source */
- srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
- /* Check if LSE is ready and if RTC clock selection is LSE */
- if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- /* Check if LSI is ready and if RTC clock selection is LSI */
- else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
- {
- frequency = LSI_VALUE;
- }
- /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
- else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
- {
- frequency = HSE_VALUE / 32U;
- }
- break;
- }
- case RCC_PERIPHCLK_USART1:
- {
- /* Get the current USART1 source */
- srcclk = __HAL_RCC_GET_USART1_SOURCE();
-
- /* Check if USART1 clock selection is PCLK1 */
-#if defined(RCC_USART1CLKSOURCE_PCLK2)
- if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
- {
- frequency = HAL_RCC_GetPCLK2Freq();
- }
-#else
- if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
-#endif /* RCC_USART1CLKSOURCE_PCLK2 */
- /* Check if HSI is ready and if USART1 clock selection is HSI */
- else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if USART1 clock selection is SYSCLK */
- else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Check if LSE is ready and if USART1 clock selection is LSE */
- else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#if defined(RCC_CFGR3_USART2SW)
- case RCC_PERIPHCLK_USART2:
- {
- /* Get the current USART2 source */
- srcclk = __HAL_RCC_GET_USART2_SOURCE();
-
- /* Check if USART2 clock selection is PCLK1 */
- if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- /* Check if HSI is ready and if USART2 clock selection is HSI */
- else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if USART2 clock selection is SYSCLK */
- else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Check if LSE is ready and if USART2 clock selection is LSE */
- else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#endif /* RCC_CFGR3_USART2SW */
-#if defined(RCC_CFGR3_USART3SW)
- case RCC_PERIPHCLK_USART3:
- {
- /* Get the current USART3 source */
- srcclk = __HAL_RCC_GET_USART3_SOURCE();
-
- /* Check if USART3 clock selection is PCLK1 */
- if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- /* Check if HSI is ready and if USART3 clock selection is HSI */
- else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if USART3 clock selection is SYSCLK */
- else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Check if LSE is ready and if USART3 clock selection is LSE */
- else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#endif /* RCC_CFGR3_USART3SW */
-#if defined(RCC_CFGR3_UART4SW)
- case RCC_PERIPHCLK_UART4:
- {
- /* Get the current UART4 source */
- srcclk = __HAL_RCC_GET_UART4_SOURCE();
-
- /* Check if UART4 clock selection is PCLK1 */
- if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- /* Check if HSI is ready and if UART4 clock selection is HSI */
- else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if UART4 clock selection is SYSCLK */
- else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Check if LSE is ready and if UART4 clock selection is LSE */
- else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#endif /* RCC_CFGR3_UART4SW */
-#if defined(RCC_CFGR3_UART5SW)
- case RCC_PERIPHCLK_UART5:
- {
- /* Get the current UART5 source */
- srcclk = __HAL_RCC_GET_UART5_SOURCE();
-
- /* Check if UART5 clock selection is PCLK1 */
- if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
- {
- frequency = HAL_RCC_GetPCLK1Freq();
- }
- /* Check if HSI is ready and if UART5 clock selection is HSI */
- else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if UART5 clock selection is SYSCLK */
- else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- /* Check if LSE is ready and if UART5 clock selection is LSE */
- else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#endif /* RCC_CFGR3_UART5SW */
- case RCC_PERIPHCLK_I2C1:
- {
- /* Get the current I2C1 source */
- srcclk = __HAL_RCC_GET_I2C1_SOURCE();
-
- /* Check if HSI is ready and if I2C1 clock selection is HSI */
- if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if I2C1 clock selection is SYSCLK */
- else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- break;
- }
-#if defined(RCC_CFGR3_I2C2SW)
- case RCC_PERIPHCLK_I2C2:
- {
- /* Get the current I2C2 source */
- srcclk = __HAL_RCC_GET_I2C2_SOURCE();
-
- /* Check if HSI is ready and if I2C2 clock selection is HSI */
- if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if I2C2 clock selection is SYSCLK */
- else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- break;
- }
-#endif /* RCC_CFGR3_I2C2SW */
-#if defined(RCC_CFGR3_I2C3SW)
- case RCC_PERIPHCLK_I2C3:
- {
- /* Get the current I2C3 source */
- srcclk = __HAL_RCC_GET_I2C3_SOURCE();
-
- /* Check if HSI is ready and if I2C3 clock selection is HSI */
- if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if I2C3 clock selection is SYSCLK */
- else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- break;
- }
-#endif /* RCC_CFGR3_I2C3SW */
-#if defined(RCC_CFGR_I2SSRC)
- case RCC_PERIPHCLK_I2S:
- {
- /* Get the current I2S source */
- srcclk = __HAL_RCC_GET_I2S_SOURCE();
-
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
- if (srcclk == RCC_I2SCLKSOURCE_EXT)
- {
- /* External clock used. Frequency cannot be returned.*/
- frequency = 0xDEADDEADU;
- }
- /* Check if I2S clock selection is SYSCLK */
- else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
- {
- frequency = HAL_RCC_GetSysClockFreq();
- }
- break;
- }
-#endif /* RCC_CFGR_I2SSRC */
-#if defined(RCC_CFGR_USBPRE)
- case RCC_PERIPHCLK_USB:
- {
- /* Check if PLL is ready */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- /* Get the current USB source */
- srcclk = __HAL_RCC_GET_USB_SOURCE();
-
- /* Check if USB clock selection is not divided */
- if (srcclk == RCC_USBCLKSOURCE_PLL)
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if USB clock selection is divided by 1.5 */
- else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
- {
- frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
- }
- }
- break;
- }
-#endif /* RCC_CFGR_USBPRE */
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
- case RCC_PERIPHCLK_ADC1:
- {
- /* Get the current ADC1 source */
- srcclk = __HAL_RCC_GET_ADC1_SOURCE();
-#if defined(RCC_CFGR2_ADC1PRES)
- /* Check if ADC1 clock selection is AHB */
- if (srcclk == RCC_ADC1PLLCLK_OFF)
- {
- frequency = SystemCoreClock;
- }
- /* PLL clock has been selected */
- else
- {
- /* Check if PLL is ready */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
- }
- }
-#else /* RCC_CFGR_ADCPRE */
- /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
- frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
-#endif /* RCC_CFGR2_ADC1PRES */
- break;
- }
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
-#if defined(RCC_CFGR2_ADCPRE12)
- case RCC_PERIPHCLK_ADC12:
- {
- /* Get the current ADC12 source */
- srcclk = __HAL_RCC_GET_ADC12_SOURCE();
- /* Check if ADC12 clock selection is AHB */
- if (srcclk == RCC_ADC12PLLCLK_OFF)
- {
- frequency = SystemCoreClock;
- }
- /* PLL clock has been selected */
- else
- {
- /* Check if PLL is ready */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
- }
- }
- break;
- }
-#endif /* RCC_CFGR2_ADCPRE12 */
-#if defined(RCC_CFGR2_ADCPRE34)
- case RCC_PERIPHCLK_ADC34:
- {
- /* Get the current ADC34 source */
- srcclk = __HAL_RCC_GET_ADC34_SOURCE();
- /* Check if ADC34 clock selection is AHB */
- if (srcclk == RCC_ADC34PLLCLK_OFF)
- {
- frequency = SystemCoreClock;
- }
- /* PLL clock has been selected */
- else
- {
- /* Check if PLL is ready */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
- {
- /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
- }
- }
- break;
- }
-#endif /* RCC_CFGR2_ADCPRE34 */
-#if defined(RCC_CFGR3_TIM1SW)
- case RCC_PERIPHCLK_TIM1:
- {
- /* Get the current TIM1 source */
- srcclk = __HAL_RCC_GET_TIM1_SOURCE();
-
- /* Check if PLL is ready and if TIM1 clock selection is PLL */
- if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM1 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM1CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM1SW */
-#if defined(RCC_CFGR3_TIM2SW)
- case RCC_PERIPHCLK_TIM2:
- {
- /* Get the current TIM2 source */
- srcclk = __HAL_RCC_GET_TIM2_SOURCE();
-
- /* Check if PLL is ready and if TIM2 clock selection is PLL */
- if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM2 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM2CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM2SW */
-#if defined(RCC_CFGR3_TIM8SW)
- case RCC_PERIPHCLK_TIM8:
- {
- /* Get the current TIM8 source */
- srcclk = __HAL_RCC_GET_TIM8_SOURCE();
-
- /* Check if PLL is ready and if TIM8 clock selection is PLL */
- if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM8 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM8CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM8SW */
-#if defined(RCC_CFGR3_TIM15SW)
- case RCC_PERIPHCLK_TIM15:
- {
- /* Get the current TIM15 source */
- srcclk = __HAL_RCC_GET_TIM15_SOURCE();
-
- /* Check if PLL is ready and if TIM15 clock selection is PLL */
- if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM15 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM15CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM15SW */
-#if defined(RCC_CFGR3_TIM16SW)
- case RCC_PERIPHCLK_TIM16:
- {
- /* Get the current TIM16 source */
- srcclk = __HAL_RCC_GET_TIM16_SOURCE();
-
- /* Check if PLL is ready and if TIM16 clock selection is PLL */
- if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM16 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM16CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM16SW */
-#if defined(RCC_CFGR3_TIM17SW)
- case RCC_PERIPHCLK_TIM17:
- {
- /* Get the current TIM17 source */
- srcclk = __HAL_RCC_GET_TIM17_SOURCE();
-
- /* Check if PLL is ready and if TIM17 clock selection is PLL */
- if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM17 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM17CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM17SW */
-#if defined(RCC_CFGR3_TIM20SW)
- case RCC_PERIPHCLK_TIM20:
- {
- /* Get the current TIM20 source */
- srcclk = __HAL_RCC_GET_TIM20_SOURCE();
-
- /* Check if PLL is ready and if TIM20 clock selection is PLL */
- if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM20 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM20CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM20SW */
-#if defined(RCC_CFGR3_TIM34SW)
- case RCC_PERIPHCLK_TIM34:
- {
- /* Get the current TIM34 source */
- srcclk = __HAL_RCC_GET_TIM34_SOURCE();
-
- /* Check if PLL is ready and if TIM34 clock selection is PLL */
- if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if TIM34 clock selection is SYSCLK */
- else if (srcclk == RCC_TIM34CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_TIM34SW */
-#if defined(RCC_CFGR3_HRTIM1SW)
- case RCC_PERIPHCLK_HRTIM1:
- {
- /* Get the current HRTIM1 source */
- srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
-
- /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
- if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
- {
- frequency = RCC_GetPLLCLKFreq();
- }
- /* Check if HRTIM1 clock selection is SYSCLK */
- else if (srcclk == RCC_HRTIM1CLK_HCLK)
- {
- frequency = SystemCoreClock;
- }
- break;
- }
-#endif /* RCC_CFGR3_HRTIM1SW */
-#if defined(RCC_CFGR_SDPRE)
- case RCC_PERIPHCLK_SDADC:
- {
- /* Get the current SDADC source */
- srcclk = __HAL_RCC_GET_SDADC_SOURCE();
- /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
- frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
- break;
- }
-#endif /* RCC_CFGR_SDPRE */
-#if defined(RCC_CFGR3_CECSW)
- case RCC_PERIPHCLK_CEC:
- {
- /* Get the current CEC source */
- srcclk = __HAL_RCC_GET_CEC_SOURCE();
-
- /* Check if HSI is ready and if CEC clock selection is HSI */
- if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
- {
- frequency = HSI_VALUE;
- }
- /* Check if LSE is ready and if CEC clock selection is LSE */
- else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- break;
- }
-#endif /* RCC_CFGR3_CECSW */
- default:
- {
- break;
- }
- }
- return(frequency);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
- || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
- || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
- || defined(RCC_CFGR3_HRTIM1SW)
-
-/** @addtogroup RCCEx_Private_Functions
- * @{
- */
-static uint32_t RCC_GetPLLCLKFreq(void)
-{
- uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
-
- pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllmul = ( pllmul >> 18U) + 2U;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
- if (pllsource != RCC_PLLSOURCE_HSI)
- {
- prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE/prediv) * pllmul;
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
- pllclk = (HSI_VALUE >> 1U) * pllmul;
- }
-#else
- prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE/prediv) * pllmul;
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
- pllclk = (HSI_VALUE/prediv) * pllmul;
- }
-#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
-
- return pllclk;
-}
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
deleted file mode 100644
index ab9c5ac96a3..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
+++ /dev/null
@@ -1,1590 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rtc.c
- * @author MCD Application Team
- * @brief RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + RTC Tamper and TimeStamp Pins Selection
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### RTC Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_OUT pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_OUT pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
-
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() function.
- (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
- (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-
-
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above).
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
- HAL_RTC_SetAlarm_IT() function.
- (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
- HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
- function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
- mode using HAL_RTC_SetTamper_IT() function.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
- function.
-
-
- ##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @brief RTC HAL module driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup RTC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RTC_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to initialize and configure the
- RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
- RTC registers Write protection, enter and exit the RTC initialization mode,
- RTC registers synchronization check and reference clock detection enable.
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
- It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize power consumption.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To configure the RTC Calendar, user application should enter
- initialization mode. In this mode, the calendar counter is stopped
- and its value can be updated. When the initialization sequence is
- complete, the calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
- implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the RTC according to the specified parameters
- * in the RTC_InitTypeDef structure and initialize the associated handle.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
- /* Check the RTC peripheral state */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
- assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
- assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
- assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
- assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
- if(hrtc->State == HAL_RTC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hrtc->Lock = HAL_UNLOCKED;
-
- /* Initialize RTC MSP */
- HAL_RTC_MspInit(hrtc);
- }
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
- hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief DeInitialize the RTC peripheral.
- * @param hrtc RTC handle
- * @note This function doesn't reset the RTC Backup Data registers.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- hrtc->Instance->TR = 0x00000000U;
- hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
- /* Reset All CR bits except CR[2:0] */
- hrtc->Instance->CR &= RTC_CR_WUCKSEL;
-
- tickstart = HAL_GetTick();
-
- /* Wait till WUTWF flag is set and if Time out is reached exit */
- while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset all RTC CR register bits */
- hrtc->Instance->CR &= 0x00000000U;
- hrtc->Instance->WUTR = RTC_WUTR_WUT;
- hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
- hrtc->Instance->ALRMAR = 0x00000000U;
- hrtc->Instance->ALRMBR = 0x00000000U;
- hrtc->Instance->SHIFTR = 0x00000000U;
- hrtc->Instance->CALR = 0x00000000U;
- hrtc->Instance->ALRMASSR = 0x00000000U;
- hrtc->Instance->ALRMBSSR = 0x00000000U;
-
- /* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = 0x00000000U;
-
- /* Reset Tamper and alternate functions configuration register */
- hrtc->Instance->TAFCR = 0x00000000U;
-
- /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* De-Initialize RTC MSP */
- HAL_RTC_MspDeInit(hrtc);
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the RTC MSP.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the RTC MSP.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group2
- * @brief RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set RTC current time.
- * @param hrtc RTC handle
- * @param sTime Pointer to Time structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sTime->Hours));
- assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
- else
- {
- sTime->TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sTime->Hours));
- }
- assert_param(IS_RTC_MINUTES(sTime->Minutes));
- assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16U));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sTime->Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
- else
- {
- sTime->TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
- ((uint32_t)(sTime->Minutes) << 8U) | \
- ((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16U));
- }
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Clear the bits to be configured */
- hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Get RTC current time.
- * @param hrtc RTC handle
- * @param sTime Pointer to Time structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
- * value in second fraction ratio with time unit following generic formula:
- * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
- * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
- * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get subseconds structure field from the corresponding register*/
- sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
-
- /* Get SecondFraction structure field from the corresponding register field*/
- sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
- /* Get the TR register */
- tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
- sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the time structure parameters to Binary format */
- sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
- sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
- sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set RTC current date.
- * @param hrtc RTC handle
- * @param sDate Pointer to date structure
- * @param Format specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- uint32_t datetmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
- {
- sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
- }
-
- assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_YEAR(sDate->Year));
- assert_param(IS_RTC_MONTH(sDate->Month));
- assert_param(IS_RTC_DATE(sDate->Date));
-
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13U));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- datetmpreg = RTC_Bcd2ToByte(sDate->Month);
- assert_param(IS_RTC_MONTH(datetmpreg));
- datetmpreg = RTC_Bcd2ToByte(sDate->Date);
- assert_param(IS_RTC_DATE(datetmpreg));
-
- datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
- (((uint32_t)sDate->Month) << 8U) | \
- ((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13U));
- }
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Get RTC current date.
- * @param hrtc RTC handle
- * @param sDate Pointer to Date structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN : Binary data format
- * @arg RTC_FORMAT_BCD : BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- uint32_t datetmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get the DR register */
- datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
- sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the date structure parameters to Binary format */
- sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
- sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
- sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group3
- * @brief RTC Alarm functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
- * @{
- */
-/**
- * @brief Set the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
-
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
-
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
-
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if(sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified RTC Alarm with Interrupt.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the HAL_RTC_DeactivateAlarm()).
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if(sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* Clear flag alarm B */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
- }
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A : AlarmA
- * @arg RTC_ALARM_B : AlarmB
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- if(Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* AlarmB */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Date structure
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @arg RTC_ALARM_B: AlarmB
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(Alarm));
-
- if(Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- sAlarm->Alarm = RTC_ALARM_A;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
- }
- else
- {
- sAlarm->Alarm = RTC_ALARM_B;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- /* Fill the structure with the read parameters */
- sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
- sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
- sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
- sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
- sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
- sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
- if(Format == RTC_FORMAT_BIN)
- {
- sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
- sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
- sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Alarm interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
- /* Get the AlarmA interrupt source enable status */
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
- {
- /* Get the pending status of the AlarmA Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
- {
- /* AlarmA callback */
- HAL_RTC_AlarmAEventCallback(hrtc);
-
- /* Clear the AlarmA interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
- }
- }
-
- /* Get the AlarmB interrupt source enable status */
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
- {
- /* Get the pending status of the AlarmB Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
- {
- /* AlarmB callback */
- HAL_RTCEx_AlarmBEventCallback(hrtc);
-
- /* Clear the AlarmB interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
- }
- }
-
- /* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Alarm A callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_AlarmAEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle AlarmA Polling request.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Clear RSF flag */
- hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- tickstart = HAL_GetTick();
-
- /* Wait the registers to be synchronised */
- while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Get RTC state
-
-@endverbatim
- * @{
- */
-/**
- * @brief Return the RTC handle state.
- * @param hrtc RTC handle
- * @retval HAL state
- */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
- /* Return RTC handle state */
- return hrtc->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @@addtogroup RTC_Private_Functions RTC Private Functions
- * @{
- */
-
-/**
- * @brief Enter the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc RTC handle
- * @retval An ErrorStatus enumeration value:
- * - HAL_OK : RTC is in Init mode
- * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
- */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Check if the Initialization mode is set */
- if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
- tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Convert a 2 digit decimal to BCD format.
- * @param Value Byte to be converted
- * @retval Converted byte
- */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint32_t bcdhigh = 0U;
-
- while(Value >= 10U)
- {
- bcdhigh++;
- Value -= 10U;
- }
-
- return ((uint8_t)(bcdhigh << 4U) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value BCD value to be converted
- * @retval Converted word
- */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint32_t tmp = 0U;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
- return (tmp + (Value & (uint8_t)0x0FU));
-}
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
deleted file mode 100644
index 9d7277c5007..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1648 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_rtc_ex.c
- * @author MCD Application Team
- * @brief Extended RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extended peripheral:
- * + RTC Time Stamp functions
- * + RTC Tamper functions
- * + RTC Wake-up functions
- * + Extended Control functions
- * + Extended RTC features functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) Enable the RTC domain access.
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
- HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
- function.
- (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
- mode using HAL_RTCEx_SetTamper_IT() function.
- (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
- function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-
-
-/** @addtogroup RTCEx
- * @brief RTC Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup RTCEx_Exported_Functions
- * @{
- */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @brief RTC TimeStamp and Tamper functions
- *
-@verbatim
- ===============================================================================
- ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set TimeStamp.
- * @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc RTC handle
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- tmpreg|= TimeStampEdge;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set TimeStamp with Interrupt.
- * @param hrtc RTC handle
- * @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
- assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- tmpreg |= TimeStampEdge;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
- /* Enable IT timestamp */
- __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-
- /* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate TimeStamp.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tmpreg = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- hrtc->Instance->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC TimeStamp value.
- * @param hrtc RTC handle
- * @param sTimeStamp Pointer to Time structure
- * @param sTimeStampDate Pointer to Date structure
- * @param Format specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
- uint32_t tmptime = 0U, tmpdate = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
- sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
- sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
-
- /* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0U;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
-
- /* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
- /* Convert the TimeStamp structure parameters to Binary format */
- sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
- sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
- sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
- /* Convert the DateTimeStamp structure parameters to Binary format */
- sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
- sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
- sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
- }
-
- /* Clear the TIMESTAMP Flag */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Tamper
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc RTC handle
- * @param sTamper Pointer to Tamper Structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
- {
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
- }
-
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
- (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
-
- hrtc->Instance->TAFCR |= tmpreg;
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Tamper with interrupt.
- * @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc RTC handle
- * @param sTamper Pointer to RTC Tamper.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Configure the tamper trigger */
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
- {
- sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1U);
- }
-
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
- (uint32_t)RTC_TAFCR_TAMPPUDIS);
-
- hrtc->Instance->TAFCR |= tmpreg;
-
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-
- /* RTC Tamper Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate Tamper.
- * @param hrtc RTC handle
- * @param Tamper Selected tamper pin.
- * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
- * @note (*) RTC_TAMPER_3 not present on all the devices
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
- assert_param(IS_RTC_TAMPER(Tamper));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the selected Tamper pin */
- hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle TimeStamp interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the TimeStamp interrupt source enable status */
- if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
- {
- /* Get the pending status of the TIMESTAMP Interrupt */
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
- {
- /* TIMESTAMP callback */
- HAL_RTCEx_TimeStampEventCallback(hrtc);
-
- /* Clear the TIMESTAMP interrupt pending bit */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
- }
- }
-
- /* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
- {
- /* Get the pending status of the Tamper1 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
- {
- /* Tamper1 callback */
- HAL_RTCEx_Tamper1EventCallback(hrtc);
-
- /* Clear the Tamper1 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
- }
- }
-
- /* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
- {
- /* Get the pending status of the Tamper2 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
- {
- /* Tamper2 callback */
- HAL_RTCEx_Tamper2EventCallback(hrtc);
-
- /* Clear the Tamper2 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
- }
- }
-
-#if defined(RTC_TAMPER3_SUPPORT)
- /* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
- {
- /* Get the pending status of the Tamper3 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
- {
- /* Tamper3 callback */
- HAL_RTCEx_Tamper3EventCallback(hrtc);
-
- /* Clear the Tamper3 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
- }
- }
-#endif /* RTC_TAMPER3_SUPPORT */
-
- /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief TimeStamp callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tamper 1 callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tamper 2 callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
- */
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
- * @brief Tamper 3 callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
- */
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
- * @brief Handle TimeStamp polling request.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
- {
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
- {
- /* Clear the TIMESTAMP OverRun Flag */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
- /* Change TIMESTAMP state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Tamper 1 Polling.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Tamper 2 Polling.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
- * @brief Handle Tamper 3 Polling.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-/**
- * @}
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @brief RTC Wake-up functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Wake-up functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set wake up timer.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
- /* Enable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set wake up timer with interrupt.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Disable the Wake-Up timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* Clear flag Wake-Up */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
- /* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
- /* Enable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate wake up timer counter.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Disable the Wakeup Timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get wake up timer counter.
- * @param hrtc RTC handle
- * @retval Counter value
- */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
- /* Get the counter value */
- return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Handle Wake Up Timer interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the pending status of the WAKEUPTIMER Interrupt */
- if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
- {
- /* WAKEUPTIMER callback */
- HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
- }
-
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Wake Up Timer callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle Wake Up Timer Polling.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the WAKEUPTIMER Flag */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Write a data in a specified RTC Backup data register
- (+) Read a data in a specified RTC Backup data register
- (+) Set the Coarse calibration parameters.
- (+) Deactivate the Coarse calibration parameters
- (+) Set the Smooth calibration parameters.
- (+) Configure the Synchronization Shift Control Settings.
- (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enable the RTC reference clock detection.
- (+) Disable the RTC reference clock detection.
- (+) Enable the Bypass Shadow feature.
- (+) Disable the Bypass Shadow feature.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Write a data in a specified RTC Backup data register.
- * @param hrtc RTC handle
- * @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @param Data Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4U);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc RTC handle
- * @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval Read value
- */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4U);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @brief Set the Smooth calibration parameters.
- * @param hrtc RTC handle
- * @param SmoothCalibPeriod Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values :
- * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
- * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
- * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
- * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
- * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmoothCalibMinusPulsesValue mut be equal to 0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* check if a calibration is pending*/
- if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
- {
- tickstart = HAL_GetTick();
-
- /* check if a calibration is pending*/
- while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc RTC handle
- * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
- * This parameter can be one of the following values :
- * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
- * @arg RTC_SHIFTADD1S_RESET: No effect.
- * @param ShiftSubFS Select the number of Second Fractions to substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- tickstart = HAL_GetTick();
-
- /* Wait until the shift is completed*/
- while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the reference clock detection is disabled */
- if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
- /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- }
- else
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
- * @param CalibOutput Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
- * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Clear flags before config */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
- /* Configure the RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)CalibOutput;
-
- __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the RTC reference clock detection.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the RTC reference clock detection.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the Bypass Shadow feature.
- * @param hrtc RTC handle
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set the BYPSHAD bit */
- hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Bypass Shadow feature.
- * @param hrtc RTC handle
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Reset the BYPSHAD bit */
- hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ===============================================================================
- ##### Extended features functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) RTC Alram B callback
- (+) RTC Poll for Alarm B request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Alarm B callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief This function handles AlarmB Polling request.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm Flag */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
deleted file mode 100644
index 0df99f1a8b7..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
+++ /dev/null
@@ -1,2692 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_sdadc.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Sigma-Delta Analog to Digital Converter
- * (SDADC) peripherals:
- * + Initialization and Configuration
- * + Regular Channels Configuration
- * + Injected channels Configuration
- * + Power saving
- * + Regular/Injected Channels DMA Configuration
- * + Interrupts and flags management
- @verbatim
- ==============================================================================
- ##### SDADC specific features #####
- ==============================================================================
- [..]
- (#) 16-bit sigma delta architecture.
- (#) Self calibration.
- (#) Interrupt generation at the end of calibration, regular/injected conversion
- and in case of overrun events.
- (#) Single and continuous conversion modes.
- (#) External trigger option with configurable polarity for injected conversion.
- (#) Multi mode (synchronized another SDADC with SDADC1).
- (#) DMA request generation during regular or injected channel conversion.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- *** Initialization ***
- ======================
- [..]
- (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
- (++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
- (++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
- (++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
- (++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
- (++) If interrupt mode is used, enable and configure SDADC global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
- with SDADC handle using __HAL_LINKDMA.
- (#) Configure the SDADC low power mode, fast conversion mode, slow clock
- mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
- Note: Common reference voltage. is common to all SDADC instances.
- (#) Prepare channel configurations (input mode, common mode, gain and
- offset) using HAL_SDADC_PrepareChannelConfig and associate channel
- with one configuration using HAL_SDADC_AssociateChannelConfig.
-
- *** Calibration ***
- ============================================
- [..]
- (#) Start calibration using HAL_SDADC_StartCalibration or
- HAL_SDADC_CalibrationStart_IT.
- (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
- calibration.
- (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
- the end of calibration.
-
- *** Regular channel conversion ***
- ============================================
- [..]
- (#) Select trigger for regular conversion using
- HAL_SDADC_SelectRegularTrigger.
- (#) Select regular channel and enable/disable continuous mode using
- HAL_SDADC_ConfigChannel.
- (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
- or HAL_SDADC_Start_DMA.
- (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
- regular conversion.
- (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
- end of regular conversion.
- (#) Get value of regular conversion using HAL_SDADC_GetValue.
- (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
- HAL_SDADC_ConvCpltCallback will be called respectively at the half
- transfer and at the transfer complete.
- (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
- or HAL_SDADC_Stop_DMA.
-
- *** Injected channels conversion ***
- ============================================
- [..]
- (#) Enable/disable delay on injected conversion using
- HAL_SDADC_SelectInjectedDelay.
- (#) If external trigger is used for injected conversion, configure this
- trigger using HAL_SDADC_SelectInjectedExtTrigger.
- (#) Select trigger for injected conversion using
- HAL_SDADC_SelectInjectedTrigger.
- (#) Select injected channels and enable/disable continuous mode using
- HAL_SDADC_InjectedConfigChannel.
- (#) Start injected conversion using HAL_SDADC_InjectedStart,
- HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
- (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
- end of injected conversion.
- (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
- at the end of injected conversion.
- (#) Get value of injected conversion and corresponding channel using
- HAL_SDADC_InjectedGetValue.
- (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
- HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
- half transfer and at the transfer complete.
- (#) Stop injected conversion using HAL_SDADC_InjectedStop,
- HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
-
- *** Multi mode regular channels conversions ***
- ======================================================
- [..]
- (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
- HAL_SDADC_MultiModeConfigChannel.
- (#) Select software trigger for SDADC1 and synchronized trigger for
- SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
- (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
- HAL_SDADC_ConfigChannel.
- (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
- (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
- HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
- (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
- regular conversion for SDADC1.
- (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
- end of regular conversion for SDADC1.
- (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
- (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
- HAL_SDADC_ConvCpltCallback will be called respectively at the half
- transfer and at the transfer complete for SDADC1.
- (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
- or HAL_SDADC_MultiModeStop_DMA for SDADC1.
- (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
-
- *** Multi mode injected channels conversions ***
- ======================================================
- [..]
- (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
- HAL_SDADC_InjectedMultiModeConfigChannel.
- (#) Select software or external trigger for SDADC1 and synchronized
- trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
- (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
- HAL_SDADC_InjectedConfigChannel.
- (#) Start injected conversion for SDADC2 (or SDADC3) with
- HAL_SDADC_InjectedStart.
- (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
- HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
- (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
- the end of injected conversion for SDADC1.
- (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
- at the end of injected conversion for SDADC1.
- (#) Get value of injected conversions using
- HAL_SDADC_InjectedMultiModeGetValue.
- (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
- HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
- half transfer and at the transfer complete for SDADC1.
- (#) Stop injected conversion using HAL_SDADC_InjectedStop,
- HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
- for SDADC1.
- (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
- (or SDADC3).
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_SDADC_MODULE_ENABLED
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup SDADC SDADC
- * @brief SDADC HAL driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SDADC_Private_Define SDADC Private Define
- * @{
- */
-#define SDADC_TIMEOUT 200
-#define SDADC_CONFREG_OFFSET 0x00000020
-#define SDADC_JDATAR_CH_OFFSET 24
-#define SDADC_MSB_MASK 0xFFFF0000U
-#define SDADC_LSB_MASK 0x0000FFFFU
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SDADC_Private_Functions SDADC Private Functions
- * @{
- */
-
-static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
-static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
-static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels);
-static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
-static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
-static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
-static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
-static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
-static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
-static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SDADC_Exported_Functions SDADC Exported Functions
- * @{
- */
-
-/** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the SDADC.
- (+) De-initialize the SDADC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDADC according to the specified
- * parameters in the SDADC_InitTypeDef structure.
- * @note If multiple SDADC are used, please configure first SDADC1 to set
- * the common reference voltage.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
-{
- /* Check SDADC handle */
- if(hsdadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
- assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
- assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
- assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
-
- /* Initialize SDADC variables with default values */
- hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
- hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
- hsdadc->InjectedChannelsNbr = 1U;
- hsdadc->InjConvRemaining = 1U;
- hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
- hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
- hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
- hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
- hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
- hsdadc->ErrorCode = SDADC_ERROR_NONE;
-
- /* Call MSP init function */
- HAL_SDADC_MspInit(hsdadc);
-
- /* Set idle low power and slow clock modes */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
- hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
- hsdadc->Init.SlowClockMode);
-
- /* Set fast conversion mode */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
- hsdadc->Instance->CR2 |= hsdadc->Init.FastConversionMode;
-
- /* Set reference voltage common to all SDADC instances */
- /* Update this parameter only if needed to avoid unnecessary settling time */
- if((SDADC1->CR1 & SDADC_CR1_REFV) != hsdadc->Init.ReferenceVoltage)
- {
- /* Voltage reference bits are common to all SADC instances but are */
- /* present in SDADC1 register. */
- SDADC1->CR1 &= ~(SDADC_CR1_REFV);
- SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
-
- /* Wait at least 2ms before setting ADON */
- HAL_Delay(2U);
- }
-
- /* Enable SDADC */
- hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
-
- /* Wait end of stabilization */
- while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0U)
- {
- }
-
- /* Set SDADC to ready state */
- hsdadc->State = HAL_SDADC_STATE_READY;
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief De-initializes the SDADC.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
-{
- /* Check SDADC handle */
- if(hsdadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Disable the SDADC */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
-
- /* Reset all registers */
- hsdadc->Instance->CR1 = 0x00000000U;
- hsdadc->Instance->CR2 = 0x00000000U;
- hsdadc->Instance->JCHGR = 0x00000001U;
- hsdadc->Instance->CONF0R = 0x00000000U;
- hsdadc->Instance->CONF1R = 0x00000000U;
- hsdadc->Instance->CONF2R = 0x00000000U;
- hsdadc->Instance->CONFCHR1 = 0x00000000U;
- hsdadc->Instance->CONFCHR2 = 0x00000000U;
-
- /* Call MSP deinit function */
- HAL_SDADC_MspDeInit(hsdadc);
-
- /* Set SDADC in reset state */
- hsdadc->State = HAL_SDADC_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the SDADC MSP.
- * @param hsdadc SDADC handle
- * @retval None
- */
-__weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_MspInit could be implemented in the user file.
- */
-}
-
-/**
- * @brief De-initializes the SDADC MSP.
- * @param hsdadc SDADC handle
- * @retval None
- */
-__weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_MspDeInit could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
- * @brief Peripheral control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Program one of the three different configurations for channels.
- (+) Associate channel to one of configurations.
- (+) Select regular and injected channels.
- (+) Enable/disable continuous mode for regular and injected conversions.
- (+) Select regular and injected triggers.
- (+) Select and configure injected external trigger.
- (+) Enable/disable delay addition for injected conversions.
- (+) Configure multimode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows the user to set parameters for a configuration.
- * Parameters are input mode, common mode, gain and offset.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc SDADC handle.
- * @param ConfIndex Index of configuration to modify.
- * This parameter can be a value of @ref SDADC_ConfIndex.
- * @param ConfParamStruct Parameters to apply for this configuration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
- uint32_t ConfIndex,
- SDADC_ConfParamTypeDef* ConfParamStruct)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmp = 0U;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
- assert_param(ConfParamStruct != NULL);
- assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
- assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
- assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
- assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
-
- /* Check SDADC state is ready */
- if(hsdadc->State != HAL_SDADC_STATE_READY)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Program configuration register with parameters */
- tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
- SDADC_CONFREG_OFFSET + \
- (uint32_t)(ConfIndex << 2U));
- *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
- ConfParamStruct->Gain | \
- ConfParamStruct->CommonMode | \
- ConfParamStruct->Offset);
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows the user to associate a channel with one of the
- * available configurations.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc SDADC handle.
- * @param Channel Channel to associate with configuration.
- * This parameter can be a value of @ref SDADC_Channel_Selection.
- * @param ConfIndex Index of configuration to associate with channel.
- * This parameter can be a value of @ref SDADC_ConfIndex.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ConfIndex)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t channelnum = 0U;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
- assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
-
- /* Check SDADC state is ready */
- if(hsdadc->State != HAL_SDADC_STATE_READY)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Program channel configuration register according parameters */
- if(Channel != SDADC_CHANNEL_8)
- {
- /* Get channel number */
- channelnum = (uint32_t)(Channel>>16U);
-
- /* Set the channel configuration */
- hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2U));
- hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2U));
- }
- else
- {
- hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
- }
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select channel for regular conversion and
- * to enable/disable continuous mode for regular conversion.
- * @param hsdadc SDADC handle.
- * @param Channel Channel for regular conversion.
- * This parameter can be a value of @ref SDADC_Channel_Selection.
- * @param ContinuousMode Enable/disable continuous mode for regular conversion.
- * This parameter can be a value of @ref SDADC_ContinuousMode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ContinuousMode)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
- assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
- {
- /* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
- hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
- if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
- {
- hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
- }
- else
- {
- hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
- }
- /* Store continuous mode information */
- hsdadc->RegularContMode = ContinuousMode;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select channels for injected conversion and
- * to enable/disable continuous mode for injected conversion.
- * @param hsdadc SDADC handle.
- * @param Channel Channels for injected conversion.
- * This parameter can be a values combination of @ref SDADC_Channel_Selection.
- * @param ContinuousMode Enable/disable continuous mode for injected conversion.
- * This parameter can be a value of @ref SDADC_ContinuousMode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
- uint32_t Channel,
- uint32_t ContinuousMode)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
- assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
- {
- /* Set JCHG[8:0] bits in SDADC_JCHG */
- hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
- /* Set or clear JCONT bit in SDADC_CR2 */
- if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
- {
- hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
- }
- else
- {
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
- }
- /* Store continuous mode information */
- hsdadc->InjectedContMode = ContinuousMode;
- /* Store number of injected channels */
- hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select trigger for regular conversions.
- * @note This function should not be called if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param Trigger Trigger for regular conversions.
- * This parameter can be one of the following value :
- * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
- * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
-
- /* Check parameters compatibility */
- if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Store regular trigger information */
- hsdadc->RegularTrigger = Trigger;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select trigger for injected conversions.
- * @note This function should not be called if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param Trigger Trigger for injected conversions.
- * This parameter can be one of the following value :
- * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
- * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
- * @arg SDADC_EXTERNAL_TRIGGER : External trigger.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
-
- /* Check parameters compatibility */
- if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Store regular trigger information */
- hsdadc->InjectedTrigger = Trigger;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to select and configure injected external trigger.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc SDADC handle.
- * @param InjectedExtTrigger External trigger for injected conversions.
- * This parameter can be a value of @ref SDADC_InjectedExtTrigger.
- * @param ExtTriggerEdge Edge of external injected trigger.
- * This parameter can be a value of @ref SDADC_ExtTriggerEdge.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
- uint32_t InjectedExtTrigger,
- uint32_t ExtTriggerEdge)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
- assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
-
- /* Check SDADC state */
- if(hsdadc->State == HAL_SDADC_STATE_READY)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
- hsdadc->Instance->CR2 |= InjectedExtTrigger;
-
- /* Store external trigger edge information */
- hsdadc->ExtTriggerEdge = ExtTriggerEdge;
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to enable/disable delay addition for injected conversions.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc SDADC handle.
- * @param InjectedDelay Enable/disable delay for injected conversions.
- * This parameter can be a value of @ref SDADC_InjectedDelay.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
- uint32_t InjectedDelay)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
-
- /* Check SDADC state */
- if(hsdadc->State == HAL_SDADC_STATE_READY)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Set JDS bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
- hsdadc->Instance->CR2 |= InjectedDelay;
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to configure multimode for regular conversions.
- * @note This function should not be called if regular conversion is ongoing
- * and should be could only for SDADC1.
- * @param hsdadc SDADC handle.
- * @param MultimodeType Type of multimode for regular conversions.
- * This parameter can be a value of @ref SDADC_MultimodeType.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
- uint32_t MultimodeType)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Store regular trigger information */
- hsdadc->RegularMultimode = MultimodeType;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to configure multimode for injected conversions.
- * @note This function should not be called if injected conversion is ongoing
- * and should be could only for SDADC1.
- * @param hsdadc SDADC handle.
- * @param MultimodeType Type of multimode for injected conversions.
- * This parameter can be a value of @ref SDADC_MultimodeType.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
- uint32_t MultimodeType)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Store regular trigger information */
- hsdadc->InjectedMultimode = MultimodeType;
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
- * @brief IO operation Control functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start calibration.
- (+) Poll for the end of calibration.
- (+) Start calibration and enable interrupt.
- (+) Start conversion of regular/injected channel.
- (+) Poll for the end of regular/injected conversion.
- (+) Stop conversion of regular/injected channel.
- (+) Start conversion of regular/injected channel and enable interrupt.
- (+) Stop conversion of regular/injected channel and disable interrupt.
- (+) Start conversion of regular/injected channel and enable DMA transfer.
- (+) Stop conversion of regular/injected channel and disable DMA transfer.
- (+) Start multimode and enable DMA transfer for regular/injected conversion.
- (+) Stop multimode and disable DMA transfer for regular/injected conversion..
- (+) Get result of regular channel conversion.
- (+) Get result of injected channel conversion.
- (+) Get result of multimode conversion.
- (+) Handle SDADC interrupt request.
- (+) Callbacks for calibration and regular/injected conversions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to start calibration in polling mode.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing).
- * @param hsdadc SDADC handle.
- * @param CalibrationSequence Calibration sequence.
- * This parameter can be a value of @ref SDADC_CalibrationSequence.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
- uint32_t CalibrationSequence)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
-
- /* Check SDADC state */
- if(hsdadc->State == HAL_SDADC_STATE_READY)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
- hsdadc->Instance->CR2 |= CalibrationSequence;
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
-
- /* Set STARTCALIB in SDADC_CR2 */
- hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
-
- /* Set SDADC in calibration state */
- hsdadc->State = HAL_SDADC_STATE_CALIB;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the end of calibration.
- * @note This function should be called only if calibration is ongoing.
- * @param hsdadc SDADC handle.
- * @param Timeout Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if(hsdadc->State != HAL_SDADC_STATE_CALIB)
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait EOCALF bit in SDADC_ISR register */
- while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
- /* Set CLREOCALF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
-
- /* Set SDADC in ready state */
- hsdadc->State = HAL_SDADC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to start calibration in interrupt mode.
- * @note This function should be called only when SDADC instance is in idle state
- * (neither calibration nor regular or injected conversion ongoing).
- * @param hsdadc SDADC handle.
- * @param CalibrationSequence Calibration sequence.
- * This parameter can be a value of @ref SDADC_CalibrationSequence.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
- uint32_t CalibrationSequence)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
-
- /* Check SDADC state */
- if(hsdadc->State == HAL_SDADC_STATE_READY)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
- hsdadc->Instance->CR2 |= CalibrationSequence;
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
-
- /* Set EOCALIE bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_EOCALIE;
-
- /* Set STARTCALIB in SDADC_CR2 */
- hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
-
- /* Set SDADC in calibration state */
- hsdadc->State = HAL_SDADC_STATE_CALIB;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in polling mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Start regular conversion */
- status = SDADC_RegConvStart(hsdadc);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the end of regular conversion.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param Timeout Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_REG) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait REOCF bit in SDADC_ISR register */
- while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
- /* Check if overrun occurs */
- if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
- {
- /* Update error code and call error callback */
- hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
- HAL_SDADC_ErrorCallback(hsdadc);
-
- /* Set CLRROVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
- }
- /* Update SDADC state only if not continuous conversion and SW trigger */
- if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
- {
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
- }
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop regular conversion in polling mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_REG) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- status = SDADC_RegConvStop(hsdadc);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in interrupt mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
-
- /* Start regular conversion */
- status = SDADC_RegConvStart(hsdadc);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop regular conversion in interrupt mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_REG) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
-
- /* Stop regular conversion */
- status = SDADC_RegConvStop(hsdadc);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start regular conversion in DMA mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param pData The destination buffer address.
- * @param Length The length of data to be transferred from SDADC peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(pData != NULL);
- assert_param(Length != 0U);
-
- /* Check that DMA is not enabled for injected conversion */
- if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length != 1U))
- {
- status = HAL_ERROR;
- }
- else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Set callbacks on DMA handler */
- hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
- hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
- if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
- {
- hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
- }
-
- /* Set RDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start regular conversion */
- status = SDADC_RegConvStart(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop regular conversion in DMA mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_REG) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear RDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
-
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- status = SDADC_RegConvStop(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get regular conversion value.
- * @param hsdadc SDADC handle.
- * @retval Regular conversion value
- */
-uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
-{
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Return regular conversion value */
- return hsdadc->Instance->RDATAR;
-}
-
-/**
- * @brief This function allows to start injected conversion in polling mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Start injected conversion */
- status = SDADC_InjConvStart(hsdadc);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to poll for the end of injected conversion.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param Timeout Timeout value in milliseconds.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
- uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- return HAL_ERROR;
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait JEOCF bit in SDADC_ISR register */
- while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
- {
- /* Check the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Return timeout status */
- return HAL_TIMEOUT;
- }
- }
- }
- /* Check if overrun occurs */
- if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
- {
- /* Update error code and call error callback */
- hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
- HAL_SDADC_ErrorCallback(hsdadc);
-
- /* Set CLRJOVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
- }
- /* Update remaining injected conversions */
- hsdadc->InjConvRemaining--;
- if(hsdadc->InjConvRemaining == 0U)
- {
- /* end of injected sequence, reset the value */
- hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
- }
-
- /* Update SDADC state only if not continuous conversion, SW trigger */
- /* and end of injected sequence */
- if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
- {
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
- }
- /* Return function status */
- return HAL_OK;
- }
-}
-
-/**
- * @brief This function allows to stop injected conversion in polling mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Stop injected conversion */
- status = SDADC_InjConvStop(hsdadc);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start injected conversion in interrupt mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
-
- /* Start injected conversion */
- status = SDADC_InjConvStart(hsdadc);
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop injected conversion in interrupt mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
-
- /* Stop injected conversion */
- status = SDADC_InjConvStop(hsdadc);
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to start injected conversion in DMA mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param pData The destination buffer address.
- * @param Length The length of data to be transferred from SDADC peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(pData != NULL);
- assert_param(Length != 0U);
-
- /* Check that DMA is not enabled for regular conversion */
- if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length > hsdadc->InjectedChannelsNbr))
- {
- status = HAL_ERROR;
- }
- else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Set callbacks on DMA handler */
- hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
- hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
- if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
- {
- hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
- }
-
- /* Set JDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
-
- /* Start DMA in interrupt mode */
- if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start injected conversion */
- status = SDADC_InjConvStart(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop injected conversion in DMA mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check SDADC state */
- if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear JDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
-
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop injected conversion */
- status = SDADC_InjConvStop(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get injected conversion value.
- * @param hsdadc SDADC handle.
- * @param Channel Corresponding channel of injected conversion.
- * @retval Injected conversion value
- */
-uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
-{
- uint32_t value = 0U;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(Channel != NULL);
-
- /* Read SDADC_JDATAR register and extract channel and conversion value */
- value = hsdadc->Instance->JDATAR;
- *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
- value &= SDADC_JDATAR_JDATA;
-
- /* Return injected conversion value */
- return value;
-}
-
-/**
- * @brief This function allows to start multimode regular conversions in DMA mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param pData The destination buffer address.
- * @param Length The length of data to be transferred from SDADC peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
- uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(pData != NULL);
- assert_param(Length != 0U);
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is not enabled for injected conversion */
- else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length != 1U))
- {
- status = HAL_ERROR;
- }
- else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_INJ))
- {
- /* Set callbacks on DMA handler */
- hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
- hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
- if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
- {
- hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
- }
- /* Set RDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
-
- /* Start DMA in interrupt mode */
- if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
- {
- status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
- (uint32_t) pData, Length);
- }
- else
- {
- status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
- (uint32_t) pData, Length);
- }
- if(status != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start regular conversion */
- status = SDADC_RegConvStart(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop multimode regular conversions in DMA mode.
- * @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear RDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
-
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop regular conversion */
- status = SDADC_RegConvStop(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get multimode regular conversion value.
- * @param hsdadc SDADC handle.
- * @retval Multimode regular conversion value
- */
-uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
-{
- uint32_t value = 0U;
-
- /* Check parameters and check instance is SDADC1 */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(hsdadc->Instance == SDADC1);
-
- /* read multimode regular value */
- value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
- hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
-
- /* Return multimode regular conversions value */
- return value;
-}
-
-/**
- * @brief This function allows to start multimode injected conversions in DMA mode.
- * @note This function should be called only when SDADC instance is in idle state
- * or if regular conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @param pData The destination buffer address.
- * @param Length The length of data to be transferred from SDADC peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
- uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(pData != NULL);
- assert_param(Length != 0U);
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check that DMA is not enabled for regular conversion */
- else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
- {
- status = HAL_ERROR;
- }
- /* Check parameters compatibility */
- else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length > (hsdadc->InjectedChannelsNbr << 1U)))
- {
- status = HAL_ERROR;
- }
- else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
- (hsdadc->State == HAL_SDADC_STATE_REG))
- {
- /* Set callbacks on DMA handler */
- hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
- hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
- if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
- {
- hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
- }
- /* Set JDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
-
- /* Start DMA in interrupt mode */
- if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
- {
- status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
- (uint32_t) pData, Length);
- }
- else
- {
- status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
- (uint32_t) pData, Length);
- }
- if(status != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Start injected conversion */
- status = SDADC_InjConvStart(hsdadc);
- }
- }
- else
- {
- status = HAL_ERROR;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to stop multimode injected conversions in DMA mode.
- * @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc SDADC handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
- /* Check instance is SDADC1 */
- if(hsdadc->Instance != SDADC1)
- {
- status = HAL_ERROR;
- }
- /* Check SDADC state */
- else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
- (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
- {
- /* Return error status */
- status = HAL_ERROR;
- }
- else
- {
- /* Clear JDMAEN bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
-
- /* Stop current DMA transfer */
- if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_ERROR;
- }
- else
- {
- /* Stop injected conversion */
- status = SDADC_InjConvStop(hsdadc);
- }
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to get multimode injected conversion value.
- * @param hsdadc SDADC handle.
- * @retval Multimode injected conversion value
- */
-uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
-{
- uint32_t value = 0U;
-
- /* Check parameters and check instance is SDADC1 */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
- assert_param(hsdadc->Instance == SDADC1);
-
- /* read multimode injected value */
- value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
- hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
-
- /* Return multimode injected conversions value */
- return value;
-}
-
-/**
- * @brief This function handles the SDADC interrupts.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
-{
- /* Check if end of regular conversion */
- if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \
- ((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE))
- {
- /* Call regular conversion complete callback */
- HAL_SDADC_ConvCpltCallback(hsdadc);
-
- /* End of conversion if mode is not continuous and software trigger */
- if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
- {
- /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
-
- /* Update SDADC state */
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
- }
- }
- /* Check if end of injected conversion */
- else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \
- ((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE))
- {
- /* Call injected conversion complete callback */
- HAL_SDADC_InjectedConvCpltCallback(hsdadc);
-
- /* Update remaining injected conversions */
- hsdadc->InjConvRemaining--;
- if(hsdadc->InjConvRemaining ==0U)
- {
- /* end of injected sequence, reset the value */
- hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
- }
- /* End of conversion if mode is not continuous, software trigger */
- /* and end of injected sequence */
- if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
- (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
- (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
- {
- /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
-
- /* Update SDADC state */
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
- }
- }
- /* Check if end of calibration */
- else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \
- ((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE))
- {
- /* Clear EOCALIE bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
-
- /* Set CLREOCALF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
-
- /* Call calibration callback */
- HAL_SDADC_CalibrationCpltCallback(hsdadc);
-
- /* Update SDADC state */
- hsdadc->State = HAL_SDADC_STATE_READY;
- }
- /* Check if overrun occurs during regular conversion */
- else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \
- ((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE))
- {
- /* Set CLRROVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
-
- /* Update error code */
- hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
-
- /* Call error callback */
- HAL_SDADC_ErrorCallback(hsdadc);
- }
- /* Check if overrun occurs during injected conversion */
- else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \
- ((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE))
- {
- /* Set CLRJOVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
-
- /* Update error code */
- hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
-
- /* Call error callback */
- HAL_SDADC_ErrorCallback(hsdadc);
- }
- else
- {
- /* No additional IRQ source */
- }
-
- return;
-}
-
-/**
- * @brief Calibration complete callback.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Half regular conversion complete callback.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Regular conversion complete callback.
- * @note In interrupt mode, user has to read conversion value in this function
- using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Half injected conversion complete callback.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Injected conversion complete callback.
- * @note In interrupt mode, user has to read conversion value in this function
- using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Error callback.
- * @param hsdadc SDADC handle.
- * @retval None
- */
-__weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsdadc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SDADC_ErrorCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief DMA half transfer complete callback for regular conversion.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get SDADC handle */
- SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call regular half conversion complete callback */
- HAL_SDADC_ConvHalfCpltCallback(hsdadc);
-}
-
-/**
- * @brief DMA transfer complete callback for regular conversion.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get SDADC handle */
- SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call regular conversion complete callback */
- HAL_SDADC_ConvCpltCallback(hsdadc);
-}
-
-/**
- * @brief DMA half transfer complete callback for injected conversion.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get SDADC handle */
- SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call injected half conversion complete callback */
- HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
-}
-
-/**
- * @brief DMA transfer complete callback for injected conversion.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Get SDADC handle */
- SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Call injected conversion complete callback */
- HAL_SDADC_InjectedConvCpltCallback(hsdadc);
-}
-
-/**
- * @brief DMA error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Get SDADC handle */
- SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Update error code */
- hsdadc->ErrorCode = SDADC_ERROR_DMA;
-
- /* Call error callback */
- HAL_SDADC_ErrorCallback(hsdadc);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
- * @brief SDADC Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### ADC Peripheral State functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to
- (+) Get the SDADC state
- (+) Get the SDADC Error
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function allows to get the current SDADC state.
- * @param hsdadc SDADC handle.
- * @retval SDADC state.
- */
-HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
-{
- return hsdadc->State;
-}
-
-/**
- * @brief This function allows to get the current SDADC error code.
- * @param hsdadc SDADC handle.
- * @retval SDADC error code.
- */
-uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
-{
- return hsdadc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup SDADC_Private_Functions SDADC Private Functions
- * @{
- */
-
-/**
- * @brief This function allows to enter in init mode for SDADC instance.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
-{
- uint32_t tickstart = 0U;
-
- /* Set INIT bit on SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
-
- /* Wait INITRDY bit on SDADC_ISR */
- tickstart = HAL_GetTick();
- while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
- {
- if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief This function allows to exit from init mode for SDADC instance.
- * @param hsdadc SDADC handle.
- * @retval None.
- */
-static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
-{
- /* Reset INIT bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
-}
-
-/**
- * @brief This function allows to get the number of injected channels.
- * @param Channels bitfield of injected channels.
- * @retval Number of injected channels.
- */
-static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
-{
- uint32_t nbChannels = 0U;
- uint32_t tmp,i;
-
- /* Get the number of channels from bitfield */
- tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
- for(i = 0U ; i < 9U ; i++)
- {
- if((tmp & 0x00000001U) != 0U)
- {
- nbChannels++;
- }
- tmp = (uint32_t) (tmp >> 1U);
- }
- return nbChannels;
-}
-
-/**
- * @brief This function allows to really start regular conversion.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check regular trigger */
- if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
- {
- /* Set RSWSTART bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
- }
- else /* synchronuous trigger */
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Set RSYNC bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_RSYNC;
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Update SDADC state only if status is OK */
- if(status == HAL_OK)
- {
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
- HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to really stop regular conversion.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
-{
- uint32_t tickstart;
- __IO uint32_t dummy_read_for_register_reset;
-
- /* Check continuous mode */
- if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
- {
- /* Clear REOCF by reading SDADC_RDATAR register */
- dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
- UNUSED(dummy_read_for_register_reset);
-
- /* Clear RCONT bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
- }
- /* Wait for the end of regular conversion */
- tickstart = HAL_GetTick();
- while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0U)
- {
- if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
- {
- /* Set SDADC in error state and return timeout status */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- return HAL_TIMEOUT;
- }
- }
- /* Check if trigger is synchronuous */
- if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state and return timeout status */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- return HAL_TIMEOUT;
- }
- else
- {
- /* Clear RSYNC bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
-
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Check if continuous mode */
- if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
- {
- /* Restore RCONT bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 |= SDADC_CR2_RCONT;
- }
- /* Clear REOCF by reading SDADC_RDATAR register */
- dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
- UNUSED(dummy_read_for_register_reset);
-
- /* Set CLRROVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
-
- /* Update SDADC state */
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function allows to really start injected conversion.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Initialize number of injected conversions remaining */
- hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
-
- /* Check injected trigger */
- if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
- {
- /* Set JSWSTART bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
- }
- else /* external or synchronuous trigger */
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- status = HAL_TIMEOUT;
- }
- else
- {
- if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
- {
- /* Set JSYNC bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 |= SDADC_CR1_JSYNC;
- }
- else /* external trigger */
- {
- /* Set JEXTEN[1:0] bits in SDADC_CR2 register */
- hsdadc->Instance->CR2 |= hsdadc->ExtTriggerEdge;
- }
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Update SDADC state only if status is OK */
- if(status == HAL_OK)
- {
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
- HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
- }
- /* Return function status */
- return status;
-}
-
-/**
- * @brief This function allows to really stop injected conversion.
- * @param hsdadc SDADC handle.
- * @retval HAL status.
- */
-static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
-{
- uint32_t tickstart;
- __IO uint32_t dummy_read_for_register_reset;
-
- /* Check continuous mode */
- if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
- {
- /* Clear JEOCF by reading SDADC_JDATAR register */
- dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
- UNUSED(dummy_read_for_register_reset);
-
- /* Clear JCONT bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
- }
- /* Wait for the end of injected conversion */
- tickstart = HAL_GetTick();
- while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0U)
- {
- if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
- {
- /* Set SDADC in error state and return timeout status */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- return HAL_TIMEOUT;
- }
- }
- /* Check if trigger is not software */
- if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
- {
- /* Enter init mode */
- if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
- {
- /* Set SDADC in error state and return timeout status */
- hsdadc->State = HAL_SDADC_STATE_ERROR;
- return HAL_TIMEOUT;
- }
- else
- {
- /* Check if trigger is synchronuous */
- if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
- {
- /* Clear JSYNC bit in SDADC_CR1 register */
- hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
- }
- else /* external trigger */
- {
- /* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
- hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
- }
- /* Exit init mode */
- SDADC_ExitInitMode(hsdadc);
- }
- }
- /* Check if continuous mode */
- if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
- {
- /* Restore JCONT bit in SDADC_CR2 register */
- hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
- }
- /* Clear JEOCF by reading SDADC_JDATAR register */
- dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
- UNUSED(dummy_read_for_register_reset);
-
- /* Set CLRJOVRF bit in SDADC_CLRISR register */
- hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
-
- /* Update SDADC state */
- hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
- HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
-#endif /* HAL_SDADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
deleted file mode 100644
index c5ccfebb860..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
+++ /dev/null
@@ -1,2294 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smartcard.c
- * @author MCD Application Team
- * @brief SMARTCARD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the SMARTCARD peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SMARTCARD HAL driver can be used as follows:
-
- (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
- (#) Associate a USART to the SMARTCARD handle hsmartcard.
- (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
- (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
- and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
- and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
- the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
- error enabling or disabling in the hsmartcard handle Init structure.
-
- (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
- in the hsmartcard handle AdvancedInit structure.
-
- (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMARTCARD_MspInit() API.
- [..]
- (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
- [..]
- [..] Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
- (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
-
- *** SMARTCARD HAL driver macros list ***
- ========================================
- [..]
- Below the list of most used macros in SMARTCARD HAL driver.
-
- (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
-
- [..]
- (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMARTCARD SMARTCARD
- * @brief SMARTCARD HAL module driver
- * @{
- */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
- * @{
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx
- associated to the SmartCard.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- (+) These parameters can be configured:
- (++) Baud Rate
- (++) Parity: should be enabled
- (++) Receiver/transmitter modes
- (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
- (++) Prescaler value
- (++) Guard bit time
- (++) NACK enabling or disabling on transmission error
-
- (+) The following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) Time out enabling (and if activated, timeout value)
- (++) Block length
- (++) Auto-retry counter
- [..]
- The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
- (details for the procedures are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/*
- Additional Table:
- Frame Length is fixed to 8 bits plus parity:
- SMARTCARD frame format is given in the following table:
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | SMARTCARD frame |
- |-----------------------|---------------------------------------|
- | 01 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
-
-*/
-
-/**
- * @brief Initialize the SMARTCARD mode according to the specified
- * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART associated to the SMARTCARD handle */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsmartcard->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_SMARTCARD_MspInit(hsmartcard);
- }
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Disable the Peripheral to set smartcard mode */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* In SmartCard mode, the following bits must be kept cleared:
- - LINEN in the USART_CR2 register,
- - HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* set the USART in SMARTCARD mode */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
-
- /* Set the SMARTCARD Communication parameters */
- if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
- {
- SMARTCARD_AdvFeatureConfig(hsmartcard);
- }
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
- return (SMARTCARD_CheckIdleState(hsmartcard));
-}
-
-/**
- * @brief DeInitialize the SMARTCARD peripheral.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the USART/UART associated to the SMARTCARD handle */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Disable the Peripheral */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
- WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
- WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
- WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
- WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
-
- /* DeInit the low level hardware */
- HAL_SMARTCARD_MspDeInit(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SMARTCARD MSP.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SMARTCARD MSP.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
- [..]
- Smartcard is a single wire half duplex communication protocol.
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard. The USART should be configured as:
- (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
- [..]
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
- or DMA, the relevant API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
- error is detected.
-
- (#) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_SMARTCARD_Abort()
- (++) HAL_SMARTCARD_AbortTransmit()
- (++) HAL_SMARTCARD_AbortReceive()
- (++) HAL_SMARTCARD_Abort_IT()
- (++) HAL_SMARTCARD_AbortTransmit_IT()
- (++) HAL_SMARTCARD_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_SMARTCARD_AbortCpltCallback()
- (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- while(hsmartcard->TxXferCount > 0U)
- {
- hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
- }
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- {
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- }
-
- /* At end of Tx process, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(hsmartcard->RxXferCount > 0U)
- {
- hsmartcard->RxXferCount--;
-
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
- }
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- /* Disable the Peripheral first to update mode for TX master */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
- /* Set the SMARTCARD error callback */
- hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the SMARTCARD transmit DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the UART Error Interrupt: (Frame error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
- * the received data contain the parity bit (MSB position).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
- /* Set the SMARTCARD DMA error callback */
- hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmatx);
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0U;
- hsmartcard->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
-
- /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsmartcard->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
- }
- else
- {
- hsmartcard->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
- }
- else
- {
- hsmartcard->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* SMARTCARD Tx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- hsmartcard->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* SMARTCARD Rx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- hsmartcard->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0U;
- hsmartcard->RxXferCount = 0U;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
- hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SMARTCARD Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
-
- /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
- hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMARTCARD interrupt requests.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
- uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
- if (errorflags == RESET)
- {
- /* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsmartcard);
- /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(hsmartcard->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
- {
- /* SMARTCARD parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- }
-
- /* SMARTCARD frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
- }
-
- /* SMARTCARD noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
- }
-
- /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
- }
-
- /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
- }
-
- /* Call SMARTCARD Error Call back function if need be --------------------------*/
- if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
- {
- /* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsmartcard);
- }
-
- /* If Error is to be considered as blocking :
- - Receiver Timeout error in Reception
- - Overrun error in Reception
- - any error occurs in DMA mode reception
- */
- if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
- || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- SMARTCARD_EndRxTransfer(hsmartcard);
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel */
- if(hsmartcard->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
- hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- /* other error type to be considered as blocking :
- - Frame error in Transmission
- */
- else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
- {
- /* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
- SMARTCARD_EndTxTransfer(hsmartcard);
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel */
- if(hsmartcard->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
- {
- /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
- hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
- if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
- {
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- __HAL_UNLOCK(hsmartcard);
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
- /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
- * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
- return;
- }
-
- /* SMARTCARD in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- SMARTCARD_Transmit_IT(hsmartcard);
- return;
- }
-
- /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
- {
- SMARTCARD_EndTransmit_IT(hsmartcard);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD error callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Receive Complete callback.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmartcard);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of SmartCard
- handle and also return Peripheral Errors occurred during communication process
- (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
- of the SMARTCARD peripheral.
- (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
- communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SMARTCARD handle state.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval SMARTCARD handle state
- */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Return SMARTCARD handle state */
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hsmartcard->gState;
- temp2 = hsmartcard->RxState;
-
- return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the SMARTCARD handle error code.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval SMARTCARD handle Error Code
-*/
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- return hsmartcard->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @{
- */
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t tmpreg = 0x00000000U;
- SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
- assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
- assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
- assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
- assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
- assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
- assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
- assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
- assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
- assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
- assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
- assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
- assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
- * Oversampling is forced to 16 (OVER8 = 0).
- * Configure the Parity and Mode:
- * set PS bit according to hsmartcard->Init.Parity value
- * set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
- MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = hsmartcard->Init.StopBits;
- /* Synchronous mode is activated by default */
- tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
- tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - one-bit sampling method versus three samples' majority rule
- * according to hsmartcard->Init.OneBitSampling
- * - NACK transmission in case of parity error according
- * to hsmartcard->Init.NACKEnable
- * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
- tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
- tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
- MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
-
- /*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
- if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
- {
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
- }
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
- switch (clocksource)
- {
- case SMARTCARD_CLOCKSOURCE_PCLK1:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_PCLK2:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_HSI:
- hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_SYSCLK:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- return ret;
-}
-
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral advanced features.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
- MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
- }
-
-}
-
-/**
- * @brief Check the SMARTCARD Idle State.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the SMARTCARD ErrorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the SMARTCARD states */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMARTCARD Communication Timeout.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param Flag Specifies the SMARTCARD flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Tx process, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
- * @brief DMA SMARTCARD transmit process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-}
-
-/**
- * @brief DMA SMARTCARD receive process complete callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD communication error callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
-
- /* Stop SMARTCARD DMA Tx request if ongoing */
- if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
- {
- hsmartcard->TxXferCount = 0U;
- SMARTCARD_EndTxTransfer(hsmartcard);
- }
-
- /* Stop SMARTCARD DMA Rx request if ongoing */
- if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
- {
- hsmartcard->RxXferCount = 0U;
- SMARTCARD_EndRxTransfer(hsmartcard);
- }
-
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0U;
- hsmartcard->TxXferCount = 0U;
-
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmarx != NULL)
- {
- if(hsmartcard->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0U;
- hsmartcard->RxXferCount = 0U;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-}
-
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmatx != NULL)
- {
- if(hsmartcard->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0U;
- hsmartcard->RxXferCount = 0U;
-
- /* Reset errorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
-}
-
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
-
- hsmartcard->TxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
-
- /* Restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
- hsmartcard->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
-
- /* Restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
-}
-
-/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Tx process is ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- if(hsmartcard->TxXferCount == 0U)
- {
- /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
- hsmartcard->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- {
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- }
-
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Rx process is ongoing */
- if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
-
- if(--hsmartcard->RxXferCount == 0U)
- {
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Check if a transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- }
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
-
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
deleted file mode 100644
index 66634198f25..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smartcard_ex.c
- * @author MCD Application Team
- * @brief SMARTCARD HAL module driver.
- * This file provides extended firmware functions to manage the following
- * functionalities of the SmartCard.
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- =============================================================================
- ##### SMARTCARD peripheral extended features #####
- =============================================================================
- [..]
- The Extended SMARTCARD HAL driver can be used as follows:
-
- (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
- then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
- auto-retry counter,...) in the hsmartcard AdvancedInit structure.
-
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMARTCARDEx SMARTCARDEx
- * @brief SMARTCARD Extension HAL module driver
- * @{
- */
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
- * @{
- */
-
-/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the SMARTCARD.
- (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
- (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
- (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
- (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Update on the fly the SMARTCARD block length in RTOR register.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param BlockLength SMARTCARD block length (8-bit long at most)
- * @retval None
- */
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
-{
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
-}
-
-/**
- * @brief Update on the fly the receiver timeout value in RTOR register.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
- * value must be less or equal to 0x0FFFFFFFF.
- * @retval None
- */
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
-{
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
-}
-
-/**
- * @brief Enable the SMARTCARD receiver timeout feature.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Set the USART RTOEN bit */
- SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the SMARTCARD receiver timeout feature.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Clear the USART RTOEN bit */
- CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
deleted file mode 100644
index 3fb3f739b23..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
+++ /dev/null
@@ -1,2172 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_smbus.c
- * @author MCD Application Team
- * @brief SMBUS HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the System Management Bus (SMBus) peripheral,
- * based on I2C principles of operation :
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SMBUS HAL driver can be used as follows:
-
- (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
- SMBUS_HandleTypeDef hsmbus;
-
- (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
- (##) Enable the SMBUSx interface clock
- (##) SMBUS pins configuration
- (+++) Enable the clock for the SMBUS GPIOs
- (+++) Configure SMBUS pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SMBUSx interrupt priority
- (+++) Enable the NVIC SMBUS IRQ Channel
-
- (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
- Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
- Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
-
- (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
-
- (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
-
- (#) For SMBUS IO operations, only one mode of operations is available within this driver
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
- (++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
- (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
- (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Error Code using function HAL_SMBUS_GetError()
-
- *** SMBUS HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in SMBUS HAL driver.
-
- (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
- (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
- (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
- (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
-
- [..]
- (@) You can refer to the SMBUS HAL driver header file for more useful macros
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMBUS SMBUS
- * @brief SMBUS HAL module driver
- * @{
- */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Define SMBUS Private Constants
- * @{
- */
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
-#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
-#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
-#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
-#define MAX_NBYTE_SIZE 255U
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @{
- */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
-
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
- * @{
- */
-
-/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- deinitialize the SMBUSx peripheral:
-
- (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
-
- (+) Call the function HAL_SMBUS_Init() to configure the selected device with
- the selected configuration:
- (++) Clock Timing
- (++) Bus Timeout
- (++) Analog Filer mode
- (++) Own Address 1
- (++) Addressing mode (Master, Slave)
- (++) Dual Addressing mode
- (++) Own Address 2
- (++) Own Address 2 Mask
- (++) General call mode
- (++) Nostretch mode
- (++) Packet Error Check mode
- (++) Peripheral mode
-
-
- (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
- of the selected SMBUSx peripheral.
-
- (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
- HAL_SMBUS_ConfigDigitalFilter().
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SMBUS according to the specified parameters
- * in the SMBUS_InitTypeDef and initialize the associated handle.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Check the SMBUS handle allocation */
- if (hsmbus == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
- assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
- assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
- assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
- assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
- assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
- assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
- assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
- assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
- assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
- assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
-
- if (hsmbus->State == HAL_SMBUS_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsmbus->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_SMBUS_MspInit(hsmbus);
- }
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
- /* Configure SMBUSx: Frequency range */
- hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
- /* Configure SMBUSx: Bus Timeout */
- hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
- hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
- hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
-
- /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
- /* Configure SMBUSx: Own Address1 and ack own address1 mode */
- hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- if (hsmbus->Init.OwnAddress1 != 0U)
- {
- if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
- }
- else /* SMBUS_ADDRESSINGMODE_10BIT */
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
- }
- }
-
- /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
- /* Configure SMBUSx: Addressing Master mode */
- if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
- {
- hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
- }
- /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
- /* AUTOEND and NACK bit will be manage during Transfer process */
- hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
- /* Configure SMBUSx: Dual mode and Own Address2 */
- hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
-
- /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
- /* Configure SMBUSx: Generalcall and NoStretch mode */
- hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
-
- /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
- {
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
- }
-
- /* Enable the selected SMBUS peripheral */
- __HAL_SMBUS_ENABLE(hsmbus);
-
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the SMBUS peripheral.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Check the SMBUS handle allocation */
- if (hsmbus == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the SMBUS Peripheral Clock */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_SMBUS_MspDeInit(hsmbus);
-
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
- hsmbus->State = HAL_SMBUS_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SMBUS MSP.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the SMBUS MSP.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Configure Analog noise filter.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param AnalogFilter This parameter can be one of the following values:
- * @arg @ref SMBUS_ANALOGFILTER_ENABLE
- * @arg @ref SMBUS_ANALOGFILTER_DISABLE
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
- assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
-
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /* Reset ANOFF bit */
- hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
- /* Set analog filter bit*/
- hsmbus->Instance->CR1 |= AnalogFilter;
-
- __HAL_SMBUS_ENABLE(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure Digital noise filter.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
- assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
-
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- /* Get the old register value */
- tmpreg = hsmbus->Instance->CR1;
-
- /* Reset I2C DNF bits [11:8] */
- tmpreg &= ~(I2C_CR1_DNF);
-
- /* Set I2Cx DNF coefficient */
- tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
-
- /* Store the new register value */
- hsmbus->Instance->CR1 = tmpreg;
-
- __HAL_SMBUS_ENABLE(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMBUS data
- transfers.
-
- (#) Blocking mode function to check if device is ready for usage is :
- (++) HAL_SMBUS_IsDeviceReady()
-
- (#) There is only one mode of transfer:
- (++) Non-Blocking mode : The communication is performed using Interrupts.
- These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated SMBUS IRQ when using Interrupt mode.
-
- (#) Non-Blocking mode functions with Interrupt are :
- (++) HAL_SMBUS_Master_Transmit_IT()
- (++) HAL_SMBUS_Master_Receive_IT()
- (++) HAL_SMBUS_Slave_Transmit_IT()
- (++) HAL_SMBUS_Slave_Receive_IT()
- (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
- (++) HAL_SMBUS_DisableListen_IT()
- (++) HAL_SMBUS_EnableAlert_IT()
- (++) HAL_SMBUS_DisableAlert_IT()
-
- (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
- (++) HAL_SMBUS_MasterTxCpltCallback()
- (++) HAL_SMBUS_MasterRxCpltCallback()
- (++) HAL_SMBUS_SlaveTxCpltCallback()
- (++) HAL_SMBUS_SlaveRxCpltCallback()
- (++) HAL_SMBUS_AddrCallback()
- (++) HAL_SMBUS_ListenCpltCallback()
- (++) HAL_SMBUS_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* In case of Quick command, remove autoend mode */
- /* Manage the stop generation by software */
- if (hsmbus->pBuffPtr == NULL)
- {
- hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
- }
-
- if (Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
- }
- else
- {
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- /* Else transfer direction change, so generate Restart with new transfer direction */
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
- }
-
- /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* In case of Quick command, remove autoend mode */
- /* Manage the stop generation by software */
- if (hsmbus->pBuffPtr == NULL)
- {
- hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
- }
-
- if (Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
- }
- else
- {
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- /* Else transfer direction change, so generate Restart with new transfer direction */
- else
- {
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master/host SMBUS process communication with Interrupt.
- * @note This abort can be called only if state is ready
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
-{
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- /* Keep the same state as previous */
- /* to perform as well the call of the corresponding end of transfer callback */
- if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
- }
- else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
- /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
- }
- else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set SBC bit to manage Acknowledge at each bit */
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
- /* Enable Address Acknowledge */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- if (Size > MAX_NBYTE_SIZE)
- {
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = Size;
- }
-
- /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
- {
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
- }
- else
- {
- /* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
-
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- if ((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- /* Set SBC bit to manage Acknowledge at each bit */
- hsmbus->Instance->CR1 |= I2C_CR1_SBC;
-
- /* Enable Address Acknowledge */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
-
- /* Prepare transfer parameters */
- hsmbus->pBuffPtr = pData;
- hsmbus->XferSize = Size;
- hsmbus->XferCount = Size;
- hsmbus->XferOptions = XferOptions;
-
- /* Convert OTHER_xxx XferOptions if any */
- SMBUS_ConvertOtherXferOptions(hsmbus);
-
- /* Set NBYTE to receive */
- /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
- /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
- /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
- /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
- {
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- else
- {
- SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
- }
-
- /* Clear ADDR flag after prepare the transfer parameters */
- /* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
- to avoid the risk of SMBUS interrupt handle execution before current
- process unlock */
- /* REnable ADDR interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-
- /* Enable the Address Match interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Disable Address listen mode only if a transfer is not ongoing */
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Disable the Address Match interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the SMBUS alert mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUSx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Enable SMBus alert */
- hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
-
- /* Enable Alert Interrupt */
- SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
- return HAL_OK;
-}
-/**
- * @brief Disable the SMBUS alert mode with Interrupt.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUSx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Enable SMBus alert */
- hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
-
- /* Disable Alert Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
-
- return HAL_OK;
-}
-
-/**
- * @brief Check if target device is ready for communication.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param Trials Number of trials
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- __IO uint32_t SMBUS_Trials = 0U;
-
- if (hsmbus->State == HAL_SMBUS_STATE_READY)
- {
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- hsmbus->State = HAL_SMBUS_STATE_BUSY;
- hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
- do
- {
- /* Generate Start */
- hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
-
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is set or a NACK flag is set*/
- tickstart = HAL_GetTick();
- while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Device is ready */
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check if the NACKF flag has not been set */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
- {
- /* Wait until STOPF flag is reset */
- if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Device is ready */
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
- }
- else
- {
- /* Wait until STOPF flag is reset */
- if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Clear STOP Flag, auto generated with autoend*/
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- }
-
- /* Check if the maximum allowed number of trials has been reached */
- if (SMBUS_Trials++ == Trials)
- {
- /* Generate Stop */
- hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- }
- }
- while (SMBUS_Trials < Trials);
-
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief Handle SMBUS event interrupt request.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
- uint32_t tmpisrvalue = 0U;
-
- /* Use a local variable to store the current ISR flags */
- /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
- tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
-
- /* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
- {
- /* Slave mode selected */
- if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- /* Master mode selected */
- else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- SMBUS_Master_ISR(hsmbus);
- }
- }
-
- /* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
- {
- /* Slave mode selected */
- if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- /* Master mode selected */
- else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Master_ISR(hsmbus);
- }
- }
-
- /* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
- {
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
- {
- SMBUS_Slave_ISR(hsmbus);
- }
- }
-}
-
-/**
- * @brief Handle SMBUS error interrupt request.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
-{
- SMBUS_ITErrorHandler(hsmbus);
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param TransferDirection Master request Transfer Direction (Write/Read)
- * @param AddrMatchCode Address Match Code
- * @retval None
- */
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_AddrCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
- */
-}
-
-/**
- * @brief SMBUS error callback.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval None
- */
-__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsmbus);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_ErrorCallback() could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SMBUS handle state.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL state
- */
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
-{
- /* Return SMBUS handle state */
- return hsmbus->State;
-}
-
-/**
-* @brief Return the SMBUS error code.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
-* @retval SMBUS Error Code
-*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
-{
- return hsmbus->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
- * @{
- */
-
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
-{
- uint16_t DevAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
- {
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Set corresponding Error Code */
- /* No need to generate STOP, it is automatically done */
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to inform upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
- {
- /* Check and treat errors if errors occurs during STOP process */
- SMBUS_ITErrorHandler(hsmbus);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
- /* Disable the selected SMBUS peripheral */
- __HAL_SMBUS_DISABLE(hsmbus);
-
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* REenable the selected SMBUS peripheral */
- __HAL_SMBUS_ENABLE(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- /* Store Last receive data if any */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
-
- if ((hsmbus->XferSize > 0U))
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
- {
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
- {
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
- {
- DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
-
- if (hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
- SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
- }
- else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
- {
- /* Call TxCpltCallback() if no stop mode is set */
- if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- }
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
- {
- if (hsmbus->XferCount == 0U)
- {
- /* Specific use case for Quick command */
- if (hsmbus->pBuffPtr == NULL)
- {
- /* Generate a Stop command */
- hsmbus->Instance->CR2 |= I2C_CR2_STOP;
- }
- /* Call TxCpltCallback() if no stop mode is set */
- else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
- {
- /* No Generate Stop, to permit restart mode */
- /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
- {
- /* Disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterTxCpltCallback(hsmbus);
- }
- else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
- {
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- HAL_SMBUS_MasterRxCpltCallback(hsmbus);
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
-{
- uint8_t TransferDirection = 0U;
- uint16_t SlaveAddrCode = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hsmbus);
-
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
- {
- /* Check that SMBUS transfer finished */
- /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if (hsmbus->XferCount == 0U)
- {
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
- }
- else
- {
- /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
- /* Clear NACK Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
- /* Set HAL State to "Idle" State, mean to LISTEN state */
- /* So reset Slave Busy state */
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
- /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to inform upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
- {
- TransferDirection = SMBUS_GET_DIR(hsmbus);
- SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
-
- /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
- /* Other ADDRInterrupt will be treat in next Listen usecase */
- __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call Slave Addr callback */
- HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
- }
- else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
- {
- if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- hsmbus->XferSize--;
- hsmbus->XferCount--;
-
- if (hsmbus->XferCount == 1U)
- {
- /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
- /* or only the last Byte of Transfer */
- /* So reset the RELOAD bit mode */
- hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- }
- else if (hsmbus->XferCount == 0U)
- {
- /* Last Byte is received, disable Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
- /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
- HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
- }
- else
- {
- /* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
-
- /* Ack last Byte Read */
- hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
- }
- }
- else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- {
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
- {
- if (hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
- SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
- hsmbus->XferSize = MAX_NBYTE_SIZE;
- }
- else
- {
- hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
- /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
- /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
- }
- }
- }
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- /* Check if all Data have already been sent */
- /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if (hsmbus->XferCount > 0U)
- {
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
- hsmbus->XferCount--;
- hsmbus->XferSize--;
- }
-
- if (hsmbus->XferCount == 0U)
- {
- /* Last Byte is Transmitted */
- /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
- HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
- }
- }
-
- /* Check if STOPF is set */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
- {
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
- {
- /* Store Last receive data if any */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
- /* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
-
- if ((hsmbus->XferSize > 0U))
- {
- hsmbus->XferSize--;
- hsmbus->XferCount--;
- }
- }
-
- /* Disable RX and TX Interrupts */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
- /* Disable ADDR Interrupt */
- SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
- /* Disable Address Acknowledge */
- hsmbus->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear Configuration Register 2 */
- SMBUS_RESET_CR2(hsmbus);
-
- /* Clear STOP Flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
- /* Clear ADDR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
-
- hsmbus->XferOptions = 0U;
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_SMBUS_ListenCpltCallback(hsmbus);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
-/**
- * @brief Manage the enabling of Interrupts.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
- {
- /* Enable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
- {
- /* Enable ADDR, STOP interrupt */
- tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
- }
-
- if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
- {
- /* Enable ERR, TC, STOP, NACK, RXI interrupt */
- tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
- }
-
- if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
- {
- /* Enable ERR, TC, STOP, NACK, TXI interrupt */
- tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
- }
-
- /* Enable interrupts only at the end */
- /* to avoid the risk of SMBUS interrupt handle execution before */
- /* all interrupts requested done */
- __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
-}
-/**
- * @brief Manage the disabling of Interrupts.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
-{
- uint32_t tmpisr = 0U;
-
- if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
- {
- /* Disable TC, STOP, NACK, TXI interrupt */
- tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
-
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
- {
- /* Disable STOPI, NACKI */
- tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- }
- }
-
- if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
- {
- /* Disable TC, STOP, NACK, RXI interrupt */
- tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
-
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
-
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
- {
- /* Disable STOPI, NACKI */
- tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- }
- }
-
- if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
- {
- /* Enable ADDR, STOP interrupt */
- tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
-
- if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- {
- /* Disable ERR interrupt */
- tmpisr |= SMBUS_IT_ERRI;
- }
- }
-
- /* Disable interrupts only at the end */
- /* to avoid a breaking situation like at "t" time */
- /* all disable interrupts request are not done */
- __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
-}
-
-/**
- * @brief SMBUS interrupts error handler.
- * @param hsmbus SMBUS handle.
- * @retval None
- */
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
-{
- uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
- uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
-
- /* SMBUS Bus error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
- }
-
- /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
- }
-
- /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
- }
-
- /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
- /* Clear TIMEOUT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
- }
-
- /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
- }
-
- /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
- /* Clear PEC error flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
- }
-
- /* Call the Error Callback in case of Error detected */
- if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
- {
- /* Do not Reset the HAL state in case of ALERT error */
- if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
- {
- if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
- {
- /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
- /* keep HAL_SMBUS_STATE_LISTEN if set */
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
- }
- }
-
- /* Call the Error callback to inform upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
-}
-
-/**
- * @brief Handle SMBUS Communication Timeout.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
- * @param Flag Specifies the SMBUS flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if (Status == RESET)
- {
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param hsmbus SMBUS handle.
- * @param DevAddress specifies the slave address to be programmed.
- * @param Size specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param Mode New state of the SMBUS START condition generation.
- * This parameter can be one or a combination of the following values:
- * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
- * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
- * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
- * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
- * @param Request New state of the SMBUS START condition generation.
- * This parameter can be one of the following values:
- * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
- * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
- * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
- * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
- * @retval None
- */
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
- assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
- assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
-
- /* Get the CR2 register value */
- tmpreg = hsmbus->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
- /* update CR2 register */
- hsmbus->Instance->CR2 = tmpreg;
-}
-
-/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
- * @param hsmbus SMBUS handle.
- * @retval None
- */
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
-{
- /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
- /* it request implicitly to generate a restart condition */
- /* set XferOptions to SMBUS_FIRST_FRAME */
- if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_FRAME;
- }
- /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
- /* it request implicitly to generate a restart condition */
- /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
- else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
- }
- /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
- /* it request implicitly to generate a restart condition */
- /* then generate a stop condition at the end of transfer */
- /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
- else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
- }
- /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
- /* it request implicitly to generate a restart condition */
- /* then generate a stop condition at the end of transfer */
- /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
- else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
- {
- hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
- }
-}
-/**
- * @}
- */
-
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
deleted file mode 100644
index b568ac8263d..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
+++ /dev/null
@@ -1,3863 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_spi.c
- * @author MCD Application Team
- * @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Peripheral Interface (SPI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
- (+++) Enable the DMAx clock
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SPI_MspInit() API.
- [..]
- Circular mode restriction:
- (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
- (##) Master 2Lines RxOnly
- (##) Master 1Line Rx
- (#) The CRC feature is not managed when the DMA circular mode is enabled
- (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
- the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
- [..]
- Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
- bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
- does not initiate a new transfer the following procedure has to be respected:
- (##) HAL_SPI_DeInit()
- (##) HAL_SPI_Init()
- [..]
- The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
- modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
- maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
- the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
-
-
- @endverbatim
-
- Additional table :
-
- DataSize = SPI_DATASIZE_8BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
- +----------------------------------------------------------------------------------------------+
-
- DataSize = SPI_DATASIZE_16BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
- +----------------------------------------------------------------------------------------------+
- @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- @note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPI SPI
- * @brief SPI HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
- uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
- uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPIx peripheral:
-
- (+) User must implement HAL_SPI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Direction
- (++) Data Size
- (++) Clock Polarity and Phase
- (++) NSS Management
- (++) BaudRate Prescaler
- (++) FirstBit
- (++) TIMode
- (++) CRC Calculation
- (++) CRC Polynomial if CRC enabled
- (++) CRC Length, used only with Data8 and Data16
- (++) FIFO reception threshold
-
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SPI according to the specified parameters
- * in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
- uint32_t frxth;
-
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
- if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
- {
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
- }
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- if (hspi->State == HAL_SPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hspi->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Align by default the rs fifo threshold on the data size */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- frxth = SPI_RXFIFO_THRESHOLD_HF;
- }
- else
- {
- frxth = SPI_RXFIFO_THRESHOLD_QF;
- }
-
- /* CRC calculation is valid only for 16Bit and 8 Bit */
- if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
- {
- /* CRC must be disabled */
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
- }
-
- /* Align the CRC Length on the data size */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
- {
- /* CRC Length aligned on the data size : value set by default */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
- }
- else
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
- }
- }
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit and CRC calculation state */
- WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
-#if (USE_SPI_CRC != 0U)
- /* Configure : CRC Length */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
- {
- hspi->Instance->CR1 |= SPI_CR1_CRCL;
- }
-#endif /* USE_SPI_CRC */
-
- /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
- hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
-
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
- }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initialize the SPI peripheral.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if (hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check SPI Instance parameter */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the SPI Peripheral Clock */
- __HAL_SPI_DISABLE(hspi);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPI_MspDeInit(hspi);
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize the SPI MSP.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPI
- data transfers.
-
- [..] The SPI supports master and slave mode :
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
- exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- /* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- /* Transmit data in 8 Bit mode */
- else
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- if (hspi->TxXferCount > 1U)
- {
- /* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- else
- {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
- hspi->TxXferCount--;
- }
- }
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- if (hspi->TxXferCount > 1U)
- {
- /* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- else
- {
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
- hspi->TxXferCount--;
- }
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- /* this is done to handle the CRCNEXT before the latest data */
- hspi->RxXferCount--;
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the Rx FiFo threshold */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* set fiforxthresold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* set fiforxthresold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Configure communication direction: 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Receive data in 8 Bit mode */
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- /* read the received data */
- (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
- pData += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- else
- {
- /* Transfer loop */
- while (hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- *((uint16_t *)pData) = hspi->Instance->DR;
- pData += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Handle the CRC Transmission */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* freeze the CRC before the latest data */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
- /* Read the latest data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Receive last data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- *((uint16_t *)pData) = hspi->Instance->DR;
- }
- /* Receive last data in 8 Bit mode */
- else
- {
- (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
-
- /* Wait the CRC data */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Read CRC to Flush DR and RXNE flag */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- else
- {
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
- /* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
-
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferCount = Size;
- hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the Rx Fifo threshold */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
- {
- /* set fiforxthreshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* set fiforxthreshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit and Receive data in 16 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
- }
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Check RXNE flag */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
- {
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- /* Transmit and Receive data in 8 Bit mode */
- else
- {
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- if (hspi->TxXferCount > 1U)
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- else
- {
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
- hspi->TxXferCount--;
- }
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- if (hspi->TxXferCount > 1U)
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- else
- {
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
- hspi->TxXferCount--;
- }
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
- }
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Wait until RXNE flag is reset */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
- {
- if (hspi->RxXferCount > 1U)
- {
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
- hspi->RxXferCount -= 2U;
- if (hspi->RxXferCount <= 1U)
- {
- /* set fiforxthresold before to switch on 8 bit data size */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- }
- else
- {
- (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->RxXferCount--;
- }
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Read CRC from DR to close CRC calculation process */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until TXE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read CRC */
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- else
- {
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
- {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- }
- }
-
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- /* Clear CRC Flag */
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->TxISR = NULL;
-
- /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* Set fiforxthresold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_16BIT;
- }
- else
- {
- /* Set fiforxthresold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1U;
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2U;
- }
- SPI_RESET_CRC(hspi);
- }
- else
- {
- hspi->CRCSize = 0U;
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @param Size amount of data to be sent and received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
-
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1U;
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2U;
- }
- SPI_RESET_CRC(hspi);
- }
- else
- {
- hspi->CRCSize = 0U;
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if packing mode is enabled and if there is more than 2 data to receive */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
- {
- /* Set fiforxthresold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* Set fiforxthresold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- /* Packing mode is enabled only if the DMA setting is HALWORD */
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
- {
- /* Check the even/odd of the data size + crc if enabled */
- if ((hspi->TxXferCount & 0x1U) == 0U)
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U);
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
- }
- }
-
- /* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* check rx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
-
- /* check tx dma handle */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
-#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
- /* Packing mode management is enabled by the DMA settings */
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- goto error;
- }
-#endif
-
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* Set fiforxthresold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* Set fiforxthresold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- /* set fiforxthresold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if ((hspi->RxXferCount & 0x1U) == 0x0U)
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1U;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
- }
- }
- }
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData pointer to transmission data buffer
- * @param pRxData pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* check rx & tx dma handles */
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
- if (!((tmp == HAL_SPI_STATE_READY) ||
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
-
-#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
- /* packing mode management is enabled by the DMA settings */
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- goto error;
- }
-#endif
-
- /* Reset the threshold bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
-
- /* The packing mode management is enabled by the DMA settings according the spi data size */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- /* Set fiforxthreshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* Set fiforxthresold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- if ((hspi->TxXferSize & 0x1U) == 0x0U)
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1U;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
- }
- }
-
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- /* Set fiforxthresold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
- if ((hspi->RxXferCount & 0x1U) == 0x0U)
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1U;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
- }
- }
- }
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- }
- else
- {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
- hspi->hdmatx->XferErrorCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
- /* Enable the SPI Error Interrupt Bit */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- __IO uint32_t count, resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
- if (hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- }
- /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
- if (hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
- }
- }
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
- HAL_StatusTypeDef errorcode;
- uint32_t abortcplt ;
- __IO uint32_t count, resetcount;
-
- /* Initialized local variable */
- errorcode = HAL_OK;
- abortcplt = 1U;
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- count = resetcount;
-
- /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- /* Wait HAL_SPI_STATE_ABORT state */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
- /* Reset Timeout Counter */
- count = resetcount;
- }
-
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if (hspi->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
- }
- else
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if (hspi->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
- }
- else
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check error during Abort procedure */
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
- {
- /* return HAL_Error in case of error during Abort procedure */
- errorcode = HAL_ERROR;
- }
- else
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
- }
-
- return errorcode;
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Enable the SPI DMA Tx & Rx requests */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
- */
-
- /* Abort the SPI DMA tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- HAL_DMA_Abort(hspi->hdmatx);
- }
- /* Abort the SPI DMA rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- HAL_DMA_Abort(hspi->hdmarx);
- }
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI interrupt request.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None
- */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
- uint32_t itsource = hspi->Instance->CR2;
- uint32_t itflag = hspi->Instance->SR;
-
- /* SPI in mode Receiver ----------------------------------------------------*/
- if (((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
- {
- hspi->RxISR(hspi);
- return;
- }
-
- /* SPI in mode Transmitter -------------------------------------------------*/
- if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
- {
- hspi->TxISR(hspi);
- return;
- }
-
- /* SPI in Error Treatment --------------------------------------------------*/
- if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
- {
- /* SPI Overrun error interrupt occurred ----------------------------------*/
- if ((itflag & SPI_FLAG_OVR) != RESET)
- {
- if (hspi->State != HAL_SPI_STATE_BUSY_TX)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- return;
- }
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if ((itflag & SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Frame error interrupt occurred ------------------------------------*/
- if ((itflag & SPI_FLAG_FRE) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
- {
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
- /* Abort the SPI DMA Rx channel */
- if (hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
- }
- /* Abort the SPI DMA Tx channel */
- if (hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SPI_ErrorCallback(hspi);
- }
- }
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Half Transfer callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief SPI error callback.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred
- */
-}
-
-/**
- * @brief SPI Abort Complete callback.
- * @param hspi SPI handle.
- * @retval None
- */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
- (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPI handle state.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI state
- */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI handle state */
- return hspi->State;
-}
-
-/**
- * @brief Return the SPI error code.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI error code in bitmap format
- */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI ErrorCode */
- return hspi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief DMA SPI transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->TxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_TxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until RXNE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- else
- {
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
- {
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_RxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
- {
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
- tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- else
- {
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Rx/Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_TxRxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication error callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Stop the disable DMA transfer on SPI side */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmarx != NULL)
- {
- if (hspi->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Check if an Abort process is still ongoing */
- if (hspi->hdmatx != NULL)
- {
- if (hspi->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Check no error during Abort procedure */
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
- {
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- }
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- __HAL_SPI_CLEAR_FREFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in packing mode */
- if (hspi->RxXferCount > 1U)
- {
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2U;
- if (hspi->RxXferCount == 1U)
- {
- /* set fiforxthresold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- }
- /* Receive data in 8 Bit mode */
- else
- {
- *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
- hspi->RxXferCount--;
- }
-
- /* check end of the reception */
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- hspi->CRCSize--;
-
- /* check end of the reception */
- if (hspi->CRCSize == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in packing Bit mode */
- if (hspi->TxXferCount >= 2U)
- {
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2U;
- }
- /* Transmit data in 8 Bit mode */
- else
- {
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
- }
-
- /* check the end of the transmission */
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if (hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Set CRC Next Bit to send CRC */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if (hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- hspi->CRCSize--;
-
- if (hspi->CRCSize == 0U)
- {
- SPI_CloseRx_ISR(hspi);
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- if (hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
- uint32_t Timeout, uint32_t Tickstart)
-{
- while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo Fifo to check
- * @param State Fifo state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
- uint32_t Timeout, uint32_t Tickstart)
-{
- __IO uint8_t tmpreg;
-
- while ((hspi->Instance->SR & Fifo) != State)
- {
- if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
- {
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
-
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RX transaction complete.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi SPI handle
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Control if the TX fifo is empty */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Control if the RX fifo is empty */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the end of the RXTX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart = 0U;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->State = HAL_SPI_STATE_READY;
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the RX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the TX transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart = 0U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Disable TXE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- HAL_SPI_TxCpltCallback(hspi);
- }
-}
-
-/**
- * @brief Handle abort a Rx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t count;
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
- /* Check RXNEIE is disabled */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
-
- /* Control the BSY flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
- * @brief Handle abort a Tx or Rx/Tx transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t count;
-
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
- /* Check TXEIE is disabled */
- do
- {
- if (count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
- break;
- }
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
-
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
-
- hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
deleted file mode 100644
index 367b208cfd9..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_spi_ex.c
- * @author MCD Application Team
- * @brief Extended SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * SPI peripheral extended functionalities :
- * + IO operation functions
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SPIEx SPIEx
- * @brief SPI Extended HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
- * @{
- */
-#define SPI_FIFO_SIZE 4
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
- * @{
- */
-
-/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of extended functions to manage the SPI
- data transfers.
-
- (#) Rx data flush function:
- (++) HAL_SPIEx_FlushRxFifo()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Flush the RX fifo.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t tmpreg;
- uint8_t count = 0U;
- while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
- {
- count++;
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
- if (count == SPI_FIFO_SIZE)
- {
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
deleted file mode 100644
index d9c141b6801..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
+++ /dev/null
@@ -1,693 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_sram.c
- * @author MCD Application Team
- * @brief SRAM HAL module driver.
- * This file provides a generic firmware to drive SRAM memories
- * mounted as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control SRAM memories. It uses the FMC layer functions to interface
- with SRAM devices.
- The following sequence should be followed to configure the FMC to interface
- with SRAM/PSRAM memories:
-
- (#) Declare a SRAM_HandleTypeDef handle structure, for example:
- SRAM_HandleTypeDef hsram; and:
-
- (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
- values of the structure member.
-
- (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
- base register instance for NOR or SRAM device
-
- (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
- base register instance for NOR or SRAM extended mode
-
- (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
- mode timings; for example:
- FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
- and fill its fields with the allowed values of the structure member.
-
- (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
- performs the following sequence:
-
- (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
- (##) Control register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Init()
- (##) Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Timing_Init()
- (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
- FMC_NORSRAM_Extended_Timing_Init()
- (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
-
- (#) At this stage you can perform read/write accesses from/to the memory connected
- to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
- following APIs:
- (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
- (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-
- (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
- HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
-
- (#) You can continuously monitor the SRAM device HAL state by calling the function
- HAL_SRAM_GetState()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-
-/** @defgroup SRAM SRAM
- * @brief SRAM HAL module driver
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
- @verbatim
- ==============================================================================
- ##### SRAM Initialization and de_initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to initialize/de-initialize
- the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Performs the SRAM device initialization sequence
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param Timing Pointer to SRAM control timing structure
- * @param ExtTiming Pointer to SRAM extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the SRAM handle parameter */
- if(hsram == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hsram->State == HAL_SRAM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsram->Lock = HAL_UNLOCKED;
-
- /* Initialize the low level hardware (MSP) */
- HAL_SRAM_MspInit(hsram);
- }
-
- /* Initialize SRAM control Interface */
- FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
-
- /* Initialize SRAM timing Interface */
- FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
-
- /* Initialize SRAM extended mode timing Interface */
- FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
-
- return HAL_OK;
-}
-
-/**
- * @brief Performs the SRAM device De-initialization sequence.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_SRAM_MspDeInit(hsram);
-
- /* Configure the SRAM registers with their reset values */
- FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
-
- hsram->State = HAL_SRAM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief SRAM MSP Init.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SRAM MSP DeInit.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete error callback.
- * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### SRAM Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to read start address
- * @param pDstBuffer Pointer to destination buffer
- * @param BufferSize Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint8_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to write start address
- * @param pSrcBuffer Pointer to source buffer to write
- * @param BufferSize Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint8_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to read start address
- * @param pDstBuffer Pointer to destination buffer
- * @param BufferSize Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint16_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to write start address
- * @param pSrcBuffer Pointer to source buffer to write
- * @param BufferSize Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint16_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to read start address
- * @param pDstBuffer Pointer to destination buffer
- * @param BufferSize Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint32_t *)pAddress;
- pDstBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to write start address
- * @param pSrcBuffer Pointer to source buffer to write
- * @param BufferSize Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint32_t *)pAddress = *pSrcBuffer;
- pSrcBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to read start address
- * @param pDstBuffer Pointer to destination buffer
- * @param BufferSize Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress Pointer to write start address
- * @param pSrcBuffer Pointer to source buffer to write
- * @param BufferSize Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the SRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically SRAM write operation.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Enable write operation */
- FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically SRAM write operation.
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Disable write operation */
- FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the SRAM controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the SRAM controller state
- * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL state
- */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
-{
- return hsram->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-/**
- * @}
- */
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
deleted file mode 100644
index 0c51e849216..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
+++ /dev/null
@@ -1,5492 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tim.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
- @verbatim
- ==============================================================================
- ##### TIMER Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
- (#) The DMA Burst is managed with the two following functions:
- HAL_TIM_DMABurst_WriteStart()
- HAL_TIM_DMABurst_ReadStart()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
- (+) De-initialize the TIM base.
- (+) Start the Time Base.
- (+) Stop the Time Base.
- (+) Start the Time Base and enable interrupt.
- (+) Stop the Time Base and disable interrupt.
- (+) Start the Time Base and enable DMA transfer.
- (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Base peripheral
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Base MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Base MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Starts the TIM Base generation.
- * @param htim TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation.
- * @param htim TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in interrupt mode.
- * @param htim TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in DMA mode.
- * @param htim TIM handle
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to peripheral.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in DMA mode.
- * @param htim TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Time Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the Time Output Compare.
- (+) Stop the Time Output Compare.
- (+) Start the Time Output Compare and enable interrupt.
- (+) Stop the Time Output Compare and disable interrupt.
- (+) Start the Time Output Compare and enable DMA transfer.
- (+) Stop the Time Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Output Compare MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM OC handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Time PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
- (+) De-initialize the TIM PWM.
- (+) Start the Time PWM.
- (+) Stop the Time PWM.
- (+) Start the Time PWM and enable interrupt.
- (+) Stop the Time PWM and disable interrupt.
- (+) Start the Time PWM and enable DMA transfer.
- (+) Stop the Time PWM and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM PWM MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim TIM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim TIM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim TIM handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim TIM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### Time Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the Time Input Capture.
- (+) Stop the Time Input Capture.
- (+) Start the Time Input Capture and enable interrupt.
- (+) Stop the Time Input Capture and disable interrupt.
- (+) Start the Time Input Capture and enable DMA transfer.
- (+) Stop the Time Input Capture and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Input Capture MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim TIM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim TIM Input Capture handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Time One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
- (+) De-initialize the TIM One Pulse.
- (+) Start the Time One Pulse.
- (+) Stop the Time One Pulse.
- (+) Start the Time One Pulse and enable interrupt.
- (+) Stop the Time One Pulse and disable interrupt.
- (+) Start the Time One Pulse and enable DMA transfer.
- (+) Stop the Time One Pulse and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM OnePulse handle
- * @param OnePulseMode Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM One Pulse
- * @param htim TIM One Pulse handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM One Pulse MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### Time Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder.
- (+) Start the Time Encoder.
- (+) Stop the Time Encoder.
- (+) Start the Time Encoder and enable interrupt.
- (+) Stop the Time Encoder and disable interrupt.
- (+) Start the Time Encoder and enable DMA transfer.
- (+) Stop the Time Encoder and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
-{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim TIM Encoder handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Encoder Interface MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2U */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1U */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2U */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2U */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1: The destination Buffer address for IC1.
- * @param pData2: The destination Buffer address for IC2.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_ALL:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- default:
- break;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim TIM Encoder Interface handle
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1U */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2U */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2U */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides Timer IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- /* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
- {
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
- HAL_TIM_PeriodElapsedCallback(htim);
- }
- }
- /* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
- HAL_TIMEx_BreakCallback(htim);
- }
- }
-
-#if defined(TIM_FLAG_BREAK2)
- /* TIM Break input 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- HAL_TIMEx_Break2Callback(htim);
- }
- }
-#endif
-
- /* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
- HAL_TIM_TriggerCallback(htim);
- }
- }
- /* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
- HAL_TIMEx_CommutationCallback(htim);
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim TIM IC handle
- * @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (Channel == TIM_CHANNEL_1)
- {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
- }
- else if (Channel == TIM_CHANNEL_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
- __HAL_LOCK(htim);
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim TIM One Pulse handle
- * @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
-{
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if(OutputChannel != InputChannel)
- {
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Ouput compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- }
- break;
- default:
- break;
- }
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
-{
-return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((BurstBuffer == 0U ) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
- }
- break;
- default:
- break;
- }
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
-{
-return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @param DataLength Data length. This parameter can be one value
- * between 1 and 0xFFFF.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((BurstBuffer == 0U ) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
- }
- break;
- default:
- break;
- }
-
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim TIM handle
- * @param BurstRequestSrc TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Generate a software event
- * @param htim TIM handle
- * @param EventSource specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
- * @retval HAL status
- * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
- * devices
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2U */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2U */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3U */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3U */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4U */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4U */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim TIM handle
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource)
- {
- case TIM_CLOCKSOURCE_INTERNAL:
- {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE1:
- {
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE2:
- {
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- }
- break;
-
- case TIM_CLOCKSOURCE_TI1:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- }
- break;
- case TIM_CLOCKSOURCE_TI2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- }
- break;
- case TIM_CLOCKSOURCE_TI1ED:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- }
- break;
- case TIM_CLOCKSOURCE_ITR0:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
- }
- break;
- case TIM_CLOCKSOURCE_ITR1:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
- case TIM_CLOCKSOURCE_ITR2:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports external clock mode 1U */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
- }
- break;
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim TIM handle.
- * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim TIM handle.
- * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim TIM handle.
- * @param Channel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0U;
-
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-
-}
-/**
- * @brief Output Compare callback in non blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-/**
- * @brief Input Capture callback in non blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timer error callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base state
- * @param htim TIM Base handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC state
- * @param htim TIM Ouput Compare handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM state
- * @param htim TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture state
- * @param htim TIM IC handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode state
- * @param htim TIM OPM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode state
- * @param htim TIM Encoder handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Private_Functions TIM_Private_Functions
- * @{
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_ErrorCallback(htim);
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_IC_CaptureCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_TriggerCallback(htim);
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx TIM periheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1 = 0U;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Time Ouput Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Reset the Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2N;
-#endif
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
-#endif
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
-#endif
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
- }
- break;
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4U);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12U);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
- * @param ExtTRGFilter External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- uint32_t tmpsmcr = 0U;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
deleted file mode 100644
index aca99ccaceb..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
+++ /dev/null
@@ -1,2802 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tim_ex.c
- * @author MCD Application Team
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
- * + Time OCRef clear configuration
- * + Timer remapping capabilities configuration
- @verbatim
- ==============================================================================
- ##### TIMER Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
- interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-
-#define BDTR_BKF_SHIFT (16U)
-#define BDTR_BK2F_SHIFT (20U)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config);
-
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
- * @{
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Hall Sensor configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101U */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1U, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor handle
- * @param pData The destination Buffer address.
- * @param Length The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel for Capture 1U*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare.
- (+) Stop the Complementary Output Compare.
- (+) Start the Complementary Output Compare and enable interrupts.
- (+) Stop the Complementary Output Compare and disable interrupts.
- (+) Start the Complementary Output Compare and enable DMA transfers.
- (+) Stop the Complementary Output Compare and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM OC handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim TIM Output Compare handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim TIM handle
- * @param Channel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData The source Buffer address.
- * @param Length The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U ) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim TIM handle
- * @param Channel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
- * output.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
- }
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure Output channels for OC and PWM mode.
-
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
- (+) Configure timer remapping capabilities.
- (+) Enable or disable channel grouping
-
-@endverbatim
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation Interrupt Request */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim TIM handle
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
- * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef* sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 5 in Output Compare */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 6 in Output Compare */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM PWM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be configured
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
- * STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef* sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim TIM handle.
- * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef * sMasterConfig)
-{
- uint32_t tmpcr2;
- uint32_t tmpsmcr;
-
- /* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Configures the TIM in master mode.
- * @param htim TIM handle.
- * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Reset the MMS Bits */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Reset the MSM Bit */
- htim->Instance->SMCR &= ~TIM_SMCR_MSM;
- /* Set or Reset the MSM Bit */
- htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim TIM handle
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
- structure that contains the BDTR Register configuration information
- for the TIM peripheral.
- * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
- STM32F398xx and STM32F303x8 two break inputs can be configured.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
-{
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
-
- if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
- {
- assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
- assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
-
- /* Set the BREAK2 input related BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
- }
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim TIM handle
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
-{
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F334x8)
-#if defined(STM32F303xE) || defined(STM32F398xx)
-/**
- * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap1: specifies the first TIM remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
- * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
- * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
- * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
- * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
- * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
- * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
- * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
- * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
- * @param Remap2: specifies the second TIMremapping source (if any).
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
- * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
- * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
- * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
- * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
- * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
- * @arg TIM_TIM16_NONE: Non significant value for TIM16
- * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
- * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
- * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
- * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
- * @retval HAL status
- */
-#elif defined(STM32F303xC) || defined(STM32F358xx)
-/**
- * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap1: specifies the first TIM remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
- * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
- * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
- * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
- * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
- * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
- * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
- * @param Remap2: specifies the second TIMremapping source (if any).
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
- * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
- * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
- * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
- * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
- * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
- * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
- * @retval HAL status
- */
-#else /* STM32F334x8 */
-/**
- * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap1: specifies the first TIM remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
- * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
- * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
- * @param Remap2: specifies the second TIMremapping source (if any).
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
- * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
- * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
- * @retval HAL status
- */
-#endif /* STM32F303xE || STM32F398xx || */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
-{
- __HAL_LOCK(htim);
-
- /* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap1));
- assert_param(IS_TIM_REMAP2(Remap2));
-
- /* Set the Timer remapping configuration */
- htim->Instance->OR = Remap1 | Remap2;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || STM32F334x8 */
-
-
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
-#if defined(STM32F302xE) || \
- defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the TIM1 and TIM16 Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap specifies the TIM remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
- * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
- * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
- * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
- * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
- * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
- * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
- * @retval HAL status
- */
-#else /* STM32F373xC || STM32F378xx */
-/**
- * @brief Configures the TIM2 and TIM14 Remapping input capabilities.
- * @param htim TIM handle.
- * @param Remap specifies the TIM remapping source.
- * This parameter can be one of the following values:
- * STM32F373xC, STM32F378xx:
- * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
- * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
- * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
- * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
- * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
- * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
- * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
- * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
- * @retval HAL status
- */
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
- __HAL_LOCK(htim);
-
- /* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap));
-
- /* Set the Timer remapping configuration */
- htim->Instance->OR = Remap;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F302xE || */
- /* STM32F302xC || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
- /* STM32F373xC || STM32F378xx */
-
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Group channel 5 and channel 1, 2 or 3
- * @param htim TIM handle.
- * @param Channels specifies the reference signal(s) the OC5REF is combined with.
- * This parameter can be any combination of the following values:
- * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
- * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
- * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
- * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
-{
- /* Check parameters */
- assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_GROUPCH5(Channels));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Clear GC5Cx bit fields */
- htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
-
- /* Set GC5Cx bit fields */
- htim->Instance->CCR5 |= Channels;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_Channel_5: TIM Channel 5
- * @arg TIM_Channel_6: TIM Channel 6
- * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
- * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
- * @retval None
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Clear the OCREF clear selection bit */
- tmpsmcr &= ~TIM_SMCR_OCCS;
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_OCREFCLR:
- {
- /* Clear the OCREF clear selection bit */
- htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- /* Set the OCREF clear selection bit */
- htim->Instance->SMCR |= TIM_SMCR_OCCS;
- }
- break;
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2U */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2U */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3U */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3U */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4U */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4U */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- case TIM_CHANNEL_5:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
- }
- }
- break;
- case TIM_CHANNEL_6:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1U */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
- }
- }
- break;
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
- * @brief Extension Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extended TIM callback functions:
- (+) Timer Commutation callback
- (+) Timer Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extended Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface state
- * @param htim TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Private_Functions
- * @{
- */
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIMEx_CommutationCallback(htim);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
- uint32_t tmp = 0U;
-
- tmp = TIM_CCER_CC1NE << Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/**
- * @brief Timer Ouput Compare 5 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Timer Ouput Compare 6 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
- /* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
- /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
deleted file mode 100644
index 8f288b7cfa2..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_timebase_rtc_alarm_template.c
- * @brief HAL time base based on the hardware RTC_ALARM Template.
- *
- * This file override the native HAL time base functions (defined as weak)
- * to use the RTC ALARM for time base generation:
- * + Intializes the RTC peripheral to increment the seconds registers each 1ms
- * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
- * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
- * + HSE (default), LSE or LSI can be selected as RTC clock source
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This file must be copied to the application folder and modified as follows:
- (#) Rename it to 'stm32f3xx_hal_timebase_rtc_alarm.c'
- (#) Add this file and the RTC HAL drivers to your project and uncomment
- HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
-
- [..]
- (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
- The wake up capability of the RTC may be intrusive in case of prior low power mode
- configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
- (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
- requiring low power modes
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Uncomment the line below to select the appropriate RTC Clock source for your application:
- + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
- + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
- precision.
- + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
- precision.
- */
-#define RTC_CLOCK_SOURCE_HSE
-/* #define RTC_CLOCK_SOURCE_LSE */
-/* #define RTC_CLOCK_SOURCE_LSI */
-
-#if defined(RTC_CLOCK_SOURCE_HSE)
- #define RTC_ASYNCH_PREDIV 49U
- #define RTC_SYNCH_PREDIV 4U
-#elif defined(RTC_CLOCK_SOURCE_LSE)
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 31U
-#else /*RTC_CLOCK_SOURCE_LSI */
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 39U
-#endif /* RTC_CLOCK_SOURCE_HSE */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-RTC_HandleTypeDef hRTC_Handle;
-/* Private function prototypes -----------------------------------------------*/
-void RTC_Alarm_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief This function configures the RTC_ALARMA as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
- __IO uint32_t counter = 0U;
-
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
-#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
-#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
-#else
-#error Please select the RTC Clock source
-#endif /* RTC_CLOCK_SOURCE_LSE */
-
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
- {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
- {
- /* Enable RTC Clock */
- __HAL_RCC_RTC_ENABLE();
- /* The time base should be 1ms
- Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
- HSE/32 as RTC clock and HSE 8MHz
- Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
- = 1ms
- LSE as RTC clock
- Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz
- = ~1ms
- LSI as RTC clock
- Time base = ((39U + 1U) * (0U + 1U)) / 40KHz
- = 1ms
- */
- hRTC_Handle.Instance = RTC;
- hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
- hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
- hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
- hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
- hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
- hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
- HAL_RTC_Init(&hRTC_Handle);
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
-
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
-
- counter = 0U;
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
- {
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
-
- hRTC_Handle.Instance->ALRMAR = 0x01U;
-
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Check if the Initialization mode is set */
- if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
- counter = 0U;
- while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
- }
- hRTC_Handle.Instance->DR = 0U;
- hRTC_Handle.Instance->TR = 0U;
-
- hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
- return HAL_OK;
- }
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note Disable the tick increment by disabling RTC ALARM interrupt.
- * @param None
- * @retval None
- */
-void HAL_SuspendTick(void)
-{
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- /* Disable RTC ALARM update Interrupt */
- __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note Enable the tick increment by Enabling RTC ALARM interrupt.
- * @param None
- * @retval None
- */
-void HAL_ResumeTick(void)
-{
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- /* Enable RTC ALARM Update interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-}
-
-/**
- * @brief ALARM A Event Callback in non blocking mode
- * @note This function is called when RTC_ALARM interrupt took place, inside
- * RTC_Alarm_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
- * a global variable "uwTick" used as application time base.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- __IO uint32_t counter = 0U;
-
- HAL_IncTick();
-
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set the Initialization mode */
- hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
- while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
- {
- break;
- }
- }
-
- hrtc->Instance->DR = 0U;
- hrtc->Instance->TR = 0U;
-
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
- * @brief This function handles RTC ALARM interrupt request.
- * @param None
- * @retval None
- */
-void RTC_Alarm_IRQHandler(void)
-{
- HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
deleted file mode 100644
index c823c9f84ee..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_timebase_rtc_wakeup_template.c
- * @brief HAL time base based on the hardware RTC_WAKEUP Template.
- *
- * This file overrides the native HAL time base functions (defined as weak)
- * to use the RTC WAKEUP for the time base generation:
- * + Intializes the RTC peripheral and configures the wakeup timer to be
- * incremented each 1ms
- * + The wakeup feature is configured to assert an interrupt each 1ms
- * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
- * + HSE (default), LSE or LSI can be selected as RTC clock source
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This file must be copied to the application folder and modified as follows:
- (#) Rename it to 'stm32f3xx_hal_timebase_rtc_wakeup.c'
- (#) Add this file and the RTC HAL drivers to your project and uncomment
- HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
-
- [..]
- (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
- The wake up capability of the RTC may be intrusive in case of prior low power mode
- configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
- (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
- requiring low power modes
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Uncomment the line below to select the appropriate RTC Clock source for your application:
- + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
- + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
- precision.
- + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
- precision.
- */
-#define RTC_CLOCK_SOURCE_HSE
-/* #define RTC_CLOCK_SOURCE_LSE */
-/* #define RTC_CLOCK_SOURCE_LSI */
-
-#if defined(RTC_CLOCK_SOURCE_HSE)
- #define RTC_ASYNCH_PREDIV 49U
- #define RTC_SYNCH_PREDIV 4U
-#elif define(RTC_CLOCK_SOURCE_LSE)
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 31U
-#else /* RTC_CLOCK_SOURCE_LSI */
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 39U
-#endif /* RTC_CLOCK_SOURCE_HSE */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-RTC_HandleTypeDef hRTC_Handle;
-
-/* Private function prototypes -----------------------------------------------*/
-void RTC_WKUP_IRQHandler(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief This function configures the RTC_WKUP as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
- = 1ms
- * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
- = 1 ms
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
- __IO uint32_t counter = 0U;
-
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
-#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
-#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
-#else
-#error Please select the RTC Clock source
-#endif /* RTC_CLOCK_SOURCE_LSE */
-
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
- {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
- {
- /* Enable RTC Clock */
- __HAL_RCC_RTC_ENABLE();
- /* The time base should be 1ms
- Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK
- HSE/32 as RTC clock and HSE 8MHz
- Time base = ((49U + 1U) * (4U + 1U)) / 250kHz
- = 1ms
- LSE as RTC clock
- Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz
- = ~1ms
- LSI as RTC clock
- Time base = ((39U + 1U) * (0U + 1U)) / 40Khz
- = 1ms
- */
- hRTC_Handle.Instance = RTC;
- hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
- hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
- hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
- hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
- hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
- hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
- HAL_RTC_Init(&hRTC_Handle);
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
-
- /* Disable the Wake-up Timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
-
- /* Wait till RTC WUTWF flag is set */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
- {
- if(counter++ == (SystemCoreClock /48U))
- {
- return HAL_ERROR;
- }
- }
-
- /* Clear PWR wake up Flag */
- __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
-
- /* Clear RTC Wake Up timer Flag */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
-
- /* Configure the Wake-up Timer counter */
- hRTC_Handle.Instance->WUTR = 0U;
-
- /* Clear the Wake-up Timer clock source bits in CR register */
- hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
-
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
- /* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
-
- /* Enable the Wake-up Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
- return HAL_OK;
- }
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note Disable the tick increment by disabling RTC_WKUP interrupt.
- * @param None
- * @retval None
- */
-void HAL_SuspendTick(void)
-{
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- /* Disable WAKE UP TIMER Interrupt */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note Enable the tick increment by Enabling RTC_WKUP interrupt.
- * @param None
- * @retval None
- */
-void HAL_ResumeTick(void)
-{
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- /* Enable WAKE UP TIMER interrupt */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-}
-
-/**
- * @brief Wake Up Timer Event Callback in non blocking mode
- * @note This function is called when RTC_WKUP interrupt took place, inside
- * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
- * a global variable "uwTick" used as application time base.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
- HAL_IncTick();
-}
-
-/**
- * @brief This function handles WAKE UP TIMER interrupt request.
- * @param None
- * @retval None
- */
-void RTC_WKUP_IRQHandler(void)
-{
- HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c
deleted file mode 100644
index e33dd82ad75..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_timebase_tim_template.c
- * @brief HAL time base based on the hardware TIM Template.
- *
- * This file override the native HAL time base functions (defined as weak)
- * the TIM time base:
- * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
- * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL_TimeBase_TIM
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_HandleTypeDef TimHandle;
-/* Private function prototypes -----------------------------------------------*/
-void TIM6_DAC_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief This function configures the TIM6 as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
- RCC_ClkInitTypeDef clkconfig;
- uint32_t uwTimclock, uwAPB1Prescaler = 0U;
- uint32_t uwPrescalerValue = 0U;
- uint32_t pFLatency;
-
- /*Configure the TIM6 IRQ priority */
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
-
- /* Enable the TIM6 global Interrupt */
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
-
- /* Enable TIM6 clock */
- __HAL_RCC_TIM6_CLK_ENABLE();
-
- /* Get clock configuration */
- HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
- /* Get APB1 prescaler */
- uwAPB1Prescaler = clkconfig.APB1CLKDivider;
-
- /* Compute TIM6 clock */
- if (uwAPB1Prescaler == RCC_HCLK_DIV1)
- {
- uwTimclock = HAL_RCC_GetPCLK1Freq();
- }
- else
- {
- uwTimclock = 2U*HAL_RCC_GetPCLK1Freq();
- }
-
- /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
- uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
-
- /* Initialize TIM6 */
- TimHandle.Instance = TIM6;
-
- /* Initialize TIMx peripheral as follow:
- + Period = [(TIM6CLK/1000U) - 1]. to have a (1U/1000U) s time base.
- + Prescaler = (uwTimclock/1000000U - 1U) to have a 1MHz counter clock.
- + ClockDivision = 0
- + Counter direction = Up
- */
- TimHandle.Init.Period = (1000000U / 1000U) - 1U;
- TimHandle.Init.Prescaler = uwPrescalerValue;
- TimHandle.Init.ClockDivision = 0U;
- TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
- {
- /* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
- }
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note Disable the tick increment by disabling TIM6 update interrupt.
- * @param None
- * @retval None
- */
-void HAL_SuspendTick(void)
-{
- /* Disable TIM6 update Interrupt */
- __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note Enable the tick increment by Enabling TIM6 update interrupt.
- * @param None
- * @retval None
- */
-void HAL_ResumeTick(void)
-{
- /* Enable TIM6 Update interrupt */
- __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @note This function is called when TIM6 interrupt took place, inside
- * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
- * a global variable "uwTick" used as application time base.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- HAL_IncTick();
-}
-
-/**
- * @brief This function handles TIM interrupt request.
- * @param None
- * @retval None
- */
-void TIM6_DAC_IRQHandler(void)
-{
- HAL_TIM_IRQHandler(&TimHandle);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
deleted file mode 100644
index 62704a0e501..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
+++ /dev/null
@@ -1,873 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_tsc.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Touch Sensing Controller (TSC) peripheral:
- * + Initialization and De-initialization
- * + Channel IOs, Shield IOs and Sampling IOs configuration
- * + Start and Stop an acquisition
- * + Read acquisition result
- * + Interrupts and flags management
- *
- @verbatim
-================================================================================
- ##### TSC specific features #####
-================================================================================
- [..]
- (#) Proven and robust surface charge transfer acquisition principle
-
- (#) Supports up to 3 capacitive sensing channels per group
-
- (#) Capacitive sensing channels can be acquired in parallel offering a very good
- response time
-
- (#) Spread spectrum feature to improve system robustness in noisy environments
-
- (#) Full hardware management of the charge transfer acquisition sequence
-
- (#) Programmable charge transfer frequency
-
- (#) Programmable sampling capacitor I/O pin
-
- (#) Programmable channel I/O pin
-
- (#) Programmable max count value to avoid long acquisition when a channel is faulty
-
- (#) Dedicated end of acquisition and max count error flags with interrupt capability
-
- (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
- components
-
- (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
-
-
- ##### How to use this driver #####
-================================================================================
- [..]
- (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
-
- (#) GPIO pins configuration
- (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
- (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
- and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
- using HAL_GPIO_Init() function.
-
- (#) Interrupts configuration
- (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
- and HAL_NVIC_EnableIRQ() and function.
-
- (#) TSC configuration
- (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
-
-
- *** Acquisition sequence ***
- ===================================
- [..]
- (+) Discharge all IOs using HAL_TSC_IODischarge() function.
- (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
- of the sampling capacitor and electrodes design.
- (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
- (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
- If the synchronized mode is selected, the acquisition will start as soon as the signal
- is received on the synchro pin.
- (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
- HAL_TSC_GetState() function or using WFI instruction for example.
- (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
- (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*
- Addition Table:
- Table 1. IOs for the STM32F3xx devices
- +--------------------------------+
- | IOs | TSC functions |
- |--------------|-----------------|
- | PA0 (AF) | TSC_G1_IO1 |
- | PA1 (AF) | TSC_G1_IO2 |
- | PA2 (AF) | TSC_G1_IO3 |
- | PA3 (AF) | TSC_G1_IO4 |
- |--------------|-----------------|
- | PA4 (AF) | TSC_G2_IO1 |
- | PA5 (AF) | TSC_G2_IO2 |
- | PA6 (AF) | TSC_G2_IO3 |
- | PA7 (AF) | TSC_G2_IO4 |
- |--------------|-----------------|
- | PC5 (AF) | TSC_G3_IO1 |
- | PB0 (AF) | TSC_G3_IO2 |
- | PB1 (AF) | TSC_G3_IO3 |
- | PB2 (AF) | TSC_G3_IO4 |
- |--------------|-----------------|
- | PA9 (AF) | TSC_G4_IO1 |
- | PA10 (AF) | TSC_G4_IO2 |
- | PA13 (AF) | TSC_G4_IO3 |
- | PA14 (AF) | TSC_G4_IO4 |
- |--------------|-----------------|
- | PB3 (AF) | TSC_G5_IO1 |
- | PB4 (AF) | TSC_G5_IO2 |
- | PB6 (AF) | TSC_G5_IO3 |
- | PB7 (AF) | TSC_G5_IO4 |
- |--------------|-----------------|
- | PB11 (AF) | TSC_G6_IO1 |
- | PB12 (AF) | TSC_G6_IO2 |
- | PB13 (AF) | TSC_G6_IO3 |
- | PB14 (AF) | TSC_G6_IO4 |
- |--------------|-----------------|
- | PE2 (AF) | TSC_G7_IO1 |
- | PE3 (AF) | TSC_G7_IO2 |
- | PE4 (AF) | TSC_G7_IO3 |
- | PE5 (AF) | TSC_G7_IO4 |
- |--------------|-----------------|
- | PD12 (AF) | TSC_G8_IO1 |
- | PD13 (AF) | TSC_G8_IO2 |
- | PD14 (AF) | TSC_G8_IO3 |
- | PD15 (AF) | TSC_G8_IO4 |
- |--------------|-----------------|
- | PB8 (AF) | TSC_SYNC |
- | PB10 (AF) | |
- +--------------------------------+
- TSC peripheral alternate functions are mapped on AF3.
-
-*/
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TSC TSC
- * @brief HAL TSC module driver
- * @{
- */
-
-#ifdef HAL_TSC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t TSC_extract_groups(uint32_t iomask);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TSC_Exported_Functions Exported Functions
- * @{
- */
-
-/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the TSC.
- (+) De-initialize the TSC.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the TSC peripheral according to the specified parameters
- * in the TSC_InitTypeDef structure and initialize the associated handle.
- * @param htsc TSC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
-{
- /* Check TSC handle allocation */
- if (htsc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
- assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
- assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
- assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
- assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
- assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
- assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
- assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
- assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
- assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
- assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-
- if(htsc->State == HAL_TSC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htsc->Lock = HAL_UNLOCKED;
- }
-
- /* Initialize the TSC state */
- htsc->State = HAL_TSC_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_TSC_MspInit(htsc);
-
- /*--------------------------------------------------------------------------*/
- /* Set TSC parameters */
-
- /* Enable TSC */
- htsc->Instance->CR = TSC_CR_TSCE;
-
- /* Set all functions */
- htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
- htsc->Init.CTPulseLowLength |
- (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
- htsc->Init.SpreadSpectrumPrescaler |
- htsc->Init.PulseGeneratorPrescaler |
- htsc->Init.MaxCountValue |
- htsc->Init.SynchroPinPolarity |
- htsc->Init.AcquisitionMode);
-
- /* Spread spectrum */
- if (htsc->Init.SpreadSpectrum == ENABLE)
- {
- htsc->Instance->CR |= TSC_CR_SSE;
- }
-
- /* Disable Schmitt trigger hysteresis on all used TSC IOs */
- htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
-
- /* Set channel and shield IOs */
- htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
-
- /* Set sampling IOs */
- htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
-
- /* Set the groups to be acquired */
- htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
-
- /* Disable interrupts */
- htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
-
- /* Clear flags */
- htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
-
- /*--------------------------------------------------------------------------*/
-
- /* Initialize the TSC state */
- htsc->State = HAL_TSC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitialize the TSC peripheral registers to their default reset values.
- * @param htsc TSC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
-{
- /* Check TSC handle allocation */
- if (htsc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_TSC_MspDeInit(htsc);
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_RESET;
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the TSC MSP.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TSC_MspInit could be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitialize the TSC MSP.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TSC_MspDeInit could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO Operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start acquisition in polling mode.
- (+) Start acquisition in interrupt mode.
- (+) Stop conversion in polling mode.
- (+) Stop conversion in interrupt mode.
- (+) Poll for acquisition completed.
- (+) Get group acquisition status.
- (+) Get group acquisition value.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the acquisition.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_BUSY;
-
- /* Clear interrupts */
- __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
-
- /* Clear flags */
- __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
- /* Set touch sensing IOs not acquired to the specified IODefaultMode */
- if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
- {
- __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
- }
- else
- {
- __HAL_TSC_SET_IODEF_INFLOAT(htsc);
- }
-
- /* Launch the acquisition */
- __HAL_TSC_START_ACQ(htsc);
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start the acquisition in interrupt mode.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_BUSY;
-
- /* Enable end of acquisition interrupt */
- __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
-
- /* Enable max count error interrupt (optional) */
- if (htsc->Init.MaxCountInterrupt == ENABLE)
- {
- __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
- }
- else
- {
- __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
- }
-
- /* Clear flags */
- __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
- /* Set touch sensing IOs not acquired to the specified IODefaultMode */
- if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
- {
- __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
- }
- else
- {
- __HAL_TSC_SET_IODEF_INFLOAT(htsc);
- }
-
- /* Launch the acquisition */
- __HAL_TSC_START_ACQ(htsc);
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the acquisition previously launched in polling mode.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Stop the acquisition */
- __HAL_TSC_STOP_ACQ(htsc);
-
- /* Set touch sensing IOs in low power mode (output push-pull) */
- __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
- /* Clear flags */
- __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the acquisition previously launched in interrupt mode.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Stop the acquisition */
- __HAL_TSC_STOP_ACQ(htsc);
-
- /* Set touch sensing IOs in low power mode (output push-pull) */
- __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
- /* Disable interrupts */
- __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
-
- /* Clear flags */
- __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Start acquisition and wait until completion.
- * @note There is no need of a timeout parameter as the max count error is already
- * managed by the TSC peripheral.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Check end of acquisition */
- while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
- {
- /* The timeout (max count error) is managed by the TSC peripheral itself. */
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the acquisition status for a group.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @param gx_index Index of the group
- * @retval Group status
- */
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_TSC_GROUP_INDEX(gx_index));
-
- /* Return the group status */
- return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
-}
-
-/**
- * @brief Get the acquisition measure for a group.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @param gx_index Index of the group
- * @retval Acquisition measure
- */
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_TSC_GROUP_INDEX(gx_index));
-
- /* Return the group acquisition counter */
- return htsc->Instance->IOGXCR[gx_index];
-}
-
-/**
- * @}
- */
-
-/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure TSC IOs
- (+) Discharge TSC IOs
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configure TSC IOs.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @param config pointer to the configuration structure.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Stop acquisition */
- __HAL_TSC_STOP_ACQ(htsc);
-
- /* Disable Schmitt trigger hysteresis on all used TSC IOs */
- htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
-
- /* Set channel and shield IOs */
- htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
-
- /* Set sampling IOs */
- htsc->Instance->IOSCR = config->SamplingIOs;
-
- /* Set groups to be acquired */
- htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Discharge TSC IOs.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @param choice enable or disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- if (choice == ENABLE)
- {
- __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
- }
- else
- {
- __HAL_TSC_SET_IODEF_INFLOAT(htsc);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- /* Return the group acquisition counter */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Get TSC state.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TSC handle state.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL state
- */
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- if (htsc->State == HAL_TSC_STATE_BUSY)
- {
- /* Check end of acquisition flag */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
- {
- /* Check max count error flag */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
- {
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_ERROR;
- }
- else
- {
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_READY;
- }
- }
- }
-
- /* Return TSC state */
- return htsc->State;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
- * @brief Handle TSC interrupt request.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Check if the end of acquisition occurred */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
- {
- /* Clear EOA flag */
- __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
- }
-
- /* Check if max count error occurred */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
- {
- /* Clear MCE flag */
- __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_ERROR;
- /* Conversion completed callback */
- HAL_TSC_ErrorCallback(htsc);
- }
- else
- {
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_READY;
- /* Conversion completed callback */
- HAL_TSC_ConvCpltCallback(htsc);
- }
-}
-
-/**
- * @brief Acquisition completed callback in non-blocking mode.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TSC_ConvCpltCallback could be implemented in the user file.
- */
-}
-
-/**
- * @brief Error callback in non-blocking mode.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TSC_ErrorCallback could be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TSC_Private_Functions Private Functions
- * @{
- */
-
-/**
- * @brief Utility function used to set the acquired groups mask.
- * @param iomask Channels IOs mask
- * @retval Acquired groups mask
- */
-static uint32_t TSC_extract_groups(uint32_t iomask)
-{
- uint32_t groups = 0U;
- uint32_t idx;
-
- for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
- {
- if ((iomask & (0x0FU << (idx * 4U))) != RESET)
- {
- groups |= (1U << idx);
- }
- }
-
- return groups;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
deleted file mode 100644
index 62f4dd9bf9f..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
+++ /dev/null
@@ -1,2795 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_uart.c
- * @author MCD Application Team
- * @brief UART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
- (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) UART pins configuration:
- (+++) Enable the clock for the UART GPIOs.
- (+++) Configure these UART pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
- and HAL_UART_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) UART interrupts handling:
- -@@- The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) are managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
- (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
- and HAL_UART_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
-
- (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
- in the huart handle AdvancedInit structure.
-
- (#) For the UART asynchronous mode, initialize the UART registers by calling
- the HAL_UART_Init() API.
-
- (#) For the UART Half duplex mode, initialize the UART registers by calling
- the HAL_HalfDuplex_Init() API.
-
- (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
- by calling the HAL_LIN_Init() API.
-
- (#) For the UART Multiprocessor mode, initialize the UART registers
- by calling the HAL_MultiProcessor_Init() API.
-
- (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
- [..]
- (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
- also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by
- calling the customized HAL_UART_MspInit() API.
-
- [..]
- [..] Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_UART_DMAPause()
- (+) Resume the DMA Transfer using HAL_UART_DMAResume()
- (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
- *** UART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in UART HAL driver.
-
- (+) __HAL_UART_ENABLE: Enable the UART peripheral
- (+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
- (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-
- [..]
- (@) You can refer to the UART HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UART UART
- * @brief UART HAL module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
- * @{
- */
-#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
- * @{
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init()
- API follow respectively the UART asynchronous, UART Half duplex, UART LIN mode and
- multiprocessor configuration procedures (details for the procedures are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible UART frame formats are as listed in the following table:
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
-/**
- * @brief Initialize the UART mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- /* Check the parameters */
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Initialize the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check UART instance */
- assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In half-duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief Initialize the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart UART handle.
- * @param BreakDetectLength specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
- * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the LIN UART instance */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Check the Break detection length parameter */
- assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
- /* LIN mode limited to 16-bit oversampling only */
- if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- return HAL_ERROR;
- }
- /* LIN mode limited to 8-bit data length */
- if(huart->Init.WordLength != UART_WORDLENGTH_8B)
- {
- return HAL_ERROR;
- }
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In LIN mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
- /* Set the USART LIN Break detection length. */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief Initialize the multiprocessor mode according to the specified
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @param Address UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod specifies the UART wakeup method.
- * This parameter can be one of the following values:
- * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
- * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
- * @note If the user resorts to idle line detection wake up, the Address parameter
- * is useless and ignored by the initialization function.
- * @note If the user resorts to address mark wake up, the address length detection
- * is configured by default to 4 bits only. For the UART to be able to
- * manage 6-, 7- or 8-bit long addresses detection, the API
- * HAL_MultiProcessorEx_AddressLength_Set() must be called after
- * HAL_MultiProcessor_Init().
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the wake up method parameter */
- assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* In multiprocessor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
- {
- /* If address mark wake up method is chosen, set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
- }
-
- /* Set the wake up method by setting the WAKE bit in the CR1 register */
- MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @brief DeInitialize the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- huart->Instance->CR1 = 0x0U;
- huart->Instance->CR2 = 0x0U;
- huart->Instance->CR3 = 0x0U;
-
- /* DeInit the low level hardware */
- HAL_UART_MspDeInit(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the UART MSP.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the UART MSP.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the UART asynchronous
- and Half duplex data transfers.
-
- (#) There are two mode of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) Blocking mode API's are :
- (++) HAL_UART_Transmit()
- (++) HAL_UART_Receive()
-
- (#) Non-Blocking mode API's with Interrupt are :
- (++) HAL_UART_Transmit_IT()
- (++) HAL_UART_Receive_IT()
- (++) HAL_UART_IRQHandler()
-
- (#) Non-Blocking mode API's with DMA are :
- (++) HAL_UART_Transmit_DMA()
- (++) HAL_UART_Receive_DMA()
- (++) HAL_UART_DMAPause()
- (++) HAL_UART_DMAResume()
- (++) HAL_UART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (++) HAL_UART_TxHalfCpltCallback()
- (++) HAL_UART_TxCpltCallback()
- (++) HAL_UART_RxHalfCpltCallback()
- (++) HAL_UART_RxCpltCallback()
- (++) HAL_UART_ErrorCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_UART_Abort()
- (++) HAL_UART_AbortTransmit()
- (++) HAL_UART_AbortReceive()
- (++) HAL_UART_Abort_IT()
- (++) HAL_UART_AbortTransmit_IT()
- (++) HAL_UART_AbortReceive_IT()
-
- (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_UART_AbortCpltCallback()
- (++) HAL_UART_AbortTransmitCpltCallback()
- (++) HAL_UART_AbortReceiveCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-
- -@- In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
- while(huart->TxXferCount > 0U)
- {
- huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2U;
- }
- else
- {
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
- }
- }
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- uhMask = huart->Mask;
-
- /* as long as data have to be received */
- while(huart->RxXferCount > 0U)
- {
- huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2U;
- }
- else
- {
- *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Transmit Data Register Empty Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART Parity Error and Data Register not empty Interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @note This function starts a DMA transfer in interrupt mode meaning that
- * DMA half transfer complete, DMA transfer complete and DMA transfer
- * error interrupts are enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check if UART instance supports continuous communication using DMA */
- assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
-
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the UART transmit DMA channel */
- HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note This function starts a DMA transfer in interrupt mode meaning that
- * DMA half transfer complete, DMA transfer complete and DMA transfer
- * error interrupts are enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check if UART instance supports continuous communication using DMA */
- assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
-
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the UART DMA Tx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- /* Enable the UART DMA Tx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART DMA Rx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
- HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
-
- /* Stop UART DMA Tx request if ongoing */
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
- {
- HAL_DMA_Abort(huart->hdmatx);
- }
-
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- HAL_DMA_Abort(huart->hdmarx);
- }
-
- UART_EndRxTransfer(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(huart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
- }
- else
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(huart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
- }
- else
- {
- huart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
- {
- /* UART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
- {
- /* UART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- huart->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Tx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the UART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
- huart->hdmatx->XferAbortCallback(huart->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable UART Interrupts (Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- UART_Receive_IT(huart);
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(huart->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- UART_Receive_IT(huart);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_UART_ErrorCallback(huart);
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
- /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
- if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
- /* Set the UART state ready to be able to start again the process */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
- HAL_UARTEx_WakeupCallback(huart);
- return;
- }
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- UART_Transmit_IT(huart);
- return;
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- UART_EndTransmit_IT(huart);
- return;
- }
-
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Receive Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the UART.
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
- (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
- (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
- (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
- (+) HAL_LIN_SendBreak() API transmits the break characters
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable UART in mute mode (does not mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Enable USART mute mode by setting the MME bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
- * as it may not have been in mute mode at this very moment).
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable USART mute mode by clearing the MME bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief Enter UART mute mode (means UART actually enters mute mode).
- * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
- __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
-
-/**
- * @brief Enable the UART transmitter and disable the UART receiver.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enable the UART receiver and disable the UART transmitter.
- * @param huart UART handle.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
- huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Transmit break characters.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Send break characters */
- huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief UART Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Return the UART handle state.
- (+) Return the UART handle error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the UART handle state.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval HAL state
- */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = huart->gState;
- temp2 = huart->RxState;
-
- return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the UART handle error code.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval UART Error Code
- */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
- return huart->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-/**
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- uint32_t tmpreg = 0x00000000U;
- UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
- MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check UART Over Sampling to set Baud Rate Register */
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- }
- else
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_PCLK2:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
- }
-
- return ret;
-
-}
-
-/**
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- /* set auto Baudrate detection parameters if detection is enabled */
- if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- }
- }
-
- /* if required, configure MSB first on communication line */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- }
-}
-
-/**
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle UART Communication Timeout.
- * @param huart UART handle.
- * @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-}
-
-
-/**
- * @brief DMA UART transmit process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- huart->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else
- {
- HAL_UART_TxCpltCallback(huart);
- }
-
-}
-
-/**
- * @brief DMA UART transmit process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- huart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- }
-
- HAL_UART_RxCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- HAL_UART_RxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART communication error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- /* Stop UART DMA Tx request if ongoing */
- if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
- {
- huart->TxXferCount = 0U;
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
- {
- huart->RxXferCount = 0U;
- UART_EndRxTransfer(huart);
- }
-
- huart->ErrorCode |= HAL_UART_ERROR_DMA;
- HAL_UART_ErrorCallback(huart);
-}
-
-/**
- * @brief DMA UART communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
-
- HAL_UART_ErrorCallback(huart);
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmarx != NULL)
- {
- if(huart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmatx != NULL)
- {
- if(huart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
-
- /* Reset errorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
- huart->TxXferCount = 0U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- if(huart->TxXferCount == 0U)
- {
- /* Disable the UART Transmit Data Register Empty Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- huart->pTxBuffPtr += 2U;
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
- huart->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(uhdata & uhMask);
- huart->pRxBuffPtr +=2U;
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
- }
-
- if(--huart->RxXferCount == 0U)
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- HAL_UART_RxCpltCallback(huart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart UART handle.
- * @param WakeUpSelection UART wake up from stop mode parameters.
- * @retval None
- */
-void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
-
- /* Set the USART address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
-
- /* Set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
deleted file mode 100644
index b94c7385ed4..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_uart_ex.c
- * @author MCD Application Team
- * @brief Extended UART HAL module driver.
- * This file provides firmware functions to manage the following extended
- * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- *
- @verbatim
- ==============================================================================
- ##### UART peripheral extended features #####
- ==============================================================================
-
- (#) Declare a UART_HandleTypeDef handle structure.
-
- (#) For the UART RS485 Driver Enable mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UARTEx UARTEx
- * @brief UART Extension HAL module driver
- * @{
- */
-
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
- * @{
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
- * @brief Extended Initialization and Configuration Functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in asynchronous mode.
- (+) For the asynchronous mode the parameters below can be configured:
- (++) Baud Rate
- (++) Word Length (Fixed to 8-bits only for LIN mode)
- (++) Stop Bit
- (++) Parity
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- (++) One-Bit Sampling Method
- (+) For the asynchronous mode, the following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) auto Baud rate detection
- [..]
- The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
- configuration procedures (details for the procedures are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible UART frame formats are as listed in the following table:
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
-/**
- * @brief Initialize the RS485 Driver enable feature according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @param Polarity select the driver enable polarity.
- * This parameter can be one of the following values:
- * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
- * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
- * @param AssertionTime Driver Enable assertion time:
- * 5-bit value defining the time between the activation of the DE (Driver Enable)
- * signal and the beginning of the start bit. It is expressed in sample time
- * units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime Driver Enable deassertion time:
- * 5-bit value defining the time between the end of the last stop bit, in a
- * transmitted message, and the de-activation of the DE (Driver Enable) signal.
- * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
- * oversampling rate).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
-{
- uint32_t temp = 0x0U;
-
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the Driver Enable UART instance */
- assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
- /* Check the Driver Enable polarity */
- assert_param(IS_UART_DE_POLARITY(Polarity));
-
- /* Check the Driver Enable assertion time */
- assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
- /* Check the Driver Enable deassertion time */
- assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
- /* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
- /* Set the Driver Enable assertion and deassertion times */
- temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
- * @brief Extended UART Interrupt handling function
- *
-@verbatim
- ===============================================================================
- ##### IO operation function #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to manage the UART interrupts
- and to handle Wake up interrupt call-back.
-
- (#) Callback provided in No_Blocking mode:
- (++) HAL_UARTEx_WakeupCallback()
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief UART wakeup from Stop mode callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_WakeupCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides extended functions allowing to control the UART.
- (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
- (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
- long as UART clock is HSI or LSE
- (+) HAL_UARTEx_DisableStopMode() API disables the above feature
- (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
- detection length to more than 4 bits for multiprocessor address mark wake up.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set Wakeup from Stop mode interrupt flag selection.
- * @param huart UART handle.
- * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
- * This parameter can be one of the following values:
- * @arg @ref UART_WAKEUP_ON_ADDRESS
- * @arg @ref UART_WAKEUP_ON_STARTBIT
- * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = 0U;
-
- /* check the wake-up from stop mode UART instance */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
- /* check the wake-up selection parameter */
- assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the wake-up selection scheme */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
- if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
- {
- UART_Wakeup_AddressConfig(huart, WakeUpSelection);
- }
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- status = HAL_TIMEOUT;
- }
- else
- {
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return status;
-}
-
-
-/**
- * @brief Enable UART Stop Mode.
- * @note The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
-{
- /* Check parameter */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Set UESM bit */
- SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable UART Stop Mode.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
-{
- /* Check parameter */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Clear UESM bit */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection;
- * this API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long).
- * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
- * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
- * @param huart UART handle.
- * @param AddressLength this parameter can be one of the following values:
- * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
- * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the address length parameter */
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
deleted file mode 100644
index 0a1181ff199..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
+++ /dev/null
@@ -1,2383 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_usart.c
- * @author MCD Application Team
- * @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
- * Peripheral (USART).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The USART HAL driver can be used as follows:
-
- (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
- (++) Enable the USARTx interface clock.
- (++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure these USART pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (++) USART interrupts handling:
- -@@- The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
- (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
-
- (#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_USART_MspInit(&husart) API.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_USART_DMAPause()
- (+) Resume the DMA Transfer using HAL_USART_DMAResume()
- (+) Stop the DMA Transfer using HAL_USART_DMAStop()
-
- *** USART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in USART HAL driver.
-
- (+) __HAL_USART_ENABLE: Enable the USART peripheral
- (+) __HAL_USART_DISABLE: Disable the USART peripheral
- (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
- (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
- (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
- (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-
- [..]
- (@) You can refer to the USART HAL driver header file for more useful macros
- [..]
- (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
- HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
- HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-/** @defgroup USART USART
- * @brief USART HAL module driver
- * @{
- */
-
-#ifdef HAL_USART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
- * @{
- */
-#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
-#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
- USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions
- * @{
- */
-static void USART_EndTransfer(USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
-
- [..]
- The HAL_USART_Init() function follows the USART synchronous configuration
- procedure (details for the procedure are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible USART frame formats are as listed in the following table:
-
- Table 1. USART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | USART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
-/**
- * @brief Initialize the USART mode according to the specified
- * parameters in the USART_InitTypeDef and initialize the associated handle.
- * @param husart USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- if(husart->State == HAL_USART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- husart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_USART_MspInit(husart);
- }
-
- husart->State = HAL_USART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_USART_DISABLE(husart);
-
- /* Set the Usart Communication parameters */
- if (USART_SetConfig(husart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- husart->Instance->CR2 &= ~USART_CR2_LINEN;
- husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
- /* Enable the Peripheral */
- __HAL_USART_ENABLE(husart);
-
- /* TEACK and/or REACK to check before moving husart->State to Ready */
- return (USART_CheckIdleState(husart));
-}
-
-/**
- * @brief DeInitialize the USART peripheral.
- * @param husart USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- husart->State = HAL_USART_STATE_BUSY;
-
- husart->Instance->CR1 = 0x0U;
- husart->Instance->CR2 = 0x0U;
- husart->Instance->CR3 = 0x0U;
-
- /* DeInit the low level hardware */
- HAL_USART_MspDeInit(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the USART MSP.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize the USART MSP.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
- data transfers.
-
- [..] The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_USART_Transmit() in simplex mode
- (++) HAL_USART_Receive() in full duplex receive only
- (++) HAL_USART_TransmitReceive() in full duplex mode
-
- (#) No-Blocking mode APIs with Interrupt are :
- (++) HAL_USART_Transmit_IT() in simplex mode
- (++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
- (++) HAL_USART_IRQHandler()
-
- (#) No-Blocking mode APIs with DMA are :
- (++) HAL_USART_Transmit_DMA() in simplex mode
- (++) HAL_USART_Receive_DMA() in full duplex receive only
- (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
- (++) HAL_USART_DMAPause()
- (++) HAL_USART_DMAResume()
- (++) HAL_USART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
- (++) HAL_USART_TxCpltCallback()
- (++) HAL_USART_RxCpltCallback()
- (++) HAL_USART_TxHalfCpltCallback()
- (++) HAL_USART_RxHalfCpltCallback()
- (++) HAL_USART_ErrorCallback()
- (++) HAL_USART_TxRxCpltCallback()
-
- (#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_USART_Abort()
- (++) HAL_USART_Abort_IT()
-
- (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
- (++) HAL_USART_AbortCpltCallback()
-
- (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
- Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Simplex send an amount of data in blocking mode.
- * @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp=0U;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- /* Check the remaining data to be sent */
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
- }
- }
-
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp=0U;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
- uhMask = husart->Mask;
-
- /* as long as data have to be received */
- while(husart->RxXferCount > 0U)
- {
- husart->RxXferCount--;
-
- /* Wait until TC flag is set to send dummy byte in order to generate the
- * clock for the slave to send data.
- * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
- * can be written for all the cases. */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
- }
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp=0U;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
- husart->RxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
- uhMask = husart->Mask;
-
- /* Check the remain data to be sent */
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- husart->RxXferCount--;
-
- /* Wait until TC flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
- }
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
- }
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of TxRx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in interrupt mode.
- * @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* The USART Error Interrupts: (Frame error, noise error, overrun error)
- are not managed by the USART Transmit Process to avoid the overrun interrupt
- when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
- to benefit for the frame error and noise interrupts the usart mode should be
- configured only for transmit "USART_MODE_TX" */
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
-
- USART_MASK_COMPUTATION(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error and Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Send dummy byte in order to generate the clock for the Slave to send the next data */
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
- }
- else
- {
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- /* Computation of USART mask to apply to RDR register */
- USART_MASK_COMPUTATION(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
- /* Enable the USART Transmit Data Register Empty Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode.
- * @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @note This function starts a DMA transfer in interrupt mode meaning that
- * DMA half transfer complete, DMA transfer complete and DMA transfer
- * error interrupts are enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- uint32_t *tmp=0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Set the USART DMA transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode.
- * @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
- * @note When the USART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note This function starts a DMA transfer in interrupt mode meaning that
- * DMA half transfer complete, DMA transfer complete and DMA transfer
- * error interrupts are enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pRxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
- /* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
- this mode isn't a simplex receive mode but a full-duplex receive mode */
- /* Set the USART DMA Tx Complete and Error callback to Null */
- husart->hdmatx->XferErrorCallback = NULL;
- husart->hdmatx->XferHalfCpltCallback = NULL;
- husart->hdmatx->XferCpltCallback = NULL;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
- * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note This function starts a 2 DMA transfers in interrupt mode meaning that
- * DMA half transfer complete, DMA transfer complete and DMA transfer
- * error interrupts are enabled
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Tx transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the USART DMA Tx transfer error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param husart USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
- {
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
- {
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the USART DMA Rx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param husart USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Enable the USART DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the USART DMA Rx request before the DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the USART DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param husart USART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
- HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
- generated if the DMA transfer interruption occurs at the middle or at the end of the stream
- and the corresponding call back is executed.
- */
-
- /* Disable the USART Tx/Rx DMA requests */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA tx channel */
- if(husart->hdmatx != NULL)
- {
- HAL_DMA_Abort(husart->hdmatx);
- }
- /* Abort the USART DMA rx channel */
- if(husart->hdmarx != NULL)
- {
- HAL_DMA_Abort(husart->hdmarx);
- }
-
- USART_EndTransfer(husart);
- husart->State = HAL_USART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable USART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the USART DMA Tx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmatx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmatx);
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable USART Interrupts (Tx and Rx)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
-{
- uint32_t abortcplt = 1U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(husart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
- }
- else
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(husart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
- }
- else
- {
- husart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at USART level */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmatx != NULL)
- {
- /* USART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmarx != NULL)
- {
- /* USART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- husart->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle USART interrupt request.
- * @param husart USART handle.
- * @retval None
- */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
- uint32_t isrflags = READ_REG(husart->Instance->ISR);
- uint32_t cr1its = READ_REG(husart->Instance->CR1);
- uint32_t cr3its;
- uint32_t errorflags;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
- {
- /* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
- }
-
- /* If some errors occur */
- cr3its = READ_REG(husart->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
- {
- /* USART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_PE;
- }
-
- /* USART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_FE;
- }
-
- /* USART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
-
- husart->ErrorCode |= HAL_USART_ERROR_NE;
- }
-
- /* USART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
-
- husart->ErrorCode |= HAL_USART_ERROR_ORE;
- }
-
- /* Call USART Error Call back function if need be --------------------------*/
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
- {
- /* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the USART state ready to be able to start again the process,
- Disable Interrupts, and disable DMA requests, if ongoing */
- USART_EndTransfer(husart);
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
-
- /* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
- {
- /* Set the USART Tx DMA Abort callback to NULL : no callback
- executed at end of DMA abort procedure */
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA TX */
- HAL_DMA_Abort_IT(husart->hdmatx);
- }
-
- /* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART Rx DMA Abort callback :
- will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
- husart->hdmarx->XferAbortCallback(husart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_USART_ErrorCallback(husart);
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- }
- }
- return;
-
- } /* End if some error occurs */
-
-
- /* USART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- USART_Transmit_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
-
- /* USART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- USART_EndTransmit_IT(husart);
- return;
- }
-
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_RxHalfCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxRxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief USART error callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief USART Abort Complete callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief USART Peripheral State and Error functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Return the USART handle state
- (+) Return the USART handle error code
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Return the USART handle state.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART handle state
- */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
- return husart->State;
-}
-
-/**
- * @brief Return the USART error code.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART handle Error Code
- */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
- return husart->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions USART Private Functions
- * @brief USART Private functions
- *
-@verbatim
- [..]
- This subsection provides a set of functions allowing to control the USART.
- (+) USART_SetConfig() API is used to set the USART communication parameters.
- (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
-
-@endverbatim
- * @{
- */
-/**
- * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
- * @param husart USART handle.
- * @retval None
- */
-static void USART_EndTransfer(USART_HandleTypeDef *husart)
-{
- /* Disable TXEIE and TCIE interrupts */
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* At end of process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-}
-
-/**
- * @brief DMA USART transmit process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- husart->TxXferCount = 0U;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
- }
- }
- /* DMA Circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- HAL_USART_TxCpltCallback(husart);
- }
- }
-}
-
-/**
- * @brief DMA USART transmit process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- HAL_USART_TxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART receive process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- husart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
- in USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* similarly, disable the DMA TX transfer that was started to provide the
- clock to the slave device */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- husart->State= HAL_USART_STATE_READY;
- }
- /* DMA circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- }
-
-}
-
-/**
- * @brief DMA USART receive process half complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- HAL_USART_RxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART communication error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
-
- husart->RxXferCount = 0U;
- husart->TxXferCount = 0U;
- USART_EndTransfer(husart);
-
- husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief DMA USART communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
- husart->RxXferCount = 0U;
- husart->TxXferCount = 0U;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief DMA USART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmarx != NULL)
- {
- if(husart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-
-/**
- * @brief DMA USART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
- husart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmatx != NULL)
- {
- if(husart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Clear the Error flags in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-
-/**
- * @brief Handle USART Communication Timeout.
- * @param husart USART handle.
- * @param Flag Specifies the USART flag to check.
- * @param Status the Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief Configure the USART peripheral.
- * @param husart USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
-{
- uint32_t tmpreg = 0x0U;
- USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
-
- /* Check the parameters */
- assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
- assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
- assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
- assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
- assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
- assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
- assert_param(IS_USART_PARITY(husart->Init.Parity));
- assert_param(IS_USART_MODE(husart->Init.Mode));
-
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity and Mode:
- * set the M bits according to husart->Init.WordLength value
- * set PCE and PS bits according to husart->Init.Parity value
- * set TE and RE bits according to husart->Init.Mode value
- * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
- tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
- MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*---------------------------- USART CR2 Configuration ---------------------*/
- /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
- * set CPOL bit according to husart->Init.CLKPolarity value
- * set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value
- * set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
- tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
- tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
- MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* no CR3 register configuration */
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
- USART_GETCLOCKSOURCE(husart, clocksource);
- switch (clocksource)
- {
- case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- husart->Instance->BRR = brrtemp;
-
- return ret;
-}
-
-/**
- * @brief Check the USART Idle State.
- * @param husart USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the USART ErrorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
-
- /* REACK bit in ISR is checked only when available (not to be checked on all instances).
- Bit is defined only for USART instances supporting WakeUp from Stop Mode feature.
- */
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
- {
- /* Check if the Receiver is enabled */
- if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Initialize the USART state*/
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Simplex send an amount of data in non-blocking mode.
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Transmit_IT().
- * @note The USART errors are not managed to avoid the overrun error.
- * @param husart USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp=0U;
-
- /* Check that a Tx process is ongoing */
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
-
- if(husart->TxXferCount == 0U)
- {
- /* Disable the USART Transmit data register empty interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
-
- husart->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Wraps up transmission in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
- /* Disable the USART Transmit Complete Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- /* Tx process is ended, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Simplex receive an amount of data in non-blocking mode.
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Receive_IT().
- * @param husart USART handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp=0U;
- uint16_t uhMask = husart->Mask;
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
-
- /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
-
- if(--husart->RxXferCount == 0U)
- {
- /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_RxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
- * @param husart USART handle.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp=0U;
- uint16_t uhMask = husart->Mask;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
-
- if(husart->TxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
- }
- husart->TxXferCount--;
-
- /* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
- {
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- }
- }
- }
-
- if(husart->RxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- husart->RxXferCount--;
- }
- }
-
- /* Check the latest data received */
- if(husart->RxXferCount == 0U)
- {
- /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxRxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
deleted file mode 100644
index 2f2ef5d0ccd..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_hal_wwdg.c
- * @author MCD Application Team
- * @brief WWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and Configuration function
- * + IO operation functions
- @verbatim
- ==============================================================================
- ##### WWDG specific features #####
- ==============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (T[6U;0] downcounter)
- before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3FU).
-
- (+) An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- (+) Once enabled the WWDG cannot be disabled except by a system reset.
-
- (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
- occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
-
- (+) The WWDG downcounter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler)
-
- (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock)
- where T[5U;0] are the lowest 6 bits of downcounter.
-
- (+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock)
- (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock)
-
- (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40U, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
- HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
-
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
-
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-/** @defgroup WWDG WWDG
- * @brief WWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and start the WWDG according to the specified parameters
- in the WWDG_InitTypeDef of associated handle.
- (+) Initialize the WWDG MSP.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the WWDG according to the specified.
- * parameters in the WWDG_InitTypeDef of associated handle.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check the WWDG handle allocation */
- if(hwwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
- assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
- assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
- assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
- assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
-
- /* Init the low level hardware */
- HAL_WWDG_MspInit(hwwdg);
-
- /* Set WWDG Counter */
- WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
-
- /* Set WWDG Prescaler and Window */
- WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the WWDG MSP.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @note When rewriting this function in user file, mechanism may be added
- * to avoid multiple initialize when HAL_WWDG_Init function is called
- * again to change parameters.
- * @retval None
- */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Refresh the WWDG.
- (+) Handle WWDG interrupt request and associated function callback.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Refresh the WWDG.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
-{
- /* Write to WWDG CR the WWDG Counter value to refresh with */
- WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handle WWDG interrupt request.
- * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
- * or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
- * EWIMode set to WWDG_EWI_ENABLE.
- * When the downcounter reaches the value 0x40, and EWI interrupt is
- * generated and the corresponding Interrupt Service Routine (ISR) can
- * be used to trigger specific actions (such as communications or data
- * logging), before resetting the device.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
- {
- /* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
- {
- /* Clear the WWDG Early Wakeup flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Early Wakeup callback */
- HAL_WWDG_EarlyWakeupCallback(hwwdg);
- }
- }
-}
-
-/**
- * @brief WWDG Early Wakeup callback.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c
deleted file mode 100644
index 6dc34873949..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c
+++ /dev/null
@@ -1,2009 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_adc.c
- * @author MCD Application Team
- * @brief ADC LL module driver
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_adc.h"
-#include "stm32f3xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. b */
-/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
-/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
-/* features (refer to reference manual). */
-/* - STM32F37x: */
-/* ADC IP 1Msamples/sec, 1 ADC instance */
-/* This file contains the drivers of these ADC IP, located in 2 area */
-/* delimited by compilation switches. */
-
-#if defined(ADC5_V1_1)
-
-#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
-
-/** @addtogroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup ADC_LL_Private_Constants
- * @{
- */
-
-/* Definitions of ADC hardware constraints delays */
-/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
-/* not timeout values: */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
-/* values definition. */
-/* Note: ADC timeout values are defined here in CPU cycles to be independent */
-/* of device clock setting. */
-/* In user application, ADC timeout values should be defined with */
-/* temporal values, in function of device clock settings. */
-/* Highest ratio CPU clock frequency vs ADC clock frequency: */
-/* - ADC clock from synchronous clock with AHB prescaler 512, */
-/* APB prescaler 16, ADC prescaler 4. */
-/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
-/* with highest ratio CPU clock frequency vs HSI clock frequency: */
-/* CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1. */
-/* Unit: CPU cycles. */
-#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
-#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
-#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* common to several ADC instances. */
-#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
- ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
- || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
- || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
- || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
- )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC instance. */
-#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
- ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
- || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
- || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
- || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
- )
-
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
- || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
- )
-
-#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
- ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
- || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
- )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group regular */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12) \
- ) \
- : \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34) \
- ) \
- )
-#elif defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
- ) \
- : \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
- ) \
- )
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
- )
-#elif defined(STM32F334x8)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
- )
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
- )
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
- )
-#endif
-
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
- || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
- )
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
- || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
- || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
- )
-
-#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
- ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
- || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
- )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
- )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
- )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group injected */
-#if defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12) \
- ) \
- : \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
- ) \
- )
-#elif defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- ) \
- : \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- ) \
- )
-
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- )
-#elif defined(STM32F334x8)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- )
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- )
-#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
- )
-#endif
-
-#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
- ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
- || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
- || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
- )
-
-#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
- || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
- )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
- )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
- || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
- )
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* multimode. */
-#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
- )
-
-#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
- ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
- || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
- || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
- || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
- || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
- )
-
-#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
- ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
- || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
- )
-
-#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
- || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
- || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
- )
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of all ADC instances belonging to
- * the same ADC common instance to their default reset values.
- * @note This function is performing a hard reset, using high level
- * clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
- * on the selected device, RCC ADC reset will reset
- * all ADC instances belonging to the common ADC instance.
- * To de-initialize only 1 ADC instance, use
- * function @ref LL_ADC_DeInit().
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-
- /* Force reset of ADC clock (core clock) */
- #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
- if(ADCxy_COMMON == ADC12_COMMON)
- {
- LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
- }
- else
- {
- LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC34);
- }
- #elif defined(ADC1) && defined(ADC2)
- LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
- #elif defined(ADC1)
- LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC1);
- #endif
-
- /* Release reset of ADC clock (core clock) */
- #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
- if(ADCxy_COMMON == ADC12_COMMON)
- {
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
- }
- else
- {
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
- }
- #elif defined(ADC1) && defined(ADC2)
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
- #elif defined(ADC1)
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
- #endif
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize some features of ADC common parameters
- * (all ADC instances belonging to the same ADC common instance)
- * and multimode (for devices with several ADC instances available).
- * @note The setting of ADC common parameters is conditioned to
- * ADC instances state:
- * All ADC instances belonging to the same ADC common instance
- * must be disabled.
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are initialized
- * - ERROR: ADC common registers are not initialized
- */
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
- assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
- if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
- {
- assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
- assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
- }
-#endif /* ADC_MULTIMODE_SUPPORT */
-
- /* Note: Hardware constraint (refer to description of functions */
- /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
- /* ADC state: */
- /* All ADC instances of the ADC common group must be disabled. */
- if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - common to several ADC */
- /* (all ADC instances belonging to the same ADC common instance) */
- /* - Set ADC clock (conversion clock) */
- /* - multimode (if several ADC instances available on the */
- /* selected device) */
- /* - Set ADC multimode configuration */
- /* - Set ADC multimode DMA transfer */
- /* - Set ADC multimode: delay between 2 sampling phases */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
- {
- MODIFY_REG(ADCxy_COMMON->CCR,
- ADC_CCR_CKMODE
- | ADC_CCR_DUAL
- | ADC_CCR_MDMA
- | ADC_CCR_DELAY
- ,
- ADC_CommonInitStruct->CommonClock
- | ADC_CommonInitStruct->Multimode
- | ADC_CommonInitStruct->MultiDMATransfer
- | ADC_CommonInitStruct->MultiTwoSamplingDelay
- );
- }
- else
- {
- MODIFY_REG(ADCxy_COMMON->CCR,
- ADC_CCR_CKMODE
- | ADC_CCR_DUAL
- | ADC_CCR_MDMA
- | ADC_CCR_DELAY
- ,
- ADC_CommonInitStruct->CommonClock
- | LL_ADC_MULTI_INDEPENDENT
- );
- }
-#else
- LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
-#endif
- }
- else
- {
- /* Initialization error: One or several ADC instances belonging to */
- /* the same ADC common instance are not disabled. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
- /* Set ADC_CommonInitStruct fields to default values */
- /* Set fields of ADC common */
- /* (all ADC instances belonging to the same ADC common instance) */
- ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Set fields of ADC multimode */
- ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
- ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
- ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
-#endif /* ADC_MULTIMODE_SUPPORT */
-}
-
-/**
- * @brief De-initialize registers of the selected ADC instance
- * to their default reset values.
- * @note To reset all ADC instances quickly (perform a hard reset),
- * use function @ref LL_ADC_CommonDeInit().
- * @note If this functions returns error status, it means that ADC instance
- * is in an unknown state.
- * In this case, perform a hard reset using high level
- * clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
- * on the selected device, RCC ADC reset will reset
- * all ADC instances belonging to the common ADC instance.
- * Refer to function @ref LL_ADC_CommonDeInit().
- * @param ADCx ADC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are de-initialized
- * - ERROR: ADC registers are not de-initialized
- */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
-{
- ErrorStatus status = SUCCESS;
-
- __IO uint32_t timeout_cpu_cycles = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- /* Disable ADC instance if not already disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 1U)
- {
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
- /* Stop potential ADC conversion on going on ADC group regular. */
- if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
- {
- if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
- {
- LL_ADC_REG_StopConversion(ADCx);
- }
- }
-
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
- /* Stop potential ADC conversion on going on ADC group injected. */
- if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
- {
- if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
- {
- LL_ADC_INJ_StopConversion(ADCx);
- }
- }
-
- /* Wait for ADC conversions are effectively stopped */
- timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
- while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
- | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
- {
- if(timeout_cpu_cycles-- == 0U)
- {
- /* Time-out error */
- status = ERROR;
- }
- }
-
- /* Flush group injected contexts queue (register JSQR): */
- /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
- /* contexts queue is maintained with the last active context). */
- LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
-
- /* Disable the ADC instance */
- LL_ADC_Disable(ADCx);
-
- /* Wait for ADC instance is effectively disabled */
- timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
- while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
- {
- if(timeout_cpu_cycles-- == 0U)
- {
- /* Time-out error */
- status = ERROR;
- }
- }
- }
-
- /* Check whether ADC state is compliant with expected state */
- if(READ_BIT(ADCx->CR,
- ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
- | ADC_CR_ADDIS | ADC_CR_ADEN )
- )
- == 0U)
- {
- /* ========== Reset ADC registers ========== */
- /* Reset register IER */
- CLEAR_BIT(ADCx->IER,
- ( LL_ADC_IT_ADRDY
- | LL_ADC_IT_EOC
- | LL_ADC_IT_EOS
- | LL_ADC_IT_OVR
- | LL_ADC_IT_EOSMP
- | LL_ADC_IT_JEOC
- | LL_ADC_IT_JEOS
- | LL_ADC_IT_JQOVF
- | LL_ADC_IT_AWD1
- | LL_ADC_IT_AWD2
- | LL_ADC_IT_AWD3 )
- );
-
- /* Reset register ISR */
- SET_BIT(ADCx->ISR,
- ( LL_ADC_FLAG_ADRDY
- | LL_ADC_FLAG_EOC
- | LL_ADC_FLAG_EOS
- | LL_ADC_FLAG_OVR
- | LL_ADC_FLAG_EOSMP
- | LL_ADC_FLAG_JEOC
- | LL_ADC_FLAG_JEOS
- | LL_ADC_FLAG_JQOVF
- | LL_ADC_FLAG_AWD1
- | LL_ADC_FLAG_AWD2
- | LL_ADC_FLAG_AWD3 )
- );
-
- /* Reset register CR */
- /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
- /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
- /* access mode "read-set": no direct reset applicable. */
- /* - Reset Calibration mode to default setting (single ended). */
- /* - Disable ADC internal voltage regulator. */
- /* Note: ADC internal voltage regulator disable is conditioned to */
- /* ADC state disabled: already done above. */
- /* Sequence to disable voltage regulator: */
- /* 1. Set the intermediate state before moving the ADC voltage regulator */
- /* to disable state. */
- CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
- /* 2. Set ADVREGEN bits to 0x10 */
- SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
-
- /* Reset register CFGR */
- CLEAR_BIT(ADCx->CFGR,
- ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
- | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
- | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
- | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
- | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
- | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
- );
-
- /* Reset register SMPR1 */
- CLEAR_BIT(ADCx->SMPR1,
- ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
- | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
- | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
- );
-
- /* Reset register SMPR2 */
- CLEAR_BIT(ADCx->SMPR2,
- ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
- | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
- | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
- );
-
- /* Reset register TR1 */
- MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
-
- /* Reset register TR2 */
- MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
-
- /* Reset register TR3 */
- MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
-
- /* Reset register SQR1 */
- CLEAR_BIT(ADCx->SQR1,
- ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
- | ADC_SQR1_SQ1 | ADC_SQR1_L)
- );
-
- /* Reset register SQR2 */
- CLEAR_BIT(ADCx->SQR2,
- ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
- | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
- );
-
- /* Reset register SQR3 */
- CLEAR_BIT(ADCx->SQR3,
- ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
- | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
- );
-
- /* Reset register SQR4 */
- CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-
- /* Reset register JSQR */
- CLEAR_BIT(ADCx->JSQR,
- ( ADC_JSQR_JL
- | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
- | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
- | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
- );
-
- /* Flush ADC group injected contexts queue */
- SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
- CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
- /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
- SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
-
- /* Reset register DR */
- /* Note: bits in access mode read only, no direct reset applicable */
-
- /* Reset register OFR1 */
- CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
- /* Reset register OFR2 */
- CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
- /* Reset register OFR3 */
- CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
- /* Reset register OFR4 */
- CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* Note: bits in access mode read only, no direct reset applicable */
-
- /* Reset register AWD2CR */
- CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
-
- /* Reset register AWD3CR */
- CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
-
- /* Reset register DIFSEL */
- CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
-
- /* Reset register CALFACT */
- CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
- }
- else
- {
- /* ADC instance is in an unknown state */
- /* Need to performing a hard reset of ADC instance, using high level */
- /* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
- /* on the selected device, RCC ADC reset will reset */
- /* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
- /* on the selected device, RCC ADC reset will reset */
- /* all ADC instances belonging to the common ADC instance. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, some other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
- assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
- assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC instance */
- /* - Set ADC data resolution */
- /* - Set ADC conversion data alignment */
- /* - Set ADC low power mode */
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_RES
- | ADC_CFGR_ALIGN
- | ADC_CFGR_AUTDLY
- ,
- ADC_InitStruct->Resolution
- | ADC_InitStruct->DataAlignment
- | ADC_InitStruct->LowPowerMode
- );
-
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- /* Set ADC_InitStruct fields to default values */
- /* Set fields of ADC instance */
- ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
- ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
- ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
-
-}
-
-/**
- * @brief Initialize some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
- assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
-#else
- assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
-#endif
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
- assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
- assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group regular */
- /* - Set ADC group regular trigger source */
- /* - Set ADC group regular sequencer length */
- /* - Set ADC group regular sequencer discontinuous mode */
- /* - Set ADC group regular continuous mode */
- /* - Set ADC group regular conversion data transfer: no transfer or */
- /* transfer by DMA, and DMA requests mode */
- /* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_EXTSEL
- | ADC_CFGR_EXTEN
- | ADC_CFGR_DISCEN
- | ADC_CFGR_DISCNUM
- | ADC_CFGR_CONT
- | ADC_CFGR_DMAEN
- | ADC_CFGR_DMACFG
- | ADC_CFGR_OVRMOD
- ,
- ADC_REG_InitStruct->TriggerSource
- | ADC_REG_InitStruct->SequencerDiscont
- | ADC_REG_InitStruct->ContinuousMode
- | ADC_REG_InitStruct->DMATransfer
- | ADC_REG_InitStruct->Overrun
- );
- }
- else
- {
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_EXTSEL
- | ADC_CFGR_EXTEN
- | ADC_CFGR_DISCEN
- | ADC_CFGR_DISCNUM
- | ADC_CFGR_CONT
- | ADC_CFGR_DMAEN
- | ADC_CFGR_DMACFG
- | ADC_CFGR_OVRMOD
- ,
- ADC_REG_InitStruct->TriggerSource
- | LL_ADC_REG_SEQ_DISCONT_DISABLE
- | ADC_REG_InitStruct->ContinuousMode
- | ADC_REG_InitStruct->DMATransfer
- | ADC_REG_InitStruct->Overrun
- );
- }
-
- /* Set ADC group regular sequencer length and scan direction */
- LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- /* Set ADC_REG_InitStruct fields to default values */
- /* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
- ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
-}
-
-/**
- * @brief Initialize some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @note Caution to ADC group injected contexts queue: On this STM32 serie,
- * using successively several times this function will appear has
- * having no effect.
- * This is due to ADC group injected contexts queue (this feature
- * cannot be disabled on this STM32 serie).
- * To set several features of ADC group injected, use
- * function @ref LL_ADC_INJ_ConfigQueueContext().
- * @param ADCx ADC instance
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
- assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
-#else
- assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
-#endif
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group injected */
- /* - Set ADC group injected trigger source */
- /* - Set ADC group injected sequencer length */
- /* - Set ADC group injected sequencer discontinuous mode */
- /* - Set ADC group injected conversion trigger: independent or */
- /* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
- /* setting of trigger source to SW start. */
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_JDISCEN
- | ADC_CFGR_JAUTO
- ,
- ADC_INJ_InitStruct->SequencerDiscont
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
- else
- {
- MODIFY_REG(ADCx->CFGR,
- ADC_CFGR_JDISCEN
- | ADC_CFGR_JAUTO
- ,
- LL_ADC_REG_SEQ_DISCONT_DISABLE
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
-
- MODIFY_REG(ADCx->JSQR,
- ADC_JSQR_JEXTSEL
- | ADC_JSQR_JEXTEN
- | ADC_JSQR_JL
- ,
- ADC_INJ_InitStruct->TriggerSource
- | ADC_INJ_InitStruct->SequencerLength
- );
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- /* Set ADC_INJ_InitStruct fields to default values */
- /* Set fields of ADC group injected */
- ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
- ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 || ADC2 || ADC3 || ADC4 */
-
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
-
-#if defined (ADC1_V2_5)
-
-#if defined (ADC1)
-
-/** @addtogroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* common to several ADC instances. */
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC instance. */
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
- || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
-
-#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
- ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
- || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
-
-#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
- ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
- || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group regular */
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
-
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
- || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
- || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
-
-#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group injected */
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
-
-#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
- || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
- || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) )
-
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of all ADC instances belonging to
- * the same ADC common instance to their default reset values.
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-
- /* Force reset of ADC clock (core clock) */
- LL_APB2_GRP1_ForceReset (LL_APB2_GRP1_PERIPH_ADC1);
-
- /* Release reset of ADC clock (core clock) */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
-
- return SUCCESS;
-}
-
-/**
- * @brief De-initialize registers of the selected ADC instance
- * to their default reset values.
- * @note To reset all ADC instances quickly (perform a hard reset),
- * use function @ref LL_ADC_CommonDeInit().
- * @param ADCx ADC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are de-initialized
- * - ERROR: ADC registers are not de-initialized
- */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- /* Disable ADC instance if not already disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 1U)
- {
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
- /* Disable the ADC instance */
- LL_ADC_Disable(ADCx);
- }
-
- /* Check whether ADC state is compliant with expected state */
- /* (hardware requirements of bits state to reset registers below) */
- if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
- {
- /* ========== Reset ADC registers ========== */
- /* Reset register SR */
- CLEAR_BIT(ADCx->SR,
- ( LL_ADC_FLAG_STRT
- | LL_ADC_FLAG_JSTRT
- | LL_ADC_FLAG_EOS
- | LL_ADC_FLAG_JEOS
- | LL_ADC_FLAG_AWD1 )
- );
-
- /* Reset register CR1 */
- CLEAR_BIT(ADCx->CR1,
- ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN
- | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
- | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
- | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
- | ADC_CR1_AWDCH )
- );
-
- /* Reset register CR2 */
- CLEAR_BIT(ADCx->CR2,
- ( ADC_CR2_TSVREFE
- | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
- | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
- | ADC_CR2_ALIGN | ADC_CR2_DMA
- | ADC_CR2_RSTCAL | ADC_CR2_CAL
- | ADC_CR2_CONT | ADC_CR2_ADON )
- );
-
- /* Reset register SMPR1 */
- CLEAR_BIT(ADCx->SMPR1,
- ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
- | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
- | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
- );
-
- /* Reset register SMPR2 */
- CLEAR_BIT(ADCx->SMPR2,
- ( ADC_SMPR2_SMP9
- | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
- | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
- | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
- );
-
- /* Reset register JOFR1 */
- CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
- /* Reset register JOFR2 */
- CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
- /* Reset register JOFR3 */
- CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
- /* Reset register JOFR4 */
- CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
-
- /* Reset register HTR */
- SET_BIT(ADCx->HTR, ADC_HTR_HT);
- /* Reset register LTR */
- CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
-
- /* Reset register SQR1 */
- CLEAR_BIT(ADCx->SQR1,
- ( ADC_SQR1_L
- | ADC_SQR1_SQ16
- | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
- );
-
- /* Reset register SQR2 */
- CLEAR_BIT(ADCx->SQR2,
- ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
- | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
- );
-
-
- /* Reset register JSQR */
- CLEAR_BIT(ADCx->JSQR,
- ( ADC_JSQR_JL
- | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
- | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
- );
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable */
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable */
-
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, some other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
- assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC instance */
- /* - Set ADC conversion data alignment */
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_SCAN
- ,
- ADC_InitStruct->SequencersScanMode
- );
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_ALIGN
- ,
- ADC_InitStruct->DataAlignment
- );
-
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- /* Set ADC_InitStruct fields to default values */
- /* Set fields of ADC instance */
- ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
-
- /* Enable scan mode to have a generic behavior with ADC of other */
- /* STM32 families, without this setting available: */
- /* ADC group regular sequencer and ADC group injected sequencer depend */
- /* only of their own configuration. */
- ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
-
-}
-
-/**
- * @brief Initialize some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
- assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
- assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group regular */
- /* - Set ADC group regular trigger source */
- /* - Set ADC group regular sequencer length */
- /* - Set ADC group regular sequencer discontinuous mode */
- /* - Set ADC group regular continuous mode */
- /* - Set ADC group regular conversion data transfer: no transfer or */
- /* transfer by DMA, and DMA requests mode */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_DISCEN
- | ADC_CR1_DISCNUM
- ,
- ADC_REG_InitStruct->SequencerLength
- | ADC_REG_InitStruct->SequencerDiscont
- );
- }
- else
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_DISCEN
- | ADC_CR1_DISCNUM
- ,
- ADC_REG_InitStruct->SequencerLength
- | LL_ADC_REG_SEQ_DISCONT_DISABLE
- );
- }
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_EXTSEL
- | ADC_CR2_CONT
- | ADC_CR2_DMA
- ,
- ADC_REG_InitStruct->TriggerSource
- | ADC_REG_InitStruct->ContinuousMode
- | ADC_REG_InitStruct->DMATransfer
- );
-
- /* Set ADC group regular sequencer length and scan direction */
- /* Note: Hardware constraint (refer to description of this function): */
- /* Note: If ADC instance feature scan mode is disabled */
- /* (refer to ADC instance initialization structure */
- /* parameter @ref SequencersScanMode */
- /* or function @ref LL_ADC_SetSequencersScanMode() ), */
- /* this parameter is discarded. */
- LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- /* Set ADC_REG_InitStruct fields to default values */
- /* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
- ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
-}
-
-/**
- * @brief Initialize some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
- assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group injected */
- /* - Set ADC group injected trigger source */
- /* - Set ADC group injected sequencer length */
- /* - Set ADC group injected sequencer discontinuous mode */
- /* - Set ADC group injected conversion trigger: independent or */
- /* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_JDISCEN
- | ADC_CR1_JAUTO
- ,
- ADC_INJ_InitStruct->SequencerDiscont
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
- else
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_JDISCEN
- | ADC_CR1_JAUTO
- ,
- LL_ADC_REG_SEQ_DISCONT_DISABLE
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_JEXTSEL
- ,
- ADC_INJ_InitStruct->TriggerSource
- );
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* Note: If ADC instance feature scan mode is disabled */
- /* (refer to ADC instance initialization structure */
- /* parameter @ref SequencersScanMode */
- /* or function @ref LL_ADC_SetSequencersScanMode() ), */
- /* this parameter is discarded. */
- LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- /* Set ADC_INJ_InitStruct fields to default values */
- /* Set fields of ADC group injected */
- ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
- ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 */
-
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c
deleted file mode 100644
index 466bc71e0a6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c
+++ /dev/null
@@ -1,1051 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_comp.c
- * @author MCD Application Team
- * @brief COMP LL module driver
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_comp.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
-/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
-/* COMP IP from 3 to 7 instances and other specific features */
-/* (comparator output blanking, ...) (refer to reference manual). */
-/* - STM32F37x: */
-/* COMP IP with 2 instances */
-/* This file contains the drivers of these COMP IP, located in 2 area */
-/* delimited by compilation switches. */
-
-#if defined(COMP_V1_3_0_0)
-
-#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
-
-/** @addtogroup COMP_LL COMP
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup COMP_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of COMP hierarchical scope: */
-/* COMP instance. */
-
-#if defined(COMP_CSR_COMPxMODE)
-#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
- ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
- )
-#else
-#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
- ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)
-#endif
-
-/* Note: On this STM32 serie, comparator input plus parameters are */
-/* the same on all COMP instances. */
-/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
-#if defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1)
-/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
-/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1) \
- )
-#elif defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
-/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
-/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
- )
-#elif defined(COMP_CSR_COMPxNONINSEL)
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
- )
-#elif defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
-/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
-/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
- )
-#else
-/* Note: Device without comparator input plus configurable: corresponds to */
-/* setting "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" */
-/* compared to other STM32F3 devices, depending on comparator instance */
-/* (refer to reference manual). */
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)
-#endif
-
-#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
- )
-#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
- )
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
- )
-#else /* STM32F301x8 || STM32F318xx || STM32F302x8 */
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
- )
-#endif
-
-#if defined(COMP_CSR_COMPxHYST)
-#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
- ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
- )
-#else
-#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
- ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)
-#endif
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
- (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
- ) \
- ? ( \
- (1U) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP2) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
- ) \
- : \
- ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
-#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
- (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
- ) \
- ? ( \
- (1U) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP2) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4)\
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
- ) \
- : \
- ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F302xC) || defined(STM32F302xE)
-#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
- (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
- ) \
- ? ( \
- (1U) \
- ) \
- : \
- ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
- ) \
- : \
- ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
- (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
- ) \
- ? ( \
- (1U) \
- ) \
- : \
- ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP3) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP5) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP6) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
- ) \
- : \
- ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
- ) \
- ) \
- ) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
- (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2) \
- ) \
- ? ( \
- (1U) \
- ) \
- : \
- ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
- || (((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_OCCLR_COMP2) \
- && ((__COMP_INSTANCE__) == COMP2) ) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP3) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP5) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP6) \
- ? ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
- ) \
- : \
- ( \
- ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
- ) \
- ) \
- ) \
- ) \
- ) \
- ) \
- )
-#endif
-
-#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
- ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
- || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
- )
-
-#if defined(COMP_CSR_COMPxBLANKING)
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
- ? ( \
- (1U) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP2) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
- ) \
- : \
- ( \
- (((__COMP_INSTANCE__) == COMP6) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
- ) \
- : \
- ( \
- (0U) \
- ) \
- ) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F302xE) || defined(STM32F302xC)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
- ? ( \
- (1U) \
- ) \
- : \
- ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
- ) \
- : \
- ( \
- (((__COMP_INSTANCE__) == COMP6) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
- ) \
- : \
- ( \
- (0U) \
- ) \
- ) \
- ) \
- ) \
- ) \
- )
-#elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
- ? ( \
- (1U) \
- ) \
- : \
- ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP3) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP4) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP5) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
- ) \
- : \
- (((__COMP_INSTANCE__) == COMP6) \
- ? ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
- ) \
- : \
- ( \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
- ) \
- ) \
- ) \
- ) \
- ) \
- ) \
- )
-#endif
-#else
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)
-#endif
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup COMP_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of the selected COMP instance
- * to their default reset values.
- * @note If comparator is locked, de-initialization by software is
- * not possible.
- * The only way to unlock the comparator is a device hardware reset.
- * @param COMPx COMP instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: COMP registers are de-initialized
- * - ERROR: COMP registers are not de-initialized
- */
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* COMP instance must not be locked. */
- if(LL_COMP_IsLocked(COMPx) == 0U)
- {
- LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
- }
- else
- {
- /* Comparator instance is locked: de-initialization by software is */
- /* not possible. */
- /* The only way to unlock the comparator is a device hardware reset. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of COMP instance.
- * @note This function configures features of the selected COMP instance.
- * Some features are also available at scope COMP common instance
- * (common to several COMP instances).
- * Refer to functions having argument "COMPxy_COMMON" as parameter.
- * @param COMPx COMP instance
- * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: COMP registers are initialized
- * - ERROR: COMP registers are not initialized
- */
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(COMPx));
- assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
- assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
- assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
- assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
- assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMPx, COMP_InitStruct->OutputSelection));
- assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
- assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
-
- /* Note: Hardware constraint (refer to description of this function) */
- /* COMP instance must not be locked. */
- if(LL_COMP_IsLocked(COMPx) == 0U)
- {
- /* Configuration of comparator instance : */
- /* - PowerMode */
- /* - InputPlus */
- /* - InputMinus */
- /* - InputHysteresis */
- /* - OutputSelection */
- /* - OutputPolarity */
- /* - OutputBlankingSource */
- MODIFY_REG(COMPx->CSR,
- ((uint32_t)0x00000000U)
-#if defined(COMP_CSR_COMPxMODE)
- | COMP_CSR_COMPxMODE
-#endif
-#if defined(COMP_CSR_COMPxNONINSEL)
- | COMP_CSR_COMPxNONINSEL
-#endif
- | COMP_CSR_COMPxINSEL
-#if defined(COMP_CSR_COMPxHYST)
- | COMP_CSR_COMPxHYST
-#endif
- | COMP_CSR_COMPxOUTSEL
- | COMP_CSR_COMPxPOL
- | COMP_CSR_COMPxBLANKING
- ,
- ((uint32_t)0x00000000U)
-#if defined(COMP_CSR_COMPxMODE)
- | COMP_InitStruct->PowerMode
-#endif
-#if defined(COMP_CSR_COMPxNONINSEL)
- | COMP_InitStruct->InputPlus
-#endif
- | COMP_InitStruct->InputMinus
-#if defined(COMP_CSR_COMPxHYST)
- | COMP_InitStruct->InputHysteresis
-#endif
- | COMP_InitStruct->OutputSelection
- | COMP_InitStruct->OutputPolarity
- | COMP_InitStruct->OutputBlankingSource
- );
-
- }
- else
- {
- /* Initialization error: COMP instance is locked. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
- * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
-{
- /* Set COMP_InitStruct fields to default values */
- /* Note: Comparator power mode "high speed" is the only mode */
- /* available on all STMF3 devices. */
- COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_HIGHSPEED;
- COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
- COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
- COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
- COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
- COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
- COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
-
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
-
-#if defined (COMP_V1_1_0_0)
-
-#if defined (COMP1) || defined (COMP2)
-
-/** @addtogroup COMP_LL COMP
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup COMP_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of COMP hierarchical scope: */
-/* COMP instance. */
-
-#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
- ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
- || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
- )
-
-/* Note: On this STM32 serie, comparator input plus parameters are */
-/* the different depending on COMP instances. */
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
- (((__COMP_INSTANCE__) == COMP1) \
- ? ( \
- ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1) \
- ) \
- : \
- ( \
- ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
- ) \
- )
-
-/* Note: On this STM32 serie, comparator input minus parameters are */
-/* the same on all COMP instances. */
-/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
- ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
- || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
- )
-
-#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
- ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
- || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
- )
-
-/* Note: Output redirection is specific to COMP instances but is checked */
-/* with literals of instance COMP2 (no differentiation possible since */
-/* literals of COMP1 and COMP2 share the same values range). */
-#define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__) \
- ( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
- || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2) \
- )
-
-#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
- ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
- || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
- )
-
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup COMP_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of the selected COMP instance
- * to their default reset values.
- * @note If comparator is locked, de-initialization by software is
- * not possible.
- * The only way to unlock the comparator is a device hardware reset.
- * @param COMPx COMP instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: COMP registers are de-initialized
- * - ERROR: COMP registers are not de-initialized
- */
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* COMP instance must not be locked. */
- if(LL_COMP_IsLocked(COMPx) == 0U)
- {
- /* Note: Connection switch is applicable only to COMP instance COMP1, */
- /* therefore is COMP2 is selected the equivalent bit is */
- /* kept unmodified. */
- if(COMPx == COMP1)
- {
- CLEAR_BIT(COMP->CSR,
- ( COMP_CSR_COMP1MODE
- | COMP_CSR_COMP1INSEL
- | COMP_CSR_COMP1SW1
- | COMP_CSR_COMP1OUTSEL
- | COMP_CSR_COMP1HYST
- | COMP_CSR_COMP1POL
- | COMP_CSR_COMP1EN
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- );
- }
- else
- {
- CLEAR_BIT(COMP->CSR,
- ( COMP_CSR_COMP1MODE
- | COMP_CSR_COMP1INSEL
- | COMP_CSR_COMP1OUTSEL
- | COMP_CSR_COMP1HYST
- | COMP_CSR_COMP1POL
- | COMP_CSR_COMP1EN
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- );
- }
-
- }
- else
- {
- /* Comparator instance is locked: de-initialization by software is */
- /* not possible. */
- /* The only way to unlock the comparator is a device hardware reset. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of COMP instance.
- * @note This function configures features of the selected COMP instance.
- * Some features are also available at scope COMP common instance
- * (common to several COMP instances).
- * Refer to functions having argument "COMPxy_COMMON" as parameter.
- * @param COMPx COMP instance
- * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: COMP registers are initialized
- * - ERROR: COMP registers are not initialized
- */
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_INSTANCE(COMPx));
- assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
- assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
- assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
- assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
- assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
- assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
-
- /* Note: Hardware constraint (refer to description of this function) */
- /* COMP instance must not be locked. */
- if(LL_COMP_IsLocked(COMPx) == 0U)
- {
- /* Configuration of comparator instance : */
- /* - PowerMode */
- /* - InputPlus */
- /* - InputMinus */
- /* - InputHysteresis */
- /* - OutputSelection */
- /* - OutputPolarity */
- /* Note: Connection switch is applicable only to COMP instance COMP1, */
- /* therefore is COMP2 is selected the equivalent bit is */
- /* kept unmodified. */
- if(COMPx == COMP1)
- {
- MODIFY_REG(COMP->CSR,
- ( COMP_CSR_COMP1MODE
- | COMP_CSR_COMP1INSEL
- | COMP_CSR_COMP1SW1
- | COMP_CSR_COMP1OUTSEL
- | COMP_CSR_COMP1HYST
- | COMP_CSR_COMP1POL
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- ,
- ( COMP_InitStruct->PowerMode
- | COMP_InitStruct->InputPlus
- | COMP_InitStruct->InputMinus
- | COMP_InitStruct->InputHysteresis
- | COMP_InitStruct->OutputSelection
- | COMP_InitStruct->OutputPolarity
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- );
- }
- else
- {
- MODIFY_REG(COMP->CSR,
- ( COMP_CSR_COMP1MODE
- | COMP_CSR_COMP1INSEL
- | COMP_CSR_COMP1OUTSEL
- | COMP_CSR_COMP1HYST
- | COMP_CSR_COMP1POL
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- ,
- ( COMP_InitStruct->PowerMode
- | COMP_InitStruct->InputPlus
- | COMP_InitStruct->InputMinus
- | COMP_InitStruct->InputHysteresis
- | COMP_InitStruct->OutputSelection
- | COMP_InitStruct->OutputPolarity
- ) << __COMP_BITOFFSET_INSTANCE(COMPx)
- );
- }
-
- }
- else
- {
- /* Initialization error: COMP instance is locked. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
- * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
-{
- /* Set COMP_InitStruct fields to default values */
- COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER;
- COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
- COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
- COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
- COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
- COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* COMP1 || COMP2 */
-
-
-#endif /* STM32F373xC || STM32F378xx */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c
deleted file mode 100644
index 82b7925932e..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_crc.c
- * @author MCD Application Team
- * @brief CRC LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_crc.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (CRC)
-
-/** @addtogroup CRC_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup CRC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize CRC registers (Registers restored to their default values).
- * @param CRCx CRC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: CRC registers are de-initialized
- * - ERROR: CRC registers are not de-initialized
- */
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(CRCx));
-
- if (CRCx == CRC)
- {
- /* Set programmable polynomial size in CR register to reset value (32 bits)*/
- LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
-
- /* Set programmable polynomial in POL register to reset value */
- LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
-
- /* Set INIT register to reset value */
- LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
-
- /* Set Reversibility options on I/O data values in CR register to reset value */
- LL_CRC_SetInputDataReverseMode(CRCx, LL_CRC_INDATA_REVERSE_NONE);
- LL_CRC_SetOutputDataReverseMode(CRCx, LL_CRC_OUTDATA_REVERSE_NONE);
-
- /* Reset the CRC calculation unit */
- LL_CRC_ResetCRCCalculationUnit(CRCx);
-
- /* Reset IDR register */
- LL_CRC_Write_IDR(CRCx, 0x00U);
- }
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (CRC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c
deleted file mode 100644
index 6a5f393b4ef..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_dac.c
- * @author MCD Application Team
- * @brief DAC LL module driver
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_dac.h"
-#include "stm32f3xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (DAC1) || defined (DAC2)
-
-/** @addtogroup DAC_LL DAC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup DAC_LL_Private_Macros
- * @{
- */
-
-#if defined(DAC_CHANNEL2_SUPPORT)
-#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
- ( \
- ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
- )
-#else
-#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
- ( \
- ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- )
-#endif /* DAC_CHANNEL2_SUPPORT */
-
-#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-
-#elif defined(STM32F303x8) || defined(STM32F328xx)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-
-#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-
-#elif defined(STM32F301x8) || defined(STM32F318xx)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-
-#elif defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-
-#elif defined(STM32F334x8)
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG2) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG3) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-#endif
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
- ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
- )
-
-#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
- ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
- )
-
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of the selected DAC instance
- * to their default reset values.
- * @param DACx DAC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DAC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(DACx));
-
- if(DACx == DAC1)
- {
- /* Force reset of DAC clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
-
- /* Release reset of DAC clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
- }
-#if defined(DAC2)
- else
- {
- /* Force reset of DAC clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2);
-
- /* Release reset of DAC clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2);
- }
-#endif
- return SUCCESS;
-}
-
-/**
- * @brief Initialize some features of DAC instance.
- * @note The setting of these parameters by function @ref LL_DAC_Init()
- * is conditioned to DAC state:
- * DAC instance must be disabled.
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2 (1)
- *
- * (1) On this STM32 serie, parameter not available on all devices.
- * Refer to device datasheet for channels availability.
- * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DAC registers are initialized
- * - ERROR: DAC registers are not initialized
- */
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(DACx));
- assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
- assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
- assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
- assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
- if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
- {
- assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
- }
-
- /* Note: Hardware constraint (refer to description of this function) */
- /* DAC instance must be disabled. */
- if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
- {
- /* Configuration of DAC channel: */
- /* - TriggerSource */
- /* - WaveAutoGeneration */
- /* - OutputBuffer */
- if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
- {
- MODIFY_REG(DACx->CR,
- ( DAC_CR_TSEL1
- | DAC_CR_WAVE1
- | DAC_CR_MAMP1
- | DAC_CR_BOFF1
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- ,
- ( DAC_InitStruct->TriggerSource
- | DAC_InitStruct->WaveAutoGeneration
- | DAC_InitStruct->WaveAutoGenerationConfig
- | DAC_InitStruct->OutputBuffer
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
- }
- else
- {
- MODIFY_REG(DACx->CR,
- ( DAC_CR_TSEL1
- | DAC_CR_WAVE1
- | DAC_CR_BOFF1
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- ,
- ( DAC_InitStruct->TriggerSource
- | LL_DAC_WAVE_AUTO_GENERATION_NONE
- | DAC_InitStruct->OutputBuffer
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
- }
- }
- else
- {
- /* Initialization error: DAC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
- * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
-{
- /* Set DAC_InitStruct fields to default values */
- DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
- DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
- /* Note: Parameter discarded if wave auto generation is disabled, */
- /* set anyway to its default value. */
- DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
- DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC1 || DAC2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
deleted file mode 100644
index 99b1d5def07..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_dma.c
- * @author MCD Application Team
- * @brief DMA LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_dma.h"
-#include "stm32f3xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
- * @{
- */
-#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-
-#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#endif
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the DMA registers to their default reset values.
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are de-initialized
- * - ERROR: DMA registers are not de-initialized
- */
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
- ErrorStatus status = SUCCESS;
-
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Disable the selected DMAx_Channely */
- CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
- /* Reset DMAx_Channely control register */
- LL_DMA_WriteReg(tmp, CCR, 0U);
-
- /* Reset DMAx_Channely remaining bytes register */
- LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
- /* Reset DMAx_Channely peripheral address register */
- LL_DMA_WriteReg(tmp, CPAR, 0U);
-
- /* Reset DMAx_Channely memory address register */
- LL_DMA_WriteReg(tmp, CMAR, 0U);
-
-
- if (Channel == LL_DMA_CHANNEL_1)
- {
- /* Reset interrupt pending bits for DMAx Channel1 */
- LL_DMA_ClearFlag_GI1(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_2)
- {
- /* Reset interrupt pending bits for DMAx Channel2 */
- LL_DMA_ClearFlag_GI2(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_3)
- {
- /* Reset interrupt pending bits for DMAx Channel3 */
- LL_DMA_ClearFlag_GI3(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_4)
- {
- /* Reset interrupt pending bits for DMAx Channel4 */
- LL_DMA_ClearFlag_GI4(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_5)
- {
- /* Reset interrupt pending bits for DMAx Channel5 */
- LL_DMA_ClearFlag_GI5(DMAx);
- }
-
- else if (Channel == LL_DMA_CHANNEL_6)
- {
- /* Reset interrupt pending bits for DMAx Channel6 */
- LL_DMA_ClearFlag_GI6(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_7)
- {
- /* Reset interrupt pending bits for DMAx Channel7 */
- LL_DMA_ClearFlag_GI7(DMAx);
- }
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
- * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
- * @arg @ref __LL_DMA_GET_INSTANCE
- * @arg @ref __LL_DMA_GET_CHANNEL
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Check the DMA parameters from DMA_InitStruct */
- assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
- assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
- assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
- assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
- assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
- assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
- assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
- assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
- /*---------------------------- DMAx CCR Configuration ------------------------
- * Configure DMAx_Channely: data transfer direction, data transfer mode,
- * peripheral and memory increment mode,
- * data size alignment and priority level with parameters :
- * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
- * - Mode: DMA_CCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
- * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
- * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
- * - Priority: DMA_CCR_PL[1:0] bits
- */
- LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
- DMA_InitStruct->Mode | \
- DMA_InitStruct->PeriphOrM2MSrcIncMode | \
- DMA_InitStruct->MemoryOrM2MDstIncMode | \
- DMA_InitStruct->PeriphOrM2MSrcDataSize | \
- DMA_InitStruct->MemoryOrM2MDstDataSize | \
- DMA_InitStruct->Priority);
-
- /*-------------------------- DMAx CMAR Configuration -------------------------
- * Configure the memory or destination base address with parameter :
- * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
- */
- LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
- /*-------------------------- DMAx CPAR Configuration -------------------------
- * Configure the peripheral or source base address with parameter :
- * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
- */
- LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
- /*--------------------------- DMAx CNDTR Configuration -----------------------
- * Configure the peripheral base address with parameter :
- * - NbData: DMA_CNDTR_NDT[15:0] bits
- */
- LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
- * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval None
- */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
- DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
- DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
- DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
- DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = 0x00000000U;
- DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
deleted file mode 100644
index c21ffed0b92..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_exti.c
- * @author MCD Application Team
- * @brief EXTI LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_exti.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-#if defined(EXTI_32_63_SUPPORT)
-#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
-#endif
-
-#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the EXTI registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are de-initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_DeInit(void)
-{
- /* Interrupt mask register set to default reset values */
- LL_EXTI_WriteReg(IMR, 0x1F800000U);
- /* Event mask register set to default reset values */
- LL_EXTI_WriteReg(EMR, 0x00000000U);
- /* Rising Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(RTSR, 0x00000000U);
- /* Falling Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(FTSR, 0x00000000U);
- /* Software interrupt event register set to default reset values */
- LL_EXTI_WriteReg(SWIER, 0x00000000U);
- /* Pending register clear */
- LL_EXTI_WriteReg(PR, 0x007FFFFFU);
-
-#if defined(EXTI_32_63_SUPPORT)
- /* Interrupt mask register 2 set to default reset values */
-#if defined(STM32F334x8)
- LL_EXTI_WriteReg(IMR2, 0xFFFFFFFEU);
-#else
- LL_EXTI_WriteReg(IMR2, 0xFFFFFFFCU);
-#endif
- /* Event mask register 2 set to default reset values */
- LL_EXTI_WriteReg(EMR2, 0x00000000U);
- /* Rising Trigger selection register 2 set to default reset values */
- LL_EXTI_WriteReg(RTSR2, 0x00000000U);
- /* Falling Trigger selection register 2 set to default reset values */
- LL_EXTI_WriteReg(FTSR2, 0x00000000U);
- /* Software interrupt event register 2 set to default reset values */
- LL_EXTI_WriteReg(SWIER2, 0x00000000U);
- /* Pending register 2 clear */
- LL_EXTI_WriteReg(PR2, 0x00000003U);
-
-#endif
- return SUCCESS;
-}
-
-/**
- * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
- * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- ErrorStatus status = SUCCESS;
- /* Check the parameters */
- assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
-#if defined(EXTI_32_63_SUPPORT)
- assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
-#endif
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
- assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
- /* ENABLE LineCommand */
- if (EXTI_InitStruct->LineCommand != DISABLE)
- {
- assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
- /* Configure EXTI Lines in range from 0 to 31 */
- if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
- {
- switch (EXTI_InitStruct->Mode)
- {
- case LL_EXTI_MODE_IT:
- /* First Disable Event on provided Lines */
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_EVENT:
- /* First Disable IT on provided Lines */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Event on provided Lines */
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_IT_EVENT:
- /* Directly Enable IT & Event on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
- {
- switch (EXTI_InitStruct->Trigger)
- {
- case LL_EXTI_TRIGGER_RISING:
- /* First Disable Falling Trigger on provided Lines */
- LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Rising Trigger on provided Lines */
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_FALLING:
- /* First Disable Rising Trigger on provided Lines */
- LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Falling Trigger on provided Lines */
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_RISING_FALLING:
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- }
- }
-#if defined(EXTI_32_63_SUPPORT)
- /* Configure EXTI Lines in range from 32 to 63 */
- if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
- {
- switch (EXTI_InitStruct->Mode)
- {
- case LL_EXTI_MODE_IT:
- /* First Disable Event on provided Lines */
- LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
- break;
- case LL_EXTI_MODE_EVENT:
- /* First Disable IT on provided Lines */
- LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
- /* Then Enable Event on provided Lines */
- LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
- break;
- case LL_EXTI_MODE_IT_EVENT:
- /* Directly Enable IT & Event on provided Lines */
- LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
- LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
- break;
- default:
- status = ERROR;
- break;
- }
- if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
- {
- switch (EXTI_InitStruct->Trigger)
- {
- case LL_EXTI_TRIGGER_RISING:
- /* First Disable Falling Trigger on provided Lines */
- LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
- break;
- case LL_EXTI_TRIGGER_FALLING:
- /* First Disable Rising Trigger on provided Lines */
- LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
- /* Then Enable Falling Trigger on provided Lines */
- LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
- break;
- case LL_EXTI_TRIGGER_RISING_FALLING:
- LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
- LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
- break;
- default:
- status = ERROR;
- break;
- }
- }
- }
-#endif
- }
- /* DISABLE LineCommand */
- else
- {
- /* De-configure EXTI Lines in range from 0 to 31 */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-#if defined(EXTI_32_63_SUPPORT)
- /* De-configure EXTI Lines in range from 32 to 63 */
- LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
- LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
-#endif
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
- * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval None
- */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
-#if defined(EXTI_32_63_SUPPORT)
- EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
-#endif
- EXTI_InitStruct->LineCommand = DISABLE;
- EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
- EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (EXTI) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
deleted file mode 100644
index c5259795db6..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
+++ /dev/null
@@ -1,997 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_fmc.c
- * @author MCD Application Team
- * @brief FMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- =============================================================================
- ##### FMC peripheral features #####
- =============================================================================
- [..] The Flexible memory controller (FMC) includes following memory controllers:
- (+) The NOR/PSRAM memory controller
- (+) The PC Card memory controller
- (+) The NAND memory controller
-
- [..] The FMC functional block makes the interface with synchronous and asynchronous static
- memories and 16-bit PC memory cards. Its main purposes are:
- (+) to translate AHB transactions into the appropriate external device protocol.
- (+) to meet the access time requirements of the external memory devices.
-
- [..] All external memories share the addresses, data and control signals with the controller.
- Each external device is accessed by means of a unique Chip Select. The FMC performs
- only one access at a time to an external device.
- The main features of the FMC controller are the following:
- (+) Interface with static-memory mapped devices including:
- (++) Static random access memory (SRAM).
- (++) NOR Flash memory.
- (++) PSRAM (4 memory banks).
- (++) 16-bit PC Card compatible devices
- (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
- data
- (+) Independent Chip Select control for each memory bank
- (+) Independent configuration for each memory bank
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal.h"
-
-/** @addtogroup STM32F3xx_HAL_Driver
- * @{
- */
-
-#if defined(FMC_BANK1)
-
-#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
-
-/** @defgroup FMC_LL FMC Low Layer
- * @brief FMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
- * @{
- */
-
-/* ----------------------- FMC registers bit mask --------------------------- */
-/* --- PCR Register ---*/
-/* PCR register clear mask */
-#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN | \
- FMC_PCRx_PTYP | FMC_PCRx_PWID | \
- FMC_PCRx_ECCEN | FMC_PCRx_TCLR | \
- FMC_PCRx_TAR | FMC_PCRx_ECCPS))
-
-/* --- PMEM Register ---*/
-/* PMEM register clear mask */
-#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEMx_MEMSETx | FMC_PMEMx_MEMWAITx |\
- FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
-
-/* --- PATT Register ---*/
-/* PATT register clear mask */
-#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATTx_ATTSETx | FMC_PATTx_ATTWAITx |\
- FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
-
-/* --- BCR Register ---*/
-/* BCR register clear mask */
-#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
- FMC_BCRx_MTYP | FMC_BCRx_MWID |\
- FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
- FMC_BCRx_WAITPOL | FMC_BCRx_WRAPMOD |\
- FMC_BCRx_WAITCFG | FMC_BCRx_WREN |\
- FMC_BCRx_WAITEN | FMC_BCRx_EXTMOD |\
- FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW |\
- FMC_BCR1_CCLKEN))
-
-/* --- BTR Register ---*/
-/* BTR register clear mask */
-#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
- FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
- FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
- FMC_BTRx_ACCMOD))
-
-/* --- BWTR Register ---*/
-/* BWTR register clear mask */
-#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
- FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
-
-/* --- PIO4 Register ---*/
-/* PIO4 register clear mask */
-#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
- FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
- * @brief NORSRAM Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NORSRAM device driver #####
- ==============================================================================
-
- [..]
- This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
- to run the NORSRAM external devices.
-
- (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
- (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
- (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
- (+) FMC NORSRAM bank extended timing configuration using the function
- FMC_NORSRAM_Extended_Timing_Init()
- (+) FMC NORSRAM bank enable/disable write operation using the functions
- FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
-
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC NORSRAM interface
- (+) De-initialize the FMC NORSRAM interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the FMC_NORSRAM device according to the specified
- * control parameters in the FMC_NORSRAM_InitTypeDef
- * @param Device Pointer to NORSRAM device instance
- * @param Init Pointer to NORSRAM Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
- assert_param(IS_FMC_MUX(Init->DataAddressMux));
- assert_param(IS_FMC_MEMORY(Init->MemoryType));
- assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
- assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
- assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
- assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
- assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
- assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
- assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
- assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
- assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
-
- /* Disable NORSRAM Device */
- __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
-
- /* Set NORSRAM device control parameters */
- if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
- {
- MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
- | Init->DataAddressMux
- | Init->MemoryType
- | Init->MemoryDataWidth
- | Init->BurstAccessMode
- | Init->WaitSignalPolarity
- | Init->WrapMode
- | Init->WaitSignalActive
- | Init->WriteOperation
- | Init->WaitSignal
- | Init->ExtendedMode
- | Init->AsynchronousWait
- | Init->WriteBurst
- | Init->ContinuousClock
- )
- );
- }
- else
- {
- MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
- | Init->DataAddressMux
- | Init->MemoryType
- | Init->MemoryDataWidth
- | Init->BurstAccessMode
- | Init->WaitSignalPolarity
- | Init->WrapMode
- | Init->WaitSignalActive
- | Init->WriteOperation
- | Init->WaitSignal
- | Init->ExtendedMode
- | Init->AsynchronousWait
- | Init->WriteBurst
- | Init->ContinuousClock
- )
- );
- }
-
- /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
- if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
- {
- MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitialize the FMC_NORSRAM peripheral
- * @param Device Pointer to NORSRAM device instance
- * @param ExDevice Pointer to NORSRAM extended mode device instance
- * @param Bank NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Disable the FMC_NORSRAM device */
- __FMC_NORSRAM_DISABLE(Device, Bank);
-
- /* De-initialize the FMC_NORSRAM device */
- /* FMC_NORSRAM_BANK1 */
- if (Bank == FMC_NORSRAM_BANK1)
- {
- Device->BTCR[Bank] = 0x000030DB;
- }
- /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
- else
- {
- Device->BTCR[Bank] = 0x000030D2;
- }
-
- Device->BTCR[Bank + 1] = 0x0FFFFFFF;
- ExDevice->BWTR[Bank] = 0x0FFFFFFF;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the FMC_NORSRAM Timing according to the specified
- * parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device Pointer to NORSRAM device instance
- * @param Timing Pointer to NORSRAM Timing structure
- * @param Bank NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Set FMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1], \
- BTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \
- ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \
- ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \
- (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \
- (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \
- (Timing->AccessMode)));
-
- /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
- if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
- {
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
- tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
- MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
- * parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device Pointer to NORSRAM device instance
- * @param Timing Pointer to NORSRAM Timing structure
- * @param Bank NORSRAM bank number
- * @param ExtendedMode FMC Extended Mode
- * This parameter can be one of the following values:
- * @arg FMC_EXTENDED_MODE_DISABLE
- * @arg FMC_EXTENDED_MODE_ENABLE
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{
- /* Check the parameters */
- assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
-
- /* Set NORSRAM device timing register for write configuration, if extended mode is used */
- if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
- {
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Set NORSRAM device timing register for write configuration, if extended mode is used */
- MODIFY_REG(Device->BWTR[Bank], \
- BWTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
- ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \
- (Timing->AccessMode)));
- }
- else
- {
- Device->BWTR[Bank] = 0x0FFFFFFF;
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_NORSRAM_Group2 Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FMC_NORSRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FMC NORSRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically FMC_NORSRAM write operation.
- * @param Device Pointer to NORSRAM device instance
- * @param Bank NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Enable write operation */
- SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NORSRAM write operation.
- * @param Device Pointer to NORSRAM device instance
- * @param Bank NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Disable write operation */
- CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/** @defgroup FMC_NAND FMC NAND Controller functions
- * @brief NAND Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NAND device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FMC NAND banks in order
- to run the NAND external devices.
-
- (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
- (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
- (+) FMC NAND bank common space timing configuration using the function
- FMC_NAND_CommonSpace_Timing_Init()
- (+) FMC NAND bank attribute space timing configuration using the function
- FMC_NAND_AttributeSpace_Timing_Init()
- (+) FMC NAND bank enable/disable ECC correction feature using the functions
- FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
- (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC NAND interface
- (+) De-initialize the FMC NAND interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FMC_NAND device according to the specified
- * control parameters in the FMC_NAND_HandleTypeDef
- * @param Device Pointer to NAND device instance
- * @param Init Pointer to NAND Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Init->NandBank));
- assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
- assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
- assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
- assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
-
- /* Set NAND device control parameters */
- if (Init->NandBank == FMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
- FMC_PCR_MEMORY_TYPE_NAND |
- Init->MemoryDataWidth |
- Init->EccComputation |
- Init->ECCPageSize |
- ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
- ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
- FMC_PCR_MEMORY_TYPE_NAND |
- Init->MemoryDataWidth |
- Init->EccComputation |
- Init->ECCPageSize |
- ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
- ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
- }
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Initializes the FMC_NAND Common space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device Pointer to NAND device instance
- * @param Timing Pointer to NAND timing structure
- * @param Bank NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Set FMC_NAND device timing parameters */
- if (Bank == FMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device Pointer to NAND device instance
- * @param Timing Pointer to NAND timing structure
- * @param Bank NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Set FMC_NAND device timing parameters */
- if (Bank == FMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitialize the FMC_NAND device
- * @param Device Pointer to NAND device instance
- * @param Bank NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Disable the NAND Bank */
- __FMC_NAND_DISABLE(Device, Bank);
-
- /* De-initialize the NAND Bank */
- if (Bank == FMC_NAND_BANK2)
- {
- /* Set the FMC_NAND_BANK2 registers to their reset values */
- WRITE_REG(Device->PCR2, 0x00000018);
- WRITE_REG(Device->SR2, 0x00000040);
- WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
- WRITE_REG(Device->PATT2, 0xFCFCFCFC);
- }
- /* FMC_Bank3_NAND */
- else
- {
- /* Set the FMC_NAND_BANK3 registers to their reset values */
- WRITE_REG(Device->PCR3, 0x00000018);
- WRITE_REG(Device->SR3, 0x00000040);
- WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
- WRITE_REG(Device->PATT3, 0xFCFCFCFC);
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FMC_NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FMC NAND interface.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device Pointer to NAND device instance
- * @param Bank NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Enable ECC feature */
- if (Bank == FMC_NAND_BANK2)
- {
- SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
- }
- else
- {
- SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device Pointer to NAND device instance
- * @param Bank NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Disable ECC feature */
- if (Bank == FMC_NAND_BANK2)
- {
- CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
- }
- else
- {
- CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device Pointer to NAND device instance
- * @param ECCval Pointer to ECC value
- * @param Bank NAND bank number
- * @param Timeout Timeout wait value
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FIFO is empty */
- while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- if (Bank == FMC_NAND_BANK2)
- {
- /* Get the ECCR2 register value */
- *ECCval = (uint32_t)Device->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- *ECCval = (uint32_t)Device->ECCR3;
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD FMC PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use PCCARD device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FMC PCCARD bank in order
- to run the PCCARD/compact flash external devices.
-
- (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
- (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
- (+) FMC PCCARD bank common space timing configuration using the function
- FMC_PCCARD_CommonSpace_Timing_Init()
- (+) FMC PCCARD bank attribute space timing configuration using the function
- FMC_PCCARD_AttributeSpace_Timing_Init()
- (+) FMC PCCARD bank IO space timing configuration using the function
- FMC_PCCARD_IOSpace_Timing_Init()
-
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FMC PCCARD interface
- (+) De-initialize the FMC PCCARD interface
- (+) Configure the FMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FMC_PCCARD device according to the specified
- * control parameters in the FMC_PCCARD_HandleTypeDef
- * @param Device Pointer to PCCARD device instance
- * @param Init Pointer to PCCARD Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
- assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
- assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
-
- /* Set FMC_PCCARD device control parameters */
- MODIFY_REG(Device->PCR4,
- (FMC_PCRx_PTYP | FMC_PCRx_PWAITEN | FMC_PCRx_PWID |
- FMC_PCRx_TCLR | FMC_PCRx_TAR),
- (FMC_PCR_MEMORY_TYPE_PCCARD |
- Init->Waitfeature |
- FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
- (Init->TCLRSetupTime << POSITION_VAL(FMC_PCRx_TCLR)) |
- (Init->TARSetupTime << POSITION_VAL(FMC_PCRx_TAR))));
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device Pointer to PCCARD device instance
- * @param Timing Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set PCCARD timing parameters */
- MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
- (Timing->SetupTime |
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device Pointer to PCCARD device instance
- * @param Timing Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set PCCARD timing parameters */
- MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
- (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device Pointer to PCCARD device instance
- * @param Timing Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set FMC_PCCARD device timing parameters */
- MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
- (Timing->SetupTime | \
- (Timing->WaitSetupTime << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
- (Timing->HoldSetupTime << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
- (Timing->HiZSetupTime << POSITION_VAL(FMC_PIO4_IOHIZ4))));
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the FMC_PCCARD device
- * @param Device Pointer to PCCARD device instance
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
-{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
-
- /* Disable the FMC_PCCARD device */
- __FMC_PCCARD_DISABLE(Device);
-
- /* De-initialize the FMC_PCCARD device */
- WRITE_REG(Device->PCR4, 0x00000018);
- WRITE_REG(Device->SR4, 0x00000040);
- WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
- WRITE_REG(Device->PATT4, 0xFCFCFCFC);
- WRITE_REG(Device->PIO4, 0xFCFCFCFC);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
-
-#endif /* FMC_BANK1 */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
deleted file mode 100644
index 9766eedbb03..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_gpio.c
- * @author MCD Application Team
- * @brief GPIO LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_gpio.h"
-#include "stm32f3xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
-
-/** @addtogroup GPIO_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
- * @{
- */
-#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
- ((__VALUE__) == LL_GPIO_MODE_ANALOG))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
- ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
-
-#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
- ((__VALUE__) == LL_GPIO_PULL_UP) ||\
- ((__VALUE__) == LL_GPIO_PULL_DOWN))
-
-#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
- ((__VALUE__) == LL_GPIO_AF_1 ) ||\
- ((__VALUE__) == LL_GPIO_AF_2 ) ||\
- ((__VALUE__) == LL_GPIO_AF_3 ) ||\
- ((__VALUE__) == LL_GPIO_AF_4 ) ||\
- ((__VALUE__) == LL_GPIO_AF_5 ) ||\
- ((__VALUE__) == LL_GPIO_AF_6 ) ||\
- ((__VALUE__) == LL_GPIO_AF_7 ) ||\
- ((__VALUE__) == LL_GPIO_AF_8 ) ||\
- ((__VALUE__) == LL_GPIO_AF_9 ) ||\
- ((__VALUE__) == LL_GPIO_AF_10 ) ||\
- ((__VALUE__) == LL_GPIO_AF_11 ) ||\
- ((__VALUE__) == LL_GPIO_AF_12 ) ||\
- ((__VALUE__) == LL_GPIO_AF_13 ) ||\
- ((__VALUE__) == LL_GPIO_AF_14 ) ||\
- ((__VALUE__) == LL_GPIO_AF_15 ))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize GPIO registers (Registers restored to their default values).
- * @param GPIOx GPIO Port
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are de-initialized
- * - ERROR: Wrong GPIO Port
- */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
- /* Force and Release reset on clock of GPIOx Port */
- if (GPIOx == GPIOA)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
- }
- else if (GPIOx == GPIOB)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
- }
- else if (GPIOx == GPIOC)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
- }
-#if defined(GPIOD)
- else if (GPIOx == GPIOD)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
- }
-#endif /* GPIOD */
-#if defined(GPIOE)
- else if (GPIOx == GPIOE)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
- }
-#endif /* GPIOE */
-#if defined(GPIOF)
- else if (GPIOx == GPIOF)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
- }
-#endif /* GPIOF */
-#if defined(GPIOG)
- else if (GPIOx == GPIOG)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
- }
-#endif /* GPIOG */
-#if defined(GPIOH)
- else if (GPIOx == GPIOH)
- {
- LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
- LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
- }
-#endif /* GPIOH */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
- * @param GPIOx GPIO Port
- * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
- * that contains the configuration information for the specified GPIO peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
- * - ERROR: Not applicable
- */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00000000U;
- uint32_t currentpin = 0x00000000U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
- assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
- assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
- /* ------------------------- Configure the port pins ---------------- */
- /* Initialize pinpos on first pin set */
- pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
-
- /* Configure the port pins */
- while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
- {
- /* Get current io position */
- currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
-
- if (currentpin)
- {
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Speed mode parameters */
- assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
- /* Speed mode configuration */
- LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
- }
-
- /* Pull-up Pull down resistor configuration*/
- LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
- if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
- {
- /* Check Alternate parameter */
- assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
- /* Speed mode configuration */
- if (POSITION_VAL(currentpin) < 0x00000008U)
- {
- LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
- }
- else
- {
- LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
- }
- }
- }
- pinpos++;
- }
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
- return (SUCCESS);
-}
-
-/**
- * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
- * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
- GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
- GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
- GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
- GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c
deleted file mode 100644
index 8088b64e0e8..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_hrtim.c
- * @author MCD Application Team
- * @brief HRTIM LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_hrtim.h"
-#include "stm32f3xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (HRTIM1)
-
-/** @addtogroup HRTIM_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HRTIM_LL_Exported_Functions
- * @{
- */
-/**
- * @brief Set HRTIM instance registers to their reset values.
- * @param HRTIMx High Resolution Timer instance
- * @retval ErrorStatus enumeration value:
- * - SUCCESS: HRTIMx registers are de-initialized
- * - ERROR: invalid HRTIMx instance
- */
-ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
-{
- ErrorStatus result = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
-
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
-
- return result;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c
deleted file mode 100644
index 6d4e63501ac..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_i2c.c
- * @author MCD Application Team
- * @brief I2C LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_i2c.h"
-#include "stm32f3xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup I2C_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-
-#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
- ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
-
-#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
-
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
-
-#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
- ((__VALUE__) == LL_I2C_NACK))
-
-#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
- ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the I2C registers to their default reset values.
- * @param I2Cx I2C Instance.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are de-initialized
- * - ERROR: I2C registers are not de-initialized
- */
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the I2C Instance I2Cx */
- assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Force reset of I2C clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
-
- /* Release reset of I2C clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
- }
-#if defined(I2C2)
- else if (I2Cx == I2C2)
- {
- /* Force reset of I2C clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
-
- /* Release reset of I2C clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
-
- }
-#endif
-#if defined(I2C3)
- else if (I2Cx == I2C3)
- {
- /* Force reset of I2C clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
-
- /* Release reset of I2C clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
- }
-#endif
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
- * @param I2Cx I2C Instance.
- * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
-{
- /* Check the I2C Instance I2Cx */
- assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
- /* Check the I2C parameters from I2C_InitStruct */
- assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
- assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
- assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
- assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
- assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
- assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
-
- /* Disable the selected I2Cx Peripheral */
- LL_I2C_Disable(I2Cx);
-
- /*---------------------------- I2Cx CR1 Configuration ------------------------
- * Configure the analog and digital noise filters with parameters :
- * - AnalogFilter: I2C_CR1_ANFOFF bit
- * - DigitalFilter: I2C_CR1_DNF[3:0] bits
- */
- LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
-
- /*---------------------------- I2Cx TIMINGR Configuration --------------------
- * Configure the SDA setup, hold time and the SCL high, low period with parameter :
- * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
- * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
- */
- LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
-
- /* Enable the selected I2Cx Peripheral */
- LL_I2C_Enable(I2Cx);
-
- /*---------------------------- I2Cx OAR1 Configuration -----------------------
- * Disable, Configure and Enable I2Cx device own address 1 with parameters :
- * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
- * - OwnAddrSize: I2C_OAR1_OA1MODE bit
- */
- LL_I2C_DisableOwnAddress1(I2Cx);
- LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-
- /* OwnAdress1 == 0 is reserved for General Call address */
- if (I2C_InitStruct->OwnAddress1 != 0U)
- {
- LL_I2C_EnableOwnAddress1(I2Cx);
- }
-
- /*---------------------------- I2Cx MODE Configuration -----------------------
- * Configure I2Cx peripheral mode with parameter :
- * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
- */
- LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
-
- /*---------------------------- I2Cx CR2 Configuration ------------------------
- * Configure the ACKnowledge or Non ACKnowledge condition
- * after the address receive match code or next received byte with parameter :
- * - TypeAcknowledge: I2C_CR2_NACK bit
- */
- LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
- * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
- * @retval None
- */
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
-{
- /* Set I2C_InitStruct fields to default values */
- I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
- I2C_InitStruct->Timing = 0U;
- I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
- I2C_InitStruct->DigitalFilter = 0U;
- I2C_InitStruct->OwnAddress1 = 0U;
- I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
- I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c
deleted file mode 100644
index 8fea1cef972..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_opamp.c
- * @author MCD Application Team
- * @brief OPAMP LL module driver
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_opamp.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
-
-/** @addtogroup OPAMP_LL OPAMP
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup OPAMP_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of OPAMP hierarchical scope: */
-/* OPAMP instance. */
-
-#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) \
- ( ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE) \
- || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER) \
- || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA) \
- )
-
-/* Note: Comparator non-inverting inputs parameters are the same on all */
-/* OPAMP instances. */
-/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
-#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \
- ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \
- || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1) \
- || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2) \
- || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3) \
- )
-
-/* Note: Comparator non-inverting inputs parameters are the same on all */
-/* OPAMP instances. */
-/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
-#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__) \
- ( ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \
- || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \
- || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \
- )
-
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMP_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup OPAMP_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of the selected OPAMP instance
- * to their default reset values.
- * @note If comparator is locked, de-initialization by software is
- * not possible.
- * The only way to unlock the comparator is a device hardware reset.
- * @param OPAMPx OPAMP instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: OPAMP registers are de-initialized
- * - ERROR: OPAMP registers are not de-initialized
- */
-ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* OPAMP instance must not be locked. */
- if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
- {
- LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
- }
- else
- {
- /* OPAMP instance is locked: de-initialization by software is */
- /* not possible. */
- /* The only way to unlock the OPAMP is a device hardware reset. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of OPAMP instance.
- * @note This function reset bit of calibration mode to ensure
- * to be in functional mode, in order to have OPAMP parameters
- * (inputs selection, ...) set with the corresponding OPAMP mode
- * to be effective.
- * @param OPAMPx OPAMP instance
- * @param OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: OPAMP registers are initialized
- * - ERROR: OPAMP registers are not initialized
- */
-ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
- assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
- assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
-
- /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */
- /* or PGA with external capacitors for filtering circuit. */
- /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */
- /* not used (not connected to GPIO pin). */
- if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
- {
- assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
- }
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* OPAMP instance must not be locked. */
- if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
- {
- /* Configuration of OPAMP instance : */
- /* - Functional mode */
- /* - Input non-inverting */
- /* - Input inverting */
- /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode. */
- if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
- {
- MODIFY_REG(OPAMPx->CSR,
- OPAMP_CSR_CALON
- | OPAMP_CSR_VMSEL
- | OPAMP_CSR_VPSEL
- ,
- OPAMP_InitStruct->FunctionalMode
- | OPAMP_InitStruct->InputNonInverting
- | OPAMP_InitStruct->InputInverting
- );
- }
- else
- {
- MODIFY_REG(OPAMPx->CSR,
- OPAMP_CSR_CALON
- | OPAMP_CSR_VMSEL
- | OPAMP_CSR_VPSEL
- ,
- LL_OPAMP_MODE_FOLLOWER
- | OPAMP_InitStruct->InputNonInverting
- );
- }
- }
- else
- {
- /* Initialization error: OPAMP instance is locked. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
- * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
-{
- /* Set OPAMP_InitStruct fields to default values */
- OPAMP_InitStruct->FunctionalMode = LL_OPAMP_MODE_FOLLOWER;
- OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
- /* Note: Parameter discarded if OPAMP in functional mode follower, */
- /* set anyway to its default value. */
- OPAMP_InitStruct->InputInverting = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c
deleted file mode 100644
index 6ea12bd14fa..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_pwr.c
- * @author MCD Application Team
- * @brief PWR LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_pwr.h"
-#include "stm32f3xx_ll_bus.h"
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup PWR_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the PWR registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PWR registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_PWR_DeInit(void)
-{
- /* Force reset of PWR clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
- /* Release reset of PWR clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(PWR) */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
deleted file mode 100644
index ec5613f0f57..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
+++ /dev/null
@@ -1,1119 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_rcc.c
- * @author MCD Application Team
- * @brief RCC LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_rcc.h"
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Variables
- * @{
- */
-#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-const uint16_t aADCPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
-#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-#if defined(RCC_CFGR_SDPRE)
-const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
-#endif /* RCC_CFGR_SDPRE */
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
- * @{
- */
-#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
-#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
-#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
-#else
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
-#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
-
-#if defined(UART4) && defined(UART5)
-#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
-#elif defined(UART4)
-#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
-#elif defined(UART5)
-#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
-#endif /* UART4 && UART5*/
-
-#if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
-
-#elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
-
-#elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
-
-#else
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
-#endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
-
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
-
-#if defined(USB)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE)
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-#else
-#if defined(RCC_CFGR2_ADC1PRES)
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
-#elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
-#else /* RCC_CFGR2_ADCPRE12 */
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
-#endif /* RCC_CFGR2_ADC1PRES */
-#endif /* RCC_CFGR_ADCPRE */
-
-#if defined(RCC_CFGR_SDPRE)
-#define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
-#endif /* RCC_CFGR_SDPRE */
-
-#if defined(CEC)
-#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
-#endif /* CEC */
-
-#if defined(RCC_CFGR3_TIMSW)
-#if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
- && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
- && defined(RCC_CFGR3_TIM34SW)
-
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
-
-#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
- && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
- && defined(RCC_CFGR3_TIM34SW)
-
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
-
-#elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
- && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
- && !defined(RCC_CFGR3_TIM34SW)
-
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
-
-#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
- && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
- && !defined(RCC_CFGR3_TIM34SW)
-
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
-
-#elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
- && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
- && !defined(RCC_CFGR3_TIM34SW)
-
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
-
-#else
-#error "Miss macro"
-#endif /* RCC_CFGR3_TIMxSW */
-#endif /* RCC_CFGR3_TIMSW */
-
-#if defined(HRTIM1)
-#define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
- * @{
- */
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE and PLL OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RCC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_RCC_DeInit(void)
-{
- uint32_t vl_mask = 0U;
-
- /* Set HSION bit */
- LL_RCC_HSI_Enable();
-
- /* Set HSITRIM bits to the reset value*/
- LL_RCC_HSI_SetCalibTrimming(0x10U);
-
- /* Reset SW, HPRE, PPRE and MCOSEL bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
- LL_RCC_WriteReg(CFGR, vl_mask);
-
- /* Reset HSEON, CSSON, PLLON bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
- LL_RCC_WriteReg(CR, vl_mask);
-
- /* Reset HSEBYP bit */
- LL_RCC_HSE_DisableBypass();
-
- /* Reset CFGR register */
- LL_RCC_WriteReg(CFGR, 0x00000000U);
-
- /* Reset CFGR2 register */
- LL_RCC_WriteReg(CFGR2, 0x00000000U);
-
- /* Reset CFGR3 register */
- LL_RCC_WriteReg(CFGR3, 0x00000000U);
-
- /* Clear pending flags */
- vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
- SET_BIT(RCC->CIR, vl_mask);
-
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * and different peripheral clocks available on the device.
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
- * @note If SYSCLK source is PLL, function returns values based on
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- * @note (**) HSI_VALUE is a defined constant but the real value may vary
- * depending on the variations in voltage and temperature.
- * @note (***) HSE_VALUE is a defined constant, user has to ensure that
- * HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- * @note The result of this function could be incorrect when using fractional
- * value for HSE crystal.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- * @{
- */
-
-/**
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update structure fields. Otherwise, any
- * configuration based on this function will be incorrect.
- * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
- * @retval None
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
- /* Get SYSCLK frequency */
- RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-/**
- * @brief Return USARTx clock frequency
- * @param USARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USART1_CLKSOURCE
- * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
- * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
- *
- * (*) value not defined in all devices.
- * @retval USART clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
- */
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
-{
- uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
-#if defined(RCC_CFGR3_USART1SW)
- if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
- {
- /* USART1CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
-#if defined(RCC_CFGR3_USART1SW_PCLK1)
- case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-#else
- case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
- default:
- usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-#endif /* RCC_CFGR3_USART1SW_PCLK1 */
- break;
- }
- }
-#endif /* RCC_CFGR3_USART1SW */
-
-#if defined(RCC_CFGR3_USART2SW)
- if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
- {
- /* USART2CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-#endif /* RCC_CFGR3_USART2SW */
-
-#if defined(RCC_CFGR3_USART3SW)
- if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
- {
- /* USART3CLK clock frequency */
- switch (LL_RCC_GetUSARTClockSource(USARTxSource))
- {
- case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
- usart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- usart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- usart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
- default:
- usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-
-#endif /* RCC_CFGR3_USART3SW */
- return usart_frequency;
-}
-
-#if defined(UART4) || defined(UART5)
-/**
- * @brief Return UARTx clock frequency
- * @param UARTxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_UART4_CLKSOURCE
- * @arg @ref LL_RCC_UART5_CLKSOURCE
- * @retval UART clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
- */
-uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
-{
- uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
-
-#if defined(UART4)
- if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
- {
- /* UART4CLK clock frequency */
- switch (LL_RCC_GetUARTClockSource(UARTxSource))
- {
- case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
- uart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- uart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- uart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
- default:
- uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-#endif /* UART4 */
-
-#if defined(UART5)
- if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
- {
- /* UART5CLK clock frequency */
- switch (LL_RCC_GetUARTClockSource(UARTxSource))
- {
- case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
- uart_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady())
- {
- uart_frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady())
- {
- uart_frequency = LSE_VALUE;
- }
- break;
-
- case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
- default:
- uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- break;
- }
- }
-#endif /* UART5 */
-
- return uart_frequency;
-}
-#endif /* UART4 || UART5 */
-
-/**
- * @brief Return I2Cx clock frequency
- * @param I2CxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
- * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
- *
- * (*) value not defined in all devices
- * @retval I2C clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
- */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
-{
- uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
-
- /* I2C1 CLK clock frequency */
- if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
- {
- switch (LL_RCC_GetI2CClockSource(I2CxSource))
- {
- case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
- i2c_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
- default:
- if (LL_RCC_HSI_IsReady())
- {
- i2c_frequency = HSI_VALUE;
- }
- break;
- }
- }
-
-#if defined(RCC_CFGR3_I2C2SW)
- /* I2C2 CLK clock frequency */
- if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
- {
- switch (LL_RCC_GetI2CClockSource(I2CxSource))
- {
- case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
- i2c_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
- default:
- if (LL_RCC_HSI_IsReady())
- {
- i2c_frequency = HSI_VALUE;
- }
- break;
- }
- }
-#endif /*RCC_CFGR3_I2C2SW*/
-
-#if defined(RCC_CFGR3_I2C3SW)
- /* I2C3 CLK clock frequency */
- if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
- {
- switch (LL_RCC_GetI2CClockSource(I2CxSource))
- {
- case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
- i2c_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
- default:
- if (LL_RCC_HSI_IsReady())
- {
- i2c_frequency = HSI_VALUE;
- }
- break;
- }
- }
-#endif /*RCC_CFGR3_I2C3SW*/
-
- return i2c_frequency;
-}
-
-#if defined(RCC_CFGR_I2SSRC)
-/**
- * @brief Return I2Sx clock frequency
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval I2S clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
- uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
- /* I2S1CLK clock frequency */
- switch (LL_RCC_GetI2SClockSource(I2SxSource))
- {
- case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
- i2s_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
- default:
- i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
- break;
- }
-
- return i2s_frequency;
-}
-#endif /* RCC_CFGR_I2SSRC */
-#if defined(USB)
-/**
- * @brief Return USBx clock frequency
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval USB clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
- */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
- uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
- /* USBCLK clock frequency */
- switch (LL_RCC_GetUSBClockSource(USBxSource))
- {
- case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
- default:
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
- }
- break;
- }
-
- return usb_frequency;
-}
-#endif /* USB */
-
-#if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-/**
- * @brief Return ADCx clock frequency
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE (*)
- * @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
- * @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
- * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
- *
- * (*) value not defined in all devices
- * @retval ADC clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
-{
- uint32_t adc_prescaler = 0U;
- uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
-
- /* Get ADC prescaler */
- adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
-
-#if defined(RCC_CFGR_ADCPRE)
- /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
- adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
- / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
-#else
- if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
- {
- /* ADC frequency = HCLK frequency */
- adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
- }
- else
- {
- /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
- adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
- / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
- }
-#endif /* RCC_CFGR_ADCPRE */
-
- return adc_frequency;
-}
-#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-
-#if defined(RCC_CFGR_SDPRE)
-/**
- * @brief Return SDADCx clock frequency
- * @param SDADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_SDADC_CLKSOURCE
- * @retval SDADC clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
-{
- uint32_t sdadc_prescaler = 0U;
- uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
-
- /* Get SDADC prescaler */
- sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
-
- /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
- sdadc_frequency = RCC_GetSystemClockFreq()
- / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
-
- return sdadc_frequency;
-}
-#endif /*RCC_CFGR_SDPRE */
-
-#if defined(CEC)
-/**
- * @brief Return CECx clock frequency
- * @param CECxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_CEC_CLKSOURCE
- * @retval CEC clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
- */
-uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
-{
- uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
-
- /* CECCLK clock frequency */
- switch (LL_RCC_GetCECClockSource(CECxSource))
- {
- case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
- if (LL_RCC_HSI_IsReady())
- {
- cec_frequency = HSI_VALUE / 244U;
- }
- break;
-
- case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
- default:
- if (LL_RCC_LSE_IsReady())
- {
- cec_frequency = LSE_VALUE;
- }
- break;
- }
-
- return cec_frequency;
-}
-#endif /* CEC */
-
-#if defined(RCC_CFGR3_TIMSW)
-/**
- * @brief Return TIMx clock frequency
- * @param TIMxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_TIM1_CLKSOURCE
- * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
- * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
- *
- * (*) value not defined in all devices
- * @retval TIM clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
-{
- uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
-
- if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
- {
- /* TIM1CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM1 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM1_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM1 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-
-#if defined(RCC_CFGR3_TIM8SW)
- if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
- {
- /* TIM8CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM8 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM8_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM8 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM8SW*/
-
-#if defined(RCC_CFGR3_TIM15SW)
- if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
- {
- /* TIM15CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM15 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM15_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM15 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM15SW*/
-
-#if defined(RCC_CFGR3_TIM16SW)
- if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
- {
- /* TIM16CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM16 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM16_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM16 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM16SW*/
-
-#if defined(RCC_CFGR3_TIM17SW)
- if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
- {
- /* TIM17CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM17 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM17_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM17 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM17SW*/
-
-#if defined(RCC_CFGR3_TIM20SW)
- if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
- {
- /* TIM20CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as TIM20 clock source */
- tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM20_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM20 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM20SW*/
-
-#if defined(RCC_CFGR3_TIM2SW)
- if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
- {
- /* TIM2CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
- {
- /* PCLK1 used as TIM2 clock source */
- tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM2_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM2 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM2SW*/
-
-#if defined(RCC_CFGR3_TIM34SW)
- if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
- {
- /* TIM3/4 CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
- {
- /* PCLK1 used as TIM3/4 clock source */
- tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_TIM34_CLKSOURCE_PLL */
- {
- /* PLL clock used as TIM3/4 clock source */
- tim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- }
-#endif /*RCC_CFGR3_TIM34SW*/
-
- return tim_frequency;
-}
-#endif /*RCC_CFGR3_TIMSW*/
-
-#if defined(HRTIM1)
-/**
- * @brief Return HRTIMx clock frequency
- * @param HRTIMxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
- * @retval HRTIM clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
-{
- uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
-
- /* HRTIM1CLK clock frequency */
- if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
- {
- /* PCLK2 used as HRTIM1 clock source */
- hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
- }
- else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
- {
- /* PLL clock used as HRTIM1 clock source */
- hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
-
- return hrtim_frequency;
-}
-#endif /* HRTIM1 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Return SYSTEM clock frequency
- * @retval SYSTEM clock frequency (in Hz)
- */
-uint32_t RCC_GetSystemClockFreq(void)
-{
- uint32_t frequency = 0U;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (LL_RCC_GetSysClkSource())
- {
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- frequency = HSI_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- frequency = HSE_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
- frequency = RCC_PLL_GetFreqDomain_SYS();
- break;
-
- default:
- frequency = HSI_VALUE;
- break;
- }
-
- return frequency;
-}
-
-/**
- * @brief Return HCLK clock frequency
- * @param SYSCLK_Frequency SYSCLK clock frequency
- * @retval HCLK clock frequency (in Hz)
- */
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
- /* HCLK clock frequency */
- return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
- * @brief Return PCLK1 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK1 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK1 clock frequency */
- return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-
-/**
- * @brief Return PCLK2 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK2 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK2 clock frequency */
- return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
-}
-
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
- uint32_t pllinputfreq = 0U, pllsource = 0U;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
-
- /* Get PLL source */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE;
-#else
- case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE / 2U;
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
- break;
-
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE;
- break;
-
- default:
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- pllinputfreq = HSI_VALUE;
-#else
- pllinputfreq = HSI_VALUE / 2U;
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
- break;
- }
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
-#else
- return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
-#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c
deleted file mode 100644
index c26cc8d7a5a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c
+++ /dev/null
@@ -1,892 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_rtc.c
- * @author MCD Application Team
- * @brief RTC LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_rtc.h"
-#include "stm32f3xx_ll_cortex.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined(RTC)
-
-/** @addtogroup RTC_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Constants
- * @{
- */
-/* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
-#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
-
-/* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
- || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
-
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
-
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
-
-#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
- || ((__VALUE__) == LL_RTC_FORMAT_BCD))
-
-#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
- || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
-
-#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
-#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
-#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
-#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
-
-#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
- || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-
-#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
-
-#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
- || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
- || ((__VALUE__) == LL_RTC_MONTH_MAY) \
- || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
- || ((__VALUE__) == LL_RTC_MONTH_JULY) \
- || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
- || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
- || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
-
-#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
-
-#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
- || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
- || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
- || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
- || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
- || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
-
-#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
- || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
- || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
- || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
- || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
- || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
-
-
-#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
- ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
- ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
-
-
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RTC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-Initializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are de-initialized
- * - ERROR: RTC registers are not de-initialized
- */
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Reset TR, DR and CR registers */
- LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
-#if defined(RTC_WAKEUP_SUPPORT)
- LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
-#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
- /* Reset All CR bits except CR[2:0] */
-#if defined(RTC_WAKEUP_SUPPORT)
- LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
-#else
- LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
-#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
- LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
-
- /* Reset ISR register and exit initialization mode */
- LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
-
- /* Reset Tamper and alternate functions configuration register */
- LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
-
- /* Wait till the RTC RSF flag is set */
- status = LL_RTC_WaitForSynchro(RTCx);
- }
-
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTCx RTC Instance
- * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
- assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
- assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Set Hour Format */
- LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
-
- /* Configure Synchronous and Asynchronous prescaler factor */
- LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
- LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
-
- /* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTCx);
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
- * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
-{
- /* Set RTC_InitStruct fields to default values */
- RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
- RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
- RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
-}
-
-/**
- * @brief Set the RTC current time.
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
- }
- else
- {
- RTC_TimeStruct->TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
- }
- assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
- assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
- }
- else
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
- }
- else
- {
- RTC_TimeStruct->TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
- }
- assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
- assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
- }
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Check the input parameters format */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
- RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
- }
- else
- {
- LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
- __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
- __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
- }
-
- /* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
- {
- status = LL_RTC_WaitForSynchro(RTCx);
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
- RTC_TimeStruct->Hours = 0U;
- RTC_TimeStruct->Minutes = 0U;
- RTC_TimeStruct->Seconds = 0U;
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Day register is configured
- * - ERROR: RTC Day register is not configured
- */
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
- {
- RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
- }
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
- assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
- assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
- }
- else
- {
- assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
- assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
- assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
- }
- assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Check the input parameters format */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
- }
- else
- {
- LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
- __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
- }
-
- /* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
- {
- status = LL_RTC_WaitForSynchro(RTCx);
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
- * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
- RTC_DateStruct->Day = 1U;
- RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
- RTC_DateStruct->Year = 0U;
-}
-
-/**
- * @brief Set the RTC Alarm A.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use @ref LL_RTC_ALMA_Disable function).
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ALARMA registers are configured
- * - ERROR: ALARMA registers are not configured
- */
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
- assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
- assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
- }
- else
- {
- RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
- }
- assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
- assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- }
- else
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
- }
- else
- {
- RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
- }
-
- assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
- assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
- }
- }
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Select weekday selection */
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
- {
- /* Set the date for ALARM */
- LL_RTC_ALMA_DisableWeekday(RTCx);
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
- }
- else
- {
- LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- }
- else
- {
- /* Set the week day for ALARM */
- LL_RTC_ALMA_EnableWeekday(RTCx);
- LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
- }
-
- /* Configure the Alarm register */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
- RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
- }
- else
- {
- LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
- }
- /* Set ALARM mask */
- LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the RTC Alarm B.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (@ref LL_RTC_ALMB_Disable function).
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ALARMB registers are configured
- * - ERROR: ALARMB registers are not configured
- */
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
- assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
- assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
- }
- else
- {
- RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
- }
- assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
- assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- }
- else
- {
- if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
- {
- assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
- assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
- }
- else
- {
- RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
- }
-
- assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
- assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
- }
- }
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Select weekday selection */
- if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
- {
- /* Set the date for ALARM */
- LL_RTC_ALMB_DisableWeekday(RTCx);
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
- }
- else
- {
- LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
- }
- }
- else
- {
- /* Set the week day for ALARM */
- LL_RTC_ALMB_EnableWeekday(RTCx);
- LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
- }
-
- /* Configure the Alarm register */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
- RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
- }
- else
- {
- LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
- __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
- }
- /* Set ALARM mask */
- LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
- * Day = 1st day of the month/Mask = all fields are masked).
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
- RTC_AlarmStruct->AlarmTime.Hours = 0U;
- RTC_AlarmStruct->AlarmTime.Minutes = 0U;
- RTC_AlarmStruct->AlarmTime.Seconds = 0U;
-
- /* Alarm Day Settings : Day = 1st day of the month */
- RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
- RTC_AlarmStruct->AlarmDateWeekDay = 1U;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
-}
-
-/**
- * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
- * Day = 1st day of the month/Mask = all fields are masked).
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
- RTC_AlarmStruct->AlarmTime.Hours = 0U;
- RTC_AlarmStruct->AlarmTime.Minutes = 0U;
- RTC_AlarmStruct->AlarmTime.Seconds = 0U;
-
- /* Alarm Day Settings : Day = 1st day of the month */
- RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
- RTC_AlarmStruct->AlarmDateWeekDay = 1U;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * @ref LL_RTC_DisableWriteProtection before calling this function.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
-{
- __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
- ErrorStatus status = SUCCESS;
- uint32_t tmp = 0U;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Check if the Initialization mode is set */
- if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
- {
- /* Set the Initialization mode */
- LL_RTC_EnableInitMode(RTCx);
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout --;
- }
- tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
- }
- return status;
-}
-
-/**
- * @brief Exit the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * @ref LL_RTC_DisableWriteProtection before calling this function.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC exited from in Init mode
- * - ERROR: Not applicable
- */
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
-{
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Disable initialization mode */
- LL_RTC_DisableInitMode(RTCx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * @ref LL_RTC_DisableWriteProtection before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
-{
- __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
- ErrorStatus status = SUCCESS;
- uint32_t tmp = 0U;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Clear RSF flag */
- LL_RTC_ClearFlag_RS(RTCx);
-
- /* Wait the registers to be synchronised */
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 0U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout--;
- }
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
-
- if (status != ERROR)
- {
- timeout = RTC_SYNCHRO_TIMEOUT;
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout--;
- }
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
- }
-
- return (status);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RTC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c
deleted file mode 100644
index db2e222e341..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c
+++ /dev/null
@@ -1,635 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_spi.c
- * @author MCD Application Team
- * @brief SPI LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_spi.h"
-#include "stm32f3xx_ll_bus.h"
-#include "stm32f3xx_ll_rcc.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
-
-/** @addtogroup SPI_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
- * @{
- */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
- SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
- SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
- SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
- SPI_CR1_BIDIMODE)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
- * @{
- */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
- if (SPIx == SPI1)
- {
- /* Force reset of SPI clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- /* Release reset of SPI clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- status = SUCCESS;
- }
-#endif /* SPI1 */
-#if defined(SPI2)
- if (SPIx == SPI2)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- status = SUCCESS;
- }
-#endif /* SPI2 */
-#if defined(SPI3)
- if (SPIx == SPI3)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- status = SUCCESS;
- }
-#endif /* SPI3 */
-#if defined(SPI4)
- if (SPIx == SPI4)
- {
- /* Force reset of SPI clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
-
- /* Release reset of SPI clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
-
- status = SUCCESS;
- }
-#endif /* SPI4 */
-
- return status;
-}
-
-/**
- * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
- */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the SPI Instance SPIx*/
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
- /* Check the SPI parameters from SPI_InitStruct*/
- assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
- assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
- assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
- assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
- assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
- assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
- assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
- assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
- assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
- if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx CR1 Configuration ------------------------
- * Configure SPIx CR1 with parameters:
- * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
- * - Master/Slave Mode: SPI_CR1_MSTR bit
- * - ClockPolarity: SPI_CR1_CPOL bit
- * - ClockPhase: SPI_CR1_CPHA bit
- * - NSS management: SPI_CR1_SSM bit
- * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
- * - BitOrder: SPI_CR1_LSBFIRST bit
- * - CRCCalculation: SPI_CR1_CRCEN bit
- */
- MODIFY_REG(SPIx->CR1,
- SPI_CR1_CLEAR_MASK,
- SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
- SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
- SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
- SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
- /*---------------------------- SPIx CR2 Configuration ------------------------
- * Configure SPIx CR2 with parameters:
- * - DataWidth: DS[3:0] bits
- * - NSS management: SSOE bit
- */
- MODIFY_REG(SPIx->CR2,
- SPI_CR2_DS | SPI_CR2_SSOE,
- SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
-
- /*---------------------------- SPIx CRCPR Configuration ----------------------
- * Configure SPIx CRCPR with parameters:
- * - CRCPoly: CRCPOLY[15:0] bits
- */
- if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
- LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
- }
- status = SUCCESS;
- }
-
-#if defined (SPI_I2S_SUPPORT)
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
- return status;
-}
-
-/**
- * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- /* Set SPI_InitStruct fields to default values */
- SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
- SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
- SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
- SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
- SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
- SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
- SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
- SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
- SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
- SPI_InitStruct->CRCPoly = 7U;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
- * @{
- */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
- SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK 0x0002U
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
- * @{
- */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI/I2S registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
- return LL_SPI_DeInit(SPIx);
-}
-
-/**
- * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are Initialized
- * - ERROR: SPI registers are not Initialized
- */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- LL_RCC_ClocksTypeDef rcc_clocks;
- uint32_t sourceclock = 0U;
- ErrorStatus status = ERROR;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
- assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
- assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
- assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
- assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
- assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
- if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx I2SCFGR Configuration --------------------
- * Configure SPIx I2SCFGR with parameters:
- * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
- * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
- * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
- * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
- */
-
- /* Write to SPIx I2SCFGR */
- MODIFY_REG(SPIx->I2SCFGR,
- I2S_I2SCFGR_CLEAR_MASK,
- I2S_InitStruct->Mode | I2S_InitStruct->Standard |
- I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
- SPI_I2SCFGR_I2SMOD);
-
- /*---------------------------- SPIx I2SPR Configuration ----------------------
- * Configure SPIx I2SPR with parameters:
- * - MCLKOutput: SPI_I2SPR_MCKOE bit
- * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
- */
-
- /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
- * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
- */
- if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing)
- * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
- */
- if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 2U;
- }
-
- /* I2S Clock source is System clock: Get System Clock frequency */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = rcc_clocks.SYSCLK_Frequency;
-
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
- status = SUCCESS;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- /*--------------- Reset I2S init structure parameters values -----------------*/
- I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
- I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
- I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
- I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
- I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
- I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
-}
-
-/**
- * @brief Set linear and parity prescaler.
- * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
- * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
- * @param SPIx SPI Instance
- * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
- assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
- /* Write to SPIx I2SPR */
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
-/**
- * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
- * I2Sxext according to the specified parameters in the I2S_InitStruct.
- * @note The structure pointed by I2S_InitStruct parameter should be the same
- * used for the master I2S peripheral. In this case, if the master is
- * configured as transmitter, the slave will be receiver and vice versa.
- * Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
- * @param I2Sxext SPI Instance
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2Sxext registers are Initialized
- * - ERROR: I2Sxext registers are not Initialized
- */
-ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- uint16_t mode = 0U;
- ErrorStatus status = ERROR;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
- assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
- assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
- assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
- assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
- if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
- {
- /*---------------------------- SPIx I2SCFGR Configuration --------------------
- * Configure SPIx I2SCFGR with parameters:
- * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
- * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
- * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
- * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
- */
-
- /* Reset I2SPR registers */
- WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
-
- /* Get the mode to be configured for the extended I2S */
- if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
- {
- mode = LL_I2S_MODE_SLAVE_RX;
- }
- else
- {
- if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
- {
- mode = LL_I2S_MODE_SLAVE_TX;
- }
- }
-
- /* Write to SPIx I2SCFGR */
- MODIFY_REG(I2Sxext->I2SCFGR,
- I2S_I2SCFGR_CLEAR_MASK,
- I2S_InitStruct->Standard |
- I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
- SPI_I2SCFGR_I2SMOD | mode);
-
- status = SUCCESS;
- }
- return status;
-}
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c
deleted file mode 100644
index 24c93465f23..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c
+++ /dev/null
@@ -1,1465 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_tim.c
- * @author MCD Application Team
- * @brief TIM LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_tim.h"
-#include "stm32f3xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
-
-/** @addtogroup TIM_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
- * @{
- */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#if defined(TIM_CCMR1_OC1M_3)
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
-#else
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-#endif
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
-
-#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
-
-#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
-
-#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
-
-#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
-#if defined(TIM_BDTR_BKF)
-
-#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
-#endif /* TIM_BDTR_BKF */
-#if defined(TIM_BDTR_BK2E)
-
-#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
-
-#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
-
-#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
-#endif /* TIM_BDTR_BK2E */
-
-#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
- * @{
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-#if defined(TIM_CCER_CC5E)
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-#endif /* TIM_CCER_CC5E */
-#if defined(TIM_CCER_CC6E)
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-#endif /* TIM_CCER_CC6E */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Set TIMx registers to their reset values.
- * @param TIMx Timer instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: invalid TIMx instance
- */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
- ErrorStatus result = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
-
-
- if (TIMx == TIM2)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
- }
-
-#if defined(TIM1)
- else if (TIMx == TIM1)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
- }
-#endif
-#if defined(TIM3)
- else if (TIMx == TIM3)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
- }
-#endif
-#if defined(TIM4)
- else if (TIMx == TIM4)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
- }
-#endif
-#if defined(TIM5)
- else if (TIMx == TIM5)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
- }
-#endif
-#if defined(TIM6)
- else if (TIMx == TIM6)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
- }
-#endif
-#if defined(TIM7)
- else if (TIMx == TIM7)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
- }
-#endif
-#if defined(TIM8)
- else if (TIMx == TIM8)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
- }
-#endif
-#if defined(TIM12)
- else if (TIMx == TIM12)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
- }
-#endif
-#if defined(TIM13)
- else if (TIMx == TIM13)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
- }
-#endif
-#if defined(TIM14)
- else if (TIMx == TIM14)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
- }
-#endif
-#if defined(TIM15)
- else if (TIMx == TIM15)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
- }
-#endif
-#if defined(TIM16)
- else if (TIMx == TIM16)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
- }
-#endif
-#if defined(TIM17)
- else if (TIMx == TIM17)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
- }
-#endif
-#if defined(TIM18)
- else if (TIMx == TIM18)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
- }
-#endif
-#if defined(TIM19)
- else if (TIMx == TIM19)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
- }
-#endif
-#if defined(TIM20)
- else if (TIMx == TIM20)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
- }
-#endif
- else
- {
- result = ERROR;
- }
-
-
- return result;
-}
-
-/**
- * @brief Set the fields of the time base unit configuration data structure
- * to their default values.
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
- * @retval None
- */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- /* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
- TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
- TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
-}
-
-/**
- * @brief Configure the TIMx time base unit.
- * @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- uint32_t tmpcr1 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
- assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
- tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
- }
-
- /* Write to TIMx CR1 */
- LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
- /* Set the Autoreload value */
- LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
- /* Set the Prescaler value */
- LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter value (if applicable) immediately */
- LL_TIM_GenerateEvent_UPDATE(TIMx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx output channel configuration data
- * structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
- * @retval None
- */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- /* Set the default configuration */
- TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
- TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->CompareValue = 0x00000000U;
- TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
-}
-
-/**
- * @brief Configure the TIMx output channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @arg @ref LL_TIM_CHANNEL_CH5
- * @arg @ref LL_TIM_CHANNEL_CH6
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
- * @note OC5 and OC6 are not available for all F3 devices
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = OC1Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = OC2Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = OC3Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = OC4Config(TIMx, TIM_OC_InitStruct);
- break;
-#if defined(TIM_CCER_CC5E)
- case LL_TIM_CHANNEL_CH5:
- result = OC5Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH6:
- result = OC6Config(TIMx, TIM_OC_InitStruct);
- break;
-#endif /* TIM_CCER_CC5E */
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the TIMx input channel configuration data
- * structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
- * @retval None
- */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
- TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
- TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the TIMx input channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = IC1Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = IC2Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = IC3Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = IC4Config(TIMx, TIM_IC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
- * @retval None
- */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- /* Set the default configuration */
- TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
- TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the encoder interface of the timer instance.
- * @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Configure TI1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
- /* Configure TI2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
- /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Set encoder mode */
- LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-#if defined TIM_CR2_MMS2
-/**
- * @brief Set the fields of the TIMx Hall sensor interface configuration data
- * structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
- * @retval None
- */
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- /* Set the default configuration */
- TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_HallSensorInitStruct->CommutationDelay = 0U;
-}
-
-/**
- * @brief Configure the Hall sensor interface of the timer instance.
- * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
- * to the TI1 input channel
- * @note TIMx slave mode controller is configured in reset mode.
- Selected internal trigger is TI1F_ED.
- * @note Channel 1 is configured as input, IC1 is mapped on TRC.
- * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
- * between 2 changes on the inputs. It gives information about motor speed.
- * @note Channel 2 is configured in output PWM 2 mode.
- * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
- * @note OC2REF is selected as trigger output on TRGO.
- * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
- * when TIMx operates in Hall sensor interface mode.
- * @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
-
- /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
- tmpcr2 |= TIM_CR2_TI1S;
-
- /* OC2REF signal is used as trigger output (TRGO) */
- tmpcr2 |= LL_TIM_TRGO_OC2REF;
-
- /* Configure the slave mode controller */
- tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
- tmpsmcr |= LL_TIM_TS_TI1F_ED;
- tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
-
- /* Configure input channel 1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
-
- /* Configure input channel 2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
- tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
-
- /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx SMCR */
- LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- /* Write to TIMx CCR2 */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
-
- return SUCCESS;
-}
-#endif /* TIM_CR2_MMS2 */
-
-/**
- * @brief Set the fields of the Break and Dead Time configuration data structure
- * to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
- * @retval None
- */
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
- TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
- TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
- TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
- TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
-#if defined(TIM_BDTR_BKF)
- TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
-#endif /* TIM_BDTR_BKF */
-#if defined(TIM_BDTR_BK2E)
- TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
- TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
- TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
-#endif /* TIM_BDTR_BK2E */
- TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
-}
-
-/**
- * @brief Configure the Break and Dead Time feature of the timer instance.
- * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
- * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
- * can be necessary to configure all of them during the first write access to
- * the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a second break input.
- * @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Break and Dead Time is initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- uint32_t tmpbdtr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
- assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
- assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
- assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
- assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
- assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-#if defined(TIM_BDTR_BKF)
- if (IS_TIM_ADVANCED_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
- }
-#endif /* TIM_BDTR_BKF */
-#if defined(TIM_BDTR_BK2E)
-
- if (IS_TIM_BKIN2_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
- assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
- assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
-
- /* Set the BREAK2 input related BDTR bit-fields */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
- }
-#endif /* TIM_BDTR_BK2E */
-
- /* Set TIMx_BDTR */
- LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
- return SUCCESS;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
- * @{
- */
-/**
- * @brief Configure the TIMx output channel 1.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
- /* Set the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 2.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
-#endif
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 3.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
-#endif
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 4.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#else
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
-#endif
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-#if defined(TIM_CCER_CC5E)
-/**
- * @brief Configure the TIMx output channel 5.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
- * @note OC5 is not available for all F3 devices
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr3 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 5: Reset the CC5E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CCMR3 register value */
- tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the Output Idle state */
- MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
-
- }
-
- /* Write to TIMx CCMR3 */
- LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 6.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
- * @note OC6 is not available for all F3 devices
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr3 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 5: Reset the CC6E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CCMR3 register value */
- tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the Output Idle state */
- MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
- }
-
- /* Write to TIMx CCMR3 */
- LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-#endif /* TIM_CCER_CC5E */
-
-/**
- * @brief Configure the TIMx input channel 1.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC1E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC1P | TIM_CCER_CC1NP),
- (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 2.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC2P | TIM_CCER_CC2NP),
- ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 3.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC3E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC3P | TIM_CCER_CC3NP),
- ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 4.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC4P | TIM_CCER_CC4NP),
- ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
- return SUCCESS;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
deleted file mode 100644
index 48d09dda5e3..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_usart.c
- * @author MCD Application Team
- * @brief USART LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_usart.h"
-#include "stm32f3xx_ll_rcc.h"
-#include "stm32f3xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @addtogroup USART_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
- * @{
- */
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- * divided by the smallest oversampling used on the USART (i.e. 8) */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
-
-/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
-#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#if defined(USART_7BITS_SUPPORT)
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-#else
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-#endif
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize USART registers (Registers restored to their default values).
- * @param USARTx USART Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are de-initialized
- * - ERROR: USART registers are not de-initialized
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
-
- if (USARTx == USART1)
- {
- /* Force reset of USART clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
-
- /* Release reset of USART clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
- }
- else if (USARTx == USART2)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
- }
- else if (USARTx == USART3)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
- }
-#if defined(UART4)
- else if (USARTx == UART4)
- {
- /* Force reset of UART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
-
- /* Release reset of UART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
- }
-#endif /* UART4 */
-#if defined(UART5)
- else if (USARTx == UART5)
- {
- /* Force reset of UART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
-
- /* Release reset of UART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
- }
-#endif /* UART5 */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize USART registers according to the specified
- * parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
- * @param USARTx USART Instance
- * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are initialized according to USART_InitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
- ErrorStatus status = ERROR;
- uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-#if defined(STM32F303x8)||defined(STM32F334x8)||defined(STM32F328xx)||defined(STM32F301x8)||defined(STM32F302x8)||defined(STM32F318xx)
- LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
- assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
- assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
- assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
- assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
- assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
- assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR1 Configuration ---------------------
- * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
- * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
- * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
- * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
- * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
- */
- MODIFY_REG(USARTx->CR1,
- (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
- (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
- USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-
- /*---------------------------- USART CR2 Configuration ---------------------
- * Configure USARTx CR2 (Stop bits) with parameters:
- * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
- * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
- */
- LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
- /*---------------------------- USART CR3 Configuration ---------------------
- * Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
- */
- LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
- /*---------------------------- USART BRR Configuration ---------------------
- * Retrieve Clock frequency used for USART Peripheral
- */
- if (USARTx == USART1)
- {
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
- }
- else if (USARTx == USART2)
- {
-#if defined (RCC_CFGR3_USART2SW)
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
-#else
- /* USART2 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
- }
- else if (USARTx == USART3)
- {
-#if defined (RCC_CFGR3_USART3SW)
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
-#else
- /* USART3 clock is PCLK */
- LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
- periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
- }
-#if defined(UART4)
- else if (USARTx == UART4)
- {
- periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
- }
-#endif /* UART4 */
-#if defined(UART5)
- else if (USARTx == UART5)
- {
- periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
- }
-#endif /* UART5 */
- else
- {
- /* Nothing to do, as error code is already assigned to ERROR value */
- }
-
- /* Configure the USART Baud Rate :
- - valid baud rate value (different from 0) is required
- - Peripheral clock as returned by RCC service, should be valid (different from 0).
- */
- if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
- && (USART_InitStruct->BaudRate != 0U))
- {
- status = SUCCESS;
- LL_USART_SetBaudRate(USARTx,
- periphclk,
- USART_InitStruct->OverSampling,
- USART_InitStruct->BaudRate);
-
- /* Check BRR is greater than or equal to 16d */
- assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-
- /* Check BRR is greater than or equal to 16d */
- assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
- }
- }
- /* Endif (=> USART not in Disabled state => return ERROR) */
-
- return (status);
-}
-
-/**
- * @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
- /* Set USART_InitStruct fields to default values */
- USART_InitStruct->BaudRate = 9600U;
- USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
- USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
- USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
- USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
- USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
- USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
-}
-
-/**
- * @brief Initialize USART Clock related settings according to the
- * specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param USARTx USART Instance
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * that contains the Clock configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check USART Instance and Clock signal output parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
-
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
- }
- /* Else (USART not in Disabled state => return ERROR */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- /* Set LL_USART_ClockInitStruct fields with default values */
- USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c b/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
deleted file mode 100644
index 9e9e11f7f4a..00000000000
--- a/lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
+++ /dev/null
@@ -1,583 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f3xx_ll_utils.c
- * @author MCD Application Team
- * @brief UTILS LL module driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_ll_rcc.h"
-#include "stm32f3xx_ll_utils.h"
-#include "stm32f3xx_ll_system.h"
-#include "stm32f3xx_ll_pwr.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F3xx_LL_Driver
- * @{
- */
-
-/** @addtogroup UTILS_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
- * @{
- */
-
-/* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MAX 72000000U /*!< Frequency max for PLL output, in Hz */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
-
-/* Defines used for FLASH latency according to SYSCLK Frequency */
-#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
-#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
- * @{
- */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_16))
-
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_16))
-
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
-
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
- || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
- * @{
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
-#endif /* FLASH_ACR_LATENCY */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup UTILS_LL_EF_DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
- * @note When a RTOS is used, it is recommended to avoid changing the Systick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param HCLKFrequency HCLK frequency in Hz
- * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
- * @retval None
- */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
- /* Use frequency provided in argument */
- LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
- * @brief This function provides accurate delay (in milliseconds) based
- * on SysTick counter flag
- * @note When a RTOS is used, it is recommended to avoid using blocking delay
- * and use rather osDelay service.
- * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
- * will configure Systick to 1ms
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-void LL_mDelay(uint32_t Delay)
-{
- __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- /* Add this code to indicate that local variable is not used */
- ((void)tmp);
-
- /* Add a period to guaranty minimum wait */
- if (Delay < LL_MAX_DELAY)
- {
- Delay++;
- }
-
- while (Delay)
- {
- if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- {
- Delay--;
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_EF_SYSTEM
- * @brief System Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### System Configuration functions #####
- ===============================================================================
- [..]
- System, AHB and APB buses clocks configuration
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz.
- @endverbatim
- @internal
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
- (++) +-----------------------------------------------+
- (++) | Latency | SYSCLK clock frequency (MHz) |
- (++) |---------------|-------------------------------|
- (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- (++) |---------------|-------------------------------|
- (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- (++) |---------------|-------------------------------|
- (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- (++) +-----------------------------------------------+
- @endinternal
- * @{
- */
-
-/**
- * @brief This function sets directly SystemCoreClock CMSIS variable.
- * @note Variable can be calculated also through SystemCoreClockUpdate function.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @retval None
- */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
- /* HCLK clock frequency */
- SystemCoreClock = HCLKFrequency;
-}
-
-/**
- * @brief This function configures system clock with HSI as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed 72MHz
- * @note FLASH latency can be modified through this function.
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- /* Check PREDIV value */
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- /* Force PREDIV value to 2 */
- UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
- /* Enable HSI if not enabled */
- if (LL_RCC_HSI_IsReady() != 1U)
- {
- LL_RCC_HSI_Enable();
- while (LL_RCC_HSI_IsReady() != 1U)
- {
- /* Wait for HSI ready */
- }
- }
-
- /* Configure PLL */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief This function configures system clock with HSE as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed @ref UTILS_PLL_OUTPUT_MAX
- * @note FLASH latency can be modified through this function.
- * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
- * @param HSEBypass This parameter can be one of the following values:
- * @arg @ref LL_UTILS_HSEBYPASS_ON
- * @arg @ref LL_UTILS_HSEBYPASS_OFF
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
- assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
- /* Check PREDIV value */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
- /* Enable HSE if not enabled */
- if (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Check if need to enable HSE bypass feature or not */
- if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- {
- LL_RCC_HSE_EnableBypass();
- }
- else
- {
- LL_RCC_HSE_DisableBypass();
- }
-
- /* Enable HSE */
- LL_RCC_HSE_Enable();
- while (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Wait for HSE ready */
- }
- }
-
- /* Configure PLL */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param Frequency SYSCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if (Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if (Frequency > UTILS_LATENCY2_FREQ)
- {
- /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if (Frequency > UTILS_LATENCY1_FREQ)
- {
- /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
- }
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/**
- * @brief Function to check that PLL can be modified
- * @param PLL_InputFrequency PLL input frequency (in Hz)
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @retval PLL output frequency (in Hz)
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-
- /* Check different PLL parameters according to RM */
- /* The application software must set correctly the PLL multiplication factor to
- not exceed @ref UTILS_PLL_OUTPUT_MAX */
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
- return pllfreq;
-}
-
-/**
- * @brief Function to check that PLL can be modified
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PLL modification can be done
- * - ERROR: PLL is busy
- */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check if PLL is busy*/
- if (LL_RCC_PLL_IsReady() != 0U)
- {
- /* PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Function to enable PLL and switch system clock to PLL
- * @param SYSCLK_Frequency SYSCLK frequency
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: No problem to switch system to PLL
- * - ERROR: Problem to switch system to PLL
- */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t sysclk_frequency_current = 0U;
-
- assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
- assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
- assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
-
- /* Calculate current SYSCLK frequency */
- sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
-
- /* Increasing the number of wait states because of higher CPU frequency */
- if (sysclk_frequency_current < SYSCLK_Frequency)
- {
- /* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-
- /* Update system clock configuration */
- if (status == SUCCESS)
- {
- /* Enable PLL */
- LL_RCC_PLL_Enable();
- while (LL_RCC_PLL_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Sysclk activation on the main PLL */
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- {
- /* Wait for system clock switch to PLL */
- }
-
- /* Set APB1 & APB2 prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if (sysclk_frequency_current > SYSCLK_Frequency)
- {
- /* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-
- /* Update SystemCoreClock variable */
- if (status == SUCCESS)
- {
- LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h
deleted file mode 100644
index 7da2e5688de..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_audio.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief header file for the usbd_audio.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_AUDIO_H
-#define __USB_AUDIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_AUDIO
- * @brief This file is the Header file for usbd_audio.c
- * @{
- */
-
-
-/** @defgroup USBD_AUDIO_Exported_Defines
- * @{
- */
-#define AUDIO_OUT_EP 0x01
-#define USB_AUDIO_CONFIG_DESC_SIZ 109
-#define AUDIO_INTERFACE_DESC_SIZE 9
-#define USB_AUDIO_DESC_SIZ 0x09
-#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09
-#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07
-
-#define AUDIO_DESCRIPTOR_TYPE 0x21
-#define USB_DEVICE_CLASS_AUDIO 0x01
-#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
-#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
-#define AUDIO_PROTOCOL_UNDEFINED 0x00
-#define AUDIO_STREAMING_GENERAL 0x01
-#define AUDIO_STREAMING_FORMAT_TYPE 0x02
-
-/* Audio Descriptor Types */
-#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24
-#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25
-
-/* Audio Control Interface Descriptor Subtypes */
-#define AUDIO_CONTROL_HEADER 0x01
-#define AUDIO_CONTROL_INPUT_TERMINAL 0x02
-#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03
-#define AUDIO_CONTROL_FEATURE_UNIT 0x06
-
-#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C
-#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09
-#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07
-
-#define AUDIO_CONTROL_MUTE 0x0001
-
-#define AUDIO_FORMAT_TYPE_I 0x01
-#define AUDIO_FORMAT_TYPE_III 0x03
-
-#define AUDIO_ENDPOINT_GENERAL 0x01
-
-#define AUDIO_REQ_GET_CUR 0x81
-#define AUDIO_REQ_SET_CUR 0x01
-
-#define AUDIO_OUT_STREAMING_CTRL 0x02
-
-
-#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000))
-#define AUDIO_DEFAULT_VOLUME 70
-
-/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure
- that it is an even number and higher than 3 */
-#define AUDIO_OUT_PACKET_NUM 80
-/* Total size of the audio transfer buffer */
-#define AUDIO_TOTAL_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * AUDIO_OUT_PACKET_NUM))
-
- /* Audio Commands enumeration */
-typedef enum
-{
- AUDIO_CMD_START = 1,
- AUDIO_CMD_PLAY,
- AUDIO_CMD_STOP,
-}AUDIO_CMD_TypeDef;
-
-
-typedef enum
-{
- AUDIO_OFFSET_NONE = 0,
- AUDIO_OFFSET_HALF,
- AUDIO_OFFSET_FULL,
- AUDIO_OFFSET_UNKNOWN,
-}
-AUDIO_OffsetTypeDef;
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
- typedef struct
-{
- uint8_t cmd;
- uint8_t data[USB_MAX_EP0_SIZE];
- uint8_t len;
- uint8_t unit;
-}
-USBD_AUDIO_ControlTypeDef;
-
-
-
-typedef struct
-{
- __IO uint32_t alt_setting;
- uint8_t buffer[AUDIO_TOTAL_BUF_SIZE];
- AUDIO_OffsetTypeDef offset;
- uint8_t rd_enable;
- uint16_t rd_ptr;
- uint16_t wr_ptr;
- USBD_AUDIO_ControlTypeDef control;
-}
-USBD_AUDIO_HandleTypeDef;
-
-
-typedef struct
-{
- int8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options);
- int8_t (*DeInit) (uint32_t options);
- int8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd);
- int8_t (*VolumeCtl) (uint8_t vol);
- int8_t (*MuteCtl) (uint8_t cmd);
- int8_t (*PeriodicTC) (uint8_t cmd);
- int8_t (*GetState) (void);
-}USBD_AUDIO_ItfTypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_AUDIO;
-#define USBD_AUDIO_CLASS &USBD_AUDIO
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_AUDIO_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_AUDIO_ItfTypeDef *fops);
-
-void USBD_AUDIO_Sync (USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_AUDIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio_if_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio_if_template.h
deleted file mode 100644
index 22debd815ff..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio_if_template.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_audio_if_template.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for usbd_audio_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_AUDIO_IF_TEMPLATE_H
-#define __USBD_AUDIO_IF_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_audio.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-extern USBD_AUDIO_ItfTypeDef USBD_AUDIO_Template_fops;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_AUDIO_IF_TEMPLATE_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c
deleted file mode 100644
index 6368a1d5f0a..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c
+++ /dev/null
@@ -1,791 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_audio.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the Audio core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * AUDIO Class Description
- * ===================================================================
- * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for
- * Audio Devices V1.0 Mar 18, 98".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Standard AC Interface Descriptor management
- * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)
- * - 1 Audio Streaming Endpoint
- * - 1 Audio Terminal Input (1 channel)
- * - Audio Class-Specific AC Interfaces
- * - Audio Class-Specific AS Interfaces
- * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)
- * - Audio Feature Unit (limited to Mute control)
- * - Audio Synchronization type: Asynchronous
- * - Single fixed audio sampling rate (configurable in usbd_conf.h file)
- * The current audio class version supports the following audio features:
- * - Pulse Coded Modulation (PCM) format
- * - sampling rate: 48KHz.
- * - Bit resolution: 16
- * - Number of channels: 2
- * - No volume control
- * - Mute/Unmute capability
- * - Asynchronous Endpoints
- *
- * @note In HS mode and when the DMA is used, all variables and data structures
- * dealing with the DMA during the transaction process should be 32-bit aligned.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_audio.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_AUDIO
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_AUDIO_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_AUDIO_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_AUDIO_Private_Macros
- * @{
- */
-#define AUDIO_SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
-
-#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \
- (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF)
-
-/**
- * @}
- */
-
-
-
-
-/** @defgroup USBD_AUDIO_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_AUDIO_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_AUDIO_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_AUDIO_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t *USBD_AUDIO_GetCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t USBD_AUDIO_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_AUDIO_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_AUDIO_EP0_RxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_AUDIO_EP0_TxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_AUDIO_SOF (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_AUDIO_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_AUDIO_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-/**
- * @}
- */
-
-/** @defgroup USBD_AUDIO_Private_Variables
- * @{
- */
-
-USBD_ClassTypeDef USBD_AUDIO =
-{
- USBD_AUDIO_Init,
- USBD_AUDIO_DeInit,
- USBD_AUDIO_Setup,
- USBD_AUDIO_EP0_TxReady,
- USBD_AUDIO_EP0_RxReady,
- USBD_AUDIO_DataIn,
- USBD_AUDIO_DataOut,
- USBD_AUDIO_SOF,
- USBD_AUDIO_IsoINIncomplete,
- USBD_AUDIO_IsoOutIncomplete,
- USBD_AUDIO_GetCfgDesc,
- USBD_AUDIO_GetCfgDesc,
- USBD_AUDIO_GetCfgDesc,
- USBD_AUDIO_GetDeviceQualifierDesc,
-};
-
-/* USB AUDIO device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- /* Configuration 1 */
- 0x09, /* bLength */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType */
- LOBYTE(USB_AUDIO_CONFIG_DESC_SIZ), /* wTotalLength 109 bytes*/
- HIBYTE(USB_AUDIO_CONFIG_DESC_SIZ),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue */
- 0x00, /* iConfiguration */
- 0xC0, /* bmAttributes BUS Powred*/
- 0x32, /* bMaxPower = 100 mA*/
- /* 09 byte*/
-
- /* USB Speaker Standard interface descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType */
- 0x00, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Class-specific AC Interface Descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */
- 0x00, /* 1.00 */ /* bcdADC */
- 0x01,
- 0x27, /* wTotalLength = 39*/
- 0x00,
- 0x01, /* bInCollection */
- 0x01, /* baInterfaceNr */
- /* 09 byte*/
-
- /* USB Speaker Input Terminal Descriptor */
- AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalID */
- 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */
- 0x01,
- 0x00, /* bAssocTerminal */
- 0x01, /* bNrChannels */
- 0x00, /* wChannelConfig 0x0000 Mono */
- 0x00,
- 0x00, /* iChannelNames */
- 0x00, /* iTerminal */
- /* 12 byte*/
-
- /* USB Speaker Audio Feature Unit Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */
- AUDIO_OUT_STREAMING_CTRL, /* bUnitID */
- 0x01, /* bSourceID */
- 0x01, /* bControlSize */
- AUDIO_CONTROL_MUTE,// |AUDIO_CONTROL_VOLUME, /* bmaControls(0) */
- 0, /* bmaControls(1) */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /*USB Speaker Output Terminal Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */
- 0x03, /* bTerminalID */
- 0x01, /* wTerminalType 0x0301*/
- 0x03,
- 0x00, /* bAssocTerminal */
- 0x02, /* bSourceID */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */
- /* Interface 1, Alternate Setting 0 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
- /* Interface 1, Alternate Setting 1 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x01, /* bAlternateSetting */
- 0x01, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Audio Streaming Interface Descriptor */
- AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalLink */
- 0x01, /* bDelay */
- 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/
- 0x00,
- /* 07 byte*/
-
- /* USB Speaker Audio Type III Format Interface Descriptor */
- 0x0B, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */
- AUDIO_FORMAT_TYPE_III, /* bFormatType */
- 0x02, /* bNrChannels */
- 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */
- 16, /* bBitResolution (16-bits per sample) */
- 0x01, /* bSamFreqType only one frequency supported */
- AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */
- /* 11 byte*/
-
- /* Endpoint 1 - Standard Descriptor */
- AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType */
- AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/
- USBD_EP_TYPE_ISOC, /* bmAttributes */
- AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */
- 0x01, /* bInterval */
- 0x00, /* bRefresh */
- 0x00, /* bSynchAddress */
- /* 09 byte*/
-
- /* Endpoint - Audio Streaming Descriptor*/
- AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */
- AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_ENDPOINT_GENERAL, /* bDescriptor */
- 0x00, /* bmAttributes */
- 0x00, /* bLockDelayUnits */
- 0x00, /* wLockDelay */
- 0x00,
- /* 07 byte*/
-} ;
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_AUDIO_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END=
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_AUDIO_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_AUDIO_Init
- * Initialize the AUDIO interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_AUDIO_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
-
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- AUDIO_OUT_EP,
- USBD_EP_TYPE_ISOC,
- AUDIO_OUT_PACKET);
-
- /* Allocate Audio structure */
- pdev->pClassData = USBD_malloc(sizeof (USBD_AUDIO_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- return USBD_FAIL;
- }
- else
- {
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
- haudio->alt_setting = 0;
- haudio->offset = AUDIO_OFFSET_UNKNOWN;
- haudio->wr_ptr = 0;
- haudio->rd_ptr = 0;
- haudio->rd_enable = 0;
-
- /* Initialize the Audio output Hardware layer */
- if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ, AUDIO_DEFAULT_VOLUME, 0) != USBD_OK)
- {
- return USBD_FAIL;
- }
-
- /* Prepare Out endpoint to receive 1st packet */
- USBD_LL_PrepareReceive(pdev,
- AUDIO_OUT_EP,
- haudio->buffer,
- AUDIO_OUT_PACKET);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_AUDIO_Init
- * DeInitialize the AUDIO layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_AUDIO_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
-
- /* Open EP OUT */
- USBD_LL_CloseEP(pdev,
- AUDIO_OUT_EP);
-
- /* DeInit physical Interface components */
- if(pdev->pClassData != NULL)
- {
- ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->DeInit(0);
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_AUDIO_Setup
- * Handle the AUDIO specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_AUDIO_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
- uint16_t len;
- uint8_t *pbuf;
- uint8_t ret = USBD_OK;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case AUDIO_REQ_GET_CUR:
- AUDIO_REQ_GetCurrent(pdev, req);
- break;
-
- case AUDIO_REQ_SET_CUR:
- AUDIO_REQ_SetCurrent(pdev, req);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- ret = USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
- {
- pbuf = USBD_AUDIO_CfgDesc + 18;
- len = MIN(USB_AUDIO_DESC_SIZ , req->wLength);
-
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- }
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&(haudio->alt_setting),
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES)
- {
- haudio->alt_setting = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
-
- default:
- USBD_CtlError (pdev, req);
- ret = USBD_FAIL;
- }
- }
- return ret;
-}
-
-
-/**
- * @brief USBD_AUDIO_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_AUDIO_GetCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_AUDIO_CfgDesc);
- return USBD_AUDIO_CfgDesc;
-}
-
-/**
- * @brief USBD_AUDIO_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_AUDIO_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- /* Only OUT data are processed */
- return USBD_OK;
-}
-
-/**
- * @brief USBD_AUDIO_EP0_RxReady
- * handle EP0 Rx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_AUDIO_EP0_RxReady (USBD_HandleTypeDef *pdev)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- if (haudio->control.cmd == AUDIO_REQ_SET_CUR)
- {/* In this driver, to simplify code, only SET_CUR request is managed */
-
- if (haudio->control.unit == AUDIO_OUT_STREAMING_CTRL)
- {
- ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->MuteCtl(haudio->control.data[0]);
- haudio->control.cmd = 0;
- haudio->control.len = 0;
- }
- }
-
- return USBD_OK;
-}
-/**
- * @brief USBD_AUDIO_EP0_TxReady
- * handle EP0 TRx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_AUDIO_EP0_TxReady (USBD_HandleTypeDef *pdev)
-{
- /* Only OUT control data are processed */
- return USBD_OK;
-}
-/**
- * @brief USBD_AUDIO_SOF
- * handle SOF event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_AUDIO_SOF (USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
- * @brief USBD_AUDIO_SOF
- * handle SOF event
- * @param pdev: device instance
- * @retval status
- */
-void USBD_AUDIO_Sync (USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset)
-{
- int8_t shift = 0;
- USBD_AUDIO_HandleTypeDef *haudio;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- haudio->offset = offset;
-
-
- if(haudio->rd_enable == 1)
- {
- haudio->rd_ptr += AUDIO_TOTAL_BUF_SIZE/2;
-
- if (haudio->rd_ptr == AUDIO_TOTAL_BUF_SIZE)
- {
- /* roll back */
- haudio->rd_ptr = 0;
- }
- }
-
- if(haudio->rd_ptr > haudio->wr_ptr)
- {
- if((haudio->rd_ptr - haudio->wr_ptr) < AUDIO_OUT_PACKET)
- {
- shift = -4;
- }
- else if((haudio->rd_ptr - haudio->wr_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
- {
- shift = 4;
- }
-
- }
- else
- {
- if((haudio->wr_ptr - haudio->rd_ptr) < AUDIO_OUT_PACKET)
- {
- shift = 4;
- }
- else if((haudio->wr_ptr - haudio->rd_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))
- {
- shift = -4;
- }
- }
-
- if(haudio->offset == AUDIO_OFFSET_FULL)
- {
- ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
- AUDIO_TOTAL_BUF_SIZE/2 - shift,
- AUDIO_CMD_PLAY);
- haudio->offset = AUDIO_OFFSET_NONE;
- }
-}
-
-/**
- * @brief USBD_AUDIO_IsoINIncomplete
- * handle data ISO IN Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_AUDIO_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_AUDIO_IsoOutIncomplete
- * handle data ISO OUT Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_AUDIO_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_AUDIO_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_AUDIO_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- if (epnum == AUDIO_OUT_EP)
- {
- /* Increment the Buffer pointer or roll it back when all buffers are full */
-
- haudio->wr_ptr += AUDIO_OUT_PACKET;
-
- if (haudio->wr_ptr == AUDIO_TOTAL_BUF_SIZE)
- {/* All buffers are full: roll back */
- haudio->wr_ptr = 0;
-
- if(haudio->offset == AUDIO_OFFSET_UNKNOWN)
- {
- ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],
- AUDIO_TOTAL_BUF_SIZE/2,
- AUDIO_CMD_START);
- haudio->offset = AUDIO_OFFSET_NONE;
- }
- }
-
- if(haudio->rd_enable == 0)
- {
- if (haudio->wr_ptr == (AUDIO_TOTAL_BUF_SIZE / 2))
- {
- haudio->rd_enable = 1;
- }
- }
-
- /* Prepare Out endpoint to receive next audio packet */
- USBD_LL_PrepareReceive(pdev,
- AUDIO_OUT_EP,
- &haudio->buffer[haudio->wr_ptr],
- AUDIO_OUT_PACKET);
-
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief AUDIO_Req_GetCurrent
- * Handles the GET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- memset(haudio->control.data, 0, 64);
- /* Send the current mute state */
- USBD_CtlSendData (pdev,
- haudio->control.data,
- req->wLength);
-}
-
-/**
- * @brief AUDIO_Req_SetCurrent
- * Handles the SET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_AUDIO_HandleTypeDef *haudio;
- haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;
-
- if (req->wLength)
- {
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- haudio->control.data,
- req->wLength);
-
- haudio->control.cmd = AUDIO_REQ_SET_CUR; /* Set the request value */
- haudio->control.len = req->wLength; /* Set the request data length */
- haudio->control.unit = HIBYTE(req->wIndex); /* Set the request target unit */
- }
-}
-
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc (uint16_t *length)
-{
- *length = sizeof (USBD_AUDIO_DeviceQualifierDesc);
- return USBD_AUDIO_DeviceQualifierDesc;
-}
-
-/**
-* @brief USBD_AUDIO_RegisterInterface
-* @param fops: Audio interface callback
-* @retval status
-*/
-uint8_t USBD_AUDIO_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_AUDIO_ItfTypeDef *fops)
-{
- if(fops != NULL)
- {
- pdev->pUserData= fops;
- }
- return 0;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c
deleted file mode 100644
index 7fe5f4e9c76..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_audio_if_template.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_AUDIO
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_AUDIO_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_AUDIO_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_AUDIO_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_AUDIO_Private_FunctionPrototypes
- * @{
- */
-
-static int8_t TEMPLATE_Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options);
-static int8_t TEMPLATE_DeInit (uint32_t options);
-static int8_t TEMPLATE_AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd);
-static int8_t TEMPLATE_VolumeCtl (uint8_t vol);
-static int8_t TEMPLATE_MuteCtl (uint8_t cmd);
-static int8_t TEMPLATE_PeriodicTC (uint8_t cmd);
-static int8_t TEMPLATE_GetState (void);
-
-USBD_AUDIO_ItfTypeDef USBD_AUDIO_Template_fops =
-{
- TEMPLATE_Init,
- TEMPLATE_DeInit,
- TEMPLATE_AudioCmd,
- TEMPLATE_VolumeCtl,
- TEMPLATE_MuteCtl,
- TEMPLATE_PeriodicTC,
- TEMPLATE_GetState,
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief TEMPLATE_Init
- * Initializes the AUDIO media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_Init(uint32_t AudioFreq, uint32_t Volume, uint32_t options)
-{
- /*
- Add your initialization code here
- */
- return (0);
-}
-
-/**
- * @brief TEMPLATE_DeInit
- * DeInitializes the AUDIO media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_DeInit(uint32_t options)
-{
- /*
- Add your deinitialization code here
- */
- return (0);
-}
-
-
-/**
- * @brief TEMPLATE_AudioCmd
- * AUDIO command handler
- * @param Buf: Buffer of data to be sent
- * @param size: Number of data to be sent (in bytes)
- * @param cmd: command opcode
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
-{
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_VolumeCtl
- * @param vol: volume level (0..100)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_VolumeCtl (uint8_t vol)
-{
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_MuteCtl
- * @param cmd: vmute command
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_MuteCtl (uint8_t cmd)
-{
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_PeriodicTC
- * @param cmd
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_PeriodicTC (uint8_t cmd)
-{
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_GetState
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_GetState (void)
-{
-
- return (0);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h
deleted file mode 100644
index d937b2e8175..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief header file for the usbd_cdc.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CDC_H
-#define __USB_CDC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_cdc
- * @brief This file is the Header file for usbd_cdc.c
- * @{
- */
-
-
-/** @defgroup usbd_cdc_Exported_Defines
- * @{
- */
-#define CDC_IN_EP 0x81 /* EP1 for data IN */
-#define CDC_OUT_EP 0x01 /* EP1 for data OUT */
-#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */
-
-/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */
-#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */
-#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */
-#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */
-
-#define USB_CDC_CONFIG_DESC_SIZ 67
-#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE
-#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE
-
-#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE
-#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE
-
-/*---------------------------------------------------------------------*/
-/* CDC definitions */
-/*---------------------------------------------------------------------*/
-#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
-#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
-#define CDC_SET_COMM_FEATURE 0x02
-#define CDC_GET_COMM_FEATURE 0x03
-#define CDC_CLEAR_COMM_FEATURE 0x04
-#define CDC_SET_LINE_CODING 0x20
-#define CDC_GET_LINE_CODING 0x21
-#define CDC_SET_CONTROL_LINE_STATE 0x22
-#define CDC_SEND_BREAK 0x23
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-typedef struct
-{
- uint32_t bitrate;
- uint8_t format;
- uint8_t paritytype;
- uint8_t datatype;
-}USBD_CDC_LineCodingTypeDef;
-
-typedef struct _USBD_CDC_Itf
-{
- int8_t (* Init) (void);
- int8_t (* DeInit) (void);
- int8_t (* Control) (uint8_t, uint8_t * , uint16_t);
- int8_t (* Receive) (uint8_t *, uint32_t *);
-
-}USBD_CDC_ItfTypeDef;
-
-
-typedef struct
-{
- uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */
- uint8_t CmdOpCode;
- uint8_t CmdLength;
- uint8_t *RxBuffer;
- uint8_t *TxBuffer;
- uint32_t RxLength;
- uint32_t TxLength;
-
- __IO uint32_t TxState;
- __IO uint32_t RxState;
-}
-USBD_CDC_HandleTypeDef;
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_CDC;
-#define USBD_CDC_CLASS &USBD_CDC
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_CDC_ItfTypeDef *fops);
-
-uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev,
- uint8_t *pbuff,
- uint16_t length);
-
-uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev,
- uint8_t *pbuff);
-
-uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev);
-
-uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_CDC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
deleted file mode 100644
index 806b2cbb529..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for usbd_cdc_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CDC_IF_TEMPLATE_H
-#define __USBD_CDC_IF_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-extern USBD_CDC_ItfTypeDef USBD_CDC_Template_fops;
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_CDC_IF_TEMPLATE_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c
deleted file mode 100644
index b2ca5f16489..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c
+++ /dev/null
@@ -1,925 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB CDC Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as CDC Device (and enumeration for each implemented memory interface)
- * - OUT/IN data transfer
- * - Command IN transfer (class requests management)
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * CDC Class Driver Description
- * ===================================================================
- * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
- * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
- * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
- * - Requests management (as described in section 6.2 in specification)
- * - Abstract Control Model compliant
- * - Union Functional collection (using 1 IN endpoint for control)
- * - Data interface class
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Any class-specific aspect relative to communication classes should be managed by user application.
- * - All communication classes other than PSTN are not managed
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_CDC
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_CDC_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);
-
-uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length);
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CDC_Private_Variables
- * @{
- */
-
-
-/* CDC interface class callbacks structure */
-USBD_ClassTypeDef USBD_CDC =
-{
- USBD_CDC_Init,
- USBD_CDC_DeInit,
- USBD_CDC_Setup,
- NULL, /* EP0_TxSent, */
- USBD_CDC_EP0_RxReady,
- USBD_CDC_DataIn,
- USBD_CDC_DataOut,
- NULL,
- NULL,
- NULL,
- USBD_CDC_GetHSCfgDesc,
- USBD_CDC_GetFSCfgDesc,
- USBD_CDC_GetOtherSpeedCfgDesc,
- USBD_CDC_GetDeviceQualifierDescriptor,
-};
-
-/* USB CDC device Configuration Descriptor */
-__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- /*Configuration Descriptor*/
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */
- 0x00,
- 0x02, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xC0, /* bmAttributes: self powered */
- 0x32, /* MaxPower 0 mA */
-
- /*---------------------------------------------------------------------------*/
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0x10, /* bInterval: */
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),
- 0x00 /* bInterval: ignore for Bulk transfer */
-} ;
-
-
-/* USB CDC device Configuration Descriptor */
-__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- /*Configuration Descriptor*/
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */
- 0x00,
- 0x02, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xC0, /* bmAttributes: self powered */
- 0x32, /* MaxPower 0 mA */
-
- /*---------------------------------------------------------------------------*/
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0x10, /* bInterval: */
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),
- 0x00 /* bInterval: ignore for Bulk transfer */
-} ;
-
-__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
- USB_CDC_CONFIG_DESC_SIZ,
- 0x00,
- 0x02, /* bNumInterfaces: 2 interfaces */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0xFF, /* bInterval: */
-
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00 /* bInterval */
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CDC_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_CDC_Init
- * Initialize the CDC interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- uint8_t ret = 0;
- USBD_CDC_HandleTypeDef *hcdc;
-
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- CDC_IN_EP,
- USBD_EP_TYPE_BULK,
- CDC_DATA_HS_IN_PACKET_SIZE);
-
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- CDC_OUT_EP,
- USBD_EP_TYPE_BULK,
- CDC_DATA_HS_OUT_PACKET_SIZE);
-
- }
- else
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- CDC_IN_EP,
- USBD_EP_TYPE_BULK,
- CDC_DATA_FS_IN_PACKET_SIZE);
-
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- CDC_OUT_EP,
- USBD_EP_TYPE_BULK,
- CDC_DATA_FS_OUT_PACKET_SIZE);
- }
- /* Open Command IN EP */
- USBD_LL_OpenEP(pdev,
- CDC_CMD_EP,
- USBD_EP_TYPE_INTR,
- CDC_CMD_PACKET_SIZE);
-
-
- pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- ret = 1;
- }
- else
- {
- hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- /* Init physical Interface components */
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
-
- /* Init Xfer states */
- hcdc->TxState =0;
- hcdc->RxState =0;
-
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Prepare Out endpoint to receive next packet */
- USBD_LL_PrepareReceive(pdev,
- CDC_OUT_EP,
- hcdc->RxBuffer,
- CDC_DATA_HS_OUT_PACKET_SIZE);
- }
- else
- {
- /* Prepare Out endpoint to receive next packet */
- USBD_LL_PrepareReceive(pdev,
- CDC_OUT_EP,
- hcdc->RxBuffer,
- CDC_DATA_FS_OUT_PACKET_SIZE);
- }
-
-
- }
- return ret;
-}
-
-/**
- * @brief USBD_CDC_Init
- * DeInitialize the CDC layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- uint8_t ret = 0;
-
- /* Open EP IN */
- USBD_LL_CloseEP(pdev,
- CDC_IN_EP);
-
- /* Open EP OUT */
- USBD_LL_CloseEP(pdev,
- CDC_OUT_EP);
-
- /* Open Command IN EP */
- USBD_LL_CloseEP(pdev,
- CDC_CMD_EP);
-
-
- /* DeInit physical Interface components */
- if(pdev->pClassData != NULL)
- {
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
-
- return ret;
-}
-
-/**
- * @brief USBD_CDC_Setup
- * Handle the CDC specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
- static uint8_t ifalt = 0;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- if (req->wLength)
- {
- if (req->bmRequest & 0x80)
- {
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
- (uint8_t *)hcdc->data,
- req->wLength);
- USBD_CtlSendData (pdev,
- (uint8_t *)hcdc->data,
- req->wLength);
- }
- else
- {
- hcdc->CmdOpCode = req->bRequest;
- hcdc->CmdLength = req->wLength;
-
- USBD_CtlPrepareRx (pdev,
- (uint8_t *)hcdc->data,
- req->wLength);
- }
-
- }
- else
- {
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
- (uint8_t*)req,
- 0);
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- &ifalt,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- break;
- }
-
- default:
- break;
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CDC_DataIn
- * Data sent on non-control IN endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- if(pdev->pClassData != NULL)
- {
-
- hcdc->TxState = 0;
-
- return USBD_OK;
- }
- else
- {
- return USBD_FAIL;
- }
-}
-
-/**
- * @brief USBD_CDC_DataOut
- * Data received on non-control Out endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- /* Get the received data length */
- hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum);
-
- /* USB data will be immediately processed, this allow next USB traffic being
- NAKed till the end of the application Xfer */
- if(pdev->pClassData != NULL)
- {
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
-
- return USBD_OK;
- }
- else
- {
- return USBD_FAIL;
- }
-}
-
-
-
-/**
- * @brief USBD_CDC_DataOut
- * Data received on non-control Out endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF))
- {
- ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
- (uint8_t *)hcdc->data,
- hcdc->CmdLength);
- hcdc->CmdOpCode = 0xFF;
-
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CDC_GetFSCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_CDC_CfgFSDesc);
- return USBD_CDC_CfgFSDesc;
-}
-
-/**
- * @brief USBD_CDC_GetHSCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_CDC_CfgHSDesc);
- return USBD_CDC_CfgHSDesc;
-}
-
-/**
- * @brief USBD_CDC_GetCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_CDC_OtherSpeedCfgDesc);
- return USBD_CDC_OtherSpeedCfgDesc;
-}
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length)
-{
- *length = sizeof (USBD_CDC_DeviceQualifierDesc);
- return USBD_CDC_DeviceQualifierDesc;
-}
-
-/**
-* @brief USBD_CDC_RegisterInterface
- * @param pdev: device instance
- * @param fops: CD Interface callback
- * @retval status
- */
-uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_CDC_ItfTypeDef *fops)
-{
- uint8_t ret = USBD_FAIL;
-
- if(fops != NULL)
- {
- pdev->pUserData= fops;
- ret = USBD_OK;
- }
-
- return ret;
-}
-
-/**
- * @brief USBD_CDC_SetTxBuffer
- * @param pdev: device instance
- * @param pbuff: Tx Buffer
- * @retval status
- */
-uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev,
- uint8_t *pbuff,
- uint16_t length)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- hcdc->TxBuffer = pbuff;
- hcdc->TxLength = length;
-
- return USBD_OK;
-}
-
-
-/**
- * @brief USBD_CDC_SetRxBuffer
- * @param pdev: device instance
- * @param pbuff: Rx Buffer
- * @retval status
- */
-uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev,
- uint8_t *pbuff)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- hcdc->RxBuffer = pbuff;
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CDC_DataOut
- * Data received on non-control Out endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- if(pdev->pClassData != NULL)
- {
- if(hcdc->TxState == 0)
- {
- /* Tx Transfer in progress */
- hcdc->TxState = 1;
-
- /* Transmit next packet */
- USBD_LL_Transmit(pdev,
- CDC_IN_EP,
- hcdc->TxBuffer,
- hcdc->TxLength);
-
- return USBD_OK;
- }
- else
- {
- return USBD_BUSY;
- }
- }
- else
- {
- return USBD_FAIL;
- }
-}
-
-
-/**
- * @brief USBD_CDC_ReceivePacket
- * prepare OUT Endpoint for reception
- * @param pdev: device instance
- * @retval status
- */
-uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
-{
- USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;
-
- /* Suspend or Resume USB Out process */
- if(pdev->pClassData != NULL)
- {
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Prepare Out endpoint to receive next packet */
- USBD_LL_PrepareReceive(pdev,
- CDC_OUT_EP,
- hcdc->RxBuffer,
- CDC_DATA_HS_OUT_PACKET_SIZE);
- }
- else
- {
- /* Prepare Out endpoint to receive next packet */
- USBD_LL_PrepareReceive(pdev,
- CDC_OUT_EP,
- hcdc->RxBuffer,
- CDC_DATA_FS_OUT_PACKET_SIZE);
- }
- return USBD_OK;
- }
- else
- {
- return USBD_FAIL;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c
deleted file mode 100644
index 5bb153a61fc..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_if_template.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_CDC
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_CDC_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CDC_Private_FunctionPrototypes
- * @{
- */
-
-static int8_t TEMPLATE_Init (void);
-static int8_t TEMPLATE_DeInit (void);
-static int8_t TEMPLATE_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length);
-static int8_t TEMPLATE_Receive (uint8_t* pbuf, uint32_t *Len);
-
-USBD_CDC_ItfTypeDef USBD_CDC_Template_fops =
-{
- TEMPLATE_Init,
- TEMPLATE_DeInit,
- TEMPLATE_Control,
- TEMPLATE_Receive
-};
-
-USBD_CDC_LineCodingTypeDef linecoding =
- {
- 115200, /* baud rate*/
- 0x00, /* stop bits-1*/
- 0x00, /* parity - none*/
- 0x08 /* nb. of bits 8*/
- };
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief TEMPLATE_Init
- * Initializes the CDC media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_Init(void)
-{
- /*
- Add your initialization code here
- */
- return (0);
-}
-
-/**
- * @brief TEMPLATE_DeInit
- * DeInitializes the CDC media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_DeInit(void)
-{
- /*
- Add your deinitialization code here
- */
- return (0);
-}
-
-
-/**
- * @brief TEMPLATE_Control
- * Manage the CDC class requests
- * @param Cmd: Command code
- * @param Buf: Buffer containing command data (request parameters)
- * @param Len: Number of data to be sent (in bytes)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length)
-{
- switch (cmd)
- {
- case CDC_SEND_ENCAPSULATED_COMMAND:
- /* Add your code here */
- break;
-
- case CDC_GET_ENCAPSULATED_RESPONSE:
- /* Add your code here */
- break;
-
- case CDC_SET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case CDC_GET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case CDC_CLEAR_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case CDC_SET_LINE_CODING:
- linecoding.bitrate = (uint32_t)(pbuf[0] | (pbuf[1] << 8) |\
- (pbuf[2] << 16) | (pbuf[3] << 24));
- linecoding.format = pbuf[4];
- linecoding.paritytype = pbuf[5];
- linecoding.datatype = pbuf[6];
-
- /* Add your code here */
- break;
-
- case CDC_GET_LINE_CODING:
- pbuf[0] = (uint8_t)(linecoding.bitrate);
- pbuf[1] = (uint8_t)(linecoding.bitrate >> 8);
- pbuf[2] = (uint8_t)(linecoding.bitrate >> 16);
- pbuf[3] = (uint8_t)(linecoding.bitrate >> 24);
- pbuf[4] = linecoding.format;
- pbuf[5] = linecoding.paritytype;
- pbuf[6] = linecoding.datatype;
-
- /* Add your code here */
- break;
-
- case CDC_SET_CONTROL_LINE_STATE:
- /* Add your code here */
- break;
-
- case CDC_SEND_BREAK:
- /* Add your code here */
- break;
-
- default:
- break;
- }
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_Receive
- * Data received over USB OUT endpoint are sent over CDC interface
- * through this function.
- *
- * @note
- * This function will issue a NAK packet on any OUT packet received on
- * USB endpoint untill exiting this function. If you exit this function
- * before transfer is complete on CDC interface (ie. using DMA controller)
- * it will result in receiving more data while previous ones are still
- * not sent.
- *
- * @param Buf: Buffer of data to be received
- * @param Len: Number of data received (in bytes)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_Receive (uint8_t* Buf, uint32_t *Len)
-{
-
- return (0);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h
deleted file mode 100644
index 1f5ddaca57e..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_customhid.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief header file for the usbd_customhid.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CUSTOMHID_H
-#define __USB_CUSTOMHID_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_CUSTOM_HID
- * @brief This file is the Header file for USBD_customhid.c
- * @{
- */
-
-
-/** @defgroup USBD_CUSTOM_HID_Exported_Defines
- * @{
- */
-#define CUSTOM_HID_EPIN_ADDR 0x81
-#define CUSTOM_HID_EPIN_SIZE 0x02
-
-#define CUSTOM_HID_EPOUT_ADDR 0x01
-#define CUSTOM_HID_EPOUT_SIZE 0x02
-
-#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41
-#define USB_CUSTOM_HID_DESC_SIZ 9
-
-#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21
-#define CUSTOM_HID_REPORT_DESC 0x22
-
-
-#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0B
-#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03
-
-#define CUSTOM_HID_REQ_SET_IDLE 0x0A
-#define CUSTOM_HID_REQ_GET_IDLE 0x02
-
-#define CUSTOM_HID_REQ_SET_REPORT 0x09
-#define CUSTOM_HID_REQ_GET_REPORT 0x01
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-typedef enum
-{
- CUSTOM_HID_IDLE = 0,
- CUSTOM_HID_BUSY,
-}
-CUSTOM_HID_StateTypeDef;
-
-typedef struct _USBD_CUSTOM_HID_Itf
-{
- uint8_t *pReport;
- int8_t (* Init) (void);
- int8_t (* DeInit) (void);
- int8_t (* OutEvent) (uint8_t, uint8_t );
-
-}USBD_CUSTOM_HID_ItfTypeDef;
-
-typedef struct
-{
- uint8_t Report_buf[USBD_CUSTOMHID_OUTREPORT_BUF_SIZE];
- uint32_t Protocol;
- uint32_t IdleState;
- uint32_t AltSetting;
- uint32_t IsReportAvailable;
- CUSTOM_HID_StateTypeDef state;
-}
-USBD_CUSTOM_HID_HandleTypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_CUSTOM_HID;
-#define USBD_CUSTOM_HID_CLASS &USBD_CUSTOM_HID
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_CUSTOM_HID_SendReport (USBD_HandleTypeDef *pdev,
- uint8_t *report,
- uint16_t len);
-
-
-
-uint8_t USBD_CUSTOM_HID_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_CUSTOM_HID_ItfTypeDef *fops);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_CUSTOMHID_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid_if_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid_if_template.h
deleted file mode 100644
index 560b80f8e36..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid_if_template.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_customhid_if_template.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for usbd_customhid_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for th?
- e specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CUSTOMHID_IF_TEMPLATE_H
-#define __USBD_CUSTOMHID_IF_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_customhid.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-extern USBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_template_fops;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_CUSTOMHID_IF_TEMPLATE_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c
deleted file mode 100644
index 775ab844895..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_customhid.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the CUSTOM_HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * CUSTOM_HID Class Description
- * ===================================================================
- * This module manages the CUSTOM_HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (CUSTOM_HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - Usage Page : Generic Desktop
- * - Usage : Vendor
- * - Collection : Application
- *
- * @note In HS mode and when the DMA is used, all variables and data structures
- * dealing with the DMA during the transaction process should be 32-bit aligned.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_customhid.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_CUSTOM_HID
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_CUSTOM_HID_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CUSTOM_HID_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CUSTOM_HID_Private_Macros
- * @{
- */
-/**
- * @}
- */
-/** @defgroup USBD_CUSTOM_HID_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_CUSTOM_HID_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CUSTOM_HID_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CUSTOM_HID_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t USBD_CUSTOM_HID_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_CUSTOM_HID_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);
-static uint8_t USBD_CUSTOM_HID_EP0_RxReady (USBD_HandleTypeDef *pdev);
-/**
- * @}
- */
-
-/** @defgroup USBD_CUSTOM_HID_Private_Variables
- * @{
- */
-
-USBD_ClassTypeDef USBD_CUSTOM_HID =
-{
- USBD_CUSTOM_HID_Init,
- USBD_CUSTOM_HID_DeInit,
- USBD_CUSTOM_HID_Setup,
- NULL, /*EP0_TxSent*/
- USBD_CUSTOM_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */
- USBD_CUSTOM_HID_DataIn, /*DataIn*/
- USBD_CUSTOM_HID_DataOut,
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_CUSTOM_HID_GetCfgDesc,
- USBD_CUSTOM_HID_GetCfgDesc,
- USBD_CUSTOM_HID_GetCfgDesc,
- USBD_CUSTOM_HID_GetDeviceQualifierDesc,
-};
-
-/* USB CUSTOM_HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_CUSTOM_HID_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xC0, /*bmAttributes: bus powered */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of CUSTOM HID interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x02, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: CUSTOM_HID*/
- 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of CUSTOM_HID *************************/
- /* 18 */
- 0x09, /*bLength: CUSTOM_HID Descriptor size*/
- CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/
- 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of Custom HID endpoints ********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/
-
- CUSTOM_HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- CUSTOM_HID_EPIN_SIZE, /*wMaxPacketSize: 2 Byte max */
- 0x00,
- 0x20, /*bInterval: Polling Interval (20 ms)*/
- /* 34 */
-
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */
- CUSTOM_HID_EPOUT_ADDR, /*bEndpointAddress: Endpoint Address (OUT)*/
- 0x03, /* bmAttributes: Interrupt endpoint */
- CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x20, /* bInterval: Polling Interval (20 ms) */
- /* 41 */
-} ;
-
-/* USB CUSTOM_HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_Desc[USB_CUSTOM_HID_DESC_SIZ] __ALIGN_END =
-{
- /* 18 */
- 0x09, /*bLength: CUSTOM_HID Descriptor size*/
- CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/
- 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CUSTOM_HID_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_CUSTOM_HID_Init
- * Initialize the CUSTOM_HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_CUSTOM_HID_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- uint8_t ret = 0;
- USBD_CUSTOM_HID_HandleTypeDef *hhid;
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- CUSTOM_HID_EPIN_ADDR,
- USBD_EP_TYPE_INTR,
- CUSTOM_HID_EPIN_SIZE);
-
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- CUSTOM_HID_EPOUT_ADDR,
- USBD_EP_TYPE_INTR,
- CUSTOM_HID_EPOUT_SIZE);
-
- pdev->pClassData = USBD_malloc(sizeof (USBD_CUSTOM_HID_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- ret = 1;
- }
- else
- {
- hhid = (USBD_CUSTOM_HID_HandleTypeDef*) pdev->pClassData;
-
- hhid->state = CUSTOM_HID_IDLE;
- ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->Init();
- /* Prepare Out endpoint to receive 1st packet */
- USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf,
- USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);
- }
-
- return ret;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_Init
- * DeInitialize the CUSTOM_HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_CUSTOM_HID_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- /* Close CUSTOM_HID EP IN */
- USBD_LL_CloseEP(pdev,
- CUSTOM_HID_EPIN_ADDR);
-
- /* Close CUSTOM_HID EP OUT */
- USBD_LL_CloseEP(pdev,
- CUSTOM_HID_EPOUT_ADDR);
-
- /* FRee allocated memory */
- if(pdev->pClassData != NULL)
- {
- ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->DeInit();
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_Setup
- * Handle the CUSTOM_HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_CUSTOM_HID_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
- USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
-
-
- case CUSTOM_HID_REQ_SET_PROTOCOL:
- hhid->Protocol = (uint8_t)(req->wValue);
- break;
-
- case CUSTOM_HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->Protocol,
- 1);
- break;
-
- case CUSTOM_HID_REQ_SET_IDLE:
- hhid->IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case CUSTOM_HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->IdleState,
- 1);
- break;
-
- case CUSTOM_HID_REQ_SET_REPORT:
- hhid->IsReportAvailable = 1;
- USBD_CtlPrepareRx (pdev, hhid->Report_buf, (uint8_t)(req->wLength));
-
- break;
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == CUSTOM_HID_REPORT_DESC)
- {
- len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE , req->wLength);
- pbuf = ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->pReport;
- }
- else if( req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE)
- {
- pbuf = USBD_CUSTOM_HID_Desc;
- len = MIN(USB_CUSTOM_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->AltSetting,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- hhid->AltSetting = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_SendReport
- * Send CUSTOM_HID Report
- * @param pdev: device instance
- * @param buff: pointer to report
- * @retval status
- */
-uint8_t USBD_CUSTOM_HID_SendReport (USBD_HandleTypeDef *pdev,
- uint8_t *report,
- uint16_t len)
-{
- USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;
-
- if (pdev->dev_state == USBD_STATE_CONFIGURED )
- {
- if(hhid->state == CUSTOM_HID_IDLE)
- {
- hhid->state = CUSTOM_HID_BUSY;
- USBD_LL_Transmit (pdev,
- CUSTOM_HID_EPIN_ADDR,
- report,
- len);
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_CUSTOM_HID_CfgDesc);
- return USBD_CUSTOM_HID_CfgDesc;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_CUSTOM_HID_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- /* Ensure that the FIFO is empty before a new transfer, this condition could
- be caused by a new transfer before the end of the previous transfer */
- ((USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData)->state = CUSTOM_HID_IDLE;
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_CUSTOM_HID_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;
-
- ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->OutEvent(hhid->Report_buf[0],
- hhid->Report_buf[1]);
-
- USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR , hhid->Report_buf,
- USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CUSTOM_HID_EP0_RxReady
- * Handles control request data.
- * @param pdev: device instance
- * @retval status
- */
-uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)
-{
- USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;
-
- if (hhid->IsReportAvailable == 1)
- {
- ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->OutEvent(hhid->Report_buf[0],
- hhid->Report_buf[1]);
- hhid->IsReportAvailable = 0;
- }
-
- return USBD_OK;
-}
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc (uint16_t *length)
-{
- *length = sizeof (USBD_CUSTOM_HID_DeviceQualifierDesc);
- return USBD_CUSTOM_HID_DeviceQualifierDesc;
-}
-
-/**
-* @brief USBD_CUSTOM_HID_RegisterInterface
- * @param pdev: device instance
- * @param fops: CUSTOMHID Interface callback
- * @retval status
- */
-uint8_t USBD_CUSTOM_HID_RegisterInterface (USBD_HandleTypeDef *pdev,
- USBD_CUSTOM_HID_ItfTypeDef *fops)
-{
- uint8_t ret = USBD_FAIL;
-
- if(fops != NULL)
- {
- pdev->pUserData= fops;
- ret = USBD_OK;
- }
-
- return ret;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c
deleted file mode 100644
index 4389e9861a6..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_customhid_if_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief USB Device Custom HID interface file.
- * This template should be copied to the user folder, renamed and customized
- * following user needs.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_customhid_if_template.h"
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-static int8_t TEMPLATE_CUSTOM_HID_Init (void);
-static int8_t TEMPLATE_CUSTOM_HID_DeInit (void);
-static int8_t TEMPLATE_CUSTOM_HID_OutEvent (uint8_t event_idx, uint8_t state);
-/* Private variables ---------------------------------------------------------*/
-USBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_template_fops =
-{
- TEMPLATE_CUSTOM_HID_ReportDesc,
- TEMPLATE_CUSTOM_HID_Init,
- TEMPLATE_CUSTOM_HID_DeInit,
- TEMPLATE_CUSTOM_HID_OutEvent,
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief TEMPLATE_CUSTOM_HID_Init
- * Initializes the CUSTOM HID media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_CUSTOM_HID_Init(void)
-{
-
- return (0);
-}
-
-/**
- * @brief TEMPLATE_CUSTOM_HID_DeInit
- * DeInitializes the CUSTOM HID media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_CUSTOM_HID_DeInit(void)
-{
- /*
- Add your deinitialization code here
- */
- return (0);
-}
-
-
-/**
- * @brief TEMPLATE_CUSTOM_HID_Control
- * Manage the CUSTOM HID class events
- * @param event_idx: event index
- * @param state: event state
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static int8_t TEMPLATE_CUSTOM_HID_OutEvent (uint8_t event_idx, uint8_t state)
-{
-
- return (0);
-}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h
deleted file mode 100644
index fdbdf816436..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_dfu.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_DFU_H
-#define __USB_DFU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_DFU
- * @brief This file is the Header file for usbd_dfu.c
- * @{
- */
-
-
-/** @defgroup USBD_DFU_Exported_Defines
- * @{
- */
-
-#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_DFU_MAX_ITF_NUM))
-#define USB_DFU_DESC_SIZ 9
-
-#define DFU_DESCRIPTOR_TYPE 0x21
-
-
-/**************************************************/
-/* DFU Requests DFU states */
-/**************************************************/
-#define APP_STATE_IDLE 0
-#define APP_STATE_DETACH 1
-#define DFU_STATE_IDLE 2
-#define DFU_STATE_DNLOAD_SYNC 3
-#define DFU_STATE_DNLOAD_BUSY 4
-#define DFU_STATE_DNLOAD_IDLE 5
-#define DFU_STATE_MANIFEST_SYNC 6
-#define DFU_STATE_MANIFEST 7
-#define DFU_STATE_MANIFEST_WAIT_RESET 8
-#define DFU_STATE_UPLOAD_IDLE 9
-#define DFU_STATE_ERROR 10
-
-/**************************************************/
-/* DFU errors */
-/**************************************************/
-#define DFU_ERROR_NONE 0x00
-#define DFU_ERROR_TARGET 0x01
-#define DFU_ERROR_FILE 0x02
-#define DFU_ERROR_WRITE 0x03
-#define DFU_ERROR_ERASE 0x04
-#define DFU_ERROR_CHECK_ERASED 0x05
-#define DFU_ERROR_PROG 0x06
-#define DFU_ERROR_VERIFY 0x07
-#define DFU_ERROR_ADDRESS 0x08
-#define DFU_ERROR_NOTDONE 0x09
-#define DFU_ERROR_FIRMWARE 0x0A
-#define DFU_ERROR_VENDOR 0x0B
-#define DFU_ERROR_USB 0x0C
-#define DFU_ERROR_POR 0x0D
-#define DFU_ERROR_UNKNOWN 0x0E
-#define DFU_ERROR_STALLEDPKT 0x0F
-
-/**************************************************/
-/* DFU Manifestation State */
-/**************************************************/
-#define DFU_MANIFEST_COMPLETE 0x00
-#define DFU_MANIFEST_IN_PROGRESS 0x01
-
-
-/**************************************************/
-/* Special Commands with Download Request */
-/**************************************************/
-#define DFU_CMD_GETCOMMANDS 0x00
-#define DFU_CMD_SETADDRESSPOINTER 0x21
-#define DFU_CMD_ERASE 0x41
-
-#define DFU_MEDIA_ERASE 0x00
-#define DFU_MEDIA_PROGRAM 0x01
-
-/**************************************************/
-/* Other defines */
-/**************************************************/
-/* Bit Detach capable = bit 3 in bmAttributes field */
-#define DFU_DETACH_MASK (uint8_t)(1 << 4)
-#define DFU_STATUS_DEPTH (6)
-
-typedef enum
-{
- DFU_DETACH = 0,
- DFU_DNLOAD ,
- DFU_UPLOAD,
- DFU_GETSTATUS,
- DFU_CLRSTATUS,
- DFU_GETSTATE,
- DFU_ABORT
-} DFU_RequestTypeDef;
-
-typedef void (*pFunction)(void);
-
-
-/********** Descriptor of DFU interface 0 Alternate setting n ****************/
-#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \
- USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ \
- 0x00, /* bInterfaceNumber: Number of Interface */ \
- (n), /* bAlternateSetting: Alternate setting */ \
- 0x00, /* bNumEndpoints*/ \
- 0xFE, /* bInterfaceClass: Application Specific Class Code */ \
- 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \
- 0x02, /* nInterfaceProtocol: DFU mode protocol */ \
- USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \
-
-#define TRANSFER_SIZE_BYTES(size) ((uint8_t)(size)), /* XFERSIZEB0 */\
- ((uint8_t)(size >> 8)) /* XFERSIZEB1 */
-
-#define IS_PROTECTED_AREA(add) (uint8_t)(((add >= 0x08000000) && (add < (APP_DEFAULT_ADD)))? 1:0)
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-typedef struct
-{
- union
- {
- uint32_t d32[USBD_DFU_XFER_SIZE/4];
- uint8_t d8[USBD_DFU_XFER_SIZE];
- }buffer;
-
- uint8_t dev_state;
- uint8_t dev_status[DFU_STATUS_DEPTH];
- uint8_t manif_state;
-
- uint32_t wblock_num;
- uint32_t wlength;
- uint32_t data_ptr;
- __IO uint32_t alt_setting;
-
-}
-USBD_DFU_HandleTypeDef;
-
-
-typedef struct
-{
- const uint8_t* pStrDesc;
- uint16_t (* Init) (void);
- uint16_t (* DeInit) (void);
- uint16_t (* Erase) (uint32_t Add);
- uint16_t (* Write) (uint8_t *src, uint8_t *dest, uint32_t Len);
- uint8_t* (* Read) (uint8_t *src, uint8_t *dest, uint32_t Len);
- uint16_t (* GetStatus)(uint32_t Add, uint8_t cmd, uint8_t *buff);
-}
-USBD_DFU_MediaTypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_DFU;
-#define USBD_DFU_CLASS &USBD_DFU
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_DFU_RegisterMedia (USBD_HandleTypeDef *pdev,
- USBD_DFU_MediaTypeDef *fops);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DFU_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu_media_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu_media_template.h
deleted file mode 100644
index e43a7ec734a..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu_media_template.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_media_template.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief header file for the usbd_dfu_media_template.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_DFU_MEDIA_TEMPLATE_H
-#define __USBD_DFU_MEDIA_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_MEDIA
- * @brief header file for the usbd_dfu_media_template.c file
- * @{
- */
-
-/** @defgroup USBD_MEDIA_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_MEDIA_Exported_Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_MEDIA_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_MEDIA_Exported_Variables
- * @{
- */
-extern USBD_DFU_MediaTypeDef USBD_DFU_MEDIA_Template_fops;
-/**
- * @}
- */
-
-/** @defgroup USBD_MEDIA_Exported_FunctionsPrototype
- * @{
- */
-
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_DFU_MEDIA_TEMPLATE_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c
deleted file mode 100644
index 4c874cd0529..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c
+++ /dev/null
@@ -1,1107 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the DFU core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * DFU Class Driver Description
- * ===================================================================
- * This driver manages the DFU class V1.1 following the "Device Class Specification for
- * Device Firmware Upgrade Version 1.1 Aug 5, 2004".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as DFU device (in DFU mode only)
- * - Requests management (supporting ST DFU sub-protocol)
- * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus)
- * - DFU state machine implementation.
- *
- * @note
- * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage
- * memory addressing, commands processing, specific memories operations (ie. Erase) ...
- * As required by the DFU specification, only endpoint 0 is used in this application.
- * Other endpoints and functions may be added to the application (ie. DFU ...)
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Manifestation Tolerant mode
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_DFU
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_DFU_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DFU_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DFU_Private_Macros
- * @{
- */
-#define DFU_SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
-
-#define DFU_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \
- (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF)
-
-/**
- * @}
- */
-
-
-
-
-/** @defgroup USBD_DFU_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_DFU_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_DFU_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_DFU_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t *USBD_DFU_GetCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_DFU_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t USBD_DFU_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_DFU_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_DFU_EP0_RxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_DFU_EP0_TxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_DFU_SOF (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_DFU_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_DFU_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-#if (USBD_SUPPORT_USER_STRING == 1)
-static uint8_t* USBD_DFU_GetUsrStringDesc ( USBD_HandleTypeDef *pdev, uint8_t index , uint16_t *length);
-#endif
-
-static void DFU_Detach (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-static void DFU_Download (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-static void DFU_Upload (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-static void DFU_GetStatus (USBD_HandleTypeDef *pdev);
-
-static void DFU_ClearStatus (USBD_HandleTypeDef *pdev);
-
-static void DFU_GetState (USBD_HandleTypeDef *pdev);
-
-static void DFU_Abort (USBD_HandleTypeDef *pdev);
-
-static void DFU_Leave (USBD_HandleTypeDef *pdev);
-
-
-/**
- * @}
- */
-
-/** @defgroup USBD_DFU_Private_Variables
- * @{
- */
-
-USBD_ClassTypeDef USBD_DFU =
-{
- USBD_DFU_Init,
- USBD_DFU_DeInit,
- USBD_DFU_Setup,
- USBD_DFU_EP0_TxReady,
- USBD_DFU_EP0_RxReady,
- USBD_DFU_DataIn,
- USBD_DFU_DataOut,
- USBD_DFU_SOF,
- USBD_DFU_IsoINIncomplete,
- USBD_DFU_IsoOutIncomplete,
- USBD_DFU_GetCfgDesc,
- USBD_DFU_GetCfgDesc,
- USBD_DFU_GetCfgDesc,
- USBD_DFU_GetDeviceQualifierDesc,
-#if (USBD_SUPPORT_USER_STRING == 1)
- USBD_DFU_GetUsrStringDesc
-#endif
-};
-
-/* USB DFU device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_DFU_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/
- 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
- /* 09 */
-
- /********** Descriptor of DFU interface 0 Alternate setting 0 **************/
- USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */
-
-#if (USBD_DFU_MAX_ITF_NUM > 1)
- /********** Descriptor of DFU interface 0 Alternate setting 1 **************/
- USBD_DFU_IF_DESC(1),
-#endif /* (USBD_DFU_MAX_ITF_NUM > 1) */
-
-#if (USBD_DFU_MAX_ITF_NUM > 2)
- /********** Descriptor of DFU interface 0 Alternate setting 2 **************/
- USBD_DFU_IF_DESC(2),
-#endif /* (USBD_DFU_MAX_ITF_NUM > 2) */
-
-#if (USBD_DFU_MAX_ITF_NUM > 3)
- /********** Descriptor of DFU interface 0 Alternate setting 3 **************/
- USBD_DFU_IF_DESC(3),
-#endif /* (USBD_DFU_MAX_ITF_NUM > 3) */
-
-#if (USBD_DFU_MAX_ITF_NUM > 4)
- /********** Descriptor of DFU interface 0 Alternate setting 4 **************/
- USBD_DFU_IF_DESC(4),
-#endif /* (USBD_DFU_MAX_ITF_NUM > 4) */
-
-#if (USBD_DFU_MAX_ITF_NUM > 5)
- /********** Descriptor of DFU interface 0 Alternate setting 5 **************/
- USBD_DFU_IF_DESC(5),
-#endif /* (USBD_DFU_MAX_ITF_NUM > 5) */
-
-#if (USBD_DFU_MAX_ITF_NUM > 6)
-#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!"
-#endif /* (USBD_DFU_MAX_ITF_NUM > 6) */
-
- /******************** DFU Functional Descriptor********************/
- 0x09, /*blength = 9 Bytes*/
- DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/
- 0x0B, /*bmAttribute
- bitCanDnload = 1 (bit 0)
- bitCanUpload = 1 (bit 1)
- bitManifestationTolerant = 0 (bit 2)
- bitWillDetach = 1 (bit 3)
- Reserved (bit4-6)
- bitAcceleratedST = 0 (bit 7)*/
- 0xFF, /*DetachTimeOut= 255 ms*/
- 0x00,
- /*WARNING: In DMA mode the multiple MPS packets feature is still not supported
- ==> In this case, when using DMA USBD_DFU_XFER_SIZE should be set to 64 in usbd_conf.h */
- TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte*/
- 0x1A, /* bcdDFUVersion*/
- 0x01
- /***********************************************************/
- /* 9*/
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_DFU_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_DFU_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_DFU_Init
- * Initialize the DFU interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_DFU_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- /* Allocate Audio structure */
- pdev->pClassData = USBD_malloc(sizeof (USBD_DFU_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- return USBD_FAIL;
- }
- else
- {
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- hdfu->alt_setting = 0;
- hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD;
- hdfu->wblock_num = 0;
- hdfu->wlength = 0;
-
- hdfu->manif_state = DFU_MANIFEST_COMPLETE;
- hdfu->dev_state = DFU_STATE_IDLE;
-
- hdfu->dev_status[0] = DFU_ERROR_NONE;
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = DFU_STATE_IDLE;
- hdfu->dev_status[5] = 0;
-
- /* Initialize Hardware layer */
- if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK)
- {
- return USBD_FAIL;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_DFU_Init
- * De-Initialize the DFU layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_DFU_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- USBD_DFU_HandleTypeDef *hdfu;
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- hdfu->wblock_num = 0;
- hdfu->wlength = 0;
-
- hdfu->dev_state = DFU_STATE_IDLE;
- hdfu->dev_status[0] = DFU_ERROR_NONE;
- hdfu->dev_status[4] = DFU_STATE_IDLE;
-
- /* DeInit physical Interface components */
- if(pdev->pClassData != NULL)
- {
- /* De-Initialize Hardware layer */
- ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit();
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_DFU_Setup
- * Handle the DFU specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_DFU_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
- uint8_t *pbuf = 0;
- uint16_t len = 0;
- uint8_t ret = USBD_OK;
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case DFU_DNLOAD:
- DFU_Download(pdev, req);
- break;
-
- case DFU_UPLOAD:
- DFU_Upload(pdev, req);
- break;
-
- case DFU_GETSTATUS:
- DFU_GetStatus(pdev);
- break;
-
- case DFU_CLRSTATUS:
- DFU_ClearStatus(pdev);
- break;
-
- case DFU_GETSTATE:
- DFU_GetState(pdev);
- break;
-
- case DFU_ABORT:
- DFU_Abort(pdev);
- break;
-
- case DFU_DETACH:
- DFU_Detach(pdev, req);
- break;
-
-
- default:
- USBD_CtlError (pdev, req);
- ret = USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE)
- {
- pbuf = USBD_DFU_CfgDesc + (9 * (USBD_DFU_MAX_ITF_NUM + 1));
- len = MIN(USB_DFU_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&hdfu->alt_setting,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM)
- {
- hdfu->alt_setting = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- ret = USBD_FAIL;
- }
- break;
-
- default:
- USBD_CtlError (pdev, req);
- ret = USBD_FAIL;
- }
- }
- return ret;
-}
-
-
-/**
- * @brief USBD_DFU_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_DFU_GetCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_DFU_CfgDesc);
- return USBD_DFU_CfgDesc;
-}
-
-/**
- * @brief USBD_DFU_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DFU_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_DFU_EP0_RxReady
- * handle EP0 Rx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_DFU_EP0_RxReady (USBD_HandleTypeDef *pdev)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_DFU_EP0_TxReady
- * handle EP0 TRx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_DFU_EP0_TxReady (USBD_HandleTypeDef *pdev)
-{
- uint32_t addr;
- USBD_SetupReqTypedef req;
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- if (hdfu->dev_state == DFU_STATE_DNLOAD_BUSY)
- {
- /* Decode the Special Command*/
- if (hdfu->wblock_num == 0)
- {
- if ((hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) && (hdfu->wlength == 1))
- {
-
- }
- else if (( hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER ) && (hdfu->wlength == 5))
- {
- hdfu->data_ptr = hdfu->buffer.d8[1];
- hdfu->data_ptr += hdfu->buffer.d8[2] << 8;
- hdfu->data_ptr += hdfu->buffer.d8[3] << 16;
- hdfu->data_ptr += hdfu->buffer.d8[4] << 24;
- }
- else if (( hdfu->buffer.d8[0] == DFU_CMD_ERASE ) && (hdfu->wlength == 5))
- {
- hdfu->data_ptr = hdfu->buffer.d8[1];
- hdfu->data_ptr += hdfu->buffer.d8[2] << 8;
- hdfu->data_ptr += hdfu->buffer.d8[3] << 16;
- hdfu->data_ptr += hdfu->buffer.d8[4] << 24;
-
- if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Erase(hdfu->data_ptr) != USBD_OK)
- {
- return USBD_FAIL;
- }
- }
- else
- {
- /* Reset the global length and block number */
- hdfu->wlength = 0;
- hdfu->wblock_num = 0;
- /* Call the error management function (command will be nacked) */
- req.bmRequest = 0;
- req.wLength = 1;
- USBD_CtlError (pdev, &req);
- }
- }
- /* Regular Download Command */
- else if (hdfu->wblock_num > 1)
- {
- /* Decode the required address */
- addr = ((hdfu->wblock_num - 2) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr;
-
- /* Preform the write operation */
- if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Write(hdfu->buffer.d8, (uint8_t *)addr, hdfu->wlength) != USBD_OK)
- {
- return USBD_FAIL;
- }
- }
- /* Reset the global length and block number */
- hdfu->wlength = 0;
- hdfu->wblock_num = 0;
-
- /* Update the state machine */
- hdfu->dev_state = DFU_STATE_DNLOAD_SYNC;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- return USBD_OK;
- }
- else if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress*/
- {
- /* Start leaving DFU mode */
- DFU_Leave(pdev);
- }
-
- return USBD_OK;
-}
-/**
- * @brief USBD_DFU_SOF
- * handle SOF event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_DFU_SOF (USBD_HandleTypeDef *pdev)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_DFU_IsoINIncomplete
- * handle data ISO IN Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DFU_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_DFU_IsoOutIncomplete
- * handle data ISO OUT Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DFU_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_DFU_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DFU_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- return USBD_OK;
-}
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-static uint8_t *USBD_DFU_GetDeviceQualifierDesc (uint16_t *length)
-{
- *length = sizeof (USBD_DFU_DeviceQualifierDesc);
- return USBD_DFU_DeviceQualifierDesc;
-}
-
-/**
- * @brief USBD_DFU_GetUsrStringDesc
- * Manages the transfer of memory interfaces string descriptors.
- * @param speed : current device speed
- * @param index: desciptor index
- * @param length : pointer data length
- * @retval pointer to the descriptor table or NULL if the descriptor is not supported.
- */
-#if (USBD_SUPPORT_USER_STRING == 1)
-static uint8_t* USBD_DFU_GetUsrStringDesc (USBD_HandleTypeDef *pdev, uint8_t index , uint16_t *length)
-{
- static uint8_t USBD_StrDesc[255];
- /* Check if the requested string interface is supported */
- if (index <= (USBD_IDX_INTERFACE_STR + USBD_DFU_MAX_ITF_NUM))
- {
- USBD_GetString ((uint8_t *)((USBD_DFU_MediaTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length);
- return USBD_StrDesc;
- }
- /* Not supported Interface Descriptor index */
- else
- {
- return NULL;
- }
-}
-#endif
-
-/**
-* @brief USBD_MSC_RegisterStorage
-* @param fops: storage callback
-* @retval status
-*/
-uint8_t USBD_DFU_RegisterMedia (USBD_HandleTypeDef *pdev,
- USBD_DFU_MediaTypeDef *fops)
-{
- if(fops != NULL)
- {
- pdev->pUserData= fops;
- }
- return 0;
-}
-
-/******************************************************************************
- DFU Class requests management
-******************************************************************************/
-/**
- * @brief DFU_Detach
- * Handles the DFU DETACH request.
- * @param pdev: device instance
- * @param req: pointer to the request structure.
- * @retval None.
- */
-static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC
- || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC
- || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE )
- {
- /* Update the state machine */
- hdfu->dev_state = DFU_STATE_IDLE;
- hdfu->dev_status[0] = DFU_ERROR_NONE;
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/
- hdfu->dev_status[4] = hdfu->dev_state;
- hdfu->dev_status[5] = 0; /*iString*/
- hdfu->wblock_num = 0;
- hdfu->wlength = 0;
- }
-
- /* Check the detach capability in the DFU functional descriptor */
- if ((USBD_DFU_CfgDesc[12 + (9 * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK)
- {
- /* Perform an Attach-Detach operation on USB bus */
- USBD_Stop (pdev);
- USBD_Start (pdev);
- }
- else
- {
- /* Wait for the period of time specified in Detach request */
- USBD_Delay (req->wValue);
- }
-}
-
-/**
- * @brief DFU_Download
- * Handles the DFU DNLOAD request.
- * @param pdev: device instance
- * @param req: pointer to the request structure
- * @retval None
- */
-static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE))
- {
- /* Update the global length and block number */
- hdfu->wblock_num = req->wValue;
- hdfu->wlength = req->wLength;
-
- /* Update the state machine */
- hdfu->dev_state = DFU_STATE_DNLOAD_SYNC;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- (uint8_t*)hdfu->buffer.d8,
- hdfu->wlength);
- }
- /* Unsupported state */
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* 0 Data DNLOAD request */
- else
- {
- /* End of DNLOAD operation*/
- if (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_IDLE )
- {
- hdfu->manif_state = DFU_MANIFEST_IN_PROGRESS;
- hdfu->dev_state = DFU_STATE_MANIFEST_SYNC;
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
-}
-
-/**
- * @brief DFU_Upload
- * Handles the DFU UPLOAD request.
- * @param pdev: instance
- * @param req: pointer to the request structure
- * @retval status
- */
-static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- uint8_t *phaddr = NULL;
- uint32_t addr = 0;
-
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE))
- {
- /* Update the global length and block number */
- hdfu->wblock_num = req->wValue;
- hdfu->wlength = req->wLength;
-
- /* DFU Get Command */
- if (hdfu->wblock_num == 0)
- {
- /* Update the state machine */
- hdfu->dev_state = (hdfu->wlength > 3)? DFU_STATE_IDLE:DFU_STATE_UPLOAD_IDLE;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- /* Store the values of all supported commands */
- hdfu->buffer.d8[0] = DFU_CMD_GETCOMMANDS;
- hdfu->buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER;
- hdfu->buffer.d8[2] = DFU_CMD_ERASE;
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(hdfu->buffer.d8[0])),
- 3);
- }
- else if (hdfu->wblock_num > 1)
- {
- hdfu->dev_state = DFU_STATE_UPLOAD_IDLE ;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- addr = ((hdfu->wblock_num - 2) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Change is Accelerated*/
-
- /* Return the physical address where data are stored */
- phaddr = ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength);
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- phaddr,
- hdfu->wlength);
- }
- else /* unsupported hdfu->wblock_num */
- {
- hdfu->dev_state = DFU_ERROR_STALLEDPKT;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* Unsupported state */
- else
- {
- hdfu->wlength = 0;
- hdfu->wblock_num = 0;
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* No Data setup request */
- else
- {
- hdfu->dev_state = DFU_STATE_IDLE;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- }
-}
-
-/**
- * @brief DFU_GetStatus
- * Handles the DFU GETSTATUS request.
- * @param pdev: instance
- * @retval status
- */
-static void DFU_GetStatus(USBD_HandleTypeDef *pdev)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- switch (hdfu->dev_state)
- {
- case DFU_STATE_DNLOAD_SYNC:
- if (hdfu->wlength != 0)
- {
- hdfu->dev_state = DFU_STATE_DNLOAD_BUSY;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- if ((hdfu->wblock_num == 0) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE))
- {
- ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status);
- }
- else
- {
- ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status);
- }
- }
- else /* (hdfu->wlength==0)*/
- {
- hdfu->dev_state = DFU_STATE_DNLOAD_IDLE;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- }
- break;
-
- case DFU_STATE_MANIFEST_SYNC :
- if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS)
- {
- hdfu->dev_state = DFU_STATE_MANIFEST;
-
- hdfu->dev_status[1] = 1; /*bwPollTimeout = 1ms*/
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- }
- else if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && \
- ((USBD_DFU_CfgDesc[(11 + (9 * USBD_DFU_MAX_ITF_NUM))]) & 0x04))
- {
- hdfu->dev_state = DFU_STATE_IDLE;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- }
- break;
-
- default :
- break;
- }
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(hdfu->dev_status[0])),
- 6);
-}
-
-/**
- * @brief DFU_ClearStatus
- * Handles the DFU CLRSTATUS request.
- * @param pdev: device instance
- * @retval status
- */
-static void DFU_ClearStatus(USBD_HandleTypeDef *pdev)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- if (hdfu->dev_state == DFU_STATE_ERROR)
- {
- hdfu->dev_state = DFU_STATE_IDLE;
- hdfu->dev_status[0] = DFU_ERROR_NONE;/*bStatus*/
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/
- hdfu->dev_status[4] = hdfu->dev_state;/*bState*/
- hdfu->dev_status[5] = 0;/*iString*/
- }
- else
- { /*State Error*/
- hdfu->dev_state = DFU_STATE_ERROR;
- hdfu->dev_status[0] = DFU_ERROR_UNKNOWN;/*bStatus*/
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/
- hdfu->dev_status[4] = hdfu->dev_state;/*bState*/
- hdfu->dev_status[5] = 0;/*iString*/
- }
-}
-
-/**
- * @brief DFU_GetState
- * Handles the DFU GETSTATE request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_GetState(USBD_HandleTypeDef *pdev)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- /* Return the current state of the DFU interface */
- USBD_CtlSendData (pdev,
- &hdfu->dev_state,
- 1);
-}
-
-/**
- * @brief DFU_Abort
- * Handles the DFU ABORT request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_Abort(USBD_HandleTypeDef *pdev)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC
- || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC
- || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE )
- {
- hdfu->dev_state = DFU_STATE_IDLE;
- hdfu->dev_status[0] = DFU_ERROR_NONE;
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/
- hdfu->dev_status[4] = hdfu->dev_state;
- hdfu->dev_status[5] = 0; /*iString*/
- hdfu->wblock_num = 0;
- hdfu->wlength = 0;
- }
-}
-
-/**
- * @brief DFU_Leave
- * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode
- * and resets device to jump to user loaded code).
- * @param pdev: device instance
- * @retval None
- */
-void DFU_Leave(USBD_HandleTypeDef *pdev)
-{
- USBD_DFU_HandleTypeDef *hdfu;
-
- hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;
-
- hdfu->manif_state = DFU_MANIFEST_COMPLETE;
-
- if ((USBD_DFU_CfgDesc[(11 + (9 * USBD_DFU_MAX_ITF_NUM))]) & 0x04)
- {
- hdfu->dev_state = DFU_STATE_MANIFEST_SYNC;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
- return;
- }
- else
- {
-
- hdfu->dev_state = DFU_STATE_MANIFEST_WAIT_RESET;
-
- hdfu->dev_status[1] = 0;
- hdfu->dev_status[2] = 0;
- hdfu->dev_status[3] = 0;
- hdfu->dev_status[4] = hdfu->dev_state;
-
- /* Disconnect the USB device */
- USBD_Stop (pdev);
-
- /* DeInitilialize the MAL(Media Access Layer) */
- ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit();
-
- /* Generate system reset to allow jumping to the user code */
- NVIC_SystemReset();
-
- /* This instruction will not be reached (system reset) */
- for(;;);
- }
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu_media_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu_media_template.c
deleted file mode 100644
index da56e59ee14..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu_media_template.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_media_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Memory management layer
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_media_template.h"
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Extern function prototypes ------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-uint16_t MEM_If_Init(void);
-uint16_t MEM_If_Erase (uint32_t Add);
-uint16_t MEM_If_Write (uint8_t *src, uint8_t *dest, uint32_t Len);
-uint8_t *MEM_If_Read (uint8_t *src, uint8_t *dest, uint32_t Len);
-uint16_t MEM_If_DeInit(void);
-uint16_t MEM_If_GetStatus (uint32_t Add, uint8_t Cmd, uint8_t *buffer);
-
-USBD_DFU_MediaTypeDef USBD_DFU_MEDIA_Template_fops =
-{
- (uint8_t *)"DFU MEDIA",
- MEM_If_Init,
- MEM_If_DeInit,
- MEM_If_Erase,
- MEM_If_Write,
- MEM_If_Read,
- MEM_If_GetStatus,
-
-};
-/**
- * @brief MEM_If_Init
- * Memory initialization routine.
- * @param None
- * @retval 0 if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Init(void)
-{
- return 0;
-}
-
-/**
- * @brief MEM_If_DeInit
- * Memory deinitialization routine.
- * @param None
- * @retval 0 if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_DeInit(void)
-{
- return 0;
-}
-
-/**
- * @brief MEM_If_Erase
- * Erase sector.
- * @param Add: Address of sector to be erased.
- * @retval 0 if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Erase(uint32_t Add)
-{
- return 0;
-}
-
-/**
- * @brief MEM_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval 0 if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Write(uint8_t *src, uint8_t *dest, uint32_t Len)
-{
- return 0;
-}
-
-/**
- * @brief MEM_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the physical address where data should be read.
- */
-uint8_t *MEM_If_Read (uint8_t *src, uint8_t *dest, uint32_t Len)
-{
- /* Return a valid address to avoid HardFault */
- return (uint8_t*)(0);
-}
-
-/**
- * @brief Flash_If_GetStatus
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param cmd: Number of data to be read (in bytes).
- * @retval Pointer to the physical address where data should be read.
- */
-uint16_t MEM_If_GetStatus (uint32_t Add, uint8_t Cmd, uint8_t *buffer)
-{
- switch (Cmd)
- {
- case DFU_MEDIA_PROGRAM:
-
- break;
-
- case DFU_MEDIA_ERASE:
- default:
-
- break;
- }
- return (0);
-}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h
deleted file mode 100644
index a78251aa40f..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_hid_core.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_H
-#define __USB_HID_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_HID
- * @brief This file is the Header file for usbd_hid.c
- * @{
- */
-
-
-/** @defgroup USBD_HID_Exported_Defines
- * @{
- */
-#define HID_EPIN_ADDR 0x81
-#define HID_EPIN_SIZE 0x04
-
-#define USB_HID_CONFIG_DESC_SIZ 34
-#define USB_HID_DESC_SIZ 9
-#define HID_MOUSE_REPORT_DESC_SIZE 74
-
-#define HID_DESCRIPTOR_TYPE 0x21
-#define HID_REPORT_DESC 0x22
-
-#define HID_HS_BINTERVAL 0x07
-#define HID_FS_BINTERVAL 0x0A
-#define HID_POLLING_INTERVAL 0x0A
-
-#define HID_REQ_SET_PROTOCOL 0x0B
-#define HID_REQ_GET_PROTOCOL 0x03
-
-#define HID_REQ_SET_IDLE 0x0A
-#define HID_REQ_GET_IDLE 0x02
-
-#define HID_REQ_SET_REPORT 0x09
-#define HID_REQ_GET_REPORT 0x01
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-typedef enum
-{
- HID_IDLE = 0,
- HID_BUSY,
-}
-HID_StateTypeDef;
-
-
-typedef struct
-{
- uint32_t Protocol;
- uint32_t IdleState;
- uint32_t AltSetting;
- HID_StateTypeDef state;
-}
-USBD_HID_HandleTypeDef;
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_HID;
-#define USBD_HID_CLASS &USBD_HID
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-uint8_t USBD_HID_SendReport (USBD_HandleTypeDef *pdev,
- uint8_t *report,
- uint16_t len);
-
-uint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HID_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
deleted file mode 100644
index 071436cd0b7..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse protocol
- * - Usage Page : Generic Desktop
- * - Usage : Joystick
- * - Collection : Application
- *
- * @note In HS mode and when the DMA is used, all variables and data structures
- * dealing with the DMA during the transaction process should be 32-bit aligned.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_HID
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_HID_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_HID_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_HID_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup USBD_HID_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_HID_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t *USBD_HID_GetCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_HID_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t USBD_HID_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-/**
- * @}
- */
-
-/** @defgroup USBD_HID_Private_Variables
- * @{
- */
-
-USBD_ClassTypeDef USBD_HID =
-{
- USBD_HID_Init,
- USBD_HID_DeInit,
- USBD_HID_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_HID_DataIn, /*DataIn*/
- NULL, /*DataOut*/
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_HID_GetCfgDesc,
- USBD_HID_GetCfgDesc,
- USBD_HID_GetCfgDesc,
- USBD_HID_GetDeviceQualifierDesc,
-};
-
-/* USB HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_HID_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x01, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of Mouse endpoint ********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/
-
- HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */
- 0x00,
- HID_FS_BINTERVAL, /*bInterval: Polling Interval (10 ms)*/
- /* 34 */
-} ;
-
-/* USB HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END =
-{
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END =
-{
- 0x05, 0x01,
- 0x09, 0x02,
- 0xA1, 0x01,
- 0x09, 0x01,
-
- 0xA1, 0x00,
- 0x05, 0x09,
- 0x19, 0x01,
- 0x29, 0x03,
-
- 0x15, 0x00,
- 0x25, 0x01,
- 0x95, 0x03,
- 0x75, 0x01,
-
- 0x81, 0x02,
- 0x95, 0x01,
- 0x75, 0x05,
- 0x81, 0x01,
-
- 0x05, 0x01,
- 0x09, 0x30,
- 0x09, 0x31,
- 0x09, 0x38,
-
- 0x15, 0x81,
- 0x25, 0x7F,
- 0x75, 0x08,
- 0x95, 0x03,
-
- 0x81, 0x06,
- 0xC0, 0x09,
- 0x3c, 0x05,
- 0xff, 0x09,
-
- 0x01, 0x15,
- 0x00, 0x25,
- 0x01, 0x75,
- 0x01, 0x95,
-
- 0x02, 0xb1,
- 0x22, 0x75,
- 0x06, 0x95,
- 0x01, 0xb1,
-
- 0x01, 0xc0
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_HID_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_HID_Init
- * Initialize the HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- uint8_t ret = 0;
-
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- HID_EPIN_ADDR,
- USBD_EP_TYPE_INTR,
- HID_EPIN_SIZE);
-
- pdev->pClassData = USBD_malloc(sizeof (USBD_HID_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- ret = 1;
- }
- else
- {
- ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;
- }
- return ret;
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- /* Close HID EPs */
- USBD_LL_CloseEP(pdev,
- HID_EPIN_ADDR);
-
- /* FRee allocated memory */
- if(pdev->pClassData != NULL)
- {
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
- USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef*) pdev->pClassData;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
-
-
- case HID_REQ_SET_PROTOCOL:
- hhid->Protocol = (uint8_t)(req->wValue);
- break;
-
- case HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->Protocol,
- 1);
- break;
-
- case HID_REQ_SET_IDLE:
- hhid->IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->IdleState,
- 1);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == HID_REPORT_DESC)
- {
- len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);
- pbuf = HID_MOUSE_ReportDesc;
- }
- else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
- {
- pbuf = USBD_HID_Desc;
- len = MIN(USB_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&hhid->AltSetting,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- hhid->AltSetting = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_SendReport
- * Send HID Report
- * @param pdev: device instance
- * @param buff: pointer to report
- * @retval status
- */
-uint8_t USBD_HID_SendReport (USBD_HandleTypeDef *pdev,
- uint8_t *report,
- uint16_t len)
-{
- USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef*)pdev->pClassData;
-
- if (pdev->dev_state == USBD_STATE_CONFIGURED )
- {
- if(hhid->state == HID_IDLE)
- {
- hhid->state = HID_BUSY;
- USBD_LL_Transmit (pdev,
- HID_EPIN_ADDR,
- report,
- len);
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_GetPollingInterval
- * return polling interval from endpoint descriptor
- * @param pdev: device instance
- * @retval polling interval
- */
-uint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev)
-{
- uint32_t polling_interval = 0;
-
- /* HIGH-speed endpoints */
- if(pdev->dev_speed == USBD_SPEED_HIGH)
- {
- /* Sets the data transfer polling interval for high speed transfers.
- Values between 1..16 are allowed. Values correspond to interval
- of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
- polling_interval = (((1 <<(HID_HS_BINTERVAL - 1)))/8);
- }
- else /* LOW and FULL-speed endpoints */
- {
- /* Sets the data transfer polling interval for low and full
- speed transfers */
- polling_interval = HID_FS_BINTERVAL;
- }
-
- return ((uint32_t)(polling_interval));
-}
-
-/**
- * @brief USBD_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_HID_GetCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_HID_CfgDesc);
- return USBD_HID_CfgDesc;
-}
-
-
-/**
- * @brief USBD_HID_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- /* Ensure that the FIFO is empty before a new transfer, this condition could
- be caused by a new transfer before the end of the previous transfer */
- ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;
- return USBD_OK;
-}
-
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-static uint8_t *USBD_HID_GetDeviceQualifierDesc (uint16_t *length)
-{
- *length = sizeof (USBD_HID_DeviceQualifierDesc);
- return USBD_HID_DeviceQualifierDesc;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h
deleted file mode 100644
index 5e671f6e6a2..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for the usbd_msc.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_H
-#define __USBD_MSC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_ioreq.h"
-
-/** @addtogroup USBD_MSC_BOT
- * @{
- */
-
-/** @defgroup USBD_MSC
- * @brief This file is the Header file for usbd_msc.c
- * @{
- */
-
-
-/** @defgroup USBD_BOT_Exported_Defines
- * @{
- */
-#define MSC_MAX_FS_PACKET 0x40
-#define MSC_MAX_HS_PACKET 0x200
-
-#define BOT_GET_MAX_LUN 0xFE
-#define BOT_RESET 0xFF
-#define USB_MSC_CONFIG_DESC_SIZ 32
-
-
-#define MSC_EPIN_ADDR 0x81
-#define MSC_EPOUT_ADDR 0x01
-
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Types
- * @{
- */
-typedef struct _USBD_STORAGE
-{
- int8_t (* Init) (uint8_t lun);
- int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint16_t *block_size);
- int8_t (* IsReady) (uint8_t lun);
- int8_t (* IsWriteProtected) (uint8_t lun);
- int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* GetMaxLun)(void);
- int8_t *pInquiry;
-
-}USBD_StorageTypeDef;
-
-
-typedef struct
-{
- uint32_t max_lun;
- uint32_t interface;
- uint8_t bot_state;
- uint8_t bot_status;
- uint16_t bot_data_length;
- uint8_t bot_data[MSC_MEDIA_PACKET];
- USBD_MSC_BOT_CBWTypeDef cbw;
- USBD_MSC_BOT_CSWTypeDef csw;
-
- USBD_SCSI_SenseTypeDef scsi_sense [SENSE_LIST_DEEPTH];
- uint8_t scsi_sense_head;
- uint8_t scsi_sense_tail;
-
- uint16_t scsi_blk_size;
- uint32_t scsi_blk_nbr;
-
- uint32_t scsi_blk_addr;
- uint32_t scsi_blk_len;
-}
-USBD_MSC_BOT_HandleTypeDef;
-
-/* Structure for MSC process */
-extern USBD_ClassTypeDef USBD_MSC;
-#define USBD_MSC_CLASS &USBD_MSC
-
-uint8_t USBD_MSC_RegisterStorage (USBD_HandleTypeDef *pdev,
- USBD_StorageTypeDef *fops);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_MSC_H */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h
deleted file mode 100644
index 4d055737cff..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_bot.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for the usbd_msc_bot.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup MSC_BOT
- * @brief This file is the Header file for usbd_msc_bot.c
- * @{
- */
-
-
-/** @defgroup USBD_CORE_Exported_Defines
- * @{
- */
-#define USBD_BOT_IDLE 0 /* Idle state */
-#define USBD_BOT_DATA_OUT 1 /* Data Out state */
-#define USBD_BOT_DATA_IN 2 /* Data In state */
-#define USBD_BOT_LAST_DATA_IN 3 /* Last Data In Last */
-#define USBD_BOT_SEND_DATA 4 /* Send Immediate data */
-#define USBD_BOT_NO_DATA 5 /* No data Stage */
-
-#define USBD_BOT_CBW_SIGNATURE 0x43425355
-#define USBD_BOT_CSW_SIGNATURE 0x53425355
-#define USBD_BOT_CBW_LENGTH 31
-#define USBD_BOT_CSW_LENGTH 13
-#define USBD_BOT_MAX_DATA 256
-
-/* CSW Status Definitions */
-#define USBD_CSW_CMD_PASSED 0x00
-#define USBD_CSW_CMD_FAILED 0x01
-#define USBD_CSW_PHASE_ERROR 0x02
-
-/* BOT Status */
-#define USBD_BOT_STATUS_NORMAL 0
-#define USBD_BOT_STATUS_RECOVERY 1
-#define USBD_BOT_STATUS_ERROR 2
-
-
-#define USBD_DIR_IN 0
-#define USBD_DIR_OUT 1
-#define USBD_BOTH_DIR 2
-
-/**
- * @}
- */
-
-/** @defgroup MSC_CORE_Private_TypesDefinitions
- * @{
- */
-
-typedef struct
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataLength;
- uint8_t bmFlags;
- uint8_t bLUN;
- uint8_t bCBLength;
- uint8_t CB[16];
- uint8_t ReservedForAlign;
-}
-USBD_MSC_BOT_CBWTypeDef;
-
-
-typedef struct
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataResidue;
- uint8_t bStatus;
- uint8_t ReservedForAlign[3];
-}
-USBD_MSC_BOT_CSWTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_Types
- * @{
- */
-
-/**
- * @}
- */
-/** @defgroup USBD_CORE_Exported_FunctionsPrototypes
- * @{
- */
-void MSC_BOT_Init (USBD_HandleTypeDef *pdev);
-void MSC_BOT_Reset (USBD_HandleTypeDef *pdev);
-void MSC_BOT_DeInit (USBD_HandleTypeDef *pdev);
-void MSC_BOT_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-void MSC_BOT_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-void MSC_BOT_SendCSW (USBD_HandleTypeDef *pdev,
- uint8_t CSW_Status);
-
-void MSC_BOT_CplClrFeature (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_MSC_BOT_H */
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h
deleted file mode 100644
index f10693122b0..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_data.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for the usbd_msc_data.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_DATA_H
-#define __USBD_MSC_DATA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USB_INFO
- * @brief general defines for the usb device library file
- * @{
- */
-
-/** @defgroup USB_INFO_Exported_Defines
- * @{
- */
-#define MODE_SENSE6_LEN 8
-#define MODE_SENSE10_LEN 8
-#define LENGTH_INQUIRY_PAGE00 7
-#define LENGTH_FORMAT_CAPACITIES 20
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_INFO_Exported_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_INFO_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_INFO_Exported_Variables
- * @{
- */
-extern const uint8_t MSC_Page00_Inquiry_Data[];
-extern const uint8_t MSC_Mode_Sense6_data[];
-extern const uint8_t MSC_Mode_Sense10_data[] ;
-
-/**
- * @}
- */
-
-/** @defgroup USBD_INFO_Exported_FunctionsPrototype
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_MSC_DATA_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h
deleted file mode 100644
index dbf3bc15101..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header for the usbd_msc_scsi.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_SCSI_H
-#define __USBD_MSC_SCSI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_SCSI
- * @brief header file for the storage disk file
- * @{
- */
-
-/** @defgroup USBD_SCSI_Exported_Defines
- * @{
- */
-
-#define SENSE_LIST_DEEPTH 4
-
-/* SCSI Commands */
-#define SCSI_FORMAT_UNIT 0x04
-#define SCSI_INQUIRY 0x12
-#define SCSI_MODE_SELECT6 0x15
-#define SCSI_MODE_SELECT10 0x55
-#define SCSI_MODE_SENSE6 0x1A
-#define SCSI_MODE_SENSE10 0x5A
-#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E
-#define SCSI_READ6 0x08
-#define SCSI_READ10 0x28
-#define SCSI_READ12 0xA8
-#define SCSI_READ16 0x88
-
-#define SCSI_READ_CAPACITY10 0x25
-#define SCSI_READ_CAPACITY16 0x9E
-
-#define SCSI_REQUEST_SENSE 0x03
-#define SCSI_START_STOP_UNIT 0x1B
-#define SCSI_TEST_UNIT_READY 0x00
-#define SCSI_WRITE6 0x0A
-#define SCSI_WRITE10 0x2A
-#define SCSI_WRITE12 0xAA
-#define SCSI_WRITE16 0x8A
-
-#define SCSI_VERIFY10 0x2F
-#define SCSI_VERIFY12 0xAF
-#define SCSI_VERIFY16 0x8F
-
-#define SCSI_SEND_DIAGNOSTIC 0x1D
-#define SCSI_READ_FORMAT_CAPACITIES 0x23
-
-#define NO_SENSE 0
-#define RECOVERED_ERROR 1
-#define NOT_READY 2
-#define MEDIUM_ERROR 3
-#define HARDWARE_ERROR 4
-#define ILLEGAL_REQUEST 5
-#define UNIT_ATTENTION 6
-#define DATA_PROTECT 7
-#define BLANK_CHECK 8
-#define VENDOR_SPECIFIC 9
-#define COPY_ABORTED 10
-#define ABORTED_COMMAND 11
-#define VOLUME_OVERFLOW 13
-#define MISCOMPARE 14
-
-
-#define INVALID_CDB 0x20
-#define INVALID_FIELED_IN_COMMAND 0x24
-#define PARAMETER_LIST_LENGTH_ERROR 0x1A
-#define INVALID_FIELD_IN_PARAMETER_LIST 0x26
-#define ADDRESS_OUT_OF_RANGE 0x21
-#define MEDIUM_NOT_PRESENT 0x3A
-#define MEDIUM_HAVE_CHANGED 0x28
-#define WRITE_PROTECTED 0x27
-#define UNRECOVERED_READ_ERROR 0x11
-#define WRITE_FAULT 0x03
-
-#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C
-#define READ_CAPACITY10_DATA_LEN 0x08
-#define MODE_SENSE10_DATA_LEN 0x08
-#define MODE_SENSE6_DATA_LEN 0x04
-#define REQUEST_SENSE_DATA_LEN 0x12
-#define STANDARD_INQUIRY_DATA_LEN 0x24
-#define BLKVFY 0x04
-
-extern uint8_t Page00_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data2[];
-extern uint8_t Mode_Sense6_data[];
-extern uint8_t Mode_Sense10_data[];
-extern uint8_t Scsi_Sense_Data[];
-extern uint8_t ReadCapacity10_Data[];
-extern uint8_t ReadFormatCapacity_Data [];
-/**
- * @}
- */
-
-
-/** @defgroup USBD_SCSI_Exported_TypesDefinitions
- * @{
- */
-
-typedef struct _SENSE_ITEM {
- char Skey;
- union {
- struct _ASCs {
- char ASC;
- char ASCQ;
- }b;
- unsigned int ASC;
- char *pData;
- } w;
-} USBD_SCSI_SenseTypeDef;
-/**
- * @}
- */
-
-/** @defgroup USBD_SCSI_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_SCSI_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-/** @defgroup USBD_SCSI_Exported_FunctionsPrototype
- * @{
- */
-int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev,
- uint8_t lun,
- uint8_t *cmd);
-
-void SCSI_SenseCode(USBD_HandleTypeDef *pdev,
- uint8_t lun,
- uint8_t sKey,
- uint8_t ASC);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_MSC_SCSI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h
deleted file mode 100644
index 877a7d2ae45..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_storage.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_msc_storage.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_STORAGE_H
-#define __USBD_MSC_STORAGE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_STORAGE
- * @brief header file for the usbd_msc_storage.c file
- * @{
- */
-
-/** @defgroup USBD_STORAGE_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_STORAGE_Exported_Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_STORAGE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_STORAGE_Exported_Variables
- * @{
- */
-extern USBD_StorageTypeDef USBD_MSC_Template_fops;
-/**
- * @}
- */
-
-/** @defgroup USBD_STORAGE_Exported_FunctionsPrototype
- * @{
- */
-
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_MSC_STORAGE_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
deleted file mode 100644
index 46b719fac5e..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides all the MSC core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * MSC Class Description
- * ===================================================================
- * This module manages the MSC class V1.0 following the "Universal
- * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
- * Sep. 31, 1999".
- * This driver implements the following aspects of the specification:
- * - Bulk-Only Transport protocol
- * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_CORE
- * @brief Mass storage core module
- * @{
- */
-
-/** @defgroup MSC_CORE_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_FunctionPrototypes
- * @{
- */
-uint8_t USBD_MSC_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-uint8_t USBD_MSC_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-
-uint8_t USBD_MSC_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum);
-
-uint8_t *USBD_MSC_GetHSCfgDesc (uint16_t *length);
-
-uint8_t *USBD_MSC_GetFSCfgDesc (uint16_t *length);
-
-uint8_t *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length);
-
-uint8_t *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length);
-
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Variables
- * @{
- */
-
-
-USBD_ClassTypeDef USBD_MSC =
-{
- USBD_MSC_Init,
- USBD_MSC_DeInit,
- USBD_MSC_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_MSC_DataIn,
- USBD_MSC_DataOut,
- NULL, /*SOF */
- NULL,
- NULL,
- USBD_MSC_GetHSCfgDesc,
- USBD_MSC_GetFSCfgDesc,
- USBD_MSC_GetOtherSpeedCfgDesc,
- USBD_MSC_GetDeviceQualifierDescriptor,
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-__ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
-
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_HS_PACKET),
- HIBYTE(MSC_MAX_HS_PACKET),
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_HS_PACKET),
- HIBYTE(MSC_MAX_HS_PACKET),
- 0x00 /*Polling interval in milliseconds*/
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
-
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_FS_PACKET),
- HIBYTE(MSC_MAX_FS_PACKET),
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_FS_PACKET),
- HIBYTE(MSC_MAX_FS_PACKET),
- 0x00 /*Polling interval in milliseconds*/
-};
-
-__ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
-{
-
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent command set*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- 0x40,
- 0x00,
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- 0x40,
- 0x00,
- 0x00 /*Polling interval in milliseconds*/
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- MSC_MAX_FS_PACKET,
- 0x01,
- 0x00,
-};
-/**
- * @}
- */
-
-
-/** @defgroup MSC_CORE_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_MSC_Init
- * Initialize the mass storage configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-uint8_t USBD_MSC_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- int16_t ret = 0;
-
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- MSC_EPOUT_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_HS_PACKET);
-
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPIN_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_HS_PACKET);
- }
- else
- {
- /* Open EP OUT */
- USBD_LL_OpenEP(pdev,
- MSC_EPOUT_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_FS_PACKET);
-
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPIN_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_FS_PACKET);
- }
- pdev->pClassData = USBD_malloc(sizeof (USBD_MSC_BOT_HandleTypeDef));
-
- if(pdev->pClassData == NULL)
- {
- ret = 1;
- }
- else
- {
- /* Init the BOT layer */
- MSC_BOT_Init(pdev);
- ret = 0;
- }
-
- return ret;
-}
-
-/**
- * @brief USBD_MSC_DeInit
- * DeInitilaize the mass storage configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-uint8_t USBD_MSC_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- /* Close MSC EPs */
- USBD_LL_CloseEP(pdev,
- MSC_EPOUT_ADDR);
-
- /* Open EP IN */
- USBD_LL_CloseEP(pdev,
- MSC_EPIN_ADDR);
-
-
- /* De-Init the BOT layer */
- MSC_BOT_DeInit(pdev);
-
- /* Free MSC Class Resources */
- if(pdev->pClassData != NULL)
- {
- USBD_free(pdev->pClassData);
- pdev->pClassData = NULL;
- }
- return 0;
-}
-/**
-* @brief USBD_MSC_Setup
-* Handle the MSC specific requests
-* @param pdev: device instance
-* @param req: USB request
-* @retval status
-*/
-uint8_t USBD_MSC_Setup (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
-
- /* Class request */
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case BOT_GET_MAX_LUN :
-
- if((req->wValue == 0) &&
- (req->wLength == 1) &&
- ((req->bmRequest & 0x80) == 0x80))
- {
- hmsc->max_lun = ((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun();
- USBD_CtlSendData (pdev,
- (uint8_t *)&hmsc->max_lun,
- 1);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- case BOT_RESET :
- if((req->wValue == 0) &&
- (req->wLength == 0) &&
- ((req->bmRequest & 0x80) != 0x80))
- {
- MSC_BOT_Reset(pdev);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
- /* Interface & Endpoint request */
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&hmsc->interface,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- hmsc->interface = (uint8_t)(req->wValue);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
-
- /* Flush the FIFO and Clear the stall status */
- USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);
-
- /* Reactivate the EP */
- USBD_LL_CloseEP (pdev , (uint8_t)req->wIndex);
- if((((uint8_t)req->wIndex) & 0x80) == 0x80)
- {
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPIN_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_HS_PACKET);
- }
- else
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPIN_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_FS_PACKET);
- }
- }
- else
- {
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPOUT_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_HS_PACKET);
- }
- else
- {
- /* Open EP IN */
- USBD_LL_OpenEP(pdev,
- MSC_EPOUT_ADDR,
- USBD_EP_TYPE_BULK,
- MSC_MAX_FS_PACKET);
- }
- }
-
- /* Handle BOT error */
- MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
- break;
-
- }
- break;
-
- default:
- break;
- }
- return 0;
-}
-
-/**
-* @brief USBD_MSC_DataIn
-* handle data IN Stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-uint8_t USBD_MSC_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataIn(pdev , epnum);
- return 0;
-}
-
-/**
-* @brief USBD_MSC_DataOut
-* handle data OUT Stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-uint8_t USBD_MSC_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataOut(pdev , epnum);
- return 0;
-}
-
-/**
-* @brief USBD_MSC_GetHSCfgDesc
-* return configuration descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_MSC_GetHSCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_MSC_CfgHSDesc);
- return USBD_MSC_CfgHSDesc;
-}
-
-/**
-* @brief USBD_MSC_GetFSCfgDesc
-* return configuration descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_MSC_GetFSCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_MSC_CfgFSDesc);
- return USBD_MSC_CfgFSDesc;
-}
-
-/**
-* @brief USBD_MSC_GetOtherSpeedCfgDesc
-* return other speed configuration descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_MSC_OtherSpeedCfgDesc);
- return USBD_MSC_OtherSpeedCfgDesc;
-}
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length)
-{
- *length = sizeof (USBD_MSC_DeviceQualifierDesc);
- return USBD_MSC_DeviceQualifierDesc;
-}
-
-/**
-* @brief USBD_MSC_RegisterStorage
-* @param fops: storage callback
-* @retval status
-*/
-uint8_t USBD_MSC_RegisterStorage (USBD_HandleTypeDef *pdev,
- USBD_StorageTypeDef *fops)
-{
- if(fops != NULL)
- {
- pdev->pUserData= fops;
- }
- return 0;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
deleted file mode 100644
index 83da84adf02..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_bot.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides all the BOT protocol core functions.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-#include "usbd_msc.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_BOT
- * @brief BOT protocol module
- * @{
- */
-
-/** @defgroup MSC_BOT_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_FunctionPrototypes
- * @{
- */
-static void MSC_BOT_CBW_Decode (USBD_HandleTypeDef *pdev);
-
-static void MSC_BOT_SendData (USBD_HandleTypeDef *pdev,
- uint8_t* pbuf,
- uint16_t len);
-
-static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev);
-/**
- * @}
- */
-
-
-/** @defgroup MSC_BOT_Private_Functions
- * @{
- */
-
-
-
-/**
-* @brief MSC_BOT_Init
-* Initialize the BOT Process
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_Init (USBD_HandleTypeDef *pdev)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->bot_state = USBD_BOT_IDLE;
- hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
-
- hmsc->scsi_sense_tail = 0;
- hmsc->scsi_sense_head = 0;
-
- ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0);
-
- USBD_LL_FlushEP(pdev, MSC_EPOUT_ADDR);
- USBD_LL_FlushEP(pdev, MSC_EPIN_ADDR);
-
- /* Prapare EP to Receive First BOT Cmd */
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- (uint8_t *)&hmsc->cbw,
- USBD_BOT_CBW_LENGTH);
-}
-
-/**
-* @brief MSC_BOT_Reset
-* Reset the BOT Machine
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_Reset (USBD_HandleTypeDef *pdev)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->bot_state = USBD_BOT_IDLE;
- hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;
-
- /* Prapare EP to Receive First BOT Cmd */
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- (uint8_t *)&hmsc->cbw,
- USBD_BOT_CBW_LENGTH);
-}
-
-/**
-* @brief MSC_BOT_DeInit
-* Deinitialize the BOT Machine
-* @param pdev: device instance
-* @retval None
-*/
-void MSC_BOT_DeInit (USBD_HandleTypeDef *pdev)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
- hmsc->bot_state = USBD_BOT_IDLE;
-}
-
-/**
-* @brief MSC_BOT_DataIn
-* Handle BOT IN data stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-void MSC_BOT_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- switch (hmsc->bot_state)
- {
- case USBD_BOT_DATA_IN:
- if(SCSI_ProcessCmd(pdev,
- hmsc->cbw.bLUN,
- &hmsc->cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
- }
- break;
-
- case USBD_BOT_SEND_DATA:
- case USBD_BOT_LAST_DATA_IN:
- MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);
-
- break;
-
- default:
- break;
- }
-}
-/**
-* @brief MSC_BOT_DataOut
-* Process MSC OUT data
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-void MSC_BOT_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- switch (hmsc->bot_state)
- {
- case USBD_BOT_IDLE:
- MSC_BOT_CBW_Decode(pdev);
- break;
-
- case USBD_BOT_DATA_OUT:
-
- if(SCSI_ProcessCmd(pdev,
- hmsc->cbw.bLUN,
- &hmsc->cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
- }
-
- break;
-
- default:
- break;
- }
-}
-
-/**
-* @brief MSC_BOT_CBW_Decode
-* Decode the CBW command and set the BOT state machine accordingly
-* @param pdev: device instance
-* @retval None
-*/
-static void MSC_BOT_CBW_Decode (USBD_HandleTypeDef *pdev)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->csw.dTag = hmsc->cbw.dTag;
- hmsc->csw.dDataResidue = hmsc->cbw.dDataLength;
-
- if ((USBD_LL_GetRxDataSize (pdev ,MSC_EPOUT_ADDR) != USBD_BOT_CBW_LENGTH) ||
- (hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE)||
- (hmsc->cbw.bLUN > 1) ||
- (hmsc->cbw.bCBLength < 1) ||
- (hmsc->cbw.bCBLength > 16))
- {
-
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
-
- hmsc->bot_status = USBD_BOT_STATUS_ERROR;
- MSC_BOT_Abort(pdev);
-
- }
- else
- {
- if(SCSI_ProcessCmd(pdev,
- hmsc->cbw.bLUN,
- &hmsc->cbw.CB[0]) < 0)
- {
- if(hmsc->bot_state == USBD_BOT_NO_DATA)
- {
- MSC_BOT_SendCSW (pdev,
- USBD_CSW_CMD_FAILED);
- }
- else
- {
- MSC_BOT_Abort(pdev);
- }
- }
- /*Burst xfer handled internally*/
- else if ((hmsc->bot_state != USBD_BOT_DATA_IN) &&
- (hmsc->bot_state != USBD_BOT_DATA_OUT) &&
- (hmsc->bot_state != USBD_BOT_LAST_DATA_IN))
- {
- if (hmsc->bot_data_length > 0)
- {
- MSC_BOT_SendData(pdev,
- hmsc->bot_data,
- hmsc->bot_data_length);
- }
- else if (hmsc->bot_data_length == 0)
- {
- MSC_BOT_SendCSW (pdev,
- USBD_CSW_CMD_PASSED);
- }
- }
- }
-}
-
-/**
-* @brief MSC_BOT_SendData
-* Send the requested data
-* @param pdev: device instance
-* @param buf: pointer to data buffer
-* @param len: Data Length
-* @retval None
-*/
-static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev,
- uint8_t* buf,
- uint16_t len)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- len = MIN (hmsc->cbw.dDataLength, len);
- hmsc->csw.dDataResidue -= len;
- hmsc->csw.bStatus = USBD_CSW_CMD_PASSED;
- hmsc->bot_state = USBD_BOT_SEND_DATA;
-
- USBD_LL_Transmit (pdev, MSC_EPIN_ADDR, buf, len);
-}
-
-/**
-* @brief MSC_BOT_SendCSW
-* Send the Command Status Wrapper
-* @param pdev: device instance
-* @param status : CSW status
-* @retval None
-*/
-void MSC_BOT_SendCSW (USBD_HandleTypeDef *pdev,
- uint8_t CSW_Status)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE;
- hmsc->csw.bStatus = CSW_Status;
- hmsc->bot_state = USBD_BOT_IDLE;
-
- USBD_LL_Transmit (pdev,
- MSC_EPIN_ADDR,
- (uint8_t *)&hmsc->csw,
- USBD_BOT_CSW_LENGTH);
-
- /* Prepare EP to Receive next Cmd */
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- (uint8_t *)&hmsc->cbw,
- USBD_BOT_CBW_LENGTH);
-
-}
-
-/**
-* @brief MSC_BOT_Abort
-* Abort the current transfer
-* @param pdev: device instance
-* @retval status
-*/
-
-static void MSC_BOT_Abort (USBD_HandleTypeDef *pdev)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- if ((hmsc->cbw.bmFlags == 0) &&
- (hmsc->cbw.dDataLength != 0) &&
- (hmsc->bot_status == USBD_BOT_STATUS_NORMAL) )
- {
- USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR );
- }
- USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);
-
- if(hmsc->bot_status == USBD_BOT_STATUS_ERROR)
- {
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- (uint8_t *)&hmsc->cbw,
- USBD_BOT_CBW_LENGTH);
- }
-}
-
-/**
-* @brief MSC_BOT_CplClrFeature
-* Complete the clear feature request
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval None
-*/
-
-void MSC_BOT_CplClrFeature (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- if(hmsc->bot_status == USBD_BOT_STATUS_ERROR )/* Bad CBW Signature */
- {
- USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);
- hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
- }
- else if(((epnum & 0x80) == 0x80) && ( hmsc->bot_status != USBD_BOT_STATUS_RECOVERY))
- {
- MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
- }
-
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
deleted file mode 100644
index 3bad8fd9234..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_data.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides all the vital inquiry pages and sense data.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_data.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_DATA
- * @brief Mass storage info/data module
- * @{
- */
-
-/** @defgroup MSC_DATA_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Variables
- * @{
- */
-
-
-/* USB Mass storage Page 0 Inquiry Data */
-const uint8_t MSC_Page00_Inquiry_Data[] = {//7
- 0x00,
- 0x00,
- 0x00,
- (LENGTH_INQUIRY_PAGE00 - 4),
- 0x00,
- 0x80,
- 0x83
-};
-/* USB Mass storage sense 6 Data */
-const uint8_t MSC_Mode_Sense6_data[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/* USB Mass storage sense 10 Data */
-const uint8_t MSC_Mode_Sense10_data[] = {
- 0x00,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_DATA_Private_Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
deleted file mode 100644
index 5d4d2521693..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides all the USBD SCSI layer functions.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_msc.h"
-#include "usbd_msc_data.h"
-
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup MSC_SCSI
- * @brief Mass storage SCSI layer module
- * @{
- */
-
-/** @defgroup MSC_SCSI_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_FunctionPrototypes
- * @{
- */
-static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_RequestSense (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun , uint8_t *params);
-static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun , uint8_t *params);
-static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef *pdev,
- uint8_t lun ,
- uint32_t blk_offset ,
- uint16_t blk_nbr);
-static int8_t SCSI_ProcessRead (USBD_HandleTypeDef *pdev,
- uint8_t lun);
-
-static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef *pdev,
- uint8_t lun);
-/**
- * @}
- */
-
-
-/** @defgroup MSC_SCSI_Private_Functions
- * @{
- */
-
-
-/**
-* @brief SCSI_ProcessCmd
-* Process SCSI commands
-* @param pdev: device instance
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev,
- uint8_t lun,
- uint8_t *params)
-{
-
- switch (params[0])
- {
- case SCSI_TEST_UNIT_READY:
- return SCSI_TestUnitReady(pdev, lun, params);
-
- case SCSI_REQUEST_SENSE:
- return SCSI_RequestSense (pdev, lun, params);
- case SCSI_INQUIRY:
- return SCSI_Inquiry(pdev, lun, params);
-
- case SCSI_START_STOP_UNIT:
- return SCSI_StartStopUnit(pdev, lun, params);
-
- case SCSI_ALLOW_MEDIUM_REMOVAL:
- return SCSI_StartStopUnit(pdev, lun, params);
-
- case SCSI_MODE_SENSE6:
- return SCSI_ModeSense6 (pdev, lun, params);
-
- case SCSI_MODE_SENSE10:
- return SCSI_ModeSense10 (pdev, lun, params);
-
- case SCSI_READ_FORMAT_CAPACITIES:
- return SCSI_ReadFormatCapacity(pdev, lun, params);
-
- case SCSI_READ_CAPACITY10:
- return SCSI_ReadCapacity10(pdev, lun, params);
-
- case SCSI_READ10:
- return SCSI_Read10(pdev, lun, params);
-
- case SCSI_WRITE10:
- return SCSI_Write10(pdev, lun, params);
-
- case SCSI_VERIFY10:
- return SCSI_Verify10(pdev, lun, params);
-
- default:
- SCSI_SenseCode(pdev,
- lun,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-}
-
-
-/**
-* @brief SCSI_TestUnitReady
-* Process SCSI Test Unit Ready Command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- /* case 9 : Hi > D0 */
- if (hmsc->cbw.dDataLength != 0)
- {
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
-
- hmsc->bot_state = USBD_BOT_NO_DATA;
- return -1;
- }
- hmsc->bot_data_length = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_Inquiry
-* Process Inquiry command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- uint8_t* pPage;
- uint16_t len;
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- if (params[1] & 0x01)/*Evpd is set*/
- {
- pPage = (uint8_t *)MSC_Page00_Inquiry_Data;
- len = LENGTH_INQUIRY_PAGE00;
- }
- else
- {
-
- pPage = (uint8_t *)&((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];
- len = pPage[4] + 5;
-
- if (params[4] <= len)
- {
- len = params[4];
- }
- }
- hmsc->bot_data_length = len;
-
- while (len)
- {
- len--;
- hmsc->bot_data[len] = pPage[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ReadCapacity10
-* Process Read Capacity 10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- else
- {
-
- hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 24);
- hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 16);
- hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 8);
- hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1);
-
- hmsc->bot_data[4] = (uint8_t)(hmsc->scsi_blk_size >> 24);
- hmsc->bot_data[5] = (uint8_t)(hmsc->scsi_blk_size >> 16);
- hmsc->bot_data[6] = (uint8_t)(hmsc->scsi_blk_size >> 8);
- hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_size);
-
- hmsc->bot_data_length = 8;
- return 0;
- }
-}
-/**
-* @brief SCSI_ReadFormatCapacity
-* Process Read Format Capacity command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- uint16_t blk_size;
- uint32_t blk_nbr;
- uint16_t i;
-
- for(i=0 ; i < 12 ; i++)
- {
- hmsc->bot_data[i] = 0;
- }
-
- if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- else
- {
- hmsc->bot_data[3] = 0x08;
- hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1) >> 24);
- hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1) >> 16);
- hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1) >> 8);
- hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1);
-
- hmsc->bot_data[8] = 0x02;
- hmsc->bot_data[9] = (uint8_t)(blk_size >> 16);
- hmsc->bot_data[10] = (uint8_t)(blk_size >> 8);
- hmsc->bot_data[11] = (uint8_t)(blk_size);
-
- hmsc->bot_data_length = 12;
- return 0;
- }
-}
-/**
-* @brief SCSI_ModeSense6
-* Process Mode Sense6 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
- uint16_t len = 8 ;
- hmsc->bot_data_length = len;
-
- while (len)
- {
- len--;
- hmsc->bot_data[len] = MSC_Mode_Sense6_data[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ModeSense10
-* Process Mode Sense10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- uint16_t len = 8;
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->bot_data_length = len;
-
- while (len)
- {
- len--;
- hmsc->bot_data[len] = MSC_Mode_Sense10_data[len];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_RequestSense
-* Process Request Sense command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_RequestSense (USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- uint8_t i;
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++)
- {
- hmsc->bot_data[i] = 0;
- }
-
- hmsc->bot_data[0] = 0x70;
- hmsc->bot_data[7] = REQUEST_SENSE_DATA_LEN - 6;
-
- if((hmsc->scsi_sense_head != hmsc->scsi_sense_tail)) {
-
- hmsc->bot_data[2] = hmsc->scsi_sense[hmsc->scsi_sense_head].Skey;
- hmsc->bot_data[12] = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ;
- hmsc->bot_data[13] = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC;
- hmsc->scsi_sense_head++;
-
- if (hmsc->scsi_sense_head == SENSE_LIST_DEEPTH)
- {
- hmsc->scsi_sense_head = 0;
- }
- }
- hmsc->bot_data_length = REQUEST_SENSE_DATA_LEN;
-
- if (params[4] <= REQUEST_SENSE_DATA_LEN)
- {
- hmsc->bot_data_length = params[4];
- }
- return 0;
-}
-
-/**
-* @brief SCSI_SenseCode
-* Load the last error code in the error list
-* @param lun: Logical unit number
-* @param sKey: Sense Key
-* @param ASC: Additional Sense Key
-* @retval none
-
-*/
-void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-
- hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey = sKey;
- hmsc->scsi_sense[hmsc->scsi_sense_tail].w.ASC = ASC << 8;
- hmsc->scsi_sense_tail++;
- if (hmsc->scsi_sense_tail == SENSE_LIST_DEEPTH)
- {
- hmsc->scsi_sense_tail = 0;
- }
-}
-/**
-* @brief SCSI_StartStopUnit
-* Process Start Stop Unit command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
- hmsc->bot_data_length = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_Read10
-* Process Read10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun , uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- if(hmsc->bot_state == USBD_BOT_IDLE) /* Idle */
- {
-
- /* case 10 : Ho <> Di */
-
- if ((hmsc->cbw.bmFlags & 0x80) != 0x80)
- {
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- hmsc->scsi_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
-
- hmsc->scsi_blk_len = (params[7] << 8) | \
- params[8];
-
-
-
- if( SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, hmsc->scsi_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- hmsc->bot_state = USBD_BOT_DATA_IN;
- hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;
- hmsc->scsi_blk_len *= hmsc->scsi_blk_size;
-
- /* cases 4,5 : Hi <> Dn */
- if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)
- {
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
- }
- hmsc->bot_data_length = MSC_MEDIA_PACKET;
-
- return SCSI_ProcessRead(pdev, lun);
-}
-
-/**
-* @brief SCSI_Write10
-* Process Write10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_Write10 (USBD_HandleTypeDef *pdev, uint8_t lun , uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */
- {
-
- /* case 8 : Hi <> Do */
-
- if ((hmsc->cbw.bmFlags & 0x80) == 0x80)
- {
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Check whether Media is ready */
- if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- /* Check If media is write-protected */
- if(((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) !=0 )
- {
- SCSI_SenseCode(pdev,
- lun,
- NOT_READY,
- WRITE_PROTECTED);
- return -1;
- }
-
-
- hmsc->scsi_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
- hmsc->scsi_blk_len = (params[7] << 8) | \
- params[8];
-
- /* check if LBA address is in the right range */
- if(SCSI_CheckAddressRange(pdev,
- lun,
- hmsc->scsi_blk_addr,
- hmsc->scsi_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;
- hmsc->scsi_blk_len *= hmsc->scsi_blk_size;
-
- /* cases 3,11,13 : Hn,Ho <> D0 */
- if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)
- {
- SCSI_SenseCode(pdev,
- hmsc->cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Prepare EP to receive first data packet */
- hmsc->bot_state = USBD_BOT_DATA_OUT;
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- hmsc->bot_data,
- MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET));
- }
- else /* Write Process ongoing */
- {
- return SCSI_ProcessWrite(pdev, lun);
- }
- return 0;
-}
-
-
-/**
-* @brief SCSI_Verify10
-* Process Verify10 command
-* @param lun: Logical unit number
-* @param params: Command parameters
-* @retval status
-*/
-
-static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun , uint8_t *params)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- if ((params[1]& 0x02) == 0x02)
- {
- SCSI_SenseCode (pdev,
- lun,
- ILLEGAL_REQUEST,
- INVALID_FIELED_IN_COMMAND);
- return -1; /* Error, Verify Mode Not supported*/
- }
-
- if(SCSI_CheckAddressRange(pdev,
- lun,
- hmsc->scsi_blk_addr,
- hmsc->scsi_blk_len) < 0)
- {
- return -1; /* error */
- }
- hmsc->bot_data_length = 0;
- return 0;
-}
-
-/**
-* @brief SCSI_CheckAddressRange
-* Check address range
-* @param lun: Logical unit number
-* @param blk_offset: first block address
-* @param blk_nbr: number of block to be processed
-* @retval status
-*/
-static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef *pdev, uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr )
- {
- SCSI_SenseCode(pdev,
- lun,
- ILLEGAL_REQUEST,
- ADDRESS_OUT_OF_RANGE);
- return -1;
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ProcessRead
-* Handle Read Process
-* @param lun: Logical unit number
-* @retval status
-*/
-static int8_t SCSI_ProcessRead (USBD_HandleTypeDef *pdev, uint8_t lun)
-{
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
- uint32_t len;
-
- len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET);
-
- if( ((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun ,
- hmsc->bot_data,
- hmsc->scsi_blk_addr / hmsc->scsi_blk_size,
- len / hmsc->scsi_blk_size) < 0)
- {
-
- SCSI_SenseCode(pdev,
- lun,
- HARDWARE_ERROR,
- UNRECOVERED_READ_ERROR);
- return -1;
- }
-
-
- USBD_LL_Transmit (pdev,
- MSC_EPIN_ADDR,
- hmsc->bot_data,
- len);
-
-
- hmsc->scsi_blk_addr += len;
- hmsc->scsi_blk_len -= len;
-
- /* case 6 : Hi = Di */
- hmsc->csw.dDataResidue -= len;
-
- if (hmsc->scsi_blk_len == 0)
- {
- hmsc->bot_state = USBD_BOT_LAST_DATA_IN;
- }
- return 0;
-}
-
-/**
-* @brief SCSI_ProcessWrite
-* Handle Write Process
-* @param lun: Logical unit number
-* @retval status
-*/
-
-static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef *pdev, uint8_t lun)
-{
- uint32_t len;
- USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-
- len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET);
-
- if(((USBD_StorageTypeDef *)pdev->pUserData)->Write(lun ,
- hmsc->bot_data,
- hmsc->scsi_blk_addr / hmsc->scsi_blk_size,
- len / hmsc->scsi_blk_size) < 0)
- {
- SCSI_SenseCode(pdev,
- lun,
- HARDWARE_ERROR,
- WRITE_FAULT);
- return -1;
- }
-
-
- hmsc->scsi_blk_addr += len;
- hmsc->scsi_blk_len -= len;
-
- /* case 12 : Ho = Do */
- hmsc->csw.dDataResidue -= len;
-
- if (hmsc->scsi_blk_len == 0)
- {
- MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);
- }
- else
- {
- /* Prepare EP to Receive next packet */
- USBD_LL_PrepareReceive (pdev,
- MSC_EPOUT_ADDR,
- hmsc->bot_data,
- MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET));
- }
-
- return 0;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c
deleted file mode 100644
index 5e05535aadc..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_storage_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Memory management layer
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_storage_template.h"
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Extern function prototypes ------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#define STORAGE_LUN_NBR 1
-#define STORAGE_BLK_NBR 0x10000
-#define STORAGE_BLK_SIZ 0x200
-
-int8_t STORAGE_Init (uint8_t lun);
-
-int8_t STORAGE_GetCapacity (uint8_t lun,
- uint32_t *block_num,
- uint16_t *block_size);
-
-int8_t STORAGE_IsReady (uint8_t lun);
-
-int8_t STORAGE_IsWriteProtected (uint8_t lun);
-
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_GetMaxLun (void);
-
-/* USB Mass storage Standard Inquiry Data */
-int8_t STORAGE_Inquirydata[] = {//36
-
- /* LUN 0 */
- 0x00,
- 0x80,
- 0x02,
- 0x02,
- (STANDARD_INQUIRY_DATA_LEN - 5),
- 0x00,
- 0x00,
- 0x00,
- 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
- 'P', 'r', 'o', 'd', 'u', 'c', 't', ' ', /* Product : 16 Bytes */
- ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
- '0', '.', '0' ,'1', /* Version : 4 Bytes */
-};
-
-USBD_StorageTypeDef USBD_MSC_Template_fops =
-{
- STORAGE_Init,
- STORAGE_GetCapacity,
- STORAGE_IsReady,
- STORAGE_IsWriteProtected,
- STORAGE_Read,
- STORAGE_Write,
- STORAGE_GetMaxLun,
- STORAGE_Inquirydata,
-
-};
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the microSD card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Init (uint8_t lun)
-{
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size)
-{
- *block_num = STORAGE_BLK_NBR;
- *block_size = STORAGE_BLK_SIZ;
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_IsReady (uint8_t lun)
-{
- return (0);
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_IsWriteProtected (uint8_t lun)
-{
- return 0;
-}
-
-/*******************************************************************************
-* Function Name : Read_Memory
-* Description : Handle the Read operation from the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return 0;
-}
-/*******************************************************************************
-* Function Name : Write_Memory
-* Description : Handle the Write operation to the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return (0);
-}
-/*******************************************************************************
-* Function Name : Write_Memory
-* Description : Handle the Write operation to the STORAGE card.
-* Input : None.
-* Output : None.
-* Return : None.
-*******************************************************************************/
-int8_t STORAGE_GetMaxLun (void)
-{
- return (STORAGE_LUN_NBR - 1);
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h
deleted file mode 100644
index c41aca22db8..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_template_core.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_template_core.c file.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_TEMPLATE_CORE_H
-#define __USB_TEMPLATE_CORE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_TEMPLATE
- * @brief This file is the header file for usbd_template_core.c
- * @{
- */
-
-
-/** @defgroup USBD_TEMPLATE_Exported_Defines
- * @{
- */
-#define TEMPLATE_EPIN_ADDR 0x81
-#define TEMPLATE_EPIN_SIZE 0x10
-
-#define USB_TEMPLATE_CONFIG_DESC_SIZ 64
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-
-extern USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver;
-/**
- * @}
- */
-
-/** @defgroup USB_CORE_Exported_Functions
- * @{
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_TEMPLATE_CORE_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c
deleted file mode 100644
index 4b93914f0ff..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * TEMPLATE Class Description
- * ===================================================================
- *
- *
- *
- *
- *
- *
- * @note In HS mode and when the DMA is used, all variables and data structures
- * dealing with the DMA during the transaction process should be 32-bit aligned.
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_template.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_TEMPLATE
- * @brief usbd core module
- * @{
- */
-
-/** @defgroup USBD_TEMPLATE_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_TEMPLATE_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_TEMPLATE_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-
-
-
-/** @defgroup USBD_TEMPLATE_Private_FunctionPrototypes
- * @{
- */
-
-
-static uint8_t USBD_TEMPLATE_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_TEMPLATE_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_TEMPLATE_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req);
-
-static uint8_t *USBD_TEMPLATE_GetCfgDesc (uint16_t *length);
-
-static uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t USBD_TEMPLATE_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_TEMPLATE_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_TEMPLATE_EP0_RxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_TEMPLATE_EP0_TxReady (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_TEMPLATE_SOF (USBD_HandleTypeDef *pdev);
-
-static uint8_t USBD_TEMPLATE_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-static uint8_t USBD_TEMPLATE_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-/**
- * @}
- */
-
-/** @defgroup USBD_TEMPLATE_Private_Variables
- * @{
- */
-
-USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver =
-{
- USBD_TEMPLATE_Init,
- USBD_TEMPLATE_DeInit,
- USBD_TEMPLATE_Setup,
- USBD_TEMPLATE_EP0_TxReady,
- USBD_TEMPLATE_EP0_RxReady,
- USBD_TEMPLATE_DataIn,
- USBD_TEMPLATE_DataOut,
- USBD_TEMPLATE_SOF,
- USBD_TEMPLATE_IsoINIncomplete,
- USBD_TEMPLATE_IsoOutIncomplete,
- USBD_TEMPLATE_GetCfgDesc,
- USBD_TEMPLATE_GetCfgDesc,
- USBD_TEMPLATE_GetCfgDesc,
- USBD_TEMPLATE_GetDeviceQualifierDesc,
-};
-
-#if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
-#endif
-/* USB TEMPLATE device Configuration Descriptor */
-static uint8_t USBD_TEMPLATE_CfgDesc[USB_TEMPLATE_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_TEMPLATE_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/
- 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
- /* 09 */
-
- /********** Descriptor of TEMPLATE interface 0 Alternate setting 0 **************/
-
-};
-
-#if defined ( __ICCARM__ ) /*!< IAR Compiler */
- #pragma data_alignment=4
-#endif
-/* USB Standard Device Descriptor */
-static uint8_t USBD_TEMPLATE_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/**
- * @}
- */
-
-/** @defgroup USBD_TEMPLATE_Private_Functions
- * @{
- */
-
-/**
- * @brief USBD_TEMPLATE_Init
- * Initialize the TEMPLATE interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_Init (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
- uint8_t ret = 0;
-
-
- return ret;
-}
-
-/**
- * @brief USBD_TEMPLATE_Init
- * DeInitialize the TEMPLATE layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_DeInit (USBD_HandleTypeDef *pdev,
- uint8_t cfgidx)
-{
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_TEMPLATE_Setup
- * Handle the TEMPLATE specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_Setup (USBD_HandleTypeDef *pdev,
- USBD_SetupReqTypedef *req)
-{
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- }
- return USBD_OK;
-}
-
-
-/**
- * @brief USBD_TEMPLATE_GetCfgDesc
- * return configuration descriptor
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_TEMPLATE_GetCfgDesc (uint16_t *length)
-{
- *length = sizeof (USBD_TEMPLATE_CfgDesc);
- return USBD_TEMPLATE_CfgDesc;
-}
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_TEMPLATE_DeviceQualifierDescriptor (uint16_t *length)
-{
- *length = sizeof (USBD_TEMPLATE_DeviceQualifierDesc);
- return USBD_TEMPLATE_DeviceQualifierDesc;
-}
-
-
-/**
- * @brief USBD_TEMPLATE_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_DataIn (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_TEMPLATE_EP0_RxReady
- * handle EP0 Rx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_EP0_RxReady (USBD_HandleTypeDef *pdev)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_TEMPLATE_EP0_TxReady
- * handle EP0 TRx Ready event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_EP0_TxReady (USBD_HandleTypeDef *pdev)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_TEMPLATE_SOF
- * handle SOF event
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_SOF (USBD_HandleTypeDef *pdev)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_TEMPLATE_IsoINIncomplete
- * handle data ISO IN Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_TEMPLATE_IsoOutIncomplete
- * handle data ISO OUT Incomplete event
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
-
- return USBD_OK;
-}
-/**
- * @brief USBD_TEMPLATE_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_TEMPLATE_DataOut (USBD_HandleTypeDef *pdev,
- uint8_t epnum)
-{
-
- return USBD_OK;
-}
-
-/**
-* @brief DeviceQualifierDescriptor
-* return Device Qualifier descriptor
-* @param length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc (uint16_t *length)
-{
- *length = sizeof (USBD_TEMPLATE_DeviceQualifierDesc);
- return USBD_TEMPLATE_DeviceQualifierDesc;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h
deleted file mode 100644
index c0891364e5b..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_conf_template.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_conf_template.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CONF_TEMPLATE_H
-#define __USBD_CONF_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32fxxx.h" /* replace 'stm32xxx' with your HAL driver header filename, ex: stm32f4xx.h */
-#include © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CORE_H
-#define __USBD_CORE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-#include "usbd_def.h"
-#include "usbd_ioreq.h"
-#include "usbd_ctlreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_CORE
- * @brief This file is the Header file for usbd_core.c file
- * @{
- */
-
-
-/** @defgroup USBD_CORE_Exported_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_Variables
- * @{
- */
-#define USBD_SOF USBD_LL_SOF
-/**
- * @}
- */
-
-/** @defgroup USBD_CORE_Exported_FunctionsPrototype
- * @{
- */
-USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
-USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
-
-USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
-USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
-
-USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
-USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);
-USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);
-
-USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
-USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev);
-
-USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
-USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum);
-
-USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
-
-/* USBD Low Level Driver */
-USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t ep_type,
- uint16_t ep_mps);
-
-USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr);
-USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t size);
-
-USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t size);
-
-uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr);
-void USBD_LL_Delay (uint32_t Delay);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_CORE_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
deleted file mode 100644
index bf8825227aa..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_req.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_req.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_REQUEST_H
-#define __USB_REQUEST_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_REQ
- * @brief header file for the usbd_req.c file
- * @{
- */
-
-/** @defgroup USBD_REQ_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Exported_Types
- * @{
- */
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_REQ_Exported_Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_REQ_Exported_Variables
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup USBD_REQ_Exported_FunctionsPrototype
- * @{
- */
-
-USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-
-void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
-
-void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata);
-
-void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_REQUEST_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
deleted file mode 100644
index 8fbe81e4a21..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_def.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief General defines for the usb device library
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_DEF_H
-#define __USBD_DEF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-
-/** @addtogroup STM32_USBD_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USB_DEF
- * @brief general defines for the usb device library file
- * @{
- */
-
-/** @defgroup USB_DEF_Exported_Defines
- * @{
- */
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-
-#define USB_LEN_DEV_QUALIFIER_DESC 0x0A
-#define USB_LEN_DEV_DESC 0x12
-#define USB_LEN_CFG_DESC 0x09
-#define USB_LEN_IF_DESC 0x09
-#define USB_LEN_EP_DESC 0x07
-#define USB_LEN_OTG_DESC 0x03
-#define USB_LEN_LANGID_STR_DESC 0x04
-#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09
-
-#define USBD_IDX_LANGID_STR 0x00
-#define USBD_IDX_MFC_STR 0x01
-#define USBD_IDX_PRODUCT_STR 0x02
-#define USBD_IDX_SERIAL_STR 0x03
-#define USBD_IDX_CONFIG_STR 0x04
-#define USBD_IDX_INTERFACE_STR 0x05
-
-#define USB_REQ_TYPE_STANDARD 0x00
-#define USB_REQ_TYPE_CLASS 0x20
-#define USB_REQ_TYPE_VENDOR 0x40
-#define USB_REQ_TYPE_MASK 0x60
-
-#define USB_REQ_RECIPIENT_DEVICE 0x00
-#define USB_REQ_RECIPIENT_INTERFACE 0x01
-#define USB_REQ_RECIPIENT_ENDPOINT 0x02
-#define USB_REQ_RECIPIENT_MASK 0x03
-
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_SET_DESCRIPTOR 0x07
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-#define USB_REQ_SYNCH_FRAME 0x0C
-
-#define USB_DESC_TYPE_DEVICE 1
-#define USB_DESC_TYPE_CONFIGURATION 2
-#define USB_DESC_TYPE_STRING 3
-#define USB_DESC_TYPE_INTERFACE 4
-#define USB_DESC_TYPE_ENDPOINT 5
-#define USB_DESC_TYPE_DEVICE_QUALIFIER 6
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
-#define USB_DESC_TYPE_BOS 0x0F
-
-#define USB_CONFIG_REMOTE_WAKEUP 2
-#define USB_CONFIG_SELF_POWERED 1
-
-#define USB_FEATURE_EP_HALT 0
-#define USB_FEATURE_REMOTE_WAKEUP 1
-#define USB_FEATURE_TEST_MODE 2
-
-#define USB_DEVICE_CAPABITY_TYPE 0x10
-
-#define USB_HS_MAX_PACKET_SIZE 512
-#define USB_FS_MAX_PACKET_SIZE 64
-#define USB_MAX_EP0_SIZE 64
-
-/* Device Status */
-#define USBD_STATE_DEFAULT 1
-#define USBD_STATE_ADDRESSED 2
-#define USBD_STATE_CONFIGURED 3
-#define USBD_STATE_SUSPENDED 4
-
-
-/* EP0 State */
-#define USBD_EP0_IDLE 0
-#define USBD_EP0_SETUP 1
-#define USBD_EP0_DATA_IN 2
-#define USBD_EP0_DATA_OUT 3
-#define USBD_EP0_STATUS_IN 4
-#define USBD_EP0_STATUS_OUT 5
-#define USBD_EP0_STALL 6
-
-#define USBD_EP_TYPE_CTRL 0
-#define USBD_EP_TYPE_ISOC 1
-#define USBD_EP_TYPE_BULK 2
-#define USBD_EP_TYPE_INTR 3
-
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_DEF_Exported_TypesDefinitions
- * @{
- */
-
-typedef struct usb_setup_req
-{
-
- uint8_t bmRequest;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-}USBD_SetupReqTypedef;
-
-struct _USBD_HandleTypeDef;
-
-typedef struct _Device_cb
-{
- uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);
- uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);
- /* Control Endpoints*/
- uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req);
- uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev );
- uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev );
- /* Class Specific Endpoints*/
- uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);
- uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);
- uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev);
- uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);
- uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);
-
- uint8_t *(*GetHSConfigDescriptor)(uint16_t *length);
- uint8_t *(*GetFSConfigDescriptor)(uint16_t *length);
- uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
- uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length);
-#if (USBD_SUPPORT_USER_STRING == 1)
- uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length);
-#endif
-
-} USBD_ClassTypeDef;
-
-/* Following USB Device Speed */
-typedef enum
-{
- USBD_SPEED_HIGH = 0,
- USBD_SPEED_FULL = 1,
- USBD_SPEED_LOW = 2,
-}USBD_SpeedTypeDef;
-
-/* Following USB Device status */
-typedef enum {
- USBD_OK = 0,
- USBD_BUSY,
- USBD_FAIL,
-}USBD_StatusTypeDef;
-
-/* USB Device descriptors structure */
-typedef struct
-{
- uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
- uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
-#if (USBD_LPM_ENABLED == 1)
- uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);
-#endif
-} USBD_DescriptorsTypeDef;
-
-/* USB Device handle structure */
-typedef struct
-{
- uint32_t status;
- uint32_t total_length;
- uint32_t rem_length;
- uint32_t maxpacket;
-} USBD_EndpointTypeDef;
-
-/* USB Device handle structure */
-typedef struct _USBD_HandleTypeDef
-{
- uint8_t id;
- uint32_t dev_config;
- uint32_t dev_default_config;
- uint32_t dev_config_status;
- USBD_SpeedTypeDef dev_speed;
- USBD_EndpointTypeDef ep_in[15];
- USBD_EndpointTypeDef ep_out[15];
- uint32_t ep0_state;
- uint32_t ep0_data_len;
- uint8_t dev_state;
- uint8_t dev_old_state;
- uint8_t dev_address;
- uint8_t dev_connection_status;
- uint8_t dev_test_mode;
- uint32_t dev_remote_wakeup;
-
- USBD_SetupReqTypedef request;
- USBD_DescriptorsTypeDef *pDesc;
- USBD_ClassTypeDef *pClass;
- void *pClassData;
- void *pUserData;
- void *pData;
-} USBD_HandleTypeDef;
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_DEF_Exported_Macros
- * @{
- */
-#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
- (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
-
-#define LOBYTE(x) ((uint8_t)(x & 0x00FF))
-#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8))
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-
-
-#if defined ( __GNUC__ )
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif /* __weak */
- #ifndef __packed
- #define __packed __attribute__((__packed__))
- #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* In HS mode and when the DMA is used, all variables and data structures dealing
- with the DMA during the transaction process should be 4-bytes aligned */
-
-#if defined (__GNUC__) /* GNU Compiler */
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #define __ALIGN_BEGIN
-#else
- #define __ALIGN_END
- #if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #elif defined (__TASKING__) /* TASKING Compiler */
- #define __ALIGN_BEGIN __align(4)
- #endif /* __CC_ARM */
-#endif /* __GNUC__ */
-
-
-/**
- * @}
- */
-
-/** @defgroup USBD_DEF_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_DEF_Exported_FunctionsPrototype
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_DEF_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
deleted file mode 100644
index b476307c5fc..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ioreq.h
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief Header file for the usbd_ioreq.c file
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_IOREQ_H
-#define __USBD_IOREQ_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-#include "usbd_core.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup USBD_IOREQ
- * @brief header file for the usbd_ioreq.c file
- * @{
- */
-
-/** @defgroup USBD_IOREQ_Exported_Defines
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Exported_Types
- * @{
- */
-
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USBD_IOREQ_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_IOREQ_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
- * @{
- */
-
-USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev,
- uint8_t *buf,
- uint16_t len);
-
-USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev);
-
-USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev);
-
-uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev ,
- uint8_t epnum);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBD_IOREQ_H */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
deleted file mode 100644
index e61553a34d0..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_conf_template.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief USB Device configuration and interface file
- * This template should be copied to the user folder, renamed and customized
- * following user needs.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief Initializes the Low Level portion of the Device driver.
- * @param pdev: Device handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
- * @brief De-Initializes the Low Level portion of the Device driver.
- * @param pdev: Device handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Starts the Low Level portion of the Device driver.
- * @param pdev: Device handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Stops the Low Level portion of the Device driver.
- * @param pdev: Device handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Opens an endpoint of the Low Level Driver.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @param ep_type: Endpoint Type
- * @param ep_mps: Endpoint Max Packet Size
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t ep_type,
- uint16_t ep_mps)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Closes an endpoint of the Low Level Driver.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Flushes an endpoint of the Low Level Driver.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Sets a Stall condition on an endpoint of the Low Level Driver.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Clears a Stall condition on an endpoint of the Low Level Driver.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Returns Stall condition.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval Stall (1: Yes, 0: No)
- */
-uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return 0;
-}
-
-/**
- * @brief Assigns a USB address to the device.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Transmits data over an endpoint.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @param pbuf: Pointer to data to be sent
- * @param size: Data size
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t size)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Prepares an endpoint for reception.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @param pbuf: Pointer to data to be received
- * @param size: Data size
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t size)
-{
- return USBD_OK;
-}
-
-/**
- * @brief Returns the last transferred packet size.
- * @param pdev: Device handle
- * @param ep_addr: Endpoint Number
- * @retval Recived Data Size
- */
-uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
-{
- return 0;
-}
-
-/**
- * @brief Delays routine for the USB Device Library.
- * @param Delay: Delay in ms
- * @retval None
- */
-void USBD_LL_Delay(uint32_t Delay)
-{
-}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
deleted file mode 100644
index 0158829c52c..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_core.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides all the USBD core functions.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-
-/** @addtogroup STM32_USBD_DEVICE_LIBRARY
-* @{
-*/
-
-
-/** @defgroup USBD_CORE
-* @brief usbd core module
-* @{
-*/
-
-/** @defgroup USBD_CORE_Private_TypesDefinitions
-* @{
-*/
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_CORE_Private_Defines
-* @{
-*/
-
-/**
-* @}
-*/
-
-
-/** @defgroup USBD_CORE_Private_Macros
-* @{
-*/
-/**
-* @}
-*/
-
-
-
-
-/** @defgroup USBD_CORE_Private_FunctionPrototypes
-* @{
-*/
-
-/**
-* @}
-*/
-
-/** @defgroup USBD_CORE_Private_Variables
-* @{
-*/
-
-/**
-* @}
-*/
-
-/** @defgroup USBD_CORE_Private_Functions
-* @{
-*/
-
-/**
-* @brief USBD_Init
-* Initializes the device stack and load the class driver
-* @param pdev: device instance
-* @param pdesc: Descriptor structure address
-* @param id: Low level core index
-* @retval None
-*/
-USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id)
-{
- /* Check whether the USB Host handle is valid */
- if(pdev == NULL)
- {
- USBD_ErrLog("Invalid Device handle");
- return USBD_FAIL;
- }
-
- /* Unlink previous class*/
- if(pdev->pClass != NULL)
- {
- pdev->pClass = NULL;
- }
-
- /* Assign USBD Descriptors */
- if(pdesc != NULL)
- {
- pdev->pDesc = pdesc;
- }
-
- /* Set Device initial State */
- pdev->dev_state = USBD_STATE_DEFAULT;
- pdev->id = id;
- /* Initialize low level driver */
- USBD_LL_Init(pdev);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DeInit
-* Re-Initialize th device library
-* @param pdev: device instance
-* @retval status: status
-*/
-USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
-{
- /* Set Default State */
- pdev->dev_state = USBD_STATE_DEFAULT;
-
- /* Free Class Resources */
- pdev->pClass->DeInit(pdev, pdev->dev_config);
-
- /* Stop the low level driver */
- USBD_LL_Stop(pdev);
-
- /* Initialize low level driver */
- USBD_LL_DeInit(pdev);
-
- return USBD_OK;
-}
-
-
-/**
- * @brief USBD_RegisterClass
- * Link class driver to Device Core.
- * @param pDevice : Device Handle
- * @param pclass: Class handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
-{
- USBD_StatusTypeDef status = USBD_OK;
- if(pclass != 0)
- {
- /* link the class to the USB Device handle */
- pdev->pClass = pclass;
- status = USBD_OK;
- }
- else
- {
- USBD_ErrLog("Invalid Class handle");
- status = USBD_FAIL;
- }
-
- return status;
-}
-
-/**
- * @brief USBD_Start
- * Start the USB Device Core.
- * @param pdev: Device Handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev)
-{
-
- /* Start the low level driver */
- USBD_LL_Start(pdev);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_Stop
- * Stop the USB Device Core.
- * @param pdev: Device Handle
- * @retval USBD Status
- */
-USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev)
-{
- /* Free Class Resources */
- pdev->pClass->DeInit(pdev, pdev->dev_config);
-
- /* Stop the low level driver */
- USBD_LL_Stop(pdev);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_RunTestMode
-* Launch test mode process
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-
-/**
-* @brief USBD_SetClassConfig
-* Configure device and start the interface
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status
-*/
-
-USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
-{
- USBD_StatusTypeDef ret = USBD_FAIL;
-
- if(pdev->pClass != NULL)
- {
- /* Set configuration and Start the Class*/
- if(pdev->pClass->Init(pdev, cfgidx) == 0)
- {
- ret = USBD_OK;
- }
- }
- return ret;
-}
-
-/**
-* @brief USBD_ClrClassConfig
-* Clear current configuration
-* @param pdev: device instance
-* @param cfgidx: configuration index
-* @retval status: USBD_StatusTypeDef
-*/
-USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
-{
- /* Clear configuration and De-initialize the Class process*/
- pdev->pClass->DeInit(pdev, cfgidx);
- return USBD_OK;
-}
-
-
-/**
-* @brief USBD_SetupStage
-* Handle the setup stage
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
-{
-
- USBD_ParseSetupRequest(&pdev->request, psetup);
-
- pdev->ep0_state = USBD_EP0_SETUP;
- pdev->ep0_data_len = pdev->request.wLength;
-
- switch (pdev->request.bmRequest & 0x1F)
- {
- case USB_REQ_RECIPIENT_DEVICE:
- USBD_StdDevReq (pdev, &pdev->request);
- break;
-
- case USB_REQ_RECIPIENT_INTERFACE:
- USBD_StdItfReq(pdev, &pdev->request);
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- USBD_StdEPReq(pdev, &pdev->request);
- break;
-
- default:
- USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80);
- break;
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DataOutStage
-* Handle data OUT stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata)
-{
- USBD_EndpointTypeDef *pep;
-
- if(epnum == 0)
- {
- pep = &pdev->ep_out[0];
-
- if ( pdev->ep0_state == USBD_EP0_DATA_OUT)
- {
- if(pep->rem_length > pep->maxpacket)
- {
- pep->rem_length -= pep->maxpacket;
-
- USBD_CtlContinueRx (pdev,
- pdata,
- MIN(pep->rem_length ,pep->maxpacket));
- }
- else
- {
- if((pdev->pClass->EP0_RxReady != NULL)&&
- (pdev->dev_state == USBD_STATE_CONFIGURED))
- {
- pdev->pClass->EP0_RxReady(pdev);
- }
- USBD_CtlSendStatus(pdev);
- }
- }
- }
- else if((pdev->pClass->DataOut != NULL)&&
- (pdev->dev_state == USBD_STATE_CONFIGURED))
- {
- pdev->pClass->DataOut(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DataInStage
-* Handle data in stage
-* @param pdev: device instance
-* @param epnum: endpoint index
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata)
-{
- USBD_EndpointTypeDef *pep;
-
- if(epnum == 0)
- {
- pep = &pdev->ep_in[0];
-
- if ( pdev->ep0_state == USBD_EP0_DATA_IN)
- {
- if(pep->rem_length > pep->maxpacket)
- {
- pep->rem_length -= pep->maxpacket;
-
- USBD_CtlContinueSendData (pdev,
- pdata,
- pep->rem_length);
-
- /* Prepare endpoint for premature end of transfer */
- USBD_LL_PrepareReceive (pdev,
- 0,
- NULL,
- 0);
- }
- else
- { /* last packet is MPS multiple, so send ZLP packet */
- if((pep->total_length % pep->maxpacket == 0) &&
- (pep->total_length >= pep->maxpacket) &&
- (pep->total_length < pdev->ep0_data_len ))
- {
-
- USBD_CtlContinueSendData(pdev , NULL, 0);
- pdev->ep0_data_len = 0;
-
- /* Prepare endpoint for premature end of transfer */
- USBD_LL_PrepareReceive (pdev,
- 0,
- NULL,
- 0);
- }
- else
- {
- if((pdev->pClass->EP0_TxSent != NULL)&&
- (pdev->dev_state == USBD_STATE_CONFIGURED))
- {
- pdev->pClass->EP0_TxSent(pdev);
- }
- USBD_CtlReceiveStatus(pdev);
- }
- }
- }
- if (pdev->dev_test_mode == 1)
- {
- USBD_RunTestMode(pdev);
- pdev->dev_test_mode = 0;
- }
- }
- else if((pdev->pClass->DataIn != NULL)&&
- (pdev->dev_state == USBD_STATE_CONFIGURED))
- {
- pdev->pClass->DataIn(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_LL_Reset
-* Handle Reset event
-* @param pdev: device instance
-* @retval status
-*/
-
-USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
-{
- /* Open EP0 OUT */
- USBD_LL_OpenEP(pdev,
- 0x00,
- USBD_EP_TYPE_CTRL,
- USB_MAX_EP0_SIZE);
-
- pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
-
- /* Open EP0 IN */
- USBD_LL_OpenEP(pdev,
- 0x80,
- USBD_EP_TYPE_CTRL,
- USB_MAX_EP0_SIZE);
-
- pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
- /* Upon Reset call user call back */
- pdev->dev_state = USBD_STATE_DEFAULT;
-
- if (pdev->pClassData)
- pdev->pClass->DeInit(pdev, pdev->dev_config);
-
-
- return USBD_OK;
-}
-
-
-
-
-/**
-* @brief USBD_LL_Reset
-* Handle Reset event
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed)
-{
- pdev->dev_speed = speed;
- return USBD_OK;
-}
-
-/**
-* @brief USBD_Suspend
-* Handle Suspend event
-* @param pdev: device instance
-* @retval status
-*/
-
-USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
-{
- pdev->dev_old_state = pdev->dev_state;
- pdev->dev_state = USBD_STATE_SUSPENDED;
- return USBD_OK;
-}
-
-/**
-* @brief USBD_Resume
-* Handle Resume event
-* @param pdev: device instance
-* @retval status
-*/
-
-USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
-{
- pdev->dev_state = pdev->dev_old_state;
- return USBD_OK;
-}
-
-/**
-* @brief USBD_SOF
-* Handle SOF event
-* @param pdev: device instance
-* @retval status
-*/
-
-USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
-{
- if(pdev->dev_state == USBD_STATE_CONFIGURED)
- {
- if(pdev->pClass->SOF != NULL)
- {
- pdev->pClass->SOF(pdev);
- }
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_IsoINIncomplete
-* Handle iso in incomplete event
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
- return USBD_OK;
-}
-
-/**
-* @brief USBD_IsoOUTIncomplete
-* Handle iso out incomplete event
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum)
-{
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DevConnected
-* Handle device connection event
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
-{
- return USBD_OK;
-}
-
-/**
-* @brief USBD_DevDisconnected
-* Handle device disconnection event
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
-{
- /* Free Class Resources */
- pdev->dev_state = USBD_STATE_DEFAULT;
- pdev->pClass->DeInit(pdev, pdev->dev_config);
-
- return USBD_OK;
-}
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-
-/**
-* @}
-*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
deleted file mode 100644
index 49330c667b8..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+++ /dev/null
@@ -1,782 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_req.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the standard USB requests following chapter 9.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ctlreq.h"
-#include "usbd_ioreq.h"
-
-
-/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_REQ
- * @brief USB standard requests module
- * @{
- */
-
-/** @defgroup USBD_REQ_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Variables
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_FunctionPrototypes
- * @{
- */
-static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_SetAddress(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_SetConfig(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_GetConfig(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_GetStatus(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_SetFeature(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static void USBD_ClrFeature(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req);
-
-static uint8_t USBD_GetLen(uint8_t *buf);
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_REQ_Private_Functions
- * @{
- */
-
-
-/**
-* @brief USBD_StdDevReq
-* Handle standard usb device requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req)
-{
- USBD_StatusTypeDef ret = USBD_OK;
-
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
-
- USBD_GetDescriptor (pdev, req) ;
- break;
-
- case USB_REQ_SET_ADDRESS:
- USBD_SetAddress(pdev, req);
- break;
-
- case USB_REQ_SET_CONFIGURATION:
- USBD_SetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_CONFIGURATION:
- USBD_GetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_STATUS:
- USBD_GetStatus (pdev , req);
- break;
-
-
- case USB_REQ_SET_FEATURE:
- USBD_SetFeature (pdev , req);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
- USBD_ClrFeature (pdev , req);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
-
- return ret;
-}
-
-/**
-* @brief USBD_StdItfReq
-* Handle standard usb interface requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req)
-{
- USBD_StatusTypeDef ret = USBD_OK;
-
- switch (pdev->dev_state)
- {
- case USBD_STATE_CONFIGURED:
-
- if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
- {
- pdev->pClass->Setup (pdev, req);
-
- if((req->wLength == 0)&& (ret == USBD_OK))
- {
- USBD_CtlSendStatus(pdev);
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- return USBD_OK;
-}
-
-/**
-* @brief USBD_StdEPReq
-* Handle standard usb endpoint requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req)
-{
-
- uint8_t ep_addr;
- USBD_StatusTypeDef ret = USBD_OK;
- USBD_EndpointTypeDef *pep;
- ep_addr = LOBYTE(req->wIndex);
-
- /* Check if it is a class request */
- if ((req->bmRequest & 0x60) == 0x20)
- {
- pdev->pClass->Setup (pdev, req);
-
- return USBD_OK;
- }
-
- switch (req->bRequest)
- {
-
- case USB_REQ_SET_FEATURE :
-
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- USBD_LL_StallEP(pdev , ep_addr);
- }
- break;
-
- case USBD_STATE_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- USBD_LL_StallEP(pdev , ep_addr);
-
- }
- }
- pdev->pClass->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
-
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_CLEAR_FEATURE :
-
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- USBD_LL_StallEP(pdev , ep_addr);
- }
- break;
-
- case USBD_STATE_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr & 0x7F) != 0x00)
- {
- USBD_LL_ClearStallEP(pdev , ep_addr);
- pdev->pClass->Setup (pdev, req);
- }
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_GET_STATUS:
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- if ((ep_addr & 0x7F) != 0x00)
- {
- USBD_LL_StallEP(pdev , ep_addr);
- }
- break;
-
- case USBD_STATE_CONFIGURED:
- pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\
- &pdev->ep_out[ep_addr & 0x7F];
- if(USBD_LL_IsStallEP(pdev, ep_addr))
- {
- pep->status = 0x0001;
- }
- else
- {
- pep->status = 0x0000;
- }
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&pep->status,
- 2);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- default:
- break;
- }
- return ret;
-}
-/**
-* @brief USBD_GetDescriptor
-* Handle Get Descriptor requests
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
- uint16_t len;
- uint8_t *pbuf;
-
-
- switch (req->wValue >> 8)
- {
-#if (USBD_LPM_ENABLED == 1)
- case USB_DESC_TYPE_BOS:
- pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
- break;
-#endif
- case USB_DESC_TYPE_DEVICE:
- pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
- break;
-
- case USB_DESC_TYPE_CONFIGURATION:
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);
- pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
- }
- else
- {
- pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);
- pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
- }
- break;
-
- case USB_DESC_TYPE_STRING:
- switch ((uint8_t)(req->wValue))
- {
- case USBD_IDX_LANGID_STR:
- pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
- break;
-
- case USBD_IDX_MFC_STR:
- pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
- break;
-
- case USBD_IDX_PRODUCT_STR:
- pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
- break;
-
- case USBD_IDX_SERIAL_STR:
- pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
- break;
-
- case USBD_IDX_CONFIG_STR:
- pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
- break;
-
- case USBD_IDX_INTERFACE_STR:
- pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
- break;
-
- default:
-#if (USBD_SUPPORT_USER_STRING == 1)
- pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len);
- break;
-#else
- USBD_CtlError(pdev , req);
- return;
-#endif
- }
- break;
- case USB_DESC_TYPE_DEVICE_QUALIFIER:
-
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);
- break;
- }
- else
- {
- USBD_CtlError(pdev , req);
- return;
- }
-
- case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
- if(pdev->dev_speed == USBD_SPEED_HIGH )
- {
- pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
- pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
- break;
- }
- else
- {
- USBD_CtlError(pdev , req);
- return;
- }
-
- default:
- USBD_CtlError(pdev , req);
- return;
- }
-
- if((len != 0)&& (req->wLength != 0))
- {
-
- len = MIN(len , req->wLength);
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- }
-
-}
-
-/**
-* @brief USBD_SetAddress
-* Set device address
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetAddress(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
- uint8_t dev_addr;
-
- if ((req->wIndex == 0) && (req->wLength == 0))
- {
- dev_addr = (uint8_t)(req->wValue) & 0x7F;
-
- if (pdev->dev_state == USBD_STATE_CONFIGURED)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- pdev->dev_address = dev_addr;
- USBD_LL_SetUSBAddress(pdev, dev_addr);
- USBD_CtlSendStatus(pdev);
-
- if (dev_addr != 0)
- {
- pdev->dev_state = USBD_STATE_ADDRESSED;
- }
- else
- {
- pdev->dev_state = USBD_STATE_DEFAULT;
- }
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
-}
-
-/**
-* @brief USBD_SetConfig
-* Handle Set device configuration request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetConfig(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
-
- static uint8_t cfgidx;
-
- cfgidx = (uint8_t)(req->wValue);
-
- if (cfgidx > USBD_MAX_NUM_CONFIGURATION )
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- if (cfgidx)
- {
- pdev->dev_config = cfgidx;
- pdev->dev_state = USBD_STATE_CONFIGURED;
- if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)
- {
- USBD_CtlError(pdev , req);
- return;
- }
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- case USBD_STATE_CONFIGURED:
- if (cfgidx == 0)
- {
- pdev->dev_state = USBD_STATE_ADDRESSED;
- pdev->dev_config = cfgidx;
- USBD_ClrClassConfig(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
-
- }
- else if (cfgidx != pdev->dev_config)
- {
- /* Clear old configuration */
- USBD_ClrClassConfig(pdev , pdev->dev_config);
-
- /* set new configuration */
- pdev->dev_config = cfgidx;
- if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)
- {
- USBD_CtlError(pdev , req);
- return;
- }
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
-* @brief USBD_GetConfig
-* Handle Get device configuration request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetConfig(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
-
- if (req->wLength != 1)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev_state )
- {
- case USBD_STATE_ADDRESSED:
- pdev->dev_default_config = 0;
- USBD_CtlSendData (pdev,
- (uint8_t *)&pdev->dev_default_config,
- 1);
- break;
-
- case USBD_STATE_CONFIGURED:
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&pdev->dev_config,
- 1);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
-* @brief USBD_GetStatus
-* Handle Get Status request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_GetStatus(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
-
-
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- case USBD_STATE_CONFIGURED:
-
-#if ( USBD_SELF_POWERED == 1)
- pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
-#else
- pdev->dev_config_status = 0;
-#endif
-
- if (pdev->dev_remote_wakeup)
- {
- pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
- }
-
- USBD_CtlSendData (pdev,
- (uint8_t *)& pdev->dev_config_status,
- 2);
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-
-/**
-* @brief USBD_SetFeature
-* Handle Set device feature request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_SetFeature(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
-
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev_remote_wakeup = 1;
- pdev->pClass->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
-
-}
-
-
-/**
-* @brief USBD_ClrFeature
-* Handle clear device feature request
-* @param pdev: device instance
-* @param req: usb request
-* @retval status
-*/
-static void USBD_ClrFeature(USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
- switch (pdev->dev_state)
- {
- case USBD_STATE_ADDRESSED:
- case USBD_STATE_CONFIGURED:
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev_remote_wakeup = 0;
- pdev->pClass->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-/**
-* @brief USBD_ParseSetupRequest
-* Copy buffer into setup structure
-* @param pdev: device instance
-* @param req: usb request
-* @retval None
-*/
-
-void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
-{
- req->bmRequest = *(uint8_t *) (pdata);
- req->bRequest = *(uint8_t *) (pdata + 1);
- req->wValue = SWAPBYTE (pdata + 2);
- req->wIndex = SWAPBYTE (pdata + 4);
- req->wLength = SWAPBYTE (pdata + 6);
-
-}
-
-/**
-* @brief USBD_CtlError
-* Handle USB low level Error
-* @param pdev: device instance
-* @param req: usb request
-* @retval None
-*/
-
-void USBD_CtlError( USBD_HandleTypeDef *pdev ,
- USBD_SetupReqTypedef *req)
-{
- USBD_LL_StallEP(pdev , 0x80);
- USBD_LL_StallEP(pdev , 0);
-}
-
-
-/**
- * @brief USBD_GetString
- * Convert Ascii string into unicode one
- * @param desc : descriptor buffer
- * @param unicode : Formatted string buffer (unicode)
- * @param len : descriptor length
- * @retval None
- */
-void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
-{
- uint8_t idx = 0;
-
- if (desc != NULL)
- {
- *len = USBD_GetLen(desc) * 2 + 2;
- unicode[idx++] = *len;
- unicode[idx++] = USB_DESC_TYPE_STRING;
-
- while (*desc != '\0')
- {
- unicode[idx++] = *desc++;
- unicode[idx++] = 0x00;
- }
- }
-}
-
-/**
- * @brief USBD_GetLen
- * return the string length
- * @param buf : pointer to the ascii string buffer
- * @retval string length
- */
-static uint8_t USBD_GetLen(uint8_t *buf)
-{
- uint8_t len = 0;
-
- while (*buf != '\0')
- {
- len++;
- buf++;
- }
-
- return len;
-}
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
deleted file mode 100644
index 093afad8644..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ioreq.c
- * @author MCD Application Team
- * @version V2.4.2
- * @date 11-December-2015
- * @brief This file provides the IO requests APIs for control endpoints.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2015 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup USBD_IOREQ
- * @brief control I/O requests module
- * @{
- */
-
-/** @defgroup USBD_IOREQ_Private_TypesDefinitions
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Macros
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
- * @{
- */
-/**
- * @}
- */
-
-
-/** @defgroup USBD_IOREQ_Private_Functions
- * @{
- */
-
-/**
-* @brief USBD_CtlSendData
-* send data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be sent
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- /* Set EP0 State */
- pdev->ep0_state = USBD_EP0_DATA_IN;
- pdev->ep_in[0].total_length = len;
- pdev->ep_in[0].rem_length = len;
- /* Start the transfer */
- USBD_LL_Transmit (pdev, 0x00, pbuf, len);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_CtlContinueSendData
-* continue sending data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be sent
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- /* Start the next transfer */
- USBD_LL_Transmit (pdev, 0x00, pbuf, len);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_CtlPrepareRx
-* receive data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be received
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- /* Set EP0 State */
- pdev->ep0_state = USBD_EP0_DATA_OUT;
- pdev->ep_out[0].total_length = len;
- pdev->ep_out[0].rem_length = len;
- /* Start the transfer */
- USBD_LL_PrepareReceive (pdev,
- 0,
- pbuf,
- len);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_CtlContinueRx
-* continue receive data on the ctl pipe
-* @param pdev: device instance
-* @param buff: pointer to data buffer
-* @param len: length of data to be received
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
-
- USBD_LL_PrepareReceive (pdev,
- 0,
- pbuf,
- len);
- return USBD_OK;
-}
-/**
-* @brief USBD_CtlSendStatus
-* send zero lzngth packet on the ctl pipe
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev)
-{
-
- /* Set EP0 State */
- pdev->ep0_state = USBD_EP0_STATUS_IN;
-
- /* Start the transfer */
- USBD_LL_Transmit (pdev, 0x00, NULL, 0);
-
- return USBD_OK;
-}
-
-/**
-* @brief USBD_CtlReceiveStatus
-* receive zero lzngth packet on the ctl pipe
-* @param pdev: device instance
-* @retval status
-*/
-USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev)
-{
- /* Set EP0 State */
- pdev->ep0_state = USBD_EP0_STATUS_OUT;
-
- /* Start the transfer */
- USBD_LL_PrepareReceive ( pdev,
- 0,
- NULL,
- 0);
-
- return USBD_OK;
-}
-
-
-/**
-* @brief USBD_GetRxCount
-* returns the received data length
-* @param pdev: device instance
-* @param ep_addr: endpoint address
-* @retval Rx Data blength
-*/
-uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr)
-{
- return USBD_LL_GetRxDataSize(pdev, ep_addr);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html b/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html
deleted file mode 100644
index a23d96df928..00000000000
--- a/lib/main/STM32F3/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html
+++ /dev/null
@@ -1,1267 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/src/main/config/config_streamer_stm32f3.c b/src/main/config/config_streamer_stm32f3.c
deleted file mode 100644
index f56f86e7a99..00000000000
--- a/src/main/config/config_streamer_stm32f3.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of Cleanflight.
- *
- * Cleanflight is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * Cleanflight is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with Cleanflight. If not, see
-
-
-
-
-
-
-
-
-
|
-
