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ARM-Mali-Midgard.md

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Midgard is a 2nd generation of Mali GPU architecture.

Content:

Midgard Gen1

Examples

  • Mali-T604
  • Mali-T658

Notes

  • Hierarchical Tiling system. [2]

Midgard Gen2

Examples

  • Mali-T622
  • Mali-T624
  • Mali-T628
  • Mali-T678

Notes

  • Forward Pixel Kill

Midgard Gen3

Examples

  • Mali-T720

  • Mali-T760

  • Rockchip RK3288 (Mali-T760 MP4)

References

3.1. Vulkan features for Mali-T760

Notes

  • core config: [5]
    • 1 fragment per cycle
    • 1 pixel per cycle
    • T720: 1 ALU, 32 fp16/cy, 20 fp32/cy
    • T760: 2 ALU, 52 fp16/cy, 28 fp32/cy
    • Max work registers (128b): 9-16 per 64 threads, 5-8 per 128 threads, 0-4 per 256 threads

Midgard Gen4

Examples

  • Mali-T820

  • Mali-T830

  • Mali-T860

  • Mali-T880

  • Rockchip RK3399 (Mali-T860)

References

4.1. ARM Announces Mali 800 Series GPUs
4.2. Arm Mali-T820 and Arm Mali-T830 Performance Counters Reference Guide, [backup]
4.3. Arm Mali-T860 and Arm Mali-T880 Performance Counters Reference Guide
4.4. Vulkan features for Mali-T880
4.5. Mali-T880 is set to Deliver the Premium Mobile Experience of 2016
4.6. Mali-T830 Benchmarks

Notes

  • core config: [5]

    • 1 fragment per cycle
    • 1 pixel per cycle
    • T820: 1 ALU, 28 fp16/cy, 16 fp32/cy
    • T830: 2 ALU, 56 fp16/cy, 32 fp32/cy
    • T860: 2 ALU, 52 fp16/cy, 28 fp32/cy
    • T880: 3 ALU, 78 fp16/cy, 42 fp32/cy
    • Max work registers (128b): 9-16 per 64 threads, 5-8 per 128 threads, 0-4 per 256 threads
    • T880: 5-8 registers per 192 threads, 9-16 registers per 96 threads.

  • T830: no AFBC [4.6]

Midgard (all gens)

References

  1. Midgard Architecture, [backup]
  2. ARM’s Mali Midgard Architecture Explored
  3. The Midgard Shader Core, [backup]
  4. Mesa driver details
  5. Arm GPU Datasheet, [backup]

Notes

  • Unified shader model

  • SIMD ISA (vector)

  • 128 bit work registers (fp32 x4)

  • Mali Midgard GPU shader cores allow variable numbers of threads to be created, depending on the number of work registers that are used by the in-flight shader programs.
    0-4 registers - Maximum thread capacity 5-8 registers - Half thread capacity 8-16 registers - Quarter thread capacity

  • Tri-Pipe ALU: ADD, MUL, SFU. [2]

  • Mix of scalar and vector ALUs: 3 vector ALUs + 2 scalar ALUs, each responsible for a specific type of operation. [2]

  • Midgard (Gen3) does not extract thread level parallelism. [2]