Release v1.4.15b

Updated Vivado version allow list to include AR73068 with older versions

v1.4.20

Release v1.4.20

• Bug Fix release to fix XDMA to fix Issue #516
• Miscellaneous documentation updates

Release v1.4.19

Bug Fix Release

We have identified a bug in the flop_ccf.sv module that can potentially impact timing closure of designs.
The module is instantiated in sh_ddr.sv and inadvertently introduces a timing path on the reset logic.
Although there is no functional impact, it may increase Vivado tool’s effort in timing closure of design.
There should be no functional impact from this bug if your design has already met timing.

Please check ERRATA for more info.

Release v1.4.18

FPGA developer kit now supports Xilinx Vitis/Vivado 2020.2

We recommend developers upgrade to 2020.2 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.10.0 and simply update to the latest FPGA developer kit v1.4.18.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2020.2

Release v1.4.17

Updates

• Updated XDMA Driver to allow builds on newer kernels
• Updated documentation on Alveo U200 to F1 platform porting
• Added Vitis 2019.2 Patching for AR#73068

Release v1.4.16

FPGA developer kit now supports Xilinx Vitis/Vivado 2020.1.

We recommend developers upgrade to 2020.1 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.9.0 and simply update to the latest FPGA developer kit v1.4.16.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2020.1
• Updated Vitis examples to include usage of Vitis Libraries.
• Added documentation and examples to show Xilinx Alveo design migration to F1.
• Re-structured README

Xilinx toolset version support removal

In this release, we have removed support for older Xilinx tool versions: 2017.4, 2018.2, 2018.3. While v1.4.16+ will not support older Xilinx tools, you can still use them using HDK releases v1.4.15a or earlier.

Release v1.4.15a

Bug Fix Release

This fix upgrades DDR IP and regenerates IP outputs to fix the issue described in Xilinx AR#73068

Changes:

• Add upgrade ip changes to the init.tcl file

• Updated the cl_dram_dma public AFI

Release v1.4.15

• AR73068 patching (#608)

  • Added patching mechanism for Vivado AR73068
  • Updated supported versions

• Updated the shell interface spec to reflect current shell (#603)

  • Updated the shell interface spec to reflect current shell and pointed to the DDR Data Retention doc
  • Update hdk/docs/AWS_Shell_Interface_Specification.md

• Enhance DDR Model Build qualifiers in hdk_setup.sh script. (#604)

  • Enhance DDR Model Build qualifiers in hdk_setup.sh script.
  • Enhance the DDR model build's lock file creation+check to not rely on external tools.

• Update Virtual_JTAG_XVC.md (#606)

• Added dma range error to interrupt status register metrics (#591)

  • added dma range error to interrupt status register metrics
  • updated tests to match change to output

• Fixing test_fpga_tools to accomodate dma range error addition. (#609)

  • Fixed the lines where we expect clock group c

Release v1.4.14

Release 1.4.14 (See ERRATA for unsupported features)

• Added a new platform file to fix DDR bandwidth issue
• Add Vitis Debug document

Release v1.4.13

Release 1.4.13 (See ERRATA for unsupported features)

• FPGA developer kit now supports Xilinx Vivado/Vitis 2019.2
• To upgrade, use Developer AMI v1.8.0 on the AWS Marketplace.