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Release v1.4.22 (#540)
* Updated README.md and FAQ.md: (#702) * Added descriptions on kernel clocks and frequency scaling. * Virtual Ethernet upgrade (#694) * Update dpdk to v20.02 for virtual eth instance and dpdk to v20.08 and pktgen to v20.09 for pktgen instance * update to include a dpdk patch for generating igb * update the script to also generate igb_uio.ko for x86_64-native-linuxapp-gcc * updated dpdk patches for 20.02 * updates to spp_ethdev.c * remove spp_ethdev.c as its updated in 0001 patch * update the patch to enable igb_uio compilation * updates to virtual_ethernet_install.py for upgrade to 20.02 * Update Virtual_Ethernet_Application_Guide.md * Updated the end of life announcement table (#703) Co-authored-by: czfpga <[email protected]> Co-authored-by: kyyalama2 <[email protected]>
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‎README.md

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z1d.xlarge/c5.4xlarge and z1d.2xlarge/c5.8xlarge instance types would provide the fastest execution time with 30GiB+ and 60GiB+ of memory respectively.
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Developers who want to save on cost, could start coding and run simulations on low-cost instances, like t2.2xlarge, and move to the aforementioned larger instances to run the synthesis of their acceleration code.
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AWS marketplace offers multiple versions of the FPGA Developer AMI. The following compatibility table describes the mapping of currently supported developer kit versions to AMI versions:
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AWS marketplace offers multiple versions of the FPGA Developer AMI. The following section table describes the mapping of currently supported developer kit versions to AMI versions.
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## Xilinx tool support
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| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
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|-----------|-----------|------|
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| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |
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| 1.4.8 - 1.4.15b | 2018.3 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3) |
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| 1.4.3 - 1.4.15b | 2018.2 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2) |
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| 1.3.7 - 1.4.15b | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) |
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|⚠️ 1.3.7 - 1.4.15b | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️|
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⚠️ Developer kit release v1.4.16 will remove support for Xilinx 2017.4, 2018.2, 2018.3 toolsets.
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While developer kit release v1.4.16 onwards will not support older Xilinx tools, you can still use them using HDK releases v1.4.15b or earlier.
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Please checkout [the latest v1.4.15b release tag from Github](https://github.com/aws/aws-fpga/releases/tag/v1.4.15b) to use Xilinx 2017.4, 2018.2, 2018.3 toolsets.
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⚠️ Developer kit release v1.4.16 will remove support for Xilinx 2017.4, 2018.2, 2018.3 toolsets. While developer kit release v1.4.16 onwards will not support older Xilinx tools, you can still use them using HDK releases v1.4.15b or earlier.
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Please check out [the latest v1.4.15b release tag from Github](https://github.com/aws/aws-fpga/releases/tag/v1.4.15b) to use Xilinx 2017.4, 2018.2, 2018.3 toolsets.
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⚠️ Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) reached end-of-life. See [AWS forum announcement](https://forums.aws.amazon.com/ann.jspa?annID=6068) for additional details.
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For deprecation notices, please check the [End of life announces](./README.md#end-of-life-announcements)
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For software-defined development please look at the runtime compatibility table based on the Xilinx toolset in use:
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[SDAccel](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatibility-table) or [Vitis](Vitis/docs/Create_Runtime_AMI.md#runtime-ami-compatibility-table)
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### End of life Announcements
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| Xilinx Tool version | State | Statement |
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|-----------|-----------|------|
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| 2017.1 | 🚫 Deprecated on 09/01/2018 | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) [reached end-of-life](https://forums.aws.amazon.com/ann.jspa?annID=6068). |
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| 2017.4 | ⚠️ Upcoming deprecation on 12/31/2021 | Support for Xilinx 2017.4 toolsets will be deprecated on 12/31/2021. Please check our [forum announcement for more details](https://forums.aws.amazon.com/ann.jspa?annID=8949). |
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## Hardware Development Kit (HDK)
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The [HDK directory](./hdk/README.md) contains documentation, examples, simulation, build and AFI creation scripts to start building Amazon FPGA Images (AFI).

‎RELEASE_NOTES.md

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**NOTE:** See [ERRATA](./ERRATA.md) for unsupported features
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## Release 1.4.22
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* FPGA developer kit update to upgrade Virtual Ethernet to support jumbo frames using newer versions of dpdk/pktgen
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## Release 1.4.21
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* FPGA developer kit now supports Xilinx Vivado/Vitis 2021.1
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‎Vitis/README.md

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# Quick Start Guide to Accelerating your C/C++ application on an AWS F1 FPGA Instance with Vitis
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There are three steps for accelerating your application on an Amazon EC2 FPGA instance using the software-defined development flow:
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1. Build the host application, and the Xilinx FPGA binary
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1. Build the host application, and the Xilinx FPGA binary
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2. Create an AFI
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3. Run the FPGA accelerated application on AWS FPGA instances
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This quick start guide will utilize a simple "Hello World" Vitis example to get you started.
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It is highly recommended you read the documentation and utilize software and hardware emulation prior to running on F1.
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It is highly recommended you read the documentation and utilize software and hardware emulation prior to running on F1.
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The F1 HW Target compile time is ~50 minutes, therefore, software and hardware emulation should be used during development.
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# Table of Content
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1. [Overview](#overview)
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1. [Overview](#overview)
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2. [Prerequisites](#prerequisites)
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* [AWS Account, F1/EC2 Instances, On-Premises, AWS IAM Permissions, AWS CLI and S3 Setup](#iss)
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* [Github and Environment Setup](#gitsetenv)
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## AWS Account, F1/EC2 Instances, On-Premises, AWS IAM Permissions, AWS CLI and S3 Setup (One-time Setup)
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* [Setup an AWS Account](https://aws.amazon.com/free/)
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* Launch an instance using the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) which comes pre-installed with Vitis and required licenses.
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* You may use this F1 instance to [build your host application and Xilinx FPGA binary](#createapp), however, it is more cost efficient to either:
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* Launch the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) on a compute EC2 instance, with a minimum of 30GiB RAM), **OR**
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* You may use this F1 instance to [build your host application and Xilinx FPGA binary](#createapp), however, it is more cost efficient to either:
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* Launch the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) on a compute EC2 instance, with a minimum of 30GiB RAM), **OR**
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* Follow the [On-Premises Instructions](../docs/on_premise_licensing_help.md) to purchase and install a license from Xilinx.
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* Setup AWS IAM permissions for creating FPGA Images (CreateFpgaImage and DescribeFpgaImages). [EC2 API Permissions are described in more detail](http://docs.aws.amazon.com/AWSEC2/latest/APIReference/ec2-api-permissions.html). It is highly recommended that you validate your AWS IAM permissions prior to proceeding with this quick start. By calling the [DescribeFpgaImages API](../hdk/docs/describe_fpga_images.md) you can check that your IAM permissions are correct.
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* [Setup AWS CLI and S3 Bucket](docs/Setup_AWS_CLI_and_S3_Bucket.md) to enable AFI creation.
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* Install optional [packages](packages.txt) required to run all examples. If you do not install these packages, some examples may not work properly. The setup scripts will warn you of any missing packages.
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* Additional dependencies may get flagged during the AWS Vitis scripts as warnings or errors.
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<a name="gitsetenv"></a>
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## Github and Environment Setup
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* Clone this github repository and source the *vitis_setup.sh* script:
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## Github and Environment Setup
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* Clone this github repository and source the *vitis_setup.sh* script:
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```
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$ git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR
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$ cd $AWS_FPGA_REPO_DIR
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$ git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR
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$ cd $AWS_FPGA_REPO_DIR
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$ source vitis_setup.sh
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```
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<a name="emu"></a>
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# Emulate your Code
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The main goal of emulation is to ensure functional correctness and to determine how to partition the application between the host CPU and the FPGA.
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The main goal of emulation is to ensure functional correctness and to determine how to partition the application between the host CPU and the FPGA.
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HW/SW Emulation does not require use of actual FPGA's and can be run on any compute instances. Using non-F1 EC2 compute instances for initial development will help reduce costs.
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<a name="swemu"></a>
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## Software (SW) Emulation
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For CPU-based (SW) emulation, both the host code and the FPGA binary code are compiled to run on an x86 processor.
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SW Emulation enables developers to iterate and refine the algorithms through fast compilation.
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The iteration time is similar to software compile and run cycles on a CPU.
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For CPU-based (SW) emulation, both the host code and the FPGA binary code are compiled to run on an x86 processor.
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SW Emulation enables developers to iterate and refine the algorithms through fast compilation.
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The iteration time is similar to software compile and run cycles on a CPU.
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The instructions below describe how to run the Vitis SW Emulation flow using the Makefile provided with a simple "hello world" example
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=sw_emu DEVICE=$AWS_PLATFORM all
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=sw_emu DEVICE=$AWS_PLATFORM all
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```
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For more information on how to debug your application in a SW Emulation environment.
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<a name="hwemu"></a>
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## Hardware (HW) Emulation
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The Vitis hardware emulation flow enables the developer to check the correctness of the logic generated for the FPGA binary. This emulation flow invokes the hardware simulator in the Vitis environment to test the functionality of the code that will be executed on the FPGA Custom Logic.
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The Vitis hardware emulation flow enables the developer to check the correctness of the logic generated for the FPGA binary. This emulation flow invokes the hardware simulator in the Vitis environment to test the functionality of the code that will be executed on the FPGA Custom Logic.
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The instructions below describe how to run the HW Emulation flow using the Makefile provided with a simple "hello world" example:
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The instructions below describe how to run the HW Emulation flow using the Makefile provided with a simple "hello world" example:
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=hw_emu DEVICE=$AWS_PLATFORM all
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=hw_emu DEVICE=$AWS_PLATFORM all
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```
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For more information on how to debug your application in a HW Emulation environment.
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<a name="hw"></a>
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# Build the Host Application and Xilinx FPGA Binary
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The Vitis system build flow enables the developer to build their host application as well as their Xilinx FPGA Binary.
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The Vitis system build flow enables the developer to build their host application as well as their Xilinx FPGA Binary.
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The instructions below describe how to build the Xilinx FPGA Binary and host application using the Makefile provided with a simple "hello world" example:
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The instructions below describe how to build the Xilinx FPGA Binary and host application using the Makefile provided with a simple "hello world" example:
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make TARGET=hw DEVICE=$AWS_PLATFORM all
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make TARGET=hw DEVICE=$AWS_PLATFORM all
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NOTE: If you encounter an error with `No current synthesis run set`, you may have previously run the [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_Setup.md) and created a `Vivado_init.tcl` file in `~/.Xilinx/Vivado`. This will cause [problems](https://forums.aws.amazon.com/thread.jspa?threadID=268202&tstart=25) with the build process, thus it is recommended to remove it before starting a hardware system build.
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<a name="createafi"></a>
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# 2. Create an Amazon FPGA Image (AFI)
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# 2. Create an Amazon FPGA Image (AFI)
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*The Vitis Flow only supports AFI's created with Device ID 0xF010 and Vendor ID 0x1D0F.*
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The runtime drivers are designed to only bind to 0xF010 and 0x1042(Cleared AFI) and loading AFI's from your application that provide other Device/Vendor ID's will require restarting the Xilinx MPD.
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This assumes you have:
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This assumes you have:
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* [Compiled your host application and Xilinx FPGA Binary](#hw)
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* Validated your code using [SW/HW Emulation](#emu) and you are ready to create an AFI and test on F1.
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* [Setup AWS CLI and S3 bucket](docs/Setup_AWS_CLI_and_S3_Bucket.md) for AFI creation
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* [Setup AWS CLI and S3 bucket](docs/Setup_AWS_CLI_and_S3_Bucket.md) for AFI creation
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The [create_vitis_afi.sh](./tools/create_vitis_afi.sh) script is provided to facilitate AFI creation from a Xilinx FPGA Binary, it:
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* Takes in your Xilinx FPGA Binary \*.xclbin file
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* Calls *aws ec2 create_fpga_image* to generate an AFI under the hood
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* Generates a \<timestamp\>_afi_id.txt which contains the identifiers for your AFI
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* Creates an AWS FPGA Binary file with an \*.awsxclbin extension that is composed of: Metadata and AGFI-ID.
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* Creates an AWS FPGA Binary file with an \*.awsxclbin extension that is composed of: Metadata and AGFI-ID.
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* **This \*.awsxclbin is the AWS FPGA Binary file that will need to be loaded by your host application to the FPGA**
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$ $VITIS_DIR/tools/create_vitis_afi.sh -xclbin=<input_xilinx_fpga_binary_xclbin_filename>
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$ $VITIS_DIR/tools/create_vitis_afi.sh -xclbin=<input_xilinx_fpga_binary_xclbin_filename>
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-o=<output_aws_fpga_binary_awsxclbin_filename_root> \
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**NOTE**: *Attempting to load your AFI immediately on an F1 instance will result in an 'Invalid AFI ID' error.
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Please wait until you confirm the AFI has been created successfully.*
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## Tracking the status of your registered AFI
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Refer to [FAQ](./docs/FAQ.md) for details.
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## Tracking the status of your registered AFI
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The \*_afi_id.txt file generated by the create_vitis_afi.sh also includes the two identifiers for your AFI:
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- **FPGA Image Identifier** or **AFI ID**: this is the main ID used to manage your AFI through the AWS EC2 CLI commands and AWS SDK APIs.
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This ID is regional, i.e., if an AFI is copied across multiple regions, it will have a different unique AFI ID in each region.
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An example AFI ID is **`afi-06d0ffc989feeea2a`**.
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- **Global FPGA Image Identifier** or **AGFI ID**: this is a global ID that is used to refer to an AFI from within an F1 instance.
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For example, to load or clear an AFI from an FPGA slot, you use the AGFI ID.
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**This is embedded into the AWS FPGA Binary \*.awsxclbin file generated by create_vitis_afi.sh.**
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Use the [describe-fpga-images](../hdk/docs/describe_fpga_images.md) API to check the AFI state during the background AFI generation process.
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Use the [describe-fpga-images](../hdk/docs/describe_fpga_images.md) API to check the AFI state during the background AFI generation process.
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* Copy any data files required for execution to the new instance
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* [Clone the github repository to the new F1 instance and install runtime drivers](#gitsetenv)
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* To setup tools, runtime environment & execute your Host Application:
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* To setup tools, runtime environment & execute your Host Application:
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$ ./hello_world ./vadd.awsxclbin
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$ ./hello_world ./vadd.awsxclbin
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* The runtime setup script also starts the Xilinx XRT Message Proxy Daemon(MPD) service. To learn more about the XRT implementation, check the [XRT Instructions](./docs/XRT_installation_instructions.md#mpd)
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<a name="read"></a>
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# Additional Vitis Information
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# Additional Vitis Information
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* [Vitis User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1393-vitis-application-acceleration.pdf)
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‎Vitis/docs/FAQ.md

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# Frequently Asked Questions (FAQ)
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## Q: What are the clocks available to the RTL kernel on the AWS F1 Platform?
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A: There are 3 clocks provided on the AWS F1 Platform. Their names and default frequencies are shown below.
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Among them, DATA_CLK and KERNEL_CLK can be used by the RTL kernel.
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* SYSTEM (clock_main_a0) @ 250 MHz
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* DATA_CLK (clock_extra_b0) @ 250 MHz
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* KERNEL_CLK (clock_extra_c0) @ 500 MHz
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**NOTE**: *Frequency scaling can be enabled by Vitis on the kernel clock (DATA_CLK or KERNEL_CLK). This happens when the kernel's timing performance cannot be achieved. Vitis will lower the clock frequency to meet timing. For more details about kernel clock, please refer to [Vitis User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1393-vitis-application-acceleration.pdf).*
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## Q: What is the lowest frequency Vitis design supported on the AWS F1 Platform?
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A: We support creating AFI's from CL's that have been built to work at Frequencies no lower than 80MHz.
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Re-clocking/Loading a dynamic clock frequency lower than 80MHz will also result in an error.

‎hdk/hdk_version.txt

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HDK_VERSION=1.4.21
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HDK_VERSION=1.4.22

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