v1.4.5 updates (#438)

* v1.4.5 updates

* Update README.md

* release notes & documents updates

* Update AWS_Shell_Interface_Specification.md

* Update sh_bfm.sv

* release notes update

Author: AWSaalluri

.gitmodules

@@ -5,3 +5,4 @@
 [submodule "SDAccel/examples/xilinx_2018.2"]
 	path = SDAccel/examples/xilinx_2018.2
 	url = https://github.com/Xilinx/SDAccel_Examples.git
+	branch = master

README.md

@@ -67,7 +67,7 @@ NOTE: For on-premises development, SDx/Vivado must have the correct license and
 | Virtual Ethernet Application | [Example Application](sdk/apps/virtual-ethernet) | [HDK SDE Example](hdk/cl/examples/cl_sde) | The Virtual Ethernet framework facilitates streaming Ethernet frames from a network interface (or any source) into the FPGA for processing and back out to some destination. Possible use cases for this include deep packet inspection, software defined networking, stream encryption or compression, and more. |
 | Pipelined Workload Applications | [cl\_dram\_dma\_data\_retention](hdk/docs/data_retention.md)| [HDK](hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_retention.c) [SDAccel](SDAccel/examples/aws/data_retention) | Demonstrates how to preserve data in DRAMs while swapping out accelerators. Applications that use a temporal accelerator pipeline can take advantage of this feature to reduce latency between FPGA image swaps  |
 | Digital Up-Converter using High Level Synthesis | [cl\_hls\_dds\_hlx](hdk/cl/examples/cl_hls_dds_hlx) | HLx - C-to-RTL  | Demonstrates an example application written in C that is synthesized to RTL (Verilog) |
-| Security   | [AES, RSA, SHA1](https://github.com/Xilinx/SDAccel_Examples/tree/master/security) | SDAccel - C/C++/OpenCL  | Developed using software defined acceleration, this example demonstrates methods of using hardware acceleration to speed up security software algorithms  |
+| Security   | [AES, RSA, SHA1](https://github.com/Xilinx/SDAccel_Examples/tree/2018.2/security) | SDAccel - C/C++/OpenCL  | Developed using software defined acceleration, this example demonstrates methods of using hardware acceleration to speed up security software algorithms  |
 | Computer Vision   | [Affine, Convolve, Huffman, IDCT](https://github.com/Xilinx/SDAccel_Examples/tree/master/vision) | SDAccel - C/C++/OpenCL  | Developed using software defined acceleration, this example demonstrates methods of using hardware acceleration to speed up image detection algorithms  |
 | Misc Algorithms   | [Kmeans, SmithWaterman, MatrixMult](https://github.com/Xilinx/SDAccel_Examples/tree/master/acceleration) | SDAccel - C/C++/OpenCL  | Developed using software defined acceleration, this example demonstrates methods of applying hardware acceleration to a variety of sorting and search algorithms  |
 | Financial   | [Blacksholes, Heston](https://github.com/KitAway/FinancialModels_AmazonF1) | SDAccel - C/C++/OpenCL  | Developed using software defined acceleration, this example demonstrates methods of using hardware acceleration on Monte Carlo financial models  |
@@ -118,6 +118,7 @@ Currently, AWS marketplace includes multiple versions of the FPGA developer AMI,
 
 Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) reached end-of-life.  See [AWS forum announcement](https://forums.aws.amazon.com/ann.jspa?annID=6068) for additional details.
 
+ If developing using SDAccel environment please refer to this [Runtime Compatibility Table](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table)
 
 <a name="fpgahdk"></a>
 # Hardware Development Kit (HDK)

RELEASE_NOTES.md

@@ -26,6 +26,15 @@
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+## Release 1.4.5 (See [ERRATA](./ERRATA.md) for unsupported features) 
+
+* [Documents SDAccel Runtime compatibility](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table)
+* [Enables SDK FPGA Mgmt tool access to Non-root users](sdk/README.md#using-fpga-as-non-root-user)
+* Fixed issues
+  * [HLX simulation failure](https://forums.aws.amazon.com/thread.jspa?threadID=293313&tstart=0)
+  * [Shell BFM  read from C host memory](https://forums.aws.amazon.com/thread.jspa?threadID=288959&tstart=0)
+  * [cl_dram_dma example design DDR read issue](https://forums.aws.amazon.com/thread.jspa?threadID=290277&tstart=50)
+
 ## Release 1.4.4 (See [ERRATA](./ERRATA.md) for unsupported features)        
 * Fixed compile issues in simulation while using 3rd party simulators (synopsys VCS, Cadence IES and Mentor Questasim).
 

SDAccel/README.md

@@ -192,7 +192,7 @@ For help with AFI creation issues, see [create-fpga-image error codes](../hdk/do
 # 3. Run the FPGA accelerated application on Amazon FPGA instances
 
 Here are the steps:
-* Start an FPGA instance using [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) and check the AMI [compatiability table](../README.md#devAmi).  Alternatively, you can [create your own Runtime AMI](docs/Create_Runtime_AMI.md) for running your SDAccel applications on Amazon FPGA instances.
+* Start an FPGA instance using [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) and check the AMI [compatiability table](../README.md#devAmi) and [runtime compatilibility table](docs/Create_Runtime_AMI.md#runtime-ami-compatability-table).  Alternatively, you can [create your own Runtime AMI](docs/Create_Runtime_AMI.md) for running your SDAccel applications on Amazon FPGA instances.
    * *Assuming the developer flow (compilation) was done on a separate instance you will need to:*
      * Copy the compiled host executable (exe) to new instance
      * Copy the \*.awsxclbin AWS FPGA binary file to the new instance

SDAccel/docs/Create_Runtime_AMI.md

@@ -1,5 +1,12 @@
 # Create a Runtime AMI Starting with an Amazon Linux AMI or Ubuntu                          
 
+## Runtime AMI Compatability Table
+
+  | SDx Version used for AFI Development |	Compatible SDAccel Runtime |
+  |--------------------------------------|-----------------------------|
+  | 2017.4 |	Runtime installed by sourcing "sdaccel_setup.sh" while using HDK Ver 1.4.X when environment variable    RELEASE_VER=2017.4 |
+  | 2018.2 |	AWS FPGA Developer AMI 1.5.0 ( XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) |
+
 ## 1. Launch a Runtime Instance & Install Required Packages 
 
 ### Using Amazon Linux

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_axi_mstr.sv

@@ -29,7 +29,7 @@ module cl_dram_dma_axi_mstr (
 );
 
  `include "cl_dram_dma_defines.vh"
- 
+
 // -----------------------------------------------------------------------------
 // Parameters
 // -----------------------------------------------------------------------------
@@ -97,7 +97,7 @@ module cl_dram_dma_axi_mstr (
             cfg_wdata_q <= axi_mstr_cfg_bus.wdata[31:0];
          end
       end
-   
+
    //Readback mux
    always @(posedge aclk)
    begin
@@ -110,7 +110,7 @@ module cl_dram_dma_axi_mstr (
             default:    axi_mstr_cfg_bus.rdata[31:0] <= 32'hffffffff;
          endcase
    end
-   
+
    //Ack for cycle
    always_ff @(posedge aclk)
       if (!aresetn)
@@ -238,7 +238,7 @@ module cl_dram_dma_axi_mstr (
    // ----------------------
 
    assign cmd_rd_data_ns[31:0] =
-         (axi_mstr_sm_rd_data & cl_axi_mstr_bus.rvalid) ? cl_axi_mstr_bus.rdata[31:0] :
+         (axi_mstr_sm_rd_data & cl_axi_mstr_bus.rvalid) ? (cl_axi_mstr_bus.rdata[511:0] >> (8 * cmd_addr_lo_q[5:0])) :
                                                           cmd_rd_data_q[31:0]         ;
 
    always_ff @(posedge aclk)
@@ -338,8 +338,9 @@ module cl_dram_dma_axi_mstr (
 
    // Write Data
    assign cl_axi_mstr_bus.wid[15:0]    = 16'b0;                        // Only 1 outstanding command
-   assign cl_axi_mstr_bus.wdata[511:0] = {480'b0, cmd_wr_data_q[31:0]};
-   assign cl_axi_mstr_bus.wstrb[63:0]  = 64'h0000_0000_0000_000F;      // Always 4 bytes
+   assign cl_axi_mstr_bus.wdata[511:0] = {480'b0, cmd_wr_data_q[31:0]} << (8 * cmd_addr_lo_q[5:0]);
+   assign cl_axi_mstr_bus.wstrb[63:0]  = 64'h0000_0000_0000_000F << cmd_addr_lo_q[5:0];      // Always 4 bytes
+
    assign cl_axi_mstr_bus.wlast        = 1'b1;                         // Always 1 burst
    assign cl_axi_mstr_bus.wvalid       = axi_mstr_sm_wr_data;
 
@@ -356,4 +357,4 @@ module cl_dram_dma_axi_mstr (
    // Read Data
    assign cl_axi_mstr_bus.rready       = axi_mstr_sm_rd_data;
 
-endmodule   
+endmodule