diff --git a/designs/.lastupdated b/designs/d31_mdhamank_lfsr/.lastupdated similarity index 100% rename from designs/.lastupdated rename to designs/d31_mdhamank_lfsr/.lastupdated diff --git a/designs/d32_ngaertne_cpu/.lastupdated b/designs/d32_ngaertne_cpu/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d32_ngaertne_cpu/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d33_mgee3_adder/.lastupdated b/designs/d33_mgee3_adder/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d33_mgee3_adder/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d34_hgrodin_collatz/.lastupdated b/designs/d34_hgrodin_collatz/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d34_hgrodin_collatz/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d35_ckasuba_comparator/.lastupdated b/designs/d35_ckasuba_comparator/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d35_ckasuba_comparator/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d36_jxli_fpmul/.lastupdated b/designs/d36_jxli_fpmul/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d36_jxli_fpmul/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d37_sophiali_calculator/.lastupdated b/designs/d37_sophiali_calculator/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d37_sophiali_calculator/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d38_jxlu_pwm/.lastupdated b/designs/d38_jxlu_pwm/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d38_jxlu_pwm/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d39_oonyeado_sevenseg/.lastupdated b/designs/d39_oonyeado_sevenseg/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d39_oonyeado_sevenseg/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d40_jrecta_asyncfifo/.lastupdated b/designs/d40_jrecta_asyncfifo/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d40_jrecta_asyncfifo/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d41_stroucki_corralgame/.lastupdated b/designs/d41_stroucki_corralgame/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d41_stroucki_corralgame/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d41_stroucki_corralgame/LICENSE b/designs/d41_stroucki_corralgame/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/designs/d41_stroucki_corralgame/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/designs/d41_stroucki_corralgame/README.md b/designs/d41_stroucki_corralgame/README.md new file mode 100644 index 0000000..2a32665 --- /dev/null +++ b/designs/d41_stroucki_corralgame/README.md @@ -0,0 +1,34 @@ +# Corral Game + +Michael Stroucken +98-154 Intro to Open-Source Chip Design, Fall 2022 + +## Description + +Implements the Corral game from Basic Computer Games vol 2. + +It has a constrained front end because of the few IO ports available. + +Submit values from 1 to 5 in move and assert enter when game asserts ready. + +### Inputs + +- clock +- reset +- move0 # bit 0 of move +- move1 # bit 1 of move +- move2 # bit 2 of move +- enter # submit move +- none +- none + +### Outputs + +- data0 # bit 0 of game data +- data1 # bit 1 of game data +- data2 # bit 2 of game data +- data3 # bit 3 of game data +- gameover # high if game over +- lostwon # if game over, then high if won, low if lost +- ready # high if game is ready for next move +- none diff --git a/designs/d41_stroucki_corralgame/info.yaml b/designs/d41_stroucki_corralgame/info.yaml new file mode 100644 index 0000000..9093925 --- /dev/null +++ b/designs/d41_stroucki_corralgame/info.yaml @@ -0,0 +1,9 @@ +--- +project: + source_files: + - stroucki_top.sv + - lfsr.v + - game.sv + top_module: "stroucki_top" + + tt02_fmt: true diff --git a/designs/d41_stroucki_corralgame/src/cells.v b/designs/d41_stroucki_corralgame/src/cells.v new file mode 100644 index 0000000..772fb21 --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/cells.v @@ -0,0 +1,102 @@ +/* +This file provides the mapping from the Wokwi modules to Verilog HDL + +It's only needed for Wokwi designs + +*/ +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= 0; + else if (s) + q <= 1; + else + q <= d; + end +endmodule diff --git a/designs/d41_stroucki_corralgame/src/config.tcl b/designs/d41_stroucki_corralgame/src/config.tcl new file mode 100644 index 0000000..36321ab --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/config.tcl @@ -0,0 +1,65 @@ +# PLEASE DO NOT EDIT THIS FILE! +# The only thing you can change is the PL_BASIC_PLACEMENT line +# If you get stuck with this config, please open an issue or get in touch via the discord. + +# User config +set script_dir [file dirname [file normalize [info script]]] + +# read some user config that is written by the setup.py program. +# - the name of the module is defined +# - the list of source files +source $::env(DESIGN_DIR)/user_config.tcl + +# save some time +set ::env(RUN_KLAYOUT_XOR) 0 +set ::env(RUN_KLAYOUT_DRC) 0 + +# don't put clock buffers on the outputs +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 + +# allow use of specific sky130 cells +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# put all the pins on the left +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + +# reduce wasted space +set ::env(TOP_MARGIN_MULT) 2 +set ::env(BOTTOM_MARGIN_MULT) 2 + +# absolute die size +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 150 170" +set ::env(FP_CORE_UTIL) 55 + +# comment this if your design has more than a few hundred cells +set ::env(PL_BASIC_PLACEMENT) {1} + +set ::env(FP_IO_HLENGTH) 2 +set ::env(FP_IO_VLENGTH) 2 + +# use alternative efabless decap cells to solve LI density issue +set ::env(DECAP_CELL) "\ + sky130_fd_sc_hd__decap_3 \ + sky130_fd_sc_hd__decap_4 \ + sky130_fd_sc_hd__decap_6 \ + sky130_fd_sc_hd__decap_8 \ + sky130_ef_sc_hd__decap_12" + +# clock +set ::env(CLOCK_TREE_SYNTH) 1 +# period is in ns, so 20000ns == 50kHz +set ::env(CLOCK_PERIOD) "20000" +set ::env(CLOCK_PORT) {io_in[0]} + +# hold/slack margin +# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 +# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 + +# don't use power rings or met5 +set ::env(DESIGN_IS_CORE) 0 +set ::env(RT_MAX_LAYER) {met4} + +# connect to first digital rails +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] diff --git a/designs/d41_stroucki_corralgame/src/game.sv b/designs/d41_stroucki_corralgame/src/game.sv new file mode 100644 index 0000000..93ef477 --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/game.sv @@ -0,0 +1,211 @@ +// Michael Stroucken +// 98-154 +// Tinytapeout Corral project + +`default_nettype none + +module game + (input logic clock, + input logic reset_n, + input logic enter, + input logic [2:0] move, + output logic [3:0] cowboyPos, + output logic [3:0] horsePos, + output logic gameover, + output logic lostwon, + output logic ready); + + typedef enum logic [2:0] {IDLE, SETUP, KICK, WAIT, GAME} state_t; + state_t state = SETUP, nextState; + + logic [3:0] horsepos; + logic [3:0] cowboypos; + + logic targetGameover, targetLostwon, targetReady; + logic [2:0] targetKickflight, targetKickcount, targetMove, targetCowboyHitpoints; + logic [3:0] targetCowboypos, targetHorsepos; + + // need random numbers 0 to 9, + // 3 bits + 2 bits? + logic [4:0] lfsrout; + LFSR #(5) lfsrinstance(.i_Clk(clock), .i_Enable(1'b0), + .o_LFSR_Data(lfsrout)); + + logic [30:0] p = { 4'd0, 4'd1, 4'd2, 4'd3, 4'd3, 4'd2, 4'd2, 4'd1, 4'd0, -4'd1 }; + logic [30:0] q = { 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd4, 4'd3, 4'd2, 4'd1, 4'd0 }; + + logic [3:0] pVal, qVal; + logic [4:0] randomVal; + + //sequential + // arena limited to 16 + logic [2:0] kickflight, kickcount, cowboyHitpoints; +/* + register #(4) cowboyposreg(.clock(clock), .reset_n(reset_n), + .ld_n(loadCowboypos_n), .cl_n(1'b1), .in(targetCowboypos), + .out(cowboypos)); + register #(4) horseposreg(.clock(clock), .reset_n(reset_n), + .ld_n(loadHorsepos_n), .cl_n(1'b1), .in(targetHorsepos), + .out(cowboypos)); + register #(3) kickflightreg(.clock(clock), .reset_n(reset_n), + .ld_n(loadKickflight_n), .cl_n(1'b1), .in(targetKickflight), + .out(kickflight)); + register #(4) cowboyhitpointsreg(.clock(clock), .reset_n(reset_n), + .ld_n(loadHitpoints_n), .cl_n(1'b1), .in(targetHitpoints), + .out(cowboyHitpoints)); +*/ + + // logic lostwon, gameover + // not counting rounds + logic kickdead; + logic [3:0] distance; + logic cowboyLeftOfHorse; + + + // set up random values + assign randomVal = lfsrout[4:2] + lfsrout[1:0]; + assign pVal = p[randomVal << 4 +: 4]; + assign qVal = q[randomVal << 4 +: 4]; + + function automatic integer cowboyDest; + input cowboyLeftOfHorse; + input [3:0] cowboyPos; + input [3:0] move; + cowboyDest = cowboyPos + (cowboyLeftOfHorse? move : - move); + endfunction + + function automatic cowboyInBound; + input cowboyLeftOfHorse; + input [3:0] cowboyPos; + input [3:0] move; + integer dest; + dest = cowboyPos + (cowboyLeftOfHorse? move : - move); + if (dest > 0 && dest < 16) begin + cowboyInBound = 1; + end else cowboyInBound = 0; + endfunction + + function automatic boundHorse; + integer horsePos; + integer targetHorsePos; + targetHorsePos = horsePos; + if (horsePos < 0) targetHorsePos = 0; + if (horsePos > (16 - 1)) targetHorsePos = (16 - 1); + boundHorse = targetHorsePos; + endfunction + + function automatic integer boltDest; + input cowboyLeftOfHorse; + input [3:0] horsePos; + // was 9 + 2*pVal + integer boltStrength; + boltStrength = 4'd5 + (pVal << 1); + boltDest = horsePos - (cowboyLeftOfHorse ? boltStrength : -boltStrength); + endfunction + + always_comb begin + targetGameover = gameover; + targetKickflight = kickflight; + targetKickcount = kickcount; + targetCowboypos = cowboypos; + targetHorsepos = horsepos; + targetLostwon = lostwon; + targetMove = move; + targetCowboyHitpoints = cowboyHitpoints; + targetReady = 0; + kickdead = (kickcount > cowboyHitpoints); + // used for game decision, so should be next values + distance = (targetCowboypos > targetHorsepos) ? targetCowboypos - targetHorsepos : targetHorsepos - targetCowboypos; + cowboyLeftOfHorse = (cowboypos > horsepos) ? 0 : 1; +// IDLE, SETUP, KICK, WAIT, GAME + unique case (state) + IDLE: if (enter && move > 3'd0 && move < 3'd6 && cowboyInBound(cowboyLeftOfHorse, cowboyPos, move)) + begin + nextState = GAME; + end + else begin + nextState = IDLE; + targetReady = 1; + end + WAIT: if (enter) begin + nextState = WAIT; + end else nextState = IDLE; + KICK: if (kickdead) + begin + targetGameover = 1; + targetLostwon = 0; + nextState = SETUP; + end + else begin + targetKickflight = kickflight - 1; + nextState = KICK; + if (targetKickflight == 0) nextState = IDLE; + if (cowboyLeftOfHorse) begin + targetHorsepos = boundHorse(horsePos + pVal + 1); + end else begin + targetHorsepos = boundHorse(horsePos - pVal - 1); + end + end + GAME: begin + targetCowboypos = cowboyDest(cowboyLeftOfHorse, cowboyPos, move); + targetHorsepos = boundHorse(horsepos + (cowboyLeftOfHorse ? pVal : -pVal)); + if (distance < (move << 1) && distance > 1) begin + // bolt + targetHorsepos = boundHorse(boltDest(cowboyLeftOfHorse, horsePos)); + if (distance < 1) begin + targetHorsepos = boundHorse(horsePos - (cowboyLeftOfHorse ? 4'd3 : -4'd3)); + end + nextState = WAIT; + end + // somewhat strange conditioning around this + else if (distance > 4'd2) begin + nextState = WAIT; + end + else if (randomVal > 5'd3) begin + if (targetHorsepos == targetCowboypos) begin + targetGameover = 1; + targetLostwon = 1; + nextState = SETUP; + end + else nextState = WAIT; + end + else begin + targetKickflight = pVal + 3'd2; + targetKickcount++; + targetHorsepos = boundHorse(horsePos - (cowboyLeftOfHorse ? 4'd5 : -4'd5)); + nextState = KICK; + end + end + SETUP: begin + targetGameover = 1; + targetCowboypos <= 4'd0; + targetKickflight <= 3'd0; + targetKickcount <= 3'd0; + targetCowboyHitpoints <= 3'd2 + pVal; + // was 13 + targetHorsepos = 4'd10 + (randomVal > 5 ? qVal : -qVal); + nextState = WAIT; + end + endcase + end + + // state transition + always @(posedge clock, negedge reset_n) begin + if (~reset_n) begin + lostwon <= 1; + state <= SETUP; + end + else begin + state <= nextState; + gameover <= targetGameover; + kickflight <= targetKickflight; + kickcount <= targetKickcount; + cowboypos <= targetCowboypos; + horsepos <= targetHorsepos; + lostwon <= targetLostwon; + cowboyHitpoints <= targetCowboyHitpoints; + end + end + + +endmodule: game diff --git a/designs/d41_stroucki_corralgame/src/lfsr.v b/designs/d41_stroucki_corralgame/src/lfsr.v new file mode 100644 index 0000000..a822b6b --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/lfsr.v @@ -0,0 +1,153 @@ +/////////////////////////////////////////////////////////////////////////////// +// File downloaded from http://www.nandland.com +/////////////////////////////////////////////////////////////////////////////// +// Description: +// A LFSR or Linear Feedback Shift Register is a quick and easy way to generate +// pseudo-random data inside of an FPGA. The LFSR can be used for things like +// counters, test patterns, scrambling of data, and others. This module +// creates an LFSR whose width gets set by a parameter. The o_LFSR_Done will +// pulse once all combinations of the LFSR are complete. The number of clock +// cycles that it takes o_LFSR_Done to pulse is equal to 2^g_Num_Bits-1. For +// example setting g_Num_Bits to 5 means that o_LFSR_Done will pulse every +// 2^5-1 = 31 clock cycles. o_LFSR_Data will change on each clock cycle that +// the module is enabled, which can be used if desired. +// +// Parameters: +// NUM_BITS - Set to the integer number of bits wide to create your LFSR. +/////////////////////////////////////////////////////////////////////////////// +module LFSR #(parameter NUM_BITS = 32) + ( + input i_Clk, + input i_Enable, + + // Optional Seed Value + input i_Seed_DV, + input [NUM_BITS-1:0] i_Seed_Data, + + output [NUM_BITS-1:0] o_LFSR_Data, + output o_LFSR_Done + ); + + reg [NUM_BITS:1] r_LFSR = 0; + reg r_XNOR; + + + // Purpose: Load up LFSR with Seed if Data Valid (DV) pulse is detected. + // Othewise just run LFSR when enabled. + always @(posedge i_Clk) + begin + if (i_Enable == 1'b1) + begin + if (i_Seed_DV == 1'b1) + r_LFSR <= i_Seed_Data; + else + r_LFSR <= {r_LFSR[NUM_BITS-1:1], r_XNOR}; + end + end + + // Create Feedback Polynomials. Based on Application Note: + // http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf + always @(*) + begin + case (NUM_BITS) + 3: begin + r_XNOR = r_LFSR[3] ^~ r_LFSR[2]; + end + 4: begin + r_XNOR = r_LFSR[4] ^~ r_LFSR[3]; + end + 5: begin + r_XNOR = r_LFSR[5] ^~ r_LFSR[3]; + end + 6: begin + r_XNOR = r_LFSR[6] ^~ r_LFSR[5]; + end + 7: begin + r_XNOR = r_LFSR[7] ^~ r_LFSR[6]; + end + 8: begin + r_XNOR = r_LFSR[8] ^~ r_LFSR[6] ^~ r_LFSR[5] ^~ r_LFSR[4]; + end + 9: begin + r_XNOR = r_LFSR[9] ^~ r_LFSR[5]; + end + 10: begin + r_XNOR = r_LFSR[10] ^~ r_LFSR[7]; + end + 11: begin + r_XNOR = r_LFSR[11] ^~ r_LFSR[9]; + end + 12: begin + r_XNOR = r_LFSR[12] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1]; + end + 13: begin + r_XNOR = r_LFSR[13] ^~ r_LFSR[4] ^~ r_LFSR[3] ^~ r_LFSR[1]; + end + 14: begin + r_XNOR = r_LFSR[14] ^~ r_LFSR[5] ^~ r_LFSR[3] ^~ r_LFSR[1]; + end + 15: begin + r_XNOR = r_LFSR[15] ^~ r_LFSR[14]; + end + 16: begin + r_XNOR = r_LFSR[16] ^~ r_LFSR[15] ^~ r_LFSR[13] ^~ r_LFSR[4]; + end + 17: begin + r_XNOR = r_LFSR[17] ^~ r_LFSR[14]; + end + 18: begin + r_XNOR = r_LFSR[18] ^~ r_LFSR[11]; + end + 19: begin + r_XNOR = r_LFSR[19] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1]; + end + 20: begin + r_XNOR = r_LFSR[20] ^~ r_LFSR[17]; + end + 21: begin + r_XNOR = r_LFSR[21] ^~ r_LFSR[19]; + end + 22: begin + r_XNOR = r_LFSR[22] ^~ r_LFSR[21]; + end + 23: begin + r_XNOR = r_LFSR[23] ^~ r_LFSR[18]; + end + 24: begin + r_XNOR = r_LFSR[24] ^~ r_LFSR[23] ^~ r_LFSR[22] ^~ r_LFSR[17]; + end + 25: begin + r_XNOR = r_LFSR[25] ^~ r_LFSR[22]; + end + 26: begin + r_XNOR = r_LFSR[26] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1]; + end + 27: begin + r_XNOR = r_LFSR[27] ^~ r_LFSR[5] ^~ r_LFSR[2] ^~ r_LFSR[1]; + end + 28: begin + r_XNOR = r_LFSR[28] ^~ r_LFSR[25]; + end + 29: begin + r_XNOR = r_LFSR[29] ^~ r_LFSR[27]; + end + 30: begin + r_XNOR = r_LFSR[30] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1]; + end + 31: begin + r_XNOR = r_LFSR[31] ^~ r_LFSR[28]; + end + 32: begin + r_XNOR = r_LFSR[32] ^~ r_LFSR[22] ^~ r_LFSR[2] ^~ r_LFSR[1]; + end + + endcase // case (NUM_BITS) + end // always @ (*) + + + assign o_LFSR_Data = r_LFSR[NUM_BITS:1]; + + // Conditional Assignment (?) + assign o_LFSR_Done = (r_LFSR[NUM_BITS:1] == i_Seed_Data) ? 1'b1 : 1'b0; + +endmodule // LFSR diff --git a/designs/d41_stroucki_corralgame/src/pin_order.cfg b/designs/d41_stroucki_corralgame/src/pin_order.cfg new file mode 100644 index 0000000..0b85c63 --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/pin_order.cfg @@ -0,0 +1,9 @@ +#N + +#S + +#E + +#W +io_in.* +io_out.* diff --git a/designs/d41_stroucki_corralgame/src/stroucki_top.sv b/designs/d41_stroucki_corralgame/src/stroucki_top.sv new file mode 100644 index 0000000..393f188 --- /dev/null +++ b/designs/d41_stroucki_corralgame/src/stroucki_top.sv @@ -0,0 +1,80 @@ +// Michael Stroucken +// 98-154 +// Tinytapeout Corral project + +`default_nettype none + +module stroucki_top + (input logic [7:0] io_in, + output logic [7:0] io_out); + + // assign inputs + logic clock, reset, enter; + logic [2:0] move; + assign {enter, move, reset, clock} = io_in; + // assign outputs + logic ready, lostwon, gameover; + logic [3:0] data; + assign io_out = {ready, lostwon, gameover, data}; + + typedef enum logic [2:0] {COWBOY, HORSE, GAME, IDLE} state_t; + state_t state = IDLE, nextState; + + // want sequential: + // data, gameover, lostwon, ready, state + + logic [3:0] horsepos; + logic [3:0] cowboypos; + + logic gameenter, gamegameover, gamelostwon, gameready; + logic [2:0] gamemove; + + + logic reset_n; + assign reset_n = !reset; + + game gameinstance(.clock(clock), .reset_n(reset_n), + .cowboyPos(cowboypos), .horsePos(horsepos), .gameover(gamegameover), + .lostwon(gamelostwon), .ready(gameready), .enter(gameenter), + .move(gamemove)); + + // current state logic + always_comb begin + gameenter = 0; + gamemove = 3'b0; + data = 4'b0; + + unique case (state) + IDLE: if (enter) + begin + gameenter = 1; + gamemove = move; + nextState = COWBOY; + end + else nextState = IDLE; + COWBOY: nextState = HORSE; + HORSE: nextState = GAME; + GAME: if (enter) + begin + nextState = COWBOY; + end + else nextState = IDLE; + endcase + end + + always @(posedge clock, negedge reset_n) begin + if (~reset_n) begin + state <= IDLE; + data <= 4'b0; + gameover <= 1; + end + else begin + gameover <= gamegameover; + ready <= gameready; + lostwon <= gamelostwon; + ready <= gameready; + + end + end + +endmodule: stroucki_top diff --git a/designs/d42_qilins_sevenseg/.lastupdated b/designs/d42_qilins_sevenseg/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d42_qilins_sevenseg/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d43_mmx_counter/.lastupdated b/designs/d43_mmx_counter/.lastupdated new file mode 100644 index 0000000..4d7b8c3 --- /dev/null +++ b/designs/d43_mmx_counter/.lastupdated @@ -0,0 +1 @@ +2023-05-14 diff --git a/designs/d43_mmx_counter/LICENSE b/designs/d43_mmx_counter/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/designs/d43_mmx_counter/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/designs/d43_mmx_counter/README.md b/designs/d43_mmx_counter/README.md new file mode 100644 index 0000000..f770e1c --- /dev/null +++ b/designs/d43_mmx_counter/README.md @@ -0,0 +1,30 @@ +# Counter + +Mason Xiao +98-154 Intro to Open-Source Chip Design, Fall 2022 + +## Description + +Count up to 10, one second at a time. Uses a register and some combinational logic. After reset, the counter should increase by one every second. + +### Inputs + +- clock +- reset +- none +- none +- none +- none +- none +- none + +### Outputs + +- counter bit 0 +- counter bit 1 +- counter bit 2 +- counter bit 3 +- counter bit 4 +- counter bit 5 +- counter bit 6 +- counter bit 7 diff --git a/designs/d43_mmx_counter/info.yaml b/designs/d43_mmx_counter/info.yaml new file mode 100644 index 0000000..38cd938 --- /dev/null +++ b/designs/d43_mmx_counter/info.yaml @@ -0,0 +1,8 @@ +--- +project: + source_files: + - chip.v + top_module: "mmx_chip" + + tt02_fmt: true + diff --git a/designs/d43_mmx_counter/src/Makefile b/designs/d43_mmx_counter/src/Makefile new file mode 100644 index 0000000..19c66af --- /dev/null +++ b/designs/d43_mmx_counter/src/Makefile @@ -0,0 +1,18 @@ +# Makefile +# See https://docs.cocotb.org/en/stable/quickstart.html for more info + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog + +VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/chip.v + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = tb + +# MODULE is the basename of the Python test file +MODULE = test + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + diff --git a/designs/d43_mmx_counter/src/cells.v b/designs/d43_mmx_counter/src/cells.v new file mode 100644 index 0000000..d9e1735 --- /dev/null +++ b/designs/d43_mmx_counter/src/cells.v @@ -0,0 +1,103 @@ +/* +This file provides the mapping from the Wokwi modules to Verilog HDL + +It's only needed for Wokwi designs + +*/ +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= 0; + else if (s) + q <= 1; + else + q <= d; + end +endmodule + diff --git a/designs/d43_mmx_counter/src/chip.v b/designs/d43_mmx_counter/src/chip.v new file mode 100644 index 0000000..3962b49 --- /dev/null +++ b/designs/d43_mmx_counter/src/chip.v @@ -0,0 +1,24 @@ +`default_nettype none + +module mmx_chip ( + input [7:0] io_in, + output [7:0] io_out +); + + wire clk = io_in[0]; + wire reset = io_in[1]; + reg [6:0] counter; + assign io_out[7:0] = counter; + + always @(posedge clk) begin + // if reset, set counter to 0 + if (reset) begin + counter <= 0; + end else begin + // if up to 16e6 + // increment counter + counter <= counter + 1'b1; + end + end + +endmodule diff --git a/designs/d43_mmx_counter/src/config.tcl b/designs/d43_mmx_counter/src/config.tcl new file mode 100644 index 0000000..36321ab --- /dev/null +++ b/designs/d43_mmx_counter/src/config.tcl @@ -0,0 +1,65 @@ +# PLEASE DO NOT EDIT THIS FILE! +# The only thing you can change is the PL_BASIC_PLACEMENT line +# If you get stuck with this config, please open an issue or get in touch via the discord. + +# User config +set script_dir [file dirname [file normalize [info script]]] + +# read some user config that is written by the setup.py program. +# - the name of the module is defined +# - the list of source files +source $::env(DESIGN_DIR)/user_config.tcl + +# save some time +set ::env(RUN_KLAYOUT_XOR) 0 +set ::env(RUN_KLAYOUT_DRC) 0 + +# don't put clock buffers on the outputs +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 + +# allow use of specific sky130 cells +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# put all the pins on the left +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + +# reduce wasted space +set ::env(TOP_MARGIN_MULT) 2 +set ::env(BOTTOM_MARGIN_MULT) 2 + +# absolute die size +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 150 170" +set ::env(FP_CORE_UTIL) 55 + +# comment this if your design has more than a few hundred cells +set ::env(PL_BASIC_PLACEMENT) {1} + +set ::env(FP_IO_HLENGTH) 2 +set ::env(FP_IO_VLENGTH) 2 + +# use alternative efabless decap cells to solve LI density issue +set ::env(DECAP_CELL) "\ + sky130_fd_sc_hd__decap_3 \ + sky130_fd_sc_hd__decap_4 \ + sky130_fd_sc_hd__decap_6 \ + sky130_fd_sc_hd__decap_8 \ + sky130_ef_sc_hd__decap_12" + +# clock +set ::env(CLOCK_TREE_SYNTH) 1 +# period is in ns, so 20000ns == 50kHz +set ::env(CLOCK_PERIOD) "20000" +set ::env(CLOCK_PORT) {io_in[0]} + +# hold/slack margin +# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 +# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 + +# don't use power rings or met5 +set ::env(DESIGN_IS_CORE) 0 +set ::env(RT_MAX_LAYER) {met4} + +# connect to first digital rails +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] diff --git a/designs/d43_mmx_counter/src/pin_order.cfg b/designs/d43_mmx_counter/src/pin_order.cfg new file mode 100644 index 0000000..0b85c63 --- /dev/null +++ b/designs/d43_mmx_counter/src/pin_order.cfg @@ -0,0 +1,9 @@ +#N + +#S + +#E + +#W +io_in.* +io_out.* diff --git a/designs/d43_mmx_counter/src/results.xml b/designs/d43_mmx_counter/src/results.xml new file mode 100644 index 0000000..70491e9 --- /dev/null +++ b/designs/d43_mmx_counter/src/results.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/designs/d43_mmx_counter/src/tb.gtkw b/designs/d43_mmx_counter/src/tb.gtkw new file mode 100644 index 0000000..52bcbba --- /dev/null +++ b/designs/d43_mmx_counter/src/tb.gtkw @@ -0,0 +1,25 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Thu Oct 27 10:17:53 2022 +[*] +[dumpfile] "/home/matt/work/asic-workshop/shuttle7/tt02-submission-template/src/tb.vcd" +[dumpfile_mtime] "Thu Oct 27 10:17:11 2022" +[dumpfile_size] 14468 +[savefile] "/home/matt/work/asic-workshop/shuttle7/tt02-submission-template/src/tb.gtkw" +[timestart] 0 +[size] 2286 698 +[pos] -1 -1 +*-30.600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] tb. +[sst_width] 343 +[signals_width] 264 +[sst_expanded] 1 +[sst_vpaned_height] 190 +@28 +tb.clk +@29 +tb.rst +@22 +tb.segments[6:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/designs/d43_mmx_counter/src/tb.v b/designs/d43_mmx_counter/src/tb.v new file mode 100644 index 0000000..acad5af --- /dev/null +++ b/designs/d43_mmx_counter/src/tb.v @@ -0,0 +1,29 @@ +`default_nettype none +`timescale 1ns/1ps + +/* +this testbench just instantiates the module and makes some convenient wires +that can be driven / tested by the cocotb test.py +*/ + +module tb ( + // testbench is controlled by test.py + input clk, + input rst, + output [7:0] outputs + ); + + // this part dumps the trace to a vcd file that can be viewed with GTKWave + initial begin + $dumpfile("tb.vcd"); + $dumpvars(0, tb); + #1; + end + + // wire up the inputs and outputs + wire [7:0] inputs = {6'b0, rst, clk}; + + // instantiate the DUT + mmx_chip dut(.io_in (inputs), .io_out(outputs)); + +endmodule diff --git a/designs/d43_mmx_counter/src/test.py b/designs/d43_mmx_counter/src/test.py new file mode 100644 index 0000000..3fa1262 --- /dev/null +++ b/designs/d43_mmx_counter/src/test.py @@ -0,0 +1,22 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer, ClockCycles + + +segments = [ 63, 6, 91, 79, 102, 109, 124, 7, 127, 103 ] + +@cocotb.test() +async def test_chip(dut): + dut._log.info("start") + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + dut._log.info("reset") + dut.rst.value = 1 + await ClockCycles(dut.clk, 10) + dut.rst.value = 0 + + for i in range(10): + await ClockCycles(dut.clk, 100) + dut._log.info("{}".format(int(dut.outputs.value))) + assert int(dut.outputs.value) == ((i*100 + 99) % 128)