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flattened.v
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/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */
/* top = 1 */
/* src = "d35_ckasuba_comparator/src/wrapper.v:2.9-12.18" */
module d35_ckasuba_comparator(io_in, io_out);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
/* src = "d35_ckasuba_comparator/src/wrapper.v:3.26-3.31" */
input [13:0] io_in;
wire [13:0] io_in;
/* src = "d35_ckasuba_comparator/src/wrapper.v:4.27-4.33" */
output [13:0] io_out;
wire [13:0] io_out;
/* hdlname = "mchip and1 b" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:18.16-18.17|d35_ckasuba_comparator/src/wokwi.v:78.12-82.4" */
wire \mchip.and1.b ;
/* hdlname = "mchip and2 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:17.16-17.17|d35_ckasuba_comparator/src/wokwi.v:83.12-87.4" */
wire \mchip.and2.a ;
/* hdlname = "mchip and3 b" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:18.16-18.17|d35_ckasuba_comparator/src/wokwi.v:105.12-109.4" */
wire \mchip.and3.b ;
/* hdlname = "mchip and4 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:17.16-17.17|d35_ckasuba_comparator/src/wokwi.v:110.12-114.4" */
wire \mchip.and4.a ;
/* hdlname = "mchip and5 b" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:18.16-18.17|d35_ckasuba_comparator/src/wokwi.v:132.12-136.4" */
wire \mchip.and5.b ;
/* hdlname = "mchip and6 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:17.16-17.17|d35_ckasuba_comparator/src/wokwi.v:137.12-141.4" */
wire \mchip.and6.a ;
/* hdlname = "mchip and7 b" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:18.16-18.17|d35_ckasuba_comparator/src/wokwi.v:159.12-163.4" */
wire \mchip.and7.b ;
/* hdlname = "mchip and8 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:17.16-17.17|d35_ckasuba_comparator/src/wokwi.v:164.12-168.4" */
wire \mchip.and8.a ;
/* hdlname = "mchip io_in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:6.15-6.20" */
wire [7:0] \mchip.io_in ;
/* hdlname = "mchip io_out" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:7.16-7.22" */
wire [7:0] \mchip.io_out ;
/* hdlname = "mchip net1" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:9.8-9.12" */
wire \mchip.net1 ;
/* hdlname = "mchip net10" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:18.8-18.13" */
wire \mchip.net10 ;
/* hdlname = "mchip net11" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:19.8-19.13" */
wire \mchip.net11 ;
/* hdlname = "mchip net12" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:20.8-20.13" */
wire \mchip.net12 ;
/* hdlname = "mchip net13" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:21.8-21.13" */
wire \mchip.net13 ;
/* hdlname = "mchip net14" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:22.8-22.13" */
wire \mchip.net14 ;
/* hdlname = "mchip net15" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:23.8-23.13" */
wire \mchip.net15 ;
/* hdlname = "mchip net2" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:10.8-10.12" */
wire \mchip.net2 ;
/* hdlname = "mchip net3" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:11.8-11.12" */
wire \mchip.net3 ;
/* hdlname = "mchip net4" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:12.8-12.12" */
wire \mchip.net4 ;
/* hdlname = "mchip net5" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:13.8-13.12" */
wire \mchip.net5 ;
/* hdlname = "mchip net6" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:14.8-14.12" */
wire \mchip.net6 ;
/* hdlname = "mchip net7" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:15.8-15.12" */
wire \mchip.net7 ;
/* hdlname = "mchip net8" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:16.8-16.12" */
wire \mchip.net8 ;
/* hdlname = "mchip net9" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/wokwi.v:17.8-17.12" */
wire \mchip.net9 ;
/* hdlname = "mchip not1 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:70.12-73.4" */
wire \mchip.not1.in ;
/* hdlname = "mchip not10 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:151.12-154.4" */
wire \mchip.not10.in ;
/* hdlname = "mchip not11 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:155.12-158.4" */
wire \mchip.not11.in ;
/* hdlname = "mchip not2 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:74.12-77.4" */
wire \mchip.not2.in ;
/* hdlname = "mchip not4 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:97.12-100.4" */
wire \mchip.not4.in ;
/* hdlname = "mchip not5 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:101.12-104.4" */
wire \mchip.not5.in ;
/* hdlname = "mchip not7 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:124.12-127.4" */
wire \mchip.not7.in ;
/* hdlname = "mchip not8 in" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:53.16-53.18|d35_ckasuba_comparator/src/wokwi.v:128.12-131.4" */
wire \mchip.not8.in ;
/* hdlname = "mchip or10 out" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:28.17-28.20|d35_ckasuba_comparator/src/wokwi.v:248.11-252.4" */
wire \mchip.or10.out ;
/* hdlname = "mchip or11 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:26.16-26.17|d35_ckasuba_comparator/src/wokwi.v:253.11-257.4" */
wire \mchip.or11.a ;
/* hdlname = "mchip or11 out" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:28.17-28.20|d35_ckasuba_comparator/src/wokwi.v:253.11-257.4" */
wire \mchip.or11.out ;
/* hdlname = "mchip or12 a" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:26.16-26.17|d35_ckasuba_comparator/src/wokwi.v:258.11-262.4" */
wire \mchip.or12.a ;
/* hdlname = "mchip or12 b" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:27.16-27.17|d35_ckasuba_comparator/src/wokwi.v:258.11-262.4" */
wire \mchip.or12.b ;
/* hdlname = "mchip or12 out" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:28.17-28.20|d35_ckasuba_comparator/src/wokwi.v:258.11-262.4" */
wire \mchip.or12.out ;
/* hdlname = "mchip or7 out" */
/* src = "d35_ckasuba_comparator/src/wrapper.v:7.44-10.14|d35_ckasuba_comparator/src/cells.v:28.17-28.20|d35_ckasuba_comparator/src/wokwi.v:233.11-237.4" */
wire \mchip.or7.out ;
assign _00_ = ~(io_in[0] ^ io_in[4]);
assign _01_ = io_in[5] ^ io_in[1];
assign _02_ = _00_ & ~(_01_);
assign _03_ = io_in[6] | ~(io_in[2]);
assign _04_ = io_in[2] | ~(io_in[6]);
assign _05_ = ~(_04_ & _03_);
assign _06_ = _02_ & ~(_05_);
assign _07_ = io_in[3] | ~(io_in[7]);
assign _08_ = _06_ & ~(_07_);
assign _09_ = _02_ & ~(_04_);
assign _10_ = _09_ | _08_;
assign _11_ = io_in[1] | ~(io_in[5]);
assign _12_ = _00_ & ~(_11_);
assign _13_ = io_in[4] & ~(io_in[0]);
assign _14_ = _13_ | _12_;
assign \mchip.net12 = _14_ | _10_;
assign _15_ = io_in[7] | ~(io_in[3]);
assign _16_ = _06_ & ~(_15_);
assign _17_ = _02_ & ~(_03_);
assign _18_ = _17_ | _16_;
assign _19_ = io_in[5] | ~(io_in[1]);
assign _20_ = _00_ & ~(_19_);
assign _21_ = io_in[0] & ~(io_in[4]);
assign _22_ = _21_ | _20_;
assign \mchip.net10 = _22_ | _18_;
assign \mchip.net11 = \mchip.net10 | \mchip.net12 ;
assign _23_ = ~(_15_ & _07_);
assign _24_ = _06_ & ~(_23_);
assign \mchip.net9 = _24_ | \mchip.net10 ;
assign io_out = { 8'h01, \mchip.net11 , \mchip.net11 , \mchip.net12 , \mchip.net11 , \mchip.net10 , \mchip.net9 };
assign \mchip.and1.b = io_in[4];
assign \mchip.and2.a = io_in[0];
assign \mchip.and3.b = io_in[5];
assign \mchip.and4.a = io_in[1];
assign \mchip.and5.b = io_in[6];
assign \mchip.and6.a = io_in[2];
assign \mchip.and7.b = io_in[7];
assign \mchip.and8.a = io_in[3];
assign \mchip.io_in = io_in[7:0];
assign \mchip.io_out = { 2'h1, \mchip.net11 , \mchip.net11 , \mchip.net12 , \mchip.net11 , \mchip.net10 , \mchip.net9 };
assign \mchip.net1 = io_in[0];
assign \mchip.net13 = 1'h1;
assign \mchip.net14 = 1'h0;
assign \mchip.net15 = 1'h1;
assign \mchip.net2 = io_in[1];
assign \mchip.net3 = io_in[2];
assign \mchip.net4 = io_in[3];
assign \mchip.net5 = io_in[4];
assign \mchip.net6 = io_in[5];
assign \mchip.net7 = io_in[6];
assign \mchip.net8 = io_in[7];
assign \mchip.not1.in = io_in[0];
assign \mchip.not10.in = io_in[3];
assign \mchip.not11.in = io_in[7];
assign \mchip.not2.in = io_in[4];
assign \mchip.not4.in = io_in[1];
assign \mchip.not5.in = io_in[5];
assign \mchip.not7.in = io_in[2];
assign \mchip.not8.in = io_in[6];
assign \mchip.or10.out = \mchip.net10 ;
assign \mchip.or11.a = \mchip.net10 ;
assign \mchip.or11.out = \mchip.net9 ;
assign \mchip.or12.a = \mchip.net12 ;
assign \mchip.or12.b = \mchip.net10 ;
assign \mchip.or12.out = \mchip.net11 ;
assign \mchip.or7.out = \mchip.net12 ;
endmodule