flattened.v

/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */

/* top =  1  */
/* src = "d30_yuchingw_fpga/src/toplevel_chip.v:4.1-18.10" */
module d30_yuchingw_fpga(io_in, io_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:5.18-5.23" */
  input [13:0] io_in;
  wire [13:0] io_in;
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:6.19-6.25" */
  output [13:0] io_out;
  wire [13:0] io_out;
  /* hdlname = "mchip clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:96.17-96.22" */
  wire \mchip.clock ;
  /* hdlname = "mchip io_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:94.24-94.29" */
  /* unused_bits = "2 3 4" */
  wire [11:0] \mchip.io_in ;
  /* hdlname = "mchip io_out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:95.25-95.31" */
  wire [11:0] \mchip.io_out ;
  /* hdlname = "mchip reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:97.17-97.22" */
  wire \mchip.reset ;
  /* hdlname = "mchip setData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:102.17-102.24" */
  wire [4:0] \mchip.setData ;
  /* hdlname = "mchip top CLBOut" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:131.18-131.24|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [15:0] \mchip.top.CLBOut ;
  /* hdlname = "mchip top addr0 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr0.LUTConfig ;
  /* hdlname = "mchip top addr0 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.clock ;
  /* hdlname = "mchip top addr0 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr0.data.D ;
  /* hdlname = "mchip top addr0 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.data.clock ;
  /* hdlname = "mchip top addr0 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.data.reset ;
  /* hdlname = "mchip top addr0 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.dataSel.D ;
  /* hdlname = "mchip top addr0 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.dataSel.clock ;
  /* hdlname = "mchip top addr0 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.dataSel.reset ;
  /* hdlname = "mchip top addr0 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.letVal.clock ;
  /* hdlname = "mchip top addr0 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.letVal.en ;
  /* hdlname = "mchip top addr0 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.letVal.reset ;
  /* hdlname = "mchip top addr0 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.memSel_in ;
  /* hdlname = "mchip top addr0 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.out ;
  /* hdlname = "mchip top addr0 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:197.9-203.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr0.reset ;
  /* hdlname = "mchip top addr1 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr1.LUTConfig ;
  /* hdlname = "mchip top addr1 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.clock ;
  /* hdlname = "mchip top addr1 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr1.data.D ;
  /* hdlname = "mchip top addr1 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.data.clock ;
  /* hdlname = "mchip top addr1 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.data.reset ;
  /* hdlname = "mchip top addr1 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.dataSel.D ;
  /* hdlname = "mchip top addr1 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.dataSel.clock ;
  /* hdlname = "mchip top addr1 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.dataSel.reset ;
  /* hdlname = "mchip top addr1 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.letVal.clock ;
  /* hdlname = "mchip top addr1 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.letVal.en ;
  /* hdlname = "mchip top addr1 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.letVal.reset ;
  /* hdlname = "mchip top addr1 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.memSel_in ;
  /* hdlname = "mchip top addr1 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.out ;
  /* hdlname = "mchip top addr1 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:205.9-211.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr1.reset ;
  /* hdlname = "mchip top addr10 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr10.LUTConfig ;
  /* hdlname = "mchip top addr10 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.clock ;
  /* hdlname = "mchip top addr10 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr10.data.D ;
  /* hdlname = "mchip top addr10 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.data.clock ;
  /* hdlname = "mchip top addr10 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.data.reset ;
  /* hdlname = "mchip top addr10 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.dataSel.D ;
  /* hdlname = "mchip top addr10 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.dataSel.clock ;
  /* hdlname = "mchip top addr10 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.dataSel.reset ;
  /* hdlname = "mchip top addr10 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.letVal.clock ;
  /* hdlname = "mchip top addr10 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.letVal.en ;
  /* hdlname = "mchip top addr10 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.letVal.reset ;
  /* hdlname = "mchip top addr10 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.memSel_in ;
  /* hdlname = "mchip top addr10 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.out ;
  /* hdlname = "mchip top addr10 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr10.reset ;
  /* hdlname = "mchip top addr10 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:279.9-285.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr10.sel ;
  /* hdlname = "mchip top addr11 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr11.LUTConfig ;
  /* hdlname = "mchip top addr11 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.clock ;
  /* hdlname = "mchip top addr11 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr11.data.D ;
  /* hdlname = "mchip top addr11 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.data.clock ;
  /* hdlname = "mchip top addr11 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.data.reset ;
  /* hdlname = "mchip top addr11 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.dataSel.D ;
  /* hdlname = "mchip top addr11 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.dataSel.clock ;
  /* hdlname = "mchip top addr11 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.dataSel.reset ;
  /* hdlname = "mchip top addr11 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.letVal.clock ;
  /* hdlname = "mchip top addr11 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.letVal.en ;
  /* hdlname = "mchip top addr11 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.letVal.reset ;
  /* hdlname = "mchip top addr11 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.memSel_in ;
  /* hdlname = "mchip top addr11 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.out ;
  /* hdlname = "mchip top addr11 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr11.reset ;
  /* hdlname = "mchip top addr11 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:287.9-293.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr11.sel ;
  /* hdlname = "mchip top addr12 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr12.LUTConfig ;
  /* hdlname = "mchip top addr12 LUTData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:46.17-46.24|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr12.LUTData ;
  /* hdlname = "mchip top addr12 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.clock ;
  /* hdlname = "mchip top addr12 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr12.data.D ;
  /* hdlname = "mchip top addr12 data Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr12.data.Q ;
  /* hdlname = "mchip top addr12 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.data.clock ;
  /* hdlname = "mchip top addr12 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.data.reset ;
  /* hdlname = "mchip top addr12 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.dataSel.D ;
  /* hdlname = "mchip top addr12 dataSel Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr12.dataSel.Q ;
  /* hdlname = "mchip top addr12 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.dataSel.clock ;
  /* hdlname = "mchip top addr12 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.dataSel.reset ;
  /* hdlname = "mchip top addr12 letVal D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.letVal.D ;
  /* hdlname = "mchip top addr12 letVal Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr12.letVal.Q ;
  /* hdlname = "mchip top addr12 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.letVal.clock ;
  /* hdlname = "mchip top addr12 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.letVal.en ;
  /* hdlname = "mchip top addr12 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.letVal.reset ;
  /* hdlname = "mchip top addr12 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.memSel_in ;
  /* hdlname = "mchip top addr12 memSel_mem" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:47.20-47.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.memSel_mem ;
  /* hdlname = "mchip top addr12 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.out ;
  /* hdlname = "mchip top addr12 regData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:47.11-47.18|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.regData ;
  /* hdlname = "mchip top addr12 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr12.reset ;
  /* hdlname = "mchip top addr12 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr12.sel ;
  /* hdlname = "mchip top addr13 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr13.LUTConfig ;
  /* hdlname = "mchip top addr13 LUTData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:46.17-46.24|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr13.LUTData ;
  /* hdlname = "mchip top addr13 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.clock ;
  /* hdlname = "mchip top addr13 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr13.data.D ;
  /* hdlname = "mchip top addr13 data Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr13.data.Q ;
  /* hdlname = "mchip top addr13 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.data.clock ;
  /* hdlname = "mchip top addr13 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.data.reset ;
  /* hdlname = "mchip top addr13 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.dataSel.D ;
  /* hdlname = "mchip top addr13 dataSel Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr13.dataSel.Q ;
  /* hdlname = "mchip top addr13 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.dataSel.clock ;
  /* hdlname = "mchip top addr13 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.dataSel.reset ;
  /* hdlname = "mchip top addr13 letVal D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.letVal.D ;
  /* hdlname = "mchip top addr13 letVal Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr13.letVal.Q ;
  /* hdlname = "mchip top addr13 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.letVal.clock ;
  /* hdlname = "mchip top addr13 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.letVal.en ;
  /* hdlname = "mchip top addr13 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.letVal.reset ;
  /* hdlname = "mchip top addr13 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.memSel_in ;
  /* hdlname = "mchip top addr13 memSel_mem" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:47.20-47.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.memSel_mem ;
  /* hdlname = "mchip top addr13 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.out ;
  /* hdlname = "mchip top addr13 regData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:47.11-47.18|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.regData ;
  /* hdlname = "mchip top addr13 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr13.reset ;
  /* hdlname = "mchip top addr13 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr13.sel ;
  /* hdlname = "mchip top addr14 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr14.LUTConfig ;
  /* hdlname = "mchip top addr14 LUTData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:46.17-46.24|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr14.LUTData ;
  /* hdlname = "mchip top addr14 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.clock ;
  /* hdlname = "mchip top addr14 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr14.data.D ;
  /* hdlname = "mchip top addr14 data Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr14.data.Q ;
  /* hdlname = "mchip top addr14 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.data.clock ;
  /* hdlname = "mchip top addr14 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.data.reset ;
  /* hdlname = "mchip top addr14 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.dataSel.D ;
  /* hdlname = "mchip top addr14 dataSel Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr14.dataSel.Q ;
  /* hdlname = "mchip top addr14 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.dataSel.clock ;
  /* hdlname = "mchip top addr14 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.dataSel.reset ;
  /* hdlname = "mchip top addr14 letVal D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.letVal.D ;
  /* hdlname = "mchip top addr14 letVal Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr14.letVal.Q ;
  /* hdlname = "mchip top addr14 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.letVal.clock ;
  /* hdlname = "mchip top addr14 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.letVal.en ;
  /* hdlname = "mchip top addr14 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.letVal.reset ;
  /* hdlname = "mchip top addr14 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.memSel_in ;
  /* hdlname = "mchip top addr14 memSel_mem" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:47.20-47.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.memSel_mem ;
  /* hdlname = "mchip top addr14 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.out ;
  /* hdlname = "mchip top addr14 regData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:47.11-47.18|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.regData ;
  /* hdlname = "mchip top addr14 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr14.reset ;
  /* hdlname = "mchip top addr14 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr14.sel ;
  /* hdlname = "mchip top addr15 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr15.LUTConfig ;
  /* hdlname = "mchip top addr15 LUTData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:46.17-46.24|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr15.LUTData ;
  /* hdlname = "mchip top addr15 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.clock ;
  /* hdlname = "mchip top addr15 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr15.data.D ;
  /* hdlname = "mchip top addr15 data Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr15.data.Q ;
  /* hdlname = "mchip top addr15 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.data.clock ;
  /* hdlname = "mchip top addr15 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.data.reset ;
  /* hdlname = "mchip top addr15 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.dataSel.D ;
  /* hdlname = "mchip top addr15 dataSel Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr15.dataSel.Q ;
  /* hdlname = "mchip top addr15 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.dataSel.clock ;
  /* hdlname = "mchip top addr15 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.dataSel.reset ;
  /* hdlname = "mchip top addr15 letVal D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.letVal.D ;
  /* hdlname = "mchip top addr15 letVal Q" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:7.26-7.27|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  reg \mchip.top.addr15.letVal.Q ;
  /* hdlname = "mchip top addr15 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.letVal.clock ;
  /* hdlname = "mchip top addr15 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.letVal.en ;
  /* hdlname = "mchip top addr15 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.letVal.reset ;
  /* hdlname = "mchip top addr15 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.memSel_in ;
  /* hdlname = "mchip top addr15 memSel_mem" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:47.20-47.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.memSel_mem ;
  /* hdlname = "mchip top addr15 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.out ;
  /* hdlname = "mchip top addr15 regData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:47.11-47.18|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.regData ;
  /* hdlname = "mchip top addr15 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr15.reset ;
  /* hdlname = "mchip top addr15 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr15.sel ;
  /* hdlname = "mchip top addr2 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr2.LUTConfig ;
  /* hdlname = "mchip top addr2 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.clock ;
  /* hdlname = "mchip top addr2 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr2.data.D ;
  /* hdlname = "mchip top addr2 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.data.clock ;
  /* hdlname = "mchip top addr2 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.data.reset ;
  /* hdlname = "mchip top addr2 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.dataSel.D ;
  /* hdlname = "mchip top addr2 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.dataSel.clock ;
  /* hdlname = "mchip top addr2 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.dataSel.reset ;
  /* hdlname = "mchip top addr2 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.letVal.clock ;
  /* hdlname = "mchip top addr2 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.letVal.en ;
  /* hdlname = "mchip top addr2 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.letVal.reset ;
  /* hdlname = "mchip top addr2 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.memSel_in ;
  /* hdlname = "mchip top addr2 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.out ;
  /* hdlname = "mchip top addr2 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:213.9-219.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr2.reset ;
  /* hdlname = "mchip top addr3 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr3.LUTConfig ;
  /* hdlname = "mchip top addr3 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.clock ;
  /* hdlname = "mchip top addr3 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr3.data.D ;
  /* hdlname = "mchip top addr3 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.data.clock ;
  /* hdlname = "mchip top addr3 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.data.reset ;
  /* hdlname = "mchip top addr3 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.dataSel.D ;
  /* hdlname = "mchip top addr3 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.dataSel.clock ;
  /* hdlname = "mchip top addr3 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.dataSel.reset ;
  /* hdlname = "mchip top addr3 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.letVal.clock ;
  /* hdlname = "mchip top addr3 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.letVal.en ;
  /* hdlname = "mchip top addr3 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.letVal.reset ;
  /* hdlname = "mchip top addr3 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.memSel_in ;
  /* hdlname = "mchip top addr3 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.out ;
  /* hdlname = "mchip top addr3 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:221.9-227.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr3.reset ;
  /* hdlname = "mchip top addr4 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr4.LUTConfig ;
  /* hdlname = "mchip top addr4 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.clock ;
  /* hdlname = "mchip top addr4 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr4.data.D ;
  /* hdlname = "mchip top addr4 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.data.clock ;
  /* hdlname = "mchip top addr4 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.data.reset ;
  /* hdlname = "mchip top addr4 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.dataSel.D ;
  /* hdlname = "mchip top addr4 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.dataSel.clock ;
  /* hdlname = "mchip top addr4 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.dataSel.reset ;
  /* hdlname = "mchip top addr4 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.letVal.clock ;
  /* hdlname = "mchip top addr4 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.letVal.en ;
  /* hdlname = "mchip top addr4 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.letVal.reset ;
  /* hdlname = "mchip top addr4 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.memSel_in ;
  /* hdlname = "mchip top addr4 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.out ;
  /* hdlname = "mchip top addr4 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr4.reset ;
  /* hdlname = "mchip top addr4 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:230.9-236.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr4.sel ;
  /* hdlname = "mchip top addr5 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr5.LUTConfig ;
  /* hdlname = "mchip top addr5 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.clock ;
  /* hdlname = "mchip top addr5 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr5.data.D ;
  /* hdlname = "mchip top addr5 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.data.clock ;
  /* hdlname = "mchip top addr5 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.data.reset ;
  /* hdlname = "mchip top addr5 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.dataSel.D ;
  /* hdlname = "mchip top addr5 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.dataSel.clock ;
  /* hdlname = "mchip top addr5 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.dataSel.reset ;
  /* hdlname = "mchip top addr5 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.letVal.clock ;
  /* hdlname = "mchip top addr5 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.letVal.en ;
  /* hdlname = "mchip top addr5 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.letVal.reset ;
  /* hdlname = "mchip top addr5 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.memSel_in ;
  /* hdlname = "mchip top addr5 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.out ;
  /* hdlname = "mchip top addr5 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr5.reset ;
  /* hdlname = "mchip top addr5 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:238.9-244.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr5.sel ;
  /* hdlname = "mchip top addr6 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr6.LUTConfig ;
  /* hdlname = "mchip top addr6 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.clock ;
  /* hdlname = "mchip top addr6 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr6.data.D ;
  /* hdlname = "mchip top addr6 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.data.clock ;
  /* hdlname = "mchip top addr6 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.data.reset ;
  /* hdlname = "mchip top addr6 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.dataSel.D ;
  /* hdlname = "mchip top addr6 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.dataSel.clock ;
  /* hdlname = "mchip top addr6 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.dataSel.reset ;
  /* hdlname = "mchip top addr6 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.letVal.clock ;
  /* hdlname = "mchip top addr6 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.letVal.en ;
  /* hdlname = "mchip top addr6 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.letVal.reset ;
  /* hdlname = "mchip top addr6 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.memSel_in ;
  /* hdlname = "mchip top addr6 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.out ;
  /* hdlname = "mchip top addr6 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr6.reset ;
  /* hdlname = "mchip top addr6 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:246.9-252.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr6.sel ;
  /* hdlname = "mchip top addr7 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr7.LUTConfig ;
  /* hdlname = "mchip top addr7 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.clock ;
  /* hdlname = "mchip top addr7 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr7.data.D ;
  /* hdlname = "mchip top addr7 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.data.clock ;
  /* hdlname = "mchip top addr7 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.data.reset ;
  /* hdlname = "mchip top addr7 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.dataSel.D ;
  /* hdlname = "mchip top addr7 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.dataSel.clock ;
  /* hdlname = "mchip top addr7 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.dataSel.reset ;
  /* hdlname = "mchip top addr7 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.letVal.clock ;
  /* hdlname = "mchip top addr7 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.letVal.en ;
  /* hdlname = "mchip top addr7 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.letVal.reset ;
  /* hdlname = "mchip top addr7 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.memSel_in ;
  /* hdlname = "mchip top addr7 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.out ;
  /* hdlname = "mchip top addr7 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr7.reset ;
  /* hdlname = "mchip top addr7 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:254.9-260.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr7.sel ;
  /* hdlname = "mchip top addr8 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr8.LUTConfig ;
  /* hdlname = "mchip top addr8 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.clock ;
  /* hdlname = "mchip top addr8 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr8.data.D ;
  /* hdlname = "mchip top addr8 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.data.clock ;
  /* hdlname = "mchip top addr8 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.data.reset ;
  /* hdlname = "mchip top addr8 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.dataSel.D ;
  /* hdlname = "mchip top addr8 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.dataSel.clock ;
  /* hdlname = "mchip top addr8 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.dataSel.reset ;
  /* hdlname = "mchip top addr8 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.letVal.clock ;
  /* hdlname = "mchip top addr8 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.letVal.en ;
  /* hdlname = "mchip top addr8 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.letVal.reset ;
  /* hdlname = "mchip top addr8 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.memSel_in ;
  /* hdlname = "mchip top addr8 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.out ;
  /* hdlname = "mchip top addr8 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr8.reset ;
  /* hdlname = "mchip top addr8 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:263.9-269.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr8.sel ;
  /* hdlname = "mchip top addr9 LUTConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:42.23-42.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr9.LUTConfig ;
  /* hdlname = "mchip top addr9 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:43.28-43.33|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.clock ;
  /* hdlname = "mchip top addr9 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.addr9.data.D ;
  /* hdlname = "mchip top addr9 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.data.clock ;
  /* hdlname = "mchip top addr9 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.data.reset ;
  /* hdlname = "mchip top addr9 dataSel D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.dataSel.D ;
  /* hdlname = "mchip top addr9 dataSel clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.dataSel.clock ;
  /* hdlname = "mchip top addr9 dataSel reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.dataSel.reset ;
  /* hdlname = "mchip top addr9 letVal clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.letVal.clock ;
  /* hdlname = "mchip top addr9 letVal en" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.31-5.33|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.letVal.en ;
  /* hdlname = "mchip top addr9 letVal reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.letVal.reset ;
  /* hdlname = "mchip top addr9 memSel_in" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:43.17-43.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.memSel_in ;
  /* hdlname = "mchip top addr9 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:44.18-44.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.out ;
  /* hdlname = "mchip top addr9 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:43.35-43.40|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.addr9.reset ;
  /* hdlname = "mchip top addr9 sel" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:271.9-277.32|d30_yuchingw_fpga/src/chip.sv:41.23-41.26|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.addr9.sel ;
  /* hdlname = "mchip top clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:122.24-122.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.clock ;
  /* hdlname = "mchip top inputSel0 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel0.clock ;
  /* hdlname = "mchip top inputSel0 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel0.regInput.D ;
  /* hdlname = "mchip top inputSel0 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel0.regInput.clock ;
  /* hdlname = "mchip top inputSel0 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel0.regInput.reset ;
  /* hdlname = "mchip top inputSel0 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel0.reset ;
  /* hdlname = "mchip top inputSel0 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:140.12-145.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel0.selConfig ;
  /* hdlname = "mchip top inputSel1 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel1.clock ;
  /* hdlname = "mchip top inputSel1 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel1.regInput.D ;
  /* hdlname = "mchip top inputSel1 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel1.regInput.clock ;
  /* hdlname = "mchip top inputSel1 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel1.regInput.reset ;
  /* hdlname = "mchip top inputSel1 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel1.reset ;
  /* hdlname = "mchip top inputSel1 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:147.12-152.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel1.selConfig ;
  /* hdlname = "mchip top inputSel2 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel2.clock ;
  /* hdlname = "mchip top inputSel2 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel2.regInput.D ;
  /* hdlname = "mchip top inputSel2 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel2.regInput.clock ;
  /* hdlname = "mchip top inputSel2 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel2.regInput.reset ;
  /* hdlname = "mchip top inputSel2 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel2.reset ;
  /* hdlname = "mchip top inputSel2 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:154.12-159.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel2.selConfig ;
  /* hdlname = "mchip top inputSel3 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel3.clock ;
  /* hdlname = "mchip top inputSel3 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel3.regInput.D ;
  /* hdlname = "mchip top inputSel3 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel3.regInput.clock ;
  /* hdlname = "mchip top inputSel3 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel3.regInput.reset ;
  /* hdlname = "mchip top inputSel3 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel3.reset ;
  /* hdlname = "mchip top inputSel3 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:161.12-166.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel3.selConfig ;
  /* hdlname = "mchip top inputSel4 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel4.clock ;
  /* hdlname = "mchip top inputSel4 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel4.regInput.D ;
  /* hdlname = "mchip top inputSel4 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel4.regInput.clock ;
  /* hdlname = "mchip top inputSel4 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel4.regInput.reset ;
  /* hdlname = "mchip top inputSel4 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel4.reset ;
  /* hdlname = "mchip top inputSel4 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:168.12-173.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel4.selConfig ;
  /* hdlname = "mchip top inputSel5 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel5.clock ;
  /* hdlname = "mchip top inputSel5 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel5.regInput.D ;
  /* hdlname = "mchip top inputSel5 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel5.regInput.clock ;
  /* hdlname = "mchip top inputSel5 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel5.regInput.reset ;
  /* hdlname = "mchip top inputSel5 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel5.reset ;
  /* hdlname = "mchip top inputSel5 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:175.12-180.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel5.selConfig ;
  /* hdlname = "mchip top inputSel6 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel6.clock ;
  /* hdlname = "mchip top inputSel6 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel6.regInput.D ;
  /* hdlname = "mchip top inputSel6 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel6.regInput.clock ;
  /* hdlname = "mchip top inputSel6 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel6.regInput.reset ;
  /* hdlname = "mchip top inputSel6 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel6.reset ;
  /* hdlname = "mchip top inputSel6 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:182.12-187.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel6.selConfig ;
  /* hdlname = "mchip top inputSel7 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:82.17-82.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel7.clock ;
  /* hdlname = "mchip top inputSel7 regInput D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel7.regInput.D ;
  /* hdlname = "mchip top inputSel7 regInput clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel7.regInput.clock ;
  /* hdlname = "mchip top inputSel7 regInput reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:87.19-87.87|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel7.regInput.reset ;
  /* hdlname = "mchip top inputSel7 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:82.24-82.29|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.inputSel7.reset ;
  /* hdlname = "mchip top inputSel7 selConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:189.12-194.40|d30_yuchingw_fpga/src/chip.sv:80.23-80.32|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.inputSel7.selConfig ;
  /* hdlname = "mchip top out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:126.24-126.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.out ;
  /* hdlname = "mchip top reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:122.17-122.22|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.reset ;
  /* hdlname = "mchip top setData" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:125.23-125.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [4:0] \mchip.top.setData ;
  /* hdlname = "mchip top switch16 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch16.clock ;
  /* hdlname = "mchip top switch16 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch16.data.D ;
  /* hdlname = "mchip top switch16 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch16.data.clock ;
  /* hdlname = "mchip top switch16 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch16.data.reset ;
  /* hdlname = "mchip top switch16 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch16.inputs ;
  /* hdlname = "mchip top switch16 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch16.out ;
  /* hdlname = "mchip top switch16 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch16.reset ;
  /* hdlname = "mchip top switch16 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:331.15-336.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch16.selectConfig ;
  /* hdlname = "mchip top switch17 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch17.clock ;
  /* hdlname = "mchip top switch17 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch17.data.D ;
  /* hdlname = "mchip top switch17 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch17.data.clock ;
  /* hdlname = "mchip top switch17 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch17.data.reset ;
  /* hdlname = "mchip top switch17 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch17.inputs ;
  /* hdlname = "mchip top switch17 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch17.out ;
  /* hdlname = "mchip top switch17 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch17.reset ;
  /* hdlname = "mchip top switch17 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:338.15-343.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch17.selectConfig ;
  /* hdlname = "mchip top switch18 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch18.clock ;
  /* hdlname = "mchip top switch18 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch18.data.D ;
  /* hdlname = "mchip top switch18 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch18.data.clock ;
  /* hdlname = "mchip top switch18 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch18.data.reset ;
  /* hdlname = "mchip top switch18 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch18.inputs ;
  /* hdlname = "mchip top switch18 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch18.out ;
  /* hdlname = "mchip top switch18 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch18.reset ;
  /* hdlname = "mchip top switch18 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:345.15-350.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch18.selectConfig ;
  /* hdlname = "mchip top switch19 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch19.clock ;
  /* hdlname = "mchip top switch19 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch19.data.D ;
  /* hdlname = "mchip top switch19 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch19.data.clock ;
  /* hdlname = "mchip top switch19 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch19.data.reset ;
  /* hdlname = "mchip top switch19 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch19.inputs ;
  /* hdlname = "mchip top switch19 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch19.out ;
  /* hdlname = "mchip top switch19 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch19.reset ;
  /* hdlname = "mchip top switch19 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:352.15-357.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch19.selectConfig ;
  /* hdlname = "mchip top switch20 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch20.clock ;
  /* hdlname = "mchip top switch20 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch20.data.D ;
  /* hdlname = "mchip top switch20 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch20.data.clock ;
  /* hdlname = "mchip top switch20 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch20.data.reset ;
  /* hdlname = "mchip top switch20 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch20.inputs ;
  /* hdlname = "mchip top switch20 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch20.out ;
  /* hdlname = "mchip top switch20 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch20.reset ;
  /* hdlname = "mchip top switch20 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:359.15-364.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch20.selectConfig ;
  /* hdlname = "mchip top switch21 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch21.clock ;
  /* hdlname = "mchip top switch21 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch21.data.D ;
  /* hdlname = "mchip top switch21 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch21.data.clock ;
  /* hdlname = "mchip top switch21 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch21.data.reset ;
  /* hdlname = "mchip top switch21 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch21.inputs ;
  /* hdlname = "mchip top switch21 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch21.out ;
  /* hdlname = "mchip top switch21 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch21.reset ;
  /* hdlname = "mchip top switch21 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:366.15-371.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch21.selectConfig ;
  /* hdlname = "mchip top switch22 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch22.clock ;
  /* hdlname = "mchip top switch22 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch22.data.D ;
  /* hdlname = "mchip top switch22 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch22.data.clock ;
  /* hdlname = "mchip top switch22 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch22.data.reset ;
  /* hdlname = "mchip top switch22 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch22.inputs ;
  /* hdlname = "mchip top switch22 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch22.out ;
  /* hdlname = "mchip top switch22 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch22.reset ;
  /* hdlname = "mchip top switch22 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:373.15-378.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch22.selectConfig ;
  /* hdlname = "mchip top switch23 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch23.clock ;
  /* hdlname = "mchip top switch23 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch23.data.D ;
  /* hdlname = "mchip top switch23 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch23.data.clock ;
  /* hdlname = "mchip top switch23 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch23.data.reset ;
  /* hdlname = "mchip top switch23 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch23.inputs ;
  /* hdlname = "mchip top switch23 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch23.out ;
  /* hdlname = "mchip top switch23 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch23.reset ;
  /* hdlname = "mchip top switch23 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:380.15-385.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch23.selectConfig ;
  /* hdlname = "mchip top switch24 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch24.clock ;
  /* hdlname = "mchip top switch24 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch24.data.D ;
  /* hdlname = "mchip top switch24 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch24.data.clock ;
  /* hdlname = "mchip top switch24 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch24.data.reset ;
  /* hdlname = "mchip top switch24 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch24.inputs ;
  /* hdlname = "mchip top switch24 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch24.out ;
  /* hdlname = "mchip top switch24 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch24.reset ;
  /* hdlname = "mchip top switch24 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:387.15-392.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch24.selectConfig ;
  /* hdlname = "mchip top switch25 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch25.clock ;
  /* hdlname = "mchip top switch25 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch25.data.D ;
  /* hdlname = "mchip top switch25 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch25.data.clock ;
  /* hdlname = "mchip top switch25 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch25.data.reset ;
  /* hdlname = "mchip top switch25 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch25.inputs ;
  /* hdlname = "mchip top switch25 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch25.out ;
  /* hdlname = "mchip top switch25 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch25.reset ;
  /* hdlname = "mchip top switch25 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:394.15-399.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch25.selectConfig ;
  /* hdlname = "mchip top switch26 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch26.clock ;
  /* hdlname = "mchip top switch26 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch26.data.D ;
  /* hdlname = "mchip top switch26 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch26.data.clock ;
  /* hdlname = "mchip top switch26 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch26.data.reset ;
  /* hdlname = "mchip top switch26 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch26.inputs ;
  /* hdlname = "mchip top switch26 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch26.out ;
  /* hdlname = "mchip top switch26 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch26.reset ;
  /* hdlname = "mchip top switch26 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:401.15-406.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch26.selectConfig ;
  /* hdlname = "mchip top switch27 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch27.clock ;
  /* hdlname = "mchip top switch27 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch27.data.D ;
  /* hdlname = "mchip top switch27 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch27.data.clock ;
  /* hdlname = "mchip top switch27 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch27.data.reset ;
  /* hdlname = "mchip top switch27 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch27.inputs ;
  /* hdlname = "mchip top switch27 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch27.out ;
  /* hdlname = "mchip top switch27 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch27.reset ;
  /* hdlname = "mchip top switch27 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:408.15-413.44|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch27.selectConfig ;
  /* hdlname = "mchip top switch28 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch28.clock ;
  /* hdlname = "mchip top switch28 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch28.data.D ;
  /* hdlname = "mchip top switch28 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch28.data.clock ;
  /* hdlname = "mchip top switch28 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch28.data.reset ;
  /* hdlname = "mchip top switch28 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch28.inputs ;
  /* hdlname = "mchip top switch28 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch28.out ;
  /* hdlname = "mchip top switch28 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch28.reset ;
  /* hdlname = "mchip top switch28 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:415.15-420.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch28.selectConfig ;
  /* hdlname = "mchip top switch29 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch29.clock ;
  /* hdlname = "mchip top switch29 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch29.data.D ;
  /* hdlname = "mchip top switch29 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch29.data.clock ;
  /* hdlname = "mchip top switch29 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch29.data.reset ;
  /* hdlname = "mchip top switch29 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch29.inputs ;
  /* hdlname = "mchip top switch29 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch29.out ;
  /* hdlname = "mchip top switch29 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch29.reset ;
  /* hdlname = "mchip top switch29 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:422.15-427.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch29.selectConfig ;
  /* hdlname = "mchip top switch30 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch30.clock ;
  /* hdlname = "mchip top switch30 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch30.data.D ;
  /* hdlname = "mchip top switch30 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch30.data.clock ;
  /* hdlname = "mchip top switch30 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch30.data.reset ;
  /* hdlname = "mchip top switch30 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch30.inputs ;
  /* hdlname = "mchip top switch30 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch30.out ;
  /* hdlname = "mchip top switch30 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch30.reset ;
  /* hdlname = "mchip top switch30 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:429.15-434.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch30.selectConfig ;
  /* hdlname = "mchip top switch31 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch31.clock ;
  /* hdlname = "mchip top switch31 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch31.data.D ;
  /* hdlname = "mchip top switch31 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch31.data.clock ;
  /* hdlname = "mchip top switch31 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch31.data.reset ;
  /* hdlname = "mchip top switch31 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch31.inputs ;
  /* hdlname = "mchip top switch31 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch31.out ;
  /* hdlname = "mchip top switch31 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch31.reset ;
  /* hdlname = "mchip top switch31 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:436.15-441.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch31.selectConfig ;
  /* hdlname = "mchip top switch32 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch32.clock ;
  /* hdlname = "mchip top switch32 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch32.data.D ;
  /* hdlname = "mchip top switch32 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch32.data.clock ;
  /* hdlname = "mchip top switch32 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch32.data.reset ;
  /* hdlname = "mchip top switch32 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch32.inputs ;
  /* hdlname = "mchip top switch32 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch32.out ;
  /* hdlname = "mchip top switch32 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch32.reset ;
  /* hdlname = "mchip top switch32 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:443.15-448.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch32.selectConfig ;
  /* hdlname = "mchip top switch33 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch33.clock ;
  /* hdlname = "mchip top switch33 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch33.data.D ;
  /* hdlname = "mchip top switch33 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch33.data.clock ;
  /* hdlname = "mchip top switch33 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch33.data.reset ;
  /* hdlname = "mchip top switch33 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch33.inputs ;
  /* hdlname = "mchip top switch33 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch33.out ;
  /* hdlname = "mchip top switch33 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch33.reset ;
  /* hdlname = "mchip top switch33 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:450.15-455.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch33.selectConfig ;
  /* hdlname = "mchip top switch34 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch34.clock ;
  /* hdlname = "mchip top switch34 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch34.data.D ;
  /* hdlname = "mchip top switch34 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch34.data.clock ;
  /* hdlname = "mchip top switch34 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch34.data.reset ;
  /* hdlname = "mchip top switch34 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch34.inputs ;
  /* hdlname = "mchip top switch34 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch34.out ;
  /* hdlname = "mchip top switch34 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch34.reset ;
  /* hdlname = "mchip top switch34 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:457.15-462.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch34.selectConfig ;
  /* hdlname = "mchip top switch35 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch35.clock ;
  /* hdlname = "mchip top switch35 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch35.data.D ;
  /* hdlname = "mchip top switch35 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch35.data.clock ;
  /* hdlname = "mchip top switch35 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch35.data.reset ;
  /* hdlname = "mchip top switch35 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch35.inputs ;
  /* hdlname = "mchip top switch35 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch35.out ;
  /* hdlname = "mchip top switch35 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch35.reset ;
  /* hdlname = "mchip top switch35 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:464.15-469.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch35.selectConfig ;
  /* hdlname = "mchip top switch36 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch36.clock ;
  /* hdlname = "mchip top switch36 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch36.data.D ;
  /* hdlname = "mchip top switch36 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch36.data.clock ;
  /* hdlname = "mchip top switch36 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch36.data.reset ;
  /* hdlname = "mchip top switch36 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch36.inputs ;
  /* hdlname = "mchip top switch36 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch36.out ;
  /* hdlname = "mchip top switch36 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch36.reset ;
  /* hdlname = "mchip top switch36 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:471.15-476.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch36.selectConfig ;
  /* hdlname = "mchip top switch37 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch37.clock ;
  /* hdlname = "mchip top switch37 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch37.data.D ;
  /* hdlname = "mchip top switch37 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch37.data.clock ;
  /* hdlname = "mchip top switch37 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch37.data.reset ;
  /* hdlname = "mchip top switch37 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch37.inputs ;
  /* hdlname = "mchip top switch37 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch37.out ;
  /* hdlname = "mchip top switch37 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch37.reset ;
  /* hdlname = "mchip top switch37 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:478.15-483.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch37.selectConfig ;
  /* hdlname = "mchip top switch38 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch38.clock ;
  /* hdlname = "mchip top switch38 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch38.data.D ;
  /* hdlname = "mchip top switch38 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch38.data.clock ;
  /* hdlname = "mchip top switch38 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch38.data.reset ;
  /* hdlname = "mchip top switch38 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch38.inputs ;
  /* hdlname = "mchip top switch38 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch38.out ;
  /* hdlname = "mchip top switch38 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch38.reset ;
  /* hdlname = "mchip top switch38 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:485.15-490.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch38.selectConfig ;
  /* hdlname = "mchip top switch39 clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:65.22-65.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch39.clock ;
  /* hdlname = "mchip top switch39 data D" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:6.25-6.26|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch39.data.D ;
  /* hdlname = "mchip top switch39 data clock" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:5.24-5.29|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch39.data.clock ;
  /* hdlname = "mchip top switch39 data reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:5.17-5.22|d30_yuchingw_fpga/src/chip.sv:71.19-71.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch39.data.reset ;
  /* hdlname = "mchip top switch39 inputs" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:64.24-64.30|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [11:0] \mchip.top.switch39.inputs ;
  /* hdlname = "mchip top switch39 out" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:67.18-67.21|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch39.out ;
  /* hdlname = "mchip top switch39 reset" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:65.29-65.34|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire \mchip.top.switch39.reset ;
  /* hdlname = "mchip top switch39 selectConfig" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:492.15-497.45|d30_yuchingw_fpga/src/chip.sv:66.23-66.35|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [3:0] \mchip.top.switch39.selectConfig ;
  /* hdlname = "mchip top switchOut10" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.53-133.64|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut10 ;
  /* hdlname = "mchip top switchOut11" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.66-133.77|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut11 ;
  /* hdlname = "mchip top switchOut12" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.79-133.90|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut12 ;
  /* hdlname = "mchip top switchOut13" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.92-133.103|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut13 ;
  /* hdlname = "mchip top switchOut14" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:134.17-134.28|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut14 ;
  /* hdlname = "mchip top switchOut15" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:134.30-134.41|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut15 ;
  /* hdlname = "mchip top switchOut4" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:132.17-132.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut4 ;
  /* hdlname = "mchip top switchOut5" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:132.29-132.39|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut5 ;
  /* hdlname = "mchip top switchOut6" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:132.41-132.51|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut6 ;
  /* hdlname = "mchip top switchOut7" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.17-133.27|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut7 ;
  /* hdlname = "mchip top switchOut8" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.29-133.39|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut8 ;
  /* hdlname = "mchip top switchOut9" */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:133.41-133.51|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  wire [1:0] \mchip.top.switchOut9 ;
  assign _04_ = io_in[11] | ~(io_in[0]);
  assign _05_ = io_in[10] | ~(io_in[0]);
  assign _06_ = _05_ | _04_;
  assign _07_ = io_in[0] & ~(io_in[9]);
  assign _08_ = io_in[0] & ~(io_in[8]);
  assign _09_ = _08_ | _07_;
  assign _10_ = io_in[7] | ~(io_in[0]);
  assign _11_ = io_in[6] | ~(io_in[0]);
  assign _12_ = _11_ | _10_;
  assign _13_ = _12_ | _09_;
  assign _00_ = _13_ | _06_;
  assign _14_ = io_in[0] & ~(io_in[6]);
  assign _15_ = _14_ | _10_;
  assign _16_ = _15_ | _09_;
  assign _01_ = _16_ | _06_;
  assign _17_ = io_in[0] & ~(io_in[7]);
  assign _18_ = _11_ | _17_;
  assign _19_ = _18_ | _09_;
  assign _02_ = _19_ | _06_;
  assign _20_ = _14_ | _17_;
  assign _21_ = _20_ | _09_;
  assign _03_ = _21_ | _06_;
  assign \mchip.top.addr12.out  = \mchip.top.addr12.dataSel.Q  ? \mchip.top.addr12.letVal.Q  : \mchip.top.addr12.data.Q [0];
  assign \mchip.top.addr13.out  = \mchip.top.addr13.dataSel.Q  ? \mchip.top.addr13.letVal.Q  : \mchip.top.addr13.data.Q [0];
  assign \mchip.top.addr14.out  = \mchip.top.addr14.dataSel.Q  ? \mchip.top.addr14.letVal.Q  : \mchip.top.addr14.data.Q [0];
  assign \mchip.top.addr15.out  = \mchip.top.addr15.dataSel.Q  ? \mchip.top.addr15.letVal.Q  : \mchip.top.addr15.data.Q [0];
  assign \mchip.setData [0] = io_in[1] & io_in[0];
  assign \mchip.top.addr0.dataSel.D  = io_in[5] & io_in[0];
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr15.letVal.Q  <= 1'h0;
    else \mchip.top.addr15.letVal.Q  <= \mchip.top.addr15.data.Q [0];
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr12.dataSel.Q  <= 1'h0;
    else if (!_00_) \mchip.top.addr12.dataSel.Q  <= \mchip.top.addr0.dataSel.D ;
  reg \mchip.top.addr12.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr12.data.Q_reg[0]  <= 1'h0;
    else if (!_00_) \mchip.top.addr12.data.Q_reg[0]  <= \mchip.setData [0];
  assign \mchip.top.addr12.data.Q [0] = \mchip.top.addr12.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr13.dataSel.Q  <= 1'h0;
    else if (!_01_) \mchip.top.addr13.dataSel.Q  <= \mchip.top.addr0.dataSel.D ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:296.9-302.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr12.letVal.Q  <= 1'h0;
    else \mchip.top.addr12.letVal.Q  <= \mchip.top.addr12.data.Q [0];
  reg \mchip.top.addr13.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr13.data.Q_reg[0]  <= 1'h0;
    else if (!_01_) \mchip.top.addr13.data.Q_reg[0]  <= \mchip.setData [0];
  assign \mchip.top.addr13.data.Q [0] = \mchip.top.addr13.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr14.dataSel.Q  <= 1'h0;
    else if (!_02_) \mchip.top.addr14.dataSel.Q  <= \mchip.top.addr0.dataSel.D ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:304.9-310.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr13.letVal.Q  <= 1'h0;
    else \mchip.top.addr13.letVal.Q  <= \mchip.top.addr13.data.Q [0];
  reg \mchip.top.addr14.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr14.data.Q_reg[0]  <= 1'h0;
    else if (!_02_) \mchip.top.addr14.data.Q_reg[0]  <= \mchip.setData [0];
  assign \mchip.top.addr14.data.Q [0] = \mchip.top.addr14.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:56.19-56.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr15.dataSel.Q  <= 1'h0;
    else if (!_03_) \mchip.top.addr15.dataSel.Q  <= \mchip.top.addr0.dataSel.D ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:312.9-318.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:53.19-53.84|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr14.letVal.Q  <= 1'h0;
    else \mchip.top.addr14.letVal.Q  <= \mchip.top.addr14.data.Q [0];
  reg \mchip.top.addr15.data.Q_reg[0] ;
  /* \always_ff  = 32'd1 */
  /* src = "d30_yuchingw_fpga/src/toplevel_chip.v:9.13-14.6|d30_yuchingw_fpga/src/chip.sv:320.9-326.33|d30_yuchingw_fpga/src/chip.sv:9.5-17.8|d30_yuchingw_fpga/src/chip.sv:50.19-50.78|d30_yuchingw_fpga/src/chip.sv:117.10-117.80" */
  always @(posedge io_in[12])
    if (io_in[13]) \mchip.top.addr15.data.Q_reg[0]  <= 1'h0;
    else if (!_03_) \mchip.top.addr15.data.Q_reg[0]  <= \mchip.setData [0];
  assign \mchip.top.addr15.data.Q [0] = \mchip.top.addr15.data.Q_reg[0] ;
  assign io_out = { 10'h000, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out  };
  assign \mchip.clock  = io_in[12];
  assign \mchip.io_in  = io_in[11:0];
  assign \mchip.io_out  = { 8'h00, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out  };
  assign \mchip.reset  = io_in[13];
  assign \mchip.setData [4:1] = { \mchip.top.addr0.dataSel.D , 3'h0 };
  assign \mchip.top.CLBOut  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 12'h000 };
  assign \mchip.top.addr0.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr0.clock  = io_in[12];
  assign \mchip.top.addr0.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr0.data.clock  = io_in[12];
  assign \mchip.top.addr0.data.reset  = io_in[13];
  assign \mchip.top.addr0.dataSel.clock  = io_in[12];
  assign \mchip.top.addr0.dataSel.reset  = io_in[13];
  assign \mchip.top.addr0.letVal.clock  = io_in[12];
  assign \mchip.top.addr0.letVal.en  = 1'h1;
  assign \mchip.top.addr0.letVal.reset  = io_in[13];
  assign \mchip.top.addr0.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr0.out  = 1'h0;
  assign \mchip.top.addr0.reset  = io_in[13];
  assign \mchip.top.addr1.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr1.clock  = io_in[12];
  assign \mchip.top.addr1.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr1.data.clock  = io_in[12];
  assign \mchip.top.addr1.data.reset  = io_in[13];
  assign \mchip.top.addr1.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr1.dataSel.clock  = io_in[12];
  assign \mchip.top.addr1.dataSel.reset  = io_in[13];
  assign \mchip.top.addr1.letVal.clock  = io_in[12];
  assign \mchip.top.addr1.letVal.en  = 1'h1;
  assign \mchip.top.addr1.letVal.reset  = io_in[13];
  assign \mchip.top.addr1.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr1.out  = 1'h0;
  assign \mchip.top.addr1.reset  = io_in[13];
  assign \mchip.top.addr10.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr10.clock  = io_in[12];
  assign \mchip.top.addr10.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr10.data.clock  = io_in[12];
  assign \mchip.top.addr10.data.reset  = io_in[13];
  assign \mchip.top.addr10.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr10.dataSel.clock  = io_in[12];
  assign \mchip.top.addr10.dataSel.reset  = io_in[13];
  assign \mchip.top.addr10.letVal.clock  = io_in[12];
  assign \mchip.top.addr10.letVal.en  = 1'h1;
  assign \mchip.top.addr10.letVal.reset  = io_in[13];
  assign \mchip.top.addr10.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr10.out  = 1'h0;
  assign \mchip.top.addr10.reset  = io_in[13];
  assign \mchip.top.addr10.sel  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.addr11.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr11.clock  = io_in[12];
  assign \mchip.top.addr11.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr11.data.clock  = io_in[12];
  assign \mchip.top.addr11.data.reset  = io_in[13];
  assign \mchip.top.addr11.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr11.dataSel.clock  = io_in[12];
  assign \mchip.top.addr11.dataSel.reset  = io_in[13];
  assign \mchip.top.addr11.letVal.clock  = io_in[12];
  assign \mchip.top.addr11.letVal.en  = 1'h1;
  assign \mchip.top.addr11.letVal.reset  = io_in[13];
  assign \mchip.top.addr11.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr11.out  = 1'h0;
  assign \mchip.top.addr11.reset  = io_in[13];
  assign \mchip.top.addr11.sel  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.addr12.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr12.LUTData  = { 3'h0, \mchip.top.addr12.data.Q [0] };
  assign \mchip.top.addr12.clock  = io_in[12];
  assign \mchip.top.addr12.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr12.data.Q [3:1] = 3'h0;
  assign \mchip.top.addr12.data.clock  = io_in[12];
  assign \mchip.top.addr12.data.reset  = io_in[13];
  assign \mchip.top.addr12.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr12.dataSel.clock  = io_in[12];
  assign \mchip.top.addr12.dataSel.reset  = io_in[13];
  assign \mchip.top.addr12.letVal.D  = \mchip.top.addr12.data.Q [0];
  assign \mchip.top.addr12.letVal.clock  = io_in[12];
  assign \mchip.top.addr12.letVal.en  = 1'h1;
  assign \mchip.top.addr12.letVal.reset  = io_in[13];
  assign \mchip.top.addr12.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr12.memSel_mem  = \mchip.top.addr12.dataSel.Q ;
  assign \mchip.top.addr12.regData  = \mchip.top.addr12.letVal.Q ;
  assign \mchip.top.addr12.reset  = io_in[13];
  assign \mchip.top.addr12.sel  = 2'h0;
  assign \mchip.top.addr13.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr13.LUTData  = { 3'h0, \mchip.top.addr13.data.Q [0] };
  assign \mchip.top.addr13.clock  = io_in[12];
  assign \mchip.top.addr13.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr13.data.Q [3:1] = 3'h0;
  assign \mchip.top.addr13.data.clock  = io_in[12];
  assign \mchip.top.addr13.data.reset  = io_in[13];
  assign \mchip.top.addr13.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr13.dataSel.clock  = io_in[12];
  assign \mchip.top.addr13.dataSel.reset  = io_in[13];
  assign \mchip.top.addr13.letVal.D  = \mchip.top.addr13.data.Q [0];
  assign \mchip.top.addr13.letVal.clock  = io_in[12];
  assign \mchip.top.addr13.letVal.en  = 1'h1;
  assign \mchip.top.addr13.letVal.reset  = io_in[13];
  assign \mchip.top.addr13.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr13.memSel_mem  = \mchip.top.addr13.dataSel.Q ;
  assign \mchip.top.addr13.regData  = \mchip.top.addr13.letVal.Q ;
  assign \mchip.top.addr13.reset  = io_in[13];
  assign \mchip.top.addr13.sel  = 2'h0;
  assign \mchip.top.addr14.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr14.LUTData  = { 3'h0, \mchip.top.addr14.data.Q [0] };
  assign \mchip.top.addr14.clock  = io_in[12];
  assign \mchip.top.addr14.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr14.data.Q [3:1] = 3'h0;
  assign \mchip.top.addr14.data.clock  = io_in[12];
  assign \mchip.top.addr14.data.reset  = io_in[13];
  assign \mchip.top.addr14.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr14.dataSel.clock  = io_in[12];
  assign \mchip.top.addr14.dataSel.reset  = io_in[13];
  assign \mchip.top.addr14.letVal.D  = \mchip.top.addr14.data.Q [0];
  assign \mchip.top.addr14.letVal.clock  = io_in[12];
  assign \mchip.top.addr14.letVal.en  = 1'h1;
  assign \mchip.top.addr14.letVal.reset  = io_in[13];
  assign \mchip.top.addr14.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr14.memSel_mem  = \mchip.top.addr14.dataSel.Q ;
  assign \mchip.top.addr14.regData  = \mchip.top.addr14.letVal.Q ;
  assign \mchip.top.addr14.reset  = io_in[13];
  assign \mchip.top.addr14.sel  = 2'h0;
  assign \mchip.top.addr15.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr15.LUTData  = { 3'h0, \mchip.top.addr15.data.Q [0] };
  assign \mchip.top.addr15.clock  = io_in[12];
  assign \mchip.top.addr15.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr15.data.Q [3:1] = 3'h0;
  assign \mchip.top.addr15.data.clock  = io_in[12];
  assign \mchip.top.addr15.data.reset  = io_in[13];
  assign \mchip.top.addr15.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr15.dataSel.clock  = io_in[12];
  assign \mchip.top.addr15.dataSel.reset  = io_in[13];
  assign \mchip.top.addr15.letVal.D  = \mchip.top.addr15.data.Q [0];
  assign \mchip.top.addr15.letVal.clock  = io_in[12];
  assign \mchip.top.addr15.letVal.en  = 1'h1;
  assign \mchip.top.addr15.letVal.reset  = io_in[13];
  assign \mchip.top.addr15.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr15.memSel_mem  = \mchip.top.addr15.dataSel.Q ;
  assign \mchip.top.addr15.regData  = \mchip.top.addr15.letVal.Q ;
  assign \mchip.top.addr15.reset  = io_in[13];
  assign \mchip.top.addr15.sel  = 2'h0;
  assign \mchip.top.addr2.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr2.clock  = io_in[12];
  assign \mchip.top.addr2.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr2.data.clock  = io_in[12];
  assign \mchip.top.addr2.data.reset  = io_in[13];
  assign \mchip.top.addr2.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr2.dataSel.clock  = io_in[12];
  assign \mchip.top.addr2.dataSel.reset  = io_in[13];
  assign \mchip.top.addr2.letVal.clock  = io_in[12];
  assign \mchip.top.addr2.letVal.en  = 1'h1;
  assign \mchip.top.addr2.letVal.reset  = io_in[13];
  assign \mchip.top.addr2.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr2.out  = 1'h0;
  assign \mchip.top.addr2.reset  = io_in[13];
  assign \mchip.top.addr3.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr3.clock  = io_in[12];
  assign \mchip.top.addr3.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr3.data.clock  = io_in[12];
  assign \mchip.top.addr3.data.reset  = io_in[13];
  assign \mchip.top.addr3.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr3.dataSel.clock  = io_in[12];
  assign \mchip.top.addr3.dataSel.reset  = io_in[13];
  assign \mchip.top.addr3.letVal.clock  = io_in[12];
  assign \mchip.top.addr3.letVal.en  = 1'h1;
  assign \mchip.top.addr3.letVal.reset  = io_in[13];
  assign \mchip.top.addr3.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr3.out  = 1'h0;
  assign \mchip.top.addr3.reset  = io_in[13];
  assign \mchip.top.addr4.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr4.clock  = io_in[12];
  assign \mchip.top.addr4.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr4.data.clock  = io_in[12];
  assign \mchip.top.addr4.data.reset  = io_in[13];
  assign \mchip.top.addr4.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr4.dataSel.clock  = io_in[12];
  assign \mchip.top.addr4.dataSel.reset  = io_in[13];
  assign \mchip.top.addr4.letVal.clock  = io_in[12];
  assign \mchip.top.addr4.letVal.en  = 1'h1;
  assign \mchip.top.addr4.letVal.reset  = io_in[13];
  assign \mchip.top.addr4.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr4.out  = 1'h0;
  assign \mchip.top.addr4.reset  = io_in[13];
  assign \mchip.top.addr4.sel  = 2'h0;
  assign \mchip.top.addr5.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr5.clock  = io_in[12];
  assign \mchip.top.addr5.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr5.data.clock  = io_in[12];
  assign \mchip.top.addr5.data.reset  = io_in[13];
  assign \mchip.top.addr5.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr5.dataSel.clock  = io_in[12];
  assign \mchip.top.addr5.dataSel.reset  = io_in[13];
  assign \mchip.top.addr5.letVal.clock  = io_in[12];
  assign \mchip.top.addr5.letVal.en  = 1'h1;
  assign \mchip.top.addr5.letVal.reset  = io_in[13];
  assign \mchip.top.addr5.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr5.out  = 1'h0;
  assign \mchip.top.addr5.reset  = io_in[13];
  assign \mchip.top.addr5.sel  = 2'h0;
  assign \mchip.top.addr6.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr6.clock  = io_in[12];
  assign \mchip.top.addr6.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr6.data.clock  = io_in[12];
  assign \mchip.top.addr6.data.reset  = io_in[13];
  assign \mchip.top.addr6.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr6.dataSel.clock  = io_in[12];
  assign \mchip.top.addr6.dataSel.reset  = io_in[13];
  assign \mchip.top.addr6.letVal.clock  = io_in[12];
  assign \mchip.top.addr6.letVal.en  = 1'h1;
  assign \mchip.top.addr6.letVal.reset  = io_in[13];
  assign \mchip.top.addr6.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr6.out  = 1'h0;
  assign \mchip.top.addr6.reset  = io_in[13];
  assign \mchip.top.addr6.sel  = 2'h0;
  assign \mchip.top.addr7.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr7.clock  = io_in[12];
  assign \mchip.top.addr7.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr7.data.clock  = io_in[12];
  assign \mchip.top.addr7.data.reset  = io_in[13];
  assign \mchip.top.addr7.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr7.dataSel.clock  = io_in[12];
  assign \mchip.top.addr7.dataSel.reset  = io_in[13];
  assign \mchip.top.addr7.letVal.clock  = io_in[12];
  assign \mchip.top.addr7.letVal.en  = 1'h1;
  assign \mchip.top.addr7.letVal.reset  = io_in[13];
  assign \mchip.top.addr7.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr7.out  = 1'h0;
  assign \mchip.top.addr7.reset  = io_in[13];
  assign \mchip.top.addr7.sel  = 2'h0;
  assign \mchip.top.addr8.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr8.clock  = io_in[12];
  assign \mchip.top.addr8.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr8.data.clock  = io_in[12];
  assign \mchip.top.addr8.data.reset  = io_in[13];
  assign \mchip.top.addr8.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr8.dataSel.clock  = io_in[12];
  assign \mchip.top.addr8.dataSel.reset  = io_in[13];
  assign \mchip.top.addr8.letVal.clock  = io_in[12];
  assign \mchip.top.addr8.letVal.en  = 1'h1;
  assign \mchip.top.addr8.letVal.reset  = io_in[13];
  assign \mchip.top.addr8.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr8.out  = 1'h0;
  assign \mchip.top.addr8.reset  = io_in[13];
  assign \mchip.top.addr8.sel  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.addr9.LUTConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr9.clock  = io_in[12];
  assign \mchip.top.addr9.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.addr9.data.clock  = io_in[12];
  assign \mchip.top.addr9.data.reset  = io_in[13];
  assign \mchip.top.addr9.dataSel.D  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr9.dataSel.clock  = io_in[12];
  assign \mchip.top.addr9.dataSel.reset  = io_in[13];
  assign \mchip.top.addr9.letVal.clock  = io_in[12];
  assign \mchip.top.addr9.letVal.en  = 1'h1;
  assign \mchip.top.addr9.letVal.reset  = io_in[13];
  assign \mchip.top.addr9.memSel_in  = \mchip.top.addr0.dataSel.D ;
  assign \mchip.top.addr9.out  = 1'h0;
  assign \mchip.top.addr9.reset  = io_in[13];
  assign \mchip.top.addr9.sel  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.clock  = io_in[12];
  assign \mchip.top.inputSel0.clock  = io_in[12];
  assign \mchip.top.inputSel0.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel0.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel0.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel0.reset  = io_in[13];
  assign \mchip.top.inputSel0.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel1.clock  = io_in[12];
  assign \mchip.top.inputSel1.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel1.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel1.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel1.reset  = io_in[13];
  assign \mchip.top.inputSel1.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel2.clock  = io_in[12];
  assign \mchip.top.inputSel2.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel2.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel2.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel2.reset  = io_in[13];
  assign \mchip.top.inputSel2.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel3.clock  = io_in[12];
  assign \mchip.top.inputSel3.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel3.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel3.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel3.reset  = io_in[13];
  assign \mchip.top.inputSel3.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel4.clock  = io_in[12];
  assign \mchip.top.inputSel4.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel4.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel4.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel4.reset  = io_in[13];
  assign \mchip.top.inputSel4.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel5.clock  = io_in[12];
  assign \mchip.top.inputSel5.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel5.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel5.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel5.reset  = io_in[13];
  assign \mchip.top.inputSel5.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel6.clock  = io_in[12];
  assign \mchip.top.inputSel6.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel6.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel6.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel6.reset  = io_in[13];
  assign \mchip.top.inputSel6.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel7.clock  = io_in[12];
  assign \mchip.top.inputSel7.regInput.D  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.inputSel7.regInput.clock  = io_in[12];
  assign \mchip.top.inputSel7.regInput.reset  = io_in[13];
  assign \mchip.top.inputSel7.reset  = io_in[13];
  assign \mchip.top.inputSel7.selConfig  = { 1'h0, \mchip.setData [0] };
  assign \mchip.top.out  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out  };
  assign \mchip.top.reset  = io_in[13];
  assign \mchip.top.setData  = { \mchip.top.addr0.dataSel.D , 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch16.clock  = io_in[12];
  assign \mchip.top.switch16.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch16.data.clock  = io_in[12];
  assign \mchip.top.switch16.data.reset  = io_in[13];
  assign \mchip.top.switch16.inputs  = 12'h000;
  assign \mchip.top.switch16.out  = 1'h0;
  assign \mchip.top.switch16.reset  = io_in[13];
  assign \mchip.top.switch16.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch17.clock  = io_in[12];
  assign \mchip.top.switch17.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch17.data.clock  = io_in[12];
  assign \mchip.top.switch17.data.reset  = io_in[13];
  assign \mchip.top.switch17.inputs  = 12'h000;
  assign \mchip.top.switch17.out  = 1'h0;
  assign \mchip.top.switch17.reset  = io_in[13];
  assign \mchip.top.switch17.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch18.clock  = io_in[12];
  assign \mchip.top.switch18.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch18.data.clock  = io_in[12];
  assign \mchip.top.switch18.data.reset  = io_in[13];
  assign \mchip.top.switch18.inputs  = 12'h000;
  assign \mchip.top.switch18.out  = 1'h0;
  assign \mchip.top.switch18.reset  = io_in[13];
  assign \mchip.top.switch18.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch19.clock  = io_in[12];
  assign \mchip.top.switch19.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch19.data.clock  = io_in[12];
  assign \mchip.top.switch19.data.reset  = io_in[13];
  assign \mchip.top.switch19.inputs  = 12'h000;
  assign \mchip.top.switch19.out  = 1'h0;
  assign \mchip.top.switch19.reset  = io_in[13];
  assign \mchip.top.switch19.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch20.clock  = io_in[12];
  assign \mchip.top.switch20.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch20.data.clock  = io_in[12];
  assign \mchip.top.switch20.data.reset  = io_in[13];
  assign \mchip.top.switch20.inputs  = 12'h000;
  assign \mchip.top.switch20.out  = 1'h0;
  assign \mchip.top.switch20.reset  = io_in[13];
  assign \mchip.top.switch20.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch21.clock  = io_in[12];
  assign \mchip.top.switch21.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch21.data.clock  = io_in[12];
  assign \mchip.top.switch21.data.reset  = io_in[13];
  assign \mchip.top.switch21.inputs  = 12'h000;
  assign \mchip.top.switch21.out  = 1'h0;
  assign \mchip.top.switch21.reset  = io_in[13];
  assign \mchip.top.switch21.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch22.clock  = io_in[12];
  assign \mchip.top.switch22.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch22.data.clock  = io_in[12];
  assign \mchip.top.switch22.data.reset  = io_in[13];
  assign \mchip.top.switch22.inputs  = 12'h000;
  assign \mchip.top.switch22.out  = 1'h0;
  assign \mchip.top.switch22.reset  = io_in[13];
  assign \mchip.top.switch22.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch23.clock  = io_in[12];
  assign \mchip.top.switch23.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch23.data.clock  = io_in[12];
  assign \mchip.top.switch23.data.reset  = io_in[13];
  assign \mchip.top.switch23.inputs  = 12'h000;
  assign \mchip.top.switch23.out  = 1'h0;
  assign \mchip.top.switch23.reset  = io_in[13];
  assign \mchip.top.switch23.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch24.clock  = io_in[12];
  assign \mchip.top.switch24.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch24.data.clock  = io_in[12];
  assign \mchip.top.switch24.data.reset  = io_in[13];
  assign \mchip.top.switch24.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch24.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch24.reset  = io_in[13];
  assign \mchip.top.switch24.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch25.clock  = io_in[12];
  assign \mchip.top.switch25.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch25.data.clock  = io_in[12];
  assign \mchip.top.switch25.data.reset  = io_in[13];
  assign \mchip.top.switch25.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch25.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch25.reset  = io_in[13];
  assign \mchip.top.switch25.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch26.clock  = io_in[12];
  assign \mchip.top.switch26.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch26.data.clock  = io_in[12];
  assign \mchip.top.switch26.data.reset  = io_in[13];
  assign \mchip.top.switch26.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch26.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch26.reset  = io_in[13];
  assign \mchip.top.switch26.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch27.clock  = io_in[12];
  assign \mchip.top.switch27.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch27.data.clock  = io_in[12];
  assign \mchip.top.switch27.data.reset  = io_in[13];
  assign \mchip.top.switch27.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch27.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch27.reset  = io_in[13];
  assign \mchip.top.switch27.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch28.clock  = io_in[12];
  assign \mchip.top.switch28.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch28.data.clock  = io_in[12];
  assign \mchip.top.switch28.data.reset  = io_in[13];
  assign \mchip.top.switch28.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch28.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch28.reset  = io_in[13];
  assign \mchip.top.switch28.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch29.clock  = io_in[12];
  assign \mchip.top.switch29.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch29.data.clock  = io_in[12];
  assign \mchip.top.switch29.data.reset  = io_in[13];
  assign \mchip.top.switch29.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch29.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch29.reset  = io_in[13];
  assign \mchip.top.switch29.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch30.clock  = io_in[12];
  assign \mchip.top.switch30.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch30.data.clock  = io_in[12];
  assign \mchip.top.switch30.data.reset  = io_in[13];
  assign \mchip.top.switch30.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch30.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch30.reset  = io_in[13];
  assign \mchip.top.switch30.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch31.clock  = io_in[12];
  assign \mchip.top.switch31.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch31.data.clock  = io_in[12];
  assign \mchip.top.switch31.data.reset  = io_in[13];
  assign \mchip.top.switch31.inputs  = { \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 8'h00 };
  assign \mchip.top.switch31.out  = \mchip.top.addr12.out ;
  assign \mchip.top.switch31.reset  = io_in[13];
  assign \mchip.top.switch31.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch32.clock  = io_in[12];
  assign \mchip.top.switch32.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch32.data.clock  = io_in[12];
  assign \mchip.top.switch32.data.reset  = io_in[13];
  assign \mchip.top.switch32.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch32.out  = 1'h0;
  assign \mchip.top.switch32.reset  = io_in[13];
  assign \mchip.top.switch32.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch33.clock  = io_in[12];
  assign \mchip.top.switch33.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch33.data.clock  = io_in[12];
  assign \mchip.top.switch33.data.reset  = io_in[13];
  assign \mchip.top.switch33.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch33.out  = 1'h0;
  assign \mchip.top.switch33.reset  = io_in[13];
  assign \mchip.top.switch33.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch34.clock  = io_in[12];
  assign \mchip.top.switch34.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch34.data.clock  = io_in[12];
  assign \mchip.top.switch34.data.reset  = io_in[13];
  assign \mchip.top.switch34.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch34.out  = 1'h0;
  assign \mchip.top.switch34.reset  = io_in[13];
  assign \mchip.top.switch34.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch35.clock  = io_in[12];
  assign \mchip.top.switch35.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch35.data.clock  = io_in[12];
  assign \mchip.top.switch35.data.reset  = io_in[13];
  assign \mchip.top.switch35.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch35.out  = 1'h0;
  assign \mchip.top.switch35.reset  = io_in[13];
  assign \mchip.top.switch35.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch36.clock  = io_in[12];
  assign \mchip.top.switch36.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch36.data.clock  = io_in[12];
  assign \mchip.top.switch36.data.reset  = io_in[13];
  assign \mchip.top.switch36.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch36.out  = 1'h0;
  assign \mchip.top.switch36.reset  = io_in[13];
  assign \mchip.top.switch36.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch37.clock  = io_in[12];
  assign \mchip.top.switch37.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch37.data.clock  = io_in[12];
  assign \mchip.top.switch37.data.reset  = io_in[13];
  assign \mchip.top.switch37.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch37.out  = 1'h0;
  assign \mchip.top.switch37.reset  = io_in[13];
  assign \mchip.top.switch37.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch38.clock  = io_in[12];
  assign \mchip.top.switch38.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch38.data.clock  = io_in[12];
  assign \mchip.top.switch38.data.reset  = io_in[13];
  assign \mchip.top.switch38.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch38.out  = 1'h0;
  assign \mchip.top.switch38.reset  = io_in[13];
  assign \mchip.top.switch38.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch39.clock  = io_in[12];
  assign \mchip.top.switch39.data.D  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switch39.data.clock  = io_in[12];
  assign \mchip.top.switch39.data.reset  = io_in[13];
  assign \mchip.top.switch39.inputs  = { 4'h0, \mchip.top.addr15.out , \mchip.top.addr14.out , \mchip.top.addr13.out , \mchip.top.addr12.out , 4'h0 };
  assign \mchip.top.switch39.out  = 1'h0;
  assign \mchip.top.switch39.reset  = io_in[13];
  assign \mchip.top.switch39.selectConfig  = { 3'h0, \mchip.setData [0] };
  assign \mchip.top.switchOut10  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.switchOut11  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.switchOut12  = 2'h0;
  assign \mchip.top.switchOut13  = 2'h0;
  assign \mchip.top.switchOut14  = 2'h0;
  assign \mchip.top.switchOut15  = 2'h0;
  assign \mchip.top.switchOut4  = 2'h0;
  assign \mchip.top.switchOut5  = 2'h0;
  assign \mchip.top.switchOut6  = 2'h0;
  assign \mchip.top.switchOut7  = 2'h0;
  assign \mchip.top.switchOut8  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
  assign \mchip.top.switchOut9  = { \mchip.top.addr12.out , \mchip.top.addr12.out  };
endmodule