Removed unnecessary PLL2 clock setting as PLL2 is no longer being used

Bexin3 · web-flow · commit 1605162c8319 · 2024-11-10T15:32:31.000Z
diff --git a/libraries/Portenta_SDRAM/src/ram_internal.c b/libraries/Portenta_SDRAM/src/ram_internal.c
@@ -39,7 +39,6 @@ static HAL_StatusTypeDef FMC_SDRAM_Clock_Config(void)
   
   RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
   RCC_PeriphCLKInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_HCLK;
-  RCC_PeriphCLKInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
   return HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
 }
 

Original file line number	Diff line number	Diff line change
`@@ -39,7 +39,6 @@ static HAL_StatusTypeDef FMC_SDRAM_Clock_Config(void)`
`39`	`39`
`40`	`40`	`RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;`
`41`	`41`	`RCC_PeriphCLKInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_HCLK;`
`42`		`- RCC_PeriphCLKInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;`
`43`	`42`	`return HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);`
`44`	`43`	`}`
`45`	`44`