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exec.c
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/*
* virtual page mapping and translated block handling
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "infrastructure.h"
#ifdef _WIN32
#include <windows.h>
#else
#include <unistd.h>
#endif
#include "bit_helper.h"
#include "cpu.h"
#include "tcg.h"
#include "osdep.h"
#include "tlib-alloc.h"
#define SMC_BITMAP_USE_THRESHOLD 10
CPUState *env;
extern void *global_retaddr;
static TranslationBlock *tbs;
static int code_gen_max_blocks;
TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
static int nb_tbs;
/* any access to the tbs or the page table must use this lock */
extern uint64_t code_gen_buffer_size;
/* threshold to flush the translated code buffer */
static uint64_t code_gen_buffer_max_size;
static uint8_t *code_gen_ptr;
CPUState *cpu;
typedef struct PageDesc {
/* list of TBs intersecting this ram page */
TranslationBlock *first_tb;
/* in order to optimize self modifying code, we count the number
of lookups we do to a given page to use a bitmap */
unsigned int code_write_count;
uint8_t *code_bitmap;
} PageDesc;
/* In system mode we want L1_MAP to be based on ram offsets,
while in user mode we want it to be based on virtual addresses. */
#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
#define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
#else
#define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
#endif
/* Size of the L2 (and L3, etc) page tables. */
#define L2_BITS 10
#define L2_SIZE (1 << L2_BITS)
/* The bits remaining after N lower levels of page tables. */
#define P_L1_BITS_REM ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
#define V_L1_BITS_REM ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
/* Size of the L1 page table. Avoid silly small sizes. */
#if P_L1_BITS_REM < 4
#define P_L1_BITS (P_L1_BITS_REM + L2_BITS)
#else
#define P_L1_BITS P_L1_BITS_REM
#endif
#if V_L1_BITS_REM < 4
#define V_L1_BITS (V_L1_BITS_REM + L2_BITS)
#else
#define V_L1_BITS V_L1_BITS_REM
#endif
#define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS)
#define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
#define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
uintptr_t tlib_real_host_page_size;
uintptr_t tlib_host_page_bits;
uintptr_t tlib_host_page_size;
uintptr_t tlib_host_page_mask;
/* This is a multi-level map on the virtual address space.
The bottom level has pointers to PageDesc. */
static void *l1_map[V_L1_SIZE];
/* This is a multi-level map on the physical address space.
The bottom level has pointers to PhysPageDesc. */
static void *l1_phys_map[P_L1_SIZE];
/* statistics */
static int tlb_flush_count;
static int tb_flush_count;
static int tb_phys_invalidate_count;
static void page_init(void)
{
/* NOTE: we can always suppose that tlib_host_page_size >=
TARGET_PAGE_SIZE */
#ifdef _WIN32
{
SYSTEM_INFO system_info;
GetSystemInfo(&system_info);
tlib_real_host_page_size = system_info.dwPageSize;
}
#else
tlib_real_host_page_size = getpagesize();
#endif
if(tlib_host_page_size == 0) {
tlib_host_page_size = tlib_real_host_page_size;
}
if(tlib_host_page_size < TARGET_PAGE_SIZE) {
tlib_host_page_size = TARGET_PAGE_SIZE;
}
tlib_host_page_bits = 0;
while((1 << tlib_host_page_bits) < tlib_host_page_size) {
tlib_host_page_bits++;
}
tlib_host_page_mask = ~(tlib_host_page_size - 1);
}
typedef void (*visitor_function)(void *opaque, int page_number);
static void free_page_code_bitmap(void *opaque, int page_number)
{
PageDesc *page;
page = ((PageDesc *)opaque) + page_number;
if(page->code_bitmap) {
tlib_free(page->code_bitmap);
}
}
static void free_all_page_descriptors_inner(void **lp, int level, visitor_function visitor)
{
int i;
if(!level) {
// why the pointer below does not have to be of type
// PageDesc/PhysPageDesc? because it does not change anything from the
// free() point of view
void *pd = *lp;
if(pd) {
for(i = 0; i < L2_SIZE; i++) {
if(visitor) {
visitor(pd, i);
}
}
tlib_free(pd);
}
} else {
void **pp = *lp;
if(!pp) {
return;
}
for(i = 0; i < L2_SIZE; i++) {
free_all_page_descriptors_inner(pp + i, level - 1, visitor);
}
tlib_free(pp);
}
}
void free_all_page_descriptors()
{
int i;
for(i = 0; i < P_L1_SIZE; i++) {
free_all_page_descriptors_inner(l1_phys_map + i, P_L1_SHIFT / L2_BITS - 1, NULL);
}
for(i = 0; i < V_L1_SIZE; i++) {
free_all_page_descriptors_inner(l1_map + i, V_L1_SHIFT / L2_BITS - 1, free_page_code_bitmap);
}
}
static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
{
PageDesc *pd;
void **lp;
int i;
/* Level 1. Always allocated. */
lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
/* Level 2..N-1. */
for(i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
void **p = *lp;
if(p == NULL) {
if(!alloc) {
return NULL;
}
p = tlib_mallocz(sizeof(void *) * L2_SIZE);
*lp = p;
}
lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
}
pd = *lp;
if(pd == NULL) {
if(!alloc) {
return NULL;
}
pd = tlib_mallocz(sizeof(PageDesc) * L2_SIZE);
*lp = pd;
}
return pd + (index & (L2_SIZE - 1));
}
static inline PageDesc *page_find(tb_page_addr_t index)
{
return page_find_alloc(index, 0);
}
static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
{
PhysPageDesc *pd;
void **lp;
int i;
target_phys_addr_t aligned_index;
/* Level 1. Always allocated. */
lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1));
/* Level 2..N-1. */
for(i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
void **p = *lp;
if(p == NULL) {
if(!alloc) {
return NULL;
}
*lp = p = tlib_mallocz(sizeof(void *) * L2_SIZE);
}
lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
}
pd = *lp;
if(pd == NULL) {
int i;
if(!alloc) {
return NULL;
}
*lp = pd = tlib_malloc(sizeof(PhysPageDesc) * L2_SIZE);
aligned_index = index & ~(L2_SIZE - 1);
for(i = 0; i < L2_SIZE; i++) {
pd[i].phys_offset = IO_MEM_UNASSIGNED;
pd[i].region_offset = (aligned_index + i) << TARGET_PAGE_BITS;
pd[i].flags = (PhysPageDescFlags) { 0 };
}
}
return pd + (index & (L2_SIZE - 1));
}
inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
{
return phys_page_find_alloc(index, /* alloc: */ 0);
}
inline PhysPageDesc *phys_page_alloc(target_phys_addr_t index, PhysPageDescFlags flags)
{
PhysPageDesc *page = phys_page_find_alloc(index, /* alloc: */ 1);
page->flags = flags;
return page;
}
void unmap_page(target_phys_addr_t address)
{
PhysPageDesc *pd;
pd = phys_page_find(address >> TARGET_PAGE_BITS);
if(pd == NULL) {
return;
}
if(pd->phys_offset != IO_MEM_UNASSIGNED) {
pd->region_offset = pd->phys_offset;
pd->phys_offset = IO_MEM_UNASSIGNED;
}
tlb_flush_page(cpu, address, /* from_generated: */ false);
}
static void tlb_protect_code(ram_addr_t ram_addr, bool is_mapped);
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, target_ulong vaddr);
#define mmap_lock() \
do { \
} while(0)
#define mmap_unlock() \
do { \
} while(0)
extern uint64_t translation_cache_size_min;
extern uint64_t translation_cache_size_max;
static bool code_gen_alloc()
{
if(code_gen_buffer_size < translation_cache_size_min) {
code_gen_buffer_size = translation_cache_size_min;
}
if(code_gen_buffer_size > translation_cache_size_max) {
code_gen_buffer_size = translation_cache_size_max;
}
// Add the extra space needed for the prologue
uint64_t alloc_size = code_gen_buffer_size + TCG_PROLOGUE_SIZE;
if(!alloc_code_gen_buf(alloc_size)) {
tlib_printf(LOG_LEVEL_WARNING, "Failed to create code_gen_buffer of size %u", alloc_size);
return false;
}
// Notify that the translation cache has changed
tlib_on_translation_cache_size_change(code_gen_buffer_size);
code_gen_buffer_max_size = code_gen_buffer_size - TCG_MAX_CODE_SIZE - TCG_MAX_SEARCH_SIZE;
code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
tbs = tlib_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
// Generate the prologue since the space for it has now been allocated
tcg->code_gen_prologue = tcg_rw_buffer + code_gen_buffer_size;
tcg_prologue_init();
// Prologue is generated, point it to the rx view of the memory
tcg->code_gen_prologue = (uint8_t *)rw_ptr_to_rx(tcg->code_gen_prologue);
return true;
}
// Attempts to expand the code_gen_buffer, keeping the same size if the larger allocation fails
static bool code_gen_try_expand()
{
if(code_gen_buffer_size >= MAX_CODE_GEN_BUFFER_SIZE) {
return false;
}
tlib_printf(LOG_LEVEL_DEBUG, "Trying to expand code_gen_buffer size from %" PRIu64 " to %" PRIu64, code_gen_buffer_size,
code_gen_buffer_size * 2);
/* Discard the current code buffer. This makes all generated code invalid (`tb_flush` should have been executed before) */
code_gen_free();
/* After increasing the size, allocate the buffer again. Note, that it might end in a different location in memory */
code_gen_buffer_size *= 2;
bool did_expand;
if(!code_gen_alloc()) {
// The larger buffer failed to allocate, so we try the old size again
did_expand = false;
code_gen_buffer_size /= 2;
if(!code_gen_alloc()) {
// Same old size failed to allocate, system is either out of memory or we are in a corrupted state, so we just crash
tlib_abort("Failed to reallocate code_gen_buffer after attempted expansion, did the system run out of memory?");
return false;
}
} else {
did_expand = true;
}
code_gen_ptr = tcg_rw_buffer;
return did_expand;
}
void code_gen_free(void)
{
// Perf labels need to be flushed since they hold pointers to tbs which will be invalidated here
tcg_perf_flush_map();
free_code_gen_buf();
tlib_free(tbs);
}
TCGv_ptr cpu_env;
/* Must be called before using the QEMU cpus.*/
void cpu_exec_init_all()
{
tcg_context_init();
if(!code_gen_alloc()) {
tlib_abort("Failed to allocate code_gen_buffer");
}
code_gen_ptr = tcg_rw_buffer;
page_init();
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
}
void cpu_exec_init(CPUState *env)
{
cpu = env;
QTAILQ_INIT(&cpu->breakpoints);
QTAILQ_INIT(&cpu->cached_address);
}
/* Allocate a new translation block. Flush the translation buffer if
too many translation blocks or too much generated code. */
static TranslationBlock *tb_alloc(target_ulong pc)
{
TranslationBlock *tb;
if(nb_tbs >= code_gen_max_blocks || (code_gen_ptr - tcg_rw_buffer) >= code_gen_buffer_max_size) {
return NULL;
}
tb = &tbs[nb_tbs++];
tb->pc = pc;
tb->cflags = 0;
tb->dirty_flag = false;
tb->phys_hash_next = NULL;
return tb;
}
void tb_free(TranslationBlock *tb)
{
/* In practice this is mostly used for single use temporary TB
Ignore the hard cases and just back up if this TB happens to
be the last one generated. */
if(nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
code_gen_ptr = tb->tc_ptr;
nb_tbs--;
}
}
static inline void invalidate_page_bitmap(PageDesc *p)
{
if(p->code_bitmap) {
tlib_free(p->code_bitmap);
p->code_bitmap = NULL;
}
p->code_write_count = 0;
}
/* Set to NULL all the 'first_tb' fields in all PageDescs. */
static void page_flush_tb_1(int level, void **lp)
{
int i;
if(*lp == NULL) {
return;
}
if(level == 0) {
PageDesc *pd = *lp;
for(i = 0; i < L2_SIZE; ++i) {
pd[i].first_tb = NULL;
invalidate_page_bitmap(pd + i);
}
} else {
void **pp = *lp;
for(i = 0; i < L2_SIZE; ++i) {
page_flush_tb_1(level - 1, pp + i);
}
}
}
static void page_flush_tb(void)
{
int i;
for(i = 0; i < V_L1_SIZE; i++) {
page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i);
}
}
/* flush all the translation blocks */
/* XXX: tb_flush is currently not thread safe */
void tb_flush(CPUState *env1)
{
if((uintptr_t)(code_gen_ptr - tcg_rw_buffer) > code_gen_buffer_size) {
cpu_abort(env1, "Internal error: code buffer overflow\n");
}
nb_tbs = 0;
memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
memset(tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof(void *));
page_flush_tb();
code_gen_ptr = tcg_rw_buffer;
/* XXX: flush processor icache at this point if cache flush is
expensive */
tb_flush_count++;
}
/* invalidate one TB */
static inline bool tb_remove(TranslationBlock **ptb, TranslationBlock *tb, int next_offset)
{
TranslationBlock *tb1;
for(;;) {
tb1 = *ptb;
if(tb1 == tb) {
*ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
return true;
}
if(tb1 == NULL) {
// We couldn't find the right TranslationBlock.
// That means it must've been invalidated already,
// for example if there was a breakpoint triggered at the same address.
return false;
}
ptb = (TranslationBlock **)((char *)tb1 + next_offset);
}
}
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
{
TranslationBlock *tb1;
unsigned int n1;
for(;;) {
tb1 = *ptb;
n1 = (uintptr_t)tb1 & 3;
tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
if(tb1 == tb) {
*ptb = tb1->page_next[n1];
break;
}
ptb = &tb1->page_next[n1];
}
}
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
{
TranslationBlock *tb1, **ptb;
unsigned int n1;
ptb = &tb->jmp_next[n];
tb1 = *ptb;
if(tb1) {
/* find tb(n) in circular list */
for(;;) {
tb1 = *ptb;
n1 = (uintptr_t)tb1 & 3;
tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
if(n1 == n && tb1 == tb) {
break;
}
if(n1 == EXIT_TB_FORCE) {
ptb = &tb1->jmp_first;
} else {
ptb = &tb1->jmp_next[n1];
}
}
/* now we can suppress tb(n) from the list */
*ptb = tb->jmp_next[n];
tb->jmp_next[n] = NULL;
}
}
/* reset the jump entry 'n' of a TB so that it is not chained to
another TB */
static inline void tb_reset_jump(TranslationBlock *tb, int n)
{
tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n]));
}
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
PageDesc *p;
unsigned int h, n1;
tb_page_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
h = tb_phys_hash_func(phys_pc);
if(!tb_remove(&tb_phys_hash[h], tb, offsetof(TranslationBlock, phys_hash_next))) {
// The TB has already been invalidated.
return;
}
/* remove the TB from the page list */
if(tb->page_addr[0] != page_addr) {
p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
tb_page_remove(&p->first_tb, tb);
invalidate_page_bitmap(p);
}
if(tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
tb_page_remove(&p->first_tb, tb);
invalidate_page_bitmap(p);
}
tb_invalidated_flag = 1;
tb_jmp_cache_remove(tb);
/* suppress this TB from the two jump lists */
tb_jmp_remove(tb, 0);
tb_jmp_remove(tb, 1);
/* suppress any remaining jumps to this TB */
tb1 = tb->jmp_first;
for(;;) {
n1 = (uintptr_t)tb1 & 3;
if(n1 == EXIT_TB_FORCE) {
break;
}
tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
tb2 = tb1->jmp_next[n1];
tb_reset_jump(tb1, n1);
tb1->jmp_next[n1] = NULL;
tb1 = tb2;
}
tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | EXIT_TB_FORCE); /* fail safe */
tb_phys_invalidate_count++;
}
static inline void set_bits(uint8_t *tab, int start, int len)
{
int end, mask, end1;
end = start + len;
tab += start >> 3;
mask = 0xff << (start & 7);
if((start & ~7) == (end & ~7)) {
if(start < end) {
mask &= ~(0xff << (end & 7));
*tab |= mask;
}
} else {
*tab++ |= mask;
start = (start + 8) & ~7;
end1 = end & ~7;
while(start < end1) {
*tab++ = 0xff;
start += 8;
}
if(start < end) {
mask = ~(0xff << (end & 7));
*tab |= mask;
}
}
}
static void build_page_bitmap(PageDesc *p)
{
int n, tb_start, tb_end;
TranslationBlock *tb;
p->code_bitmap = tlib_mallocz(TARGET_PAGE_SIZE / 8);
tb = p->first_tb;
while(tb != NULL) {
n = (uintptr_t)tb & 3;
tb = (TranslationBlock *)((uintptr_t)tb & ~3);
/* NOTE: this is subtle as a TB may span two physical pages */
if(n == EXIT_TB_NO_JUMP) {
/* NOTE: tb_end may be after the end of the page, but
it is not a problem */
tb_start = tb->pc & ~TARGET_PAGE_MASK;
tb_end = tb_start + tb->size;
if(tb_end > TARGET_PAGE_SIZE) {
tb_end = TARGET_PAGE_SIZE;
}
} else {
tb_start = 0;
tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
}
set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
tb = tb->page_next[n];
}
}
TranslationBlock *tb_gen_code(CPUState *env, target_ulong pc, target_ulong cs_base, int flags, uint16_t cflags)
{
TranslationBlock *tb;
uint8_t *tc_ptr;
tb_page_addr_t phys_page1, phys_page2;
target_ulong virt_page2;
int code_gen_size, search_size;
phys_page1 = get_page_addr_code(env, pc, true);
tb = tb_alloc(pc);
if(!tb) {
/* flush must be done */
tb_flush(env);
/* try to expand code gen buffer */
code_gen_try_expand();
/* cannot fail at this point */
tb = tb_alloc(pc);
/* Don't forget to invalidate previous TB info. */
tb_invalidated_flag = 1;
}
tc_ptr = code_gen_ptr;
tb->tc_ptr = tc_ptr;
tb->cs_base = cs_base;
tb->flags = flags;
tb->cflags = cflags;
cpu_gen_code(env, tb, &code_gen_size, &search_size);
code_gen_ptr = (void *)(((uintptr_t)code_gen_ptr + code_gen_size + search_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
tcg_perf_out_symbol_i(code_gen_ptr, code_gen_size, tb->icount, tb);
/* check next page if needed */
phys_page2 = -1;
if(tb->size > 0) {
// size will be 0 when tb contains a breakpoint instruction; in such case no other instructions are generated and there
// is no page2 at all
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
if((pc & TARGET_PAGE_MASK) != virt_page2) {
phys_page2 = get_page_addr_code(env, virt_page2, true);
}
}
tb_link_page(tb, phys_page1, phys_page2);
return tb;
}
void helper_mark_tbs_as_dirty(CPUState *env, target_ulong pc, int access_width, int broadcast)
{
int n;
PageDesc *p;
tb_page_addr_t phys_page;
TranslationBlock *tb, *tb_next;
tb_page_addr_t tb_start, tb_end;
target_ulong phys_pc;
if(cpu->tb_cache_disabled) {
return;
}
// Try to find the page using the tlb contents
phys_page = get_page_addr_code(cpu, pc, false);
if(phys_page == -1 || !(p = page_find(phys_page >> TARGET_PAGE_BITS))) {
if((env->current_tb != 0) && (pc < env->current_tb->pc) && (pc >= (env->current_tb->pc + env->current_tb->size))) {
// we are not on the same mem page, the mapping just does not exist
return;
}
// Find the page using the platform specific mapping function
// This is way slower, but it should be used only if the same page is being executed
phys_page = cpu_get_phys_page_debug(cpu, pc);
if(phys_page == -1 || !(p = page_find(phys_page >> TARGET_PAGE_BITS))) {
return;
}
}
phys_pc = phys_page | (pc & ~TARGET_PAGE_MASK);
if(broadcast && cpu->tb_broadcast_dirty) {
append_dirty_address(phys_pc);
}
// Below code is a simplified version of the `tb_invalidate_phys_page_range_inner` search
tb = p->first_tb;
while(tb != NULL) {
n = (uintptr_t)tb & 3;
tb = (TranslationBlock *)((uintptr_t)tb & ~3);
tb_next = tb->page_next[n];
tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
tb_end = tb_start + tb->size;
if((tb_start <= phys_pc && phys_pc < tb_end) || (phys_pc <= tb_start && tb_start < phys_pc + access_width)) {
tb->dirty_flag = true;
}
tb = tb_next;
}
}
static inline bool tb_blocks_related(TranslationBlock *tb1, TranslationBlock *tb2)
{
if(tb1->pc == tb2->pc && tb1->page_addr[0] == tb2->page_addr[0] && tb1->cs_base == tb2->cs_base && tb1->flags == tb2->flags) {
return tb2->page_addr[1] == -1 || tb1->page_addr[1] == tb2->page_addr[1];
}
return false;
}
static void tb_phys_hash_insert(TranslationBlock *tb)
{
TranslationBlock **ptb;
unsigned int h;
tb_page_addr_t phys_page;
target_ulong phys_pc;
phys_page = get_page_addr_code(env, tb->pc, true);
phys_pc = phys_page | (tb->pc & ~TARGET_PAGE_MASK);
h = tb_phys_hash_func(phys_pc);
ptb = &tb_phys_hash[h];
while(*ptb) {
TranslationBlock *act_tb = *ptb;
if(tb_blocks_related(tb, act_tb) && tb->icount >= act_tb->icount) {
break;
}
ptb = &act_tb->phys_hash_next;
}
tb->phys_hash_next = *ptb;
*ptb = tb;
}
/* invalidate all TBs which intersect with the target physical page
starting in range [start;end[. NOTE: start and end must refer to
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
void tb_invalidate_phys_page_range_inner(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access, int broadcast)
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *env = cpu;
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
#ifdef TARGET_HAS_PRECISE_SMC
int current_tb_not_found = is_cpu_write_access;
TranslationBlock *current_tb = NULL;
int current_tb_modified = 0;
target_ulong current_pc = 0;
target_ulong current_cs_base = 0;
int current_flags = 0;
#endif /* TARGET_HAS_PRECISE_SMC */
if(start / TARGET_PAGE_SIZE != (end - 1) / TARGET_PAGE_SIZE) {
tlib_abortf("Attempted to invalidate more than 1 physical page. Addresses: 0x" TARGET_FMT_lx " and 0x" TARGET_FMT_lx
" are not on the same page",
start, end);
}
p = page_find(start >> TARGET_PAGE_BITS);
if(!p) {
return;
}
if(!p->code_bitmap && ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && is_cpu_write_access) {
/* build code bitmap */
build_page_bitmap(p);
}
/* we remove all the TBs in the range [start, end[ */
/* XXX: see if in some cases it could be faster to invalidate all the code */
tb = p->first_tb;
while(tb != NULL) {
n = (uintptr_t)tb & 3;
tb = (TranslationBlock *)((uintptr_t)tb & ~3);
tb_next = tb->page_next[n];
/* NOTE: this is subtle as a TB may span two physical pages */
if(n == EXIT_TB_NO_JUMP) {
/* NOTE: tb_end may be after the end of the page, but
it is not a problem */
tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
tb_end = tb_start + tb->size;
} else {
tb_start = tb->page_addr[1];
tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
}
// condition in this form supports blocks where 'tb_start' == 'tb_end' (empty blocks with just a breakpoint)
if((tb_start >= start && tb_start < end) || (tb_end >= start && tb_end < end) || (tb_start <= start && tb_end >= end)) {
#ifdef TARGET_HAS_PRECISE_SMC
if(current_tb_not_found) {
current_tb_not_found = 0;
current_tb = NULL;
if(env->mem_io_pc) {
/* now we have a real cpu fault */
current_tb = tb_find_pc(env->mem_io_pc);
}
}
if(current_tb == tb && (current_tb->cflags & CF_COUNT_MASK) != 1) {
/* If we are modifying the current TB, we must stop
its execution. We could be more precise by checking
that the modification is after the current PC, but it
would require a specialized function to partially
restore the CPU state */
current_tb_modified = 1;
cpu_restore_state_from_tb(env, current_tb, env->mem_io_pc);
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, ¤t_flags);
}
#endif /* TARGET_HAS_PRECISE_SMC */
/* we need to do that to handle the case where a signal
occurs while doing tb_phys_invalidate() */
saved_tb = NULL;
if(env) {
saved_tb = env->current_tb;
env->current_tb = NULL;
}
tb_phys_invalidate(tb, -1);
if(env) {
env->current_tb = saved_tb;
if(env->interrupt_request && env->current_tb) {
cpu_interrupt(env, env->interrupt_request);
}
}
}
tb = tb_next;
}
/* if no code remaining, no need to continue to use slow writes */
if(!p->first_tb) {
invalidate_page_bitmap(p);
if(is_cpu_write_access) {
tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
}
}
if(broadcast) {
tlib_invalidate_tb_in_other_cpus(start, end);
}
#ifdef TARGET_HAS_PRECISE_SMC
if(current_tb_modified) {
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
itself */
tb = tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
tb_phys_hash_insert(tb);
env->exception_index = -1;
cpu_loop_exit(env);
}
#endif
}
/* Same as `tb_invalidate_phys_page_range_inner`, but start and end addresses don't have to be on the same physical page. */
void tb_invalidate_phys_page_range_checked(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access, int broadcast)
{
tb_page_addr_t length = end - start;
tb_page_addr_t first_length = TARGET_PAGE_SIZE - start % TARGET_PAGE_SIZE;
if(length < first_length) {
first_length = length;
}
tb_invalidate_phys_page_range_inner(start, start + first_length, is_cpu_write_access, broadcast);
start += first_length;
length -= first_length;
while(length > 0) {
tb_page_addr_t invalidate_length = length > TARGET_PAGE_SIZE ? TARGET_PAGE_SIZE : length;
tb_invalidate_phys_page_range_inner(start, start + invalidate_length, is_cpu_write_access, broadcast);
start += invalidate_length;
length -= invalidate_length;
}
}
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, int is_cpu_write_access)
{
tb_invalidate_phys_page_range_checked(start, end, is_cpu_write_access, 1);
}
/* len must be <= 8 and start must be a multiple of len */
static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
{
PageDesc *p;
int offset, b;
p = page_find(start >> TARGET_PAGE_BITS);
if(!p) {
return;
}
if(p->code_bitmap) {
offset = start & ~TARGET_PAGE_MASK;
b = p->code_bitmap[offset >> 3] >> (offset & 7);
if(b & ((1 << len) - 1)) {
goto do_invalidate;
}
} else {
do_invalidate:
tb_invalidate_phys_page_range(start, start + len, 1);
}
}
/* add the tb in the target page and protect it if necessary */
static inline void tb_alloc_page(TranslationBlock *tb, unsigned int n, tb_page_addr_t page_addr)
{
PageDesc *p;
bool is_mapped;
bool page_already_protected;
is_mapped = !(page_addr & IO_MEM_EXECUTABLE_IO);
page_addr &= ~IO_MEM_EXECUTABLE_IO;
tb->page_addr[n] = page_addr;
p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
tb->page_next[n] = p->first_tb;
page_already_protected = p->first_tb != NULL;
p->first_tb = (TranslationBlock *)((uintptr_t)tb | n);
invalidate_page_bitmap(p);
/* if some code is already present, then the pages are already
protected. So we handle the case where only the first TB is
allocated in a physical page */
if(!page_already_protected) {
tlb_protect_code(page_addr, is_mapped);
}
}
/* add a new TB. phys_page2 is (-1) to indicate that only one page contains the TB. */
void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_page1, tb_page_addr_t phys_page2)
{
/* Grab the mmap lock to stop another thread invalidating this TB
before we are done. */
mmap_lock();
/* add in the page list */
tb_alloc_page(tb, 0, phys_page1 & (TARGET_PAGE_MASK | IO_MEM_EXECUTABLE_IO));
if(phys_page2 != -1) {
tb_alloc_page(tb, 1, phys_page2);
} else {