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$ perf --version perf version 6.11.11-300.fc41.x86_64
(FC41)
(most nodes missing multiplex indicator)
$ toplev --all ./workloads/BC1s
C0 FE Frontend_Bound % Slots 21.1 C0 BE Backend_Bound % Slots 33.5 C0 RET Retiring % Slots 39.7 C0 Info.Core CoreIPC Core_Metric 0.20 C0 FE Frontend_Bound.Fetch_Latency % Slots 14.0 C0 FE Frontend_Bound.Fetch_Bandwidth % Slots 6.8 C0 BAD Bad_Speculation.Branch_Mispredicts % Slots 4.2 C0 BAD Bad_Speculation.Machine_Clears % Slots 1.1 C0 BE/Core Backend_Bound.Core_Bound % Slots 20.2 C0 RET Retiring.Heavy_Operations % Slots 33.4 C0 RET Retiring.Heavy_Operations.Microcode_Sequencer % Slots 33.6 C0 RET Retiring.Heavy_Operations.Microcode_Sequencer.CISC % Slots 32.9 <== This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction... C0 Info.Bad_Spec Branch_Misprediction_Cost Core_Metric -412.79 C0 Info.Memory.Core L1D_Cache_Fill_BW_2T Core_Metric 0.13 C0 Info.Memory.Core L2_Cache_Fill_BW_2T Core_Metric 0.04 C0 Info.Memory.Core L3_Cache_Fill_BW_2T Core_Metric 0.00 C0 Info.Memory.Core L3_Cache_Access_BW_2T Core_Metric 0.05 C0 Info.Memory.Core L2_Evictions_Silent_PKI Core_Metric 0.54 C0 Info.Memory.Core L2_Evictions_NonSilent_PKI Core_Metric 0.11 C0 Info.System Turbo_Utilization Core_Metric 0.90 C0 Info.System Power_License0_Utilization Core_Metric 1.00 C0 Info.System SMT_2T_Utilization Core_Metric 0.05 C0-T0 FE Frontend_Bound.Fetch_Latency.Branch_Resteers.Mispredicts_Resteers % Clocks 2.9 C0-T0 FE Frontend_Bound.Fetch_Latency.Branch_Resteers.Clears_Resteers % Clocks 0.2 C0-T0 Info.Bad_Spec Spec_Clears_Ratio Metric 10.62 C0-T0 FE Frontend_Bound.Fetch_Latency.MS_Switches % Clocks_est 5.1 C0-T0 FE Frontend_Bound.Fetch_Latency.LCP % Clocks 0.0 C0-T0 FE Frontend_Bound.Fetch_Latency.DSB_Switches % Clocks 0.2 [ 2.0%]
The text was updated successfully, but these errors were encountered:
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$ perf --version
perf version 6.11.11-300.fc41.x86_64
(FC41)
(most nodes missing multiplex indicator)
$ toplev --all ./workloads/BC1s
5.01-full-perf on Intel(R) Core(TM) i9-7980XE CPU @ 2.60GHz [skx/skylake]
C0 FE Frontend_Bound % Slots 21.1
C0 BE Backend_Bound % Slots 33.5
C0 RET Retiring % Slots 39.7
C0 Info.Core CoreIPC Core_Metric 0.20
C0 FE Frontend_Bound.Fetch_Latency % Slots 14.0
C0 FE Frontend_Bound.Fetch_Bandwidth % Slots 6.8
C0 BAD Bad_Speculation.Branch_Mispredicts % Slots 4.2
C0 BAD Bad_Speculation.Machine_Clears % Slots 1.1
C0 BE/Core Backend_Bound.Core_Bound % Slots 20.2
C0 RET Retiring.Heavy_Operations % Slots 33.4
C0 RET Retiring.Heavy_Operations.Microcode_Sequencer % Slots 33.6
C0 RET Retiring.Heavy_Operations.Microcode_Sequencer.CISC % Slots 32.9 <==
This metric estimates fraction of cycles the CPU retired
uops originated from CISC (complex instruction set computer)
instruction...
C0 Info.Bad_Spec Branch_Misprediction_Cost Core_Metric -412.79
C0 Info.Memory.Core L1D_Cache_Fill_BW_2T Core_Metric 0.13
C0 Info.Memory.Core L2_Cache_Fill_BW_2T Core_Metric 0.04
C0 Info.Memory.Core L3_Cache_Fill_BW_2T Core_Metric 0.00
C0 Info.Memory.Core L3_Cache_Access_BW_2T Core_Metric 0.05
C0 Info.Memory.Core L2_Evictions_Silent_PKI Core_Metric 0.54
C0 Info.Memory.Core L2_Evictions_NonSilent_PKI Core_Metric 0.11
C0 Info.System Turbo_Utilization Core_Metric 0.90
C0 Info.System Power_License0_Utilization Core_Metric 1.00
C0 Info.System SMT_2T_Utilization Core_Metric 0.05
C0-T0 FE Frontend_Bound.Fetch_Latency.Branch_Resteers.Mispredicts_Resteers % Clocks 2.9
C0-T0 FE Frontend_Bound.Fetch_Latency.Branch_Resteers.Clears_Resteers % Clocks 0.2
C0-T0 Info.Bad_Spec Spec_Clears_Ratio Metric 10.62
C0-T0 FE Frontend_Bound.Fetch_Latency.MS_Switches % Clocks_est 5.1
C0-T0 FE Frontend_Bound.Fetch_Latency.LCP % Clocks 0.0
C0-T0 FE Frontend_Bound.Fetch_Latency.DSB_Switches % Clocks 0.2 [ 2.0%]
The text was updated successfully, but these errors were encountered: