refactor(gfx): align signex-gfx to iced's wgpu and revive the GPU path through the shader widget (implements #100)

[hkngln]

Implementation work order for the consolidation #100 recommends. All facts below were independently verified, including a compile experiment: signex-gfx was built against iced's wgpu in a scratch copy and every error catalogued.

Verified fact base

1. The shader widget is already enabled. The workspace's iced dep carries the wgpu feature (root Cargo.toml:44); iced 0.14's feature chain (wgpu → wgpu-bare → iced_widget/wgpu) compiles iced::widget::shader::{Program, Primitive, Pipeline} today — zero Cargo changes needed on the app side.
2. Alignment target: the wgpu that iced_wgpu 0.14.0 resolves (currently 27.0.1) — sharing iced's device/queue requires the same major.
3. Measured downgrade cost (29.0.3 → 27.0.1): 25 compile errors, 22 mechanical.
   • 15 across 5 pipelines (pipeline/{line,circle,arc,polygon,grid}.rs): bind_group_layouts: &[Some(l)] → &[l], immediate_size: 0 → push_constant_ranges: &[], multiview_mask → multiview (e.g. line.rs:32-34, 96).
   • 7× multiview_mask on RenderPassDescriptor in debug_pass.rs (156/241/338/426/518/639/784).
   • 3 in pipeline/text.rs: glyphon 0.11 (needs wgpu 29) swaps to cryoglyph 0.1 (already in-tree via iced_wgpu): custom_glyphs field, SwashCache iteration, TextRenderer::prepare arity — note cryoglyph's prepare needs a CommandEncoder, which iced's Primitive::prepare does not supply, so text prep needs its own encoder or moves into Primitive::render.
   • Zero uses of wgpu 28/29-only APIs anywhere in signex-gfx/signex-renderer (transition_resources, map_buffer_on_submit, StagingBelt::allocate, TextureChannel, buffer-slice bindings — grepped).
4. signex-renderer is untouched by the change: pcb.rs/pcb3d.rs/schematic.rs emit CPU Scene primitives only, zero wgpu types. iced_bridge is confirmed dead (only the lib.rs mod decl) — delete it per [Architecture] signex-gfx links a second, incompatible wgpu/naga/cosmic-text stack of dead GPU code #100.
5. The integration seam already fits: signex-gfx's pipeline API (new(device, format, layout) / upload(device, queue, &[T]) / draw(pass)) plus scene::upload::apply_dirty_uploads_with_culling maps 1:1 onto iced's Primitive/Pipeline contract. The GPU plug-in points are exactly the three CPU canvas::Program sites: schematic_runtime.rs:814, pcb_canvas.rs:299, symbol canvas.rs:1761.
6. NEW gap found on the way: the fully-tested pcb3d runtime GLB ingest (crates/signex-renderer/src/pcb3d.rs:241-911, ~962 lines) has zero application consumers — the footprint 3D preview is an unrelated CPU isometric stub. Record for the future board-3D work; not in scope here.

Plan

1. PR 1 — version alignment (no behavioural change): pin signex-gfx to the exact wgpu iced_wgpu resolves; apply the 22 mechanical fixes; port pipeline/text.rs to cryoglyph; delete signex-renderer::iced_bridge. Result: one wgpu/naga stack, one text shaper in the binary. Add cargo deny check bans to CI with multiple-versions = "deny" + reviewed [[bans.skip]] (per [Architecture] signex-gfx links a second, incompatible wgpu/naga/cosmic-text stack of dead GPU code #100) so the dual stack cannot regress.
2. PR 2 — first shader-widget consumer (feature-gated): wire ONE canvas (recommend the PCB canvas — it is the 100K+-element case CPU tessellation serves worst) through iced::widget::shader using the existing signex-gfx pipelines, behind a feature flag / preferences toggle, CPU canvas remains the default until parity is proven. Fix the known gfx render bugs listed in [Architecture] signex-gfx links a second, incompatible wgpu/naga/cosmic-text stack of dead GPU code #100 (polygon %3 triangulation, text pan/rotation, arc/line shader issues) as they block parity.

Acceptance criteria

• cargo tree shows a single wgpu/naga chain and a single cosmic-text; deny-bans gate green.
• signex-gfx GPU smoke tests (lavapipe CI job) still pass after the downgrade.
• PR 2: PCB canvas renders identically (golden-image or manual A/B) with the GPU path toggled on; pan/zoom does not re-tessellate on CPU.