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LDRIO.MAC
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; 041190 Tilmann Reh
; 10-July-2017 Tony Nicholson
; Comments translated from German to English (using Google
; Translate with some appropriate language adjustments resulting
; from an examination of the instruction sequences). Also
; corrected the syntax to be compatible with Hector Peraza's
; ZSM4 Z80/Z180/Z280 assembler
; Macros for Character-I/O for use by the CPU280-Boot-Loader.
; All console operations use these macros, so that customisation
; to other Terminals MUST BE DONE HERE.
; This version drives the CPU internal serial interface using the
; internal Clock Timer CT1 for baud rate generation.
def1h equ 11000100b ; Default 8N1, with no flowcontrol
def1bd equ 14 ; Default 9600 Baud
;***********************************************************************
;** Initialise the Console Interface **
;***********************************************************************
; Entry with the CPU clock factor (x 614400 Hz) in B.
; All Registers except SP may be used.
; Still stuck at 19200 Baud. --> Setup!
chrnit: macro
local ct1tab,exit
iopage boardp
out (rts1_en),a ; RTS1 := active
in a,(s$c1bd)
add a,a
exts a ; 2* Baud in HL
in a,(s$c1h)
ldw hl,(hl++ct1tab-2) ; Normalise the divisor (*256) in HL
ld c,0 ; CPU frequency *256 to BC
multuw hl,bc ; Multiply (/65536) result in DE
ld b,a ; Hardware Parameter to B
iopage ctp
ex de,hl ; Prescaler --> HL
dec hl ; -1 for Time Constant Register
ld c,tc1
outw (c),hl ; new 'Time Constant' for CT1
ld a,10001000b
out (cr1),a ; CT1: Cont. Timer, Output
ld a,11100000b
out (cs1),a ; CT1 Enable
ld a,b ; Hardware Parameter
rrca
rrca ; Bits 7..4 now contains bits 1076
rept 4
rla
rr d
endm ; D(7..4) has bits 6701
ld a,d
and 0F0h
or 00001010b
out (ucr),a ; UART Control Register
ld a,b
and 00001000b ; Isolate bit 3 (Stopbits)
rlca ; --> Bit 4
or 10000001b
out (tcs),a ; Transmitter Control
ld a,10000000b
out (rcs),a ; Receiver Control
in a,(rdr)
in a,(rdr) ; RX empty
jr exit
ct1tab: defw 64,32768,22342,18273,16384,8192,4096,2048,1366,1024,683,512,342,256,128
exit:
endm
;***********************************************************************
;** Console Character Output **
;***********************************************************************
; The primary registers may not be changed, and we don't use any RAM.
; You may use: AF and the secondary registers BC' and HL'.
outchr macro data
local outc1,outc2,outc3
exx ; -> switch registers
iopage boardp
in a,(s$c1h) ; Hardware Parameter CRT1
bit 5,a ; Test flow control bit
jr z,outc2 ; no Handshake: do not check CTS
outc1: in a,(gpi)
bit b$cts1,a
jr nz,outc1 ; wait for CTS
outc2: iopage uartp
outc3: in a,(tcs)
rra
jr nc,outc3 ; wait for Buffer Empty (BE)
exx ; -> back to primary registers
ld a,data
out (tdr),a ; Output the character
endm
;***********************************************************************
;** Character input from Console **
;***********************************************************************
; Macro to check for (and Read in) the received character.
; Result returned in A or CY set if none.
; No usage restrictions.
inchar macro
local exit
iopage uartp
in a,(rcs) ; UART Status Register
bit 4,a ; Character available ?
scf
jr z,exit ; no: Exit with CY set
in a,(rdr) ; Read character
or a ; clear CY
exit:
endm