uartrx-fifo/Makefile at master · adumont/uartrx-fifo · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
# Generic Makefile to synthesize, simulate and program an FPGA
# using opensource toolchain
# Author: Alexandre Dumont

# TOP:
# 	make sim|bin|upload
# Submodules:
#   make MODULE=moduleName sim|svg

TOP:=top

ifndef $(MODULE)
	MODULE:=$(TOP)
endif
ifeq ($(MODULE), $(TOP))
  DEPS:=\
    debouncer.v \
    rxuartlite.v \
	txuartlite.v \
    ufifo.v

# AUXFILES:=\
    const.vh

# YOSYSOPT:=-retime -abc2
endif

ifndef $(MEMORY)
	MEMORY="1k"
endif

all: bin

bin: $(MODULE).bin
sim: $(MODULE)_tb.vcd
json: $(MODULE).json
svg: assets/$(MODULE).svg

$(MODULE)_tb.vcd: $(MODULE).v $(DEPS) $(MODULE)_tb.v  $(AUXFILES)

	iverilog $^ -o $(MODULE)_tb.out
	./$(MODULE)_tb.out
	gtkwave $@ $(MODULE)_tb.gtkw &

$(MODULE).bin: $(MODULE).pcf $(MODULE).v $(DEPS) $(AUXFILES)

	yosys -p "synth_ice40 -blif $(MODULE).blif $(YOSYSOPT)"\
              -l $(MODULE).log -q $(MODULE).v $(DEPS)

	arachne-pnr -d $(MEMORY) -p $(MODULE).pcf $(MODULE).blif -o $(MODULE).pnr

	icepack $(MODULE).pnr $(MODULE).bin

$(MODULE).json: $(MODULE).v $(DEPS)
	yosys -p "prep -top $(MODULE); write_json $(MODULE).json" $(MODULE).v $(DEPS)

assets/$(MODULE).svg: $(MODULE).json
	netlistsvg $(MODULE).json -o assets/$(MODULE).svg

upload: $(MODULE).bin
	iceprog $(MODULE).bin

clean:
	rm -f *.bin *.pnr *.blif *.out *.vcd *~

.PHONY: all clean json svg sim