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Tweak flaky test
Now the bsim PHY will stay active until the test harness terminates it. This requires the CircuitPython device process to exit correctly first but is backed up by wall clock timeouts in the harness. (Sim timeouts were in simulated time.)
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+4
-3
lines changed

2 files changed

+4
-3
lines changed

ports/zephyr-cp/tests/bsim/conftest.py

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,15 +97,16 @@ def bsim_phy(request, bsim_phy_binary, native_sim_env, sim_id):
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sample_device_id = int(sample_marker.kwargs.get("device_id", 1))
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devices = max(devices, sample_device_id + 1)
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100-
sim_length_us = int(duration * 1e6)
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# Do not pass -sim_length: if the PHY exits on simulated time, device 0 can
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# still be flushing UART output and test output can get truncated. Instead,
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# let pytest own process lifetime and terminate the PHY at fixture teardown.
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cmd = [
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"stdbuf",
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"-oL",
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str(bsim_phy_binary),
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"-v=9", # Cleaning up level is on 9. Connecting is 7.
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f"-s={sim_id}",
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f"-D={devices}",
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f"-sim_length={sim_length_us}",
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]
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print("Running:", " ".join(cmd))
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proc = subprocess.Popen(

ports/zephyr-cp/zephyr-config/west.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ manifest:
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projects:
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- name: nrf_hw_models
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url: https://github.com/tannewt/ext_nRF_hw_models
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revision: 24de78c485dce1a6048f8ae1c69a8d70c93b8cdd
7+
revision: bb351cef9e5ab4d175fe3cb7c4d6761d837bac20
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path: modules/bsim_hw_models/nrf_hw_models
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- name: zephyr
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url: https://github.com/adafruit/zephyr

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