Commit a358cd5
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Tweak flaky test
Now the bsim PHY will stay active until the test harness terminates it.
This requires the CircuitPython device process to exit correctly first
but is backed up by wall clock timeouts in the harness. (Sim timeouts
were in simulated time.)1 parent ab84b9f commit a358cd5
2 files changed
+4
-3
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