From 545b4b539b7a23770dd01fc29747ac2b8a094462 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Tue, 22 Apr 2025 10:56:31 -0400
Subject: [PATCH 01/14] wip ram image

---
 build.zig                                   |  1 +
 core/src/cpus/cortex_m.zig                  | 44 +++++++++++++-
 examples/raspberrypi/rp2xxx/build.zig       |  2 +
 port/raspberrypi/rp2xxx/build.zig           | 11 ++++
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 66 +++++++++++++++++++++
 5 files changed, 121 insertions(+), 3 deletions(-)
 create mode 100644 port/raspberrypi/rp2xxx/rp2040_ram_image.ld

diff --git a/build.zig b/build.zig
index 3f031881e..10006bfd1 100644
--- a/build.zig
+++ b/build.zig
@@ -541,6 +541,7 @@ pub fn MicroBuild(port_select: PortSelect) type {
 
             fw.artifact.root_module.addImport("microzig", core_mod);
             fw.artifact.root_module.addImport("app", app_mod);
+            fw.artifact.entry = .{ .symbol_name = "_entry_point" };
 
             // If not specified then generate the linker script
             const linker_script = options.linker_script orelse target.linker_script orelse blk: {
diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index 07953015b..6d10eb04e 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -575,6 +575,24 @@ const vector_count = @sizeOf(microzig.chip.VectorTable) / @sizeOf(usize);
 
 var ram_vectors: [vector_count]usize align(256) = undefined;
 
+pub fn ram_image_entrypoint() linksection(".entry") callconv(.naked) void {
+    asm volatile (
+        \\
+        // Set VTOR to point to ram table
+        \\mov r0, %[_vector_table]
+        \\mov r1, %[_VTOR_ADDRESS]
+        \\str r0, [r1]
+        // Set up stack and jump to _start
+        \\ldm r0!, {r1, r2}
+        \\msr msp, r1
+        \\bx r2
+        :
+        : [_vector_table] "r" (&startup_logic._vector_table),
+          [_VTOR_ADDRESS] "r" (&peripherals.scb.VTOR),
+        : "memory", "r0", "r1", "r2"
+    );
+}
+
 pub const startup_logic = struct {
     extern fn microzig_main() noreturn;
 
@@ -588,7 +606,6 @@ pub const startup_logic = struct {
     extern const microzig_data_load_start: u8;
 
     pub fn _start() callconv(.c) noreturn {
-
         // fill .bss with zeroes
         {
             const bss_start: [*]u8 = @ptrCast(&microzig_bss_start);
@@ -612,7 +629,7 @@ pub const startup_logic = struct {
         if (interrupt.has_ram_vectors()) {
             // Copy vector table to RAM and set VTOR to point to it
 
-            if (interrupt.has_ram_vectors_section()) {
+            if (comptime interrupt.has_ram_vectors_section()) {
                 @export(&ram_vectors, .{
                     .name = "_ram_vectors",
                     .section = "ram_vectors",
@@ -635,13 +652,20 @@ pub const startup_logic = struct {
         microzig_main();
     }
 
+    pub fn ramimage_start() callconv(.c) noreturn {
+        microzig_main();
+    }
+
     const VectorTable = microzig.chip.VectorTable;
 
     // will be imported by microzig.zig to allow system startup.
     pub const _vector_table: VectorTable = blk: {
         var tmp: VectorTable = .{
             .initial_stack_pointer = microzig.config.end_of_stack,
-            .Reset = .{ .c = microzig.cpu.startup_logic._start },
+            .Reset = .{ .c = if (is_ramimage())
+                microzig.cpu.startup_logic.ramimage_start
+            else
+                microzig.cpu.startup_logic._start },
         };
 
         for (@typeInfo(@TypeOf(microzig_options.interrupts)).@"struct".fields) |field| {
@@ -655,7 +679,21 @@ pub const startup_logic = struct {
     };
 };
 
+fn is_ramimage() bool {
+    // HACK
+    // TODO: Use microzig_options?
+    if (microzig.config.board_name) |board_name|
+        return std.mem.containsAtLeast(u8, board_name, 1, "ram image");
+    return false;
+}
+
 pub fn export_startup_logic() void {
+    if (is_ramimage())
+        @export(&ram_image_entrypoint, .{
+            .name = "_entry_point",
+            .linkage = .strong,
+        });
+
     @export(&startup_logic._start, .{
         .name = "_start",
     });
diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig
index 13ce2f48a..a2f68df2d 100644
--- a/examples/raspberrypi/rp2xxx/build.zig
+++ b/examples/raspberrypi/rp2xxx/build.zig
@@ -23,6 +23,8 @@ pub fn build(b: *std.Build) void {
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_hd44780", .file = "src/rp2040_only/hd44780.zig" },
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_pcf8574", .file = "src/rp2040_only/pcf8574.zig" },
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_i2c_slave", .file = "src/rp2040_only/i2c_slave.zig" },
+        // TODO: Fix
+        .{ .target = mb.ports.rp2xxx.chips.rp2040_ram_image, .name = "ram_blinky", .file = "src/blinky.zig" },
 
         // WaveShare Boards:
         .{ .target = mb.ports.rp2xxx.boards.waveshare.rp2040_matrix, .name = "rp2040-matrix_tiles", .file = "src/rp2040_only/tiles.zig" },
diff --git a/port/raspberrypi/rp2xxx/build.zig b/port/raspberrypi/rp2xxx/build.zig
index 113ec6536..29a11e222 100644
--- a/port/raspberrypi/rp2xxx/build.zig
+++ b/port/raspberrypi/rp2xxx/build.zig
@@ -5,6 +5,7 @@ const Self = @This();
 
 chips: struct {
     rp2040: *const microzig.Target,
+    rp2040_ram_image: *const microzig.Target,
     rp2350_arm: *const microzig.Target,
     rp2350_riscv: *const microzig.Target,
 },
@@ -141,6 +142,16 @@ pub fn init(dep: *std.Build.Dependency) Self {
     return .{
         .chips = .{
             .rp2040 = chip_rp2040.derive(.{}),
+            // This should probably be a board? Here it's a mix of a flash-less pico, so rp2040 on
+            // its own, but with an external oscillator
+            .rp2040_ram_image = chip_rp2040.derive(.{
+                .linker_script = b.path("rp2040_ram_image.ld"),
+                .board = .{
+                    .name = "RaspberryPi Pico (ram image)",
+                    .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/",
+                    .root_source_file = b.path("src/boards/raspberry_pi_pico2.zig"),
+                },
+            }),
             .rp2350_arm = chip_rp2350_arm.derive(.{}),
             .rp2350_riscv = chip_rp2350_riscv.derive(.{}),
         },
diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
new file mode 100644
index 000000000..a161d36c2
--- /dev/null
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -0,0 +1,66 @@
+/*
+ * This file was (not) auto-generated by microzig
+ *
+ * Target CPU:  ARM Cortex-M0+
+ * Target Chip: RP2040
+ */
+
+/* For ELFs this would set the entry, but for ucs it basically doesn't matter,
+ * though it should tell the linker that the symbol is referenced and to not
+ * optimize it away.
+ */
+ENTRY(_entry_point);
+
+MEMORY
+{
+  entry  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000100
+  ram0   (rwx) : ORIGIN = 0x20000100, LENGTH = 0x0003ff00
+}
+
+SECTIONS
+{
+  .entry :
+  {
+     KEEP(*(_entry_point))
+  } > entry
+
+  .text :
+  {
+     /* Using microzig_flash_start here because we put the vector table here */
+     KEEP(*(microzig_flash_start))
+     *(.text*)
+     *(.rodata*)
+  } > ram0
+
+  .ARM.extab : {
+      *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > ram0
+
+  .ARM.exidx : {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ram0
+
+  /* TODO: We would like to skip over the clearing of bss and writing of data since it's already in ram */
+  .data :
+  {
+     microzig_data_start = .;
+     KEEP(*(.time_critical*))
+     *(.data*)
+     microzig_data_end = .;
+  } > ram0
+
+  .bss :
+  {
+      microzig_bss_start = .;
+      *(.bss*)
+      microzig_bss_end = .;
+  } > ram0
+
+  .ram_vectors (NOLOAD) :
+  {
+    KEEP(*(ram_vectors))
+  } > ram0
+
+  /* Would not be used */
+  microzig_data_load_start = LOADADDR(.data);
+}

From 4243f5a6032f1665d0ea8b86bdc20ccb8652747f Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 10:32:30 -0400
Subject: [PATCH 02/14] Tuck ram_image_entrypoint into startup_logic

---
 core/src/cpus/cortex_m.zig | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index 6d10eb04e..91c9f4534 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -575,24 +575,6 @@ const vector_count = @sizeOf(microzig.chip.VectorTable) / @sizeOf(usize);
 
 var ram_vectors: [vector_count]usize align(256) = undefined;
 
-pub fn ram_image_entrypoint() linksection(".entry") callconv(.naked) void {
-    asm volatile (
-        \\
-        // Set VTOR to point to ram table
-        \\mov r0, %[_vector_table]
-        \\mov r1, %[_VTOR_ADDRESS]
-        \\str r0, [r1]
-        // Set up stack and jump to _start
-        \\ldm r0!, {r1, r2}
-        \\msr msp, r1
-        \\bx r2
-        :
-        : [_vector_table] "r" (&startup_logic._vector_table),
-          [_VTOR_ADDRESS] "r" (&peripherals.scb.VTOR),
-        : "memory", "r0", "r1", "r2"
-    );
-}
-
 pub const startup_logic = struct {
     extern fn microzig_main() noreturn;
 
@@ -605,6 +587,24 @@ pub const startup_logic = struct {
     extern var microzig_bss_end: u8;
     extern const microzig_data_load_start: u8;
 
+    pub fn ram_image_entrypoint() linksection(".entry") callconv(.naked) void {
+        asm volatile (
+            \\
+            // Set VTOR to point to ram table
+            \\mov r0, %[_vector_table]
+            \\mov r1, %[_VTOR_ADDRESS]
+            \\str r0, [r1]
+            // Set up stack and jump to _start
+            \\ldm r0!, {r1, r2}
+            \\msr msp, r1
+            \\bx r2
+            :
+            : [_vector_table] "r" (&startup_logic._vector_table),
+              [_VTOR_ADDRESS] "r" (&peripherals.scb.VTOR),
+            : "memory", "r0", "r1", "r2"
+        );
+    }
+
     pub fn _start() callconv(.c) noreturn {
         // fill .bss with zeroes
         {
@@ -689,7 +689,7 @@ fn is_ramimage() bool {
 
 pub fn export_startup_logic() void {
     if (is_ramimage())
-        @export(&ram_image_entrypoint, .{
+        @export(&startup_logic.ram_image_entrypoint, .{
             .name = "_entry_point",
             .linkage = .strong,
         });

From 9dade70c28abc1e2a03645eef1bcd3dc66fbbe7e Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 10:43:51 -0400
Subject: [PATCH 03/14] cleanup linker script

---
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index a161d36c2..2f095a4e3 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -1,14 +1,8 @@
 /*
- * This file was (not) auto-generated by microzig
- *
  * Target CPU:  ARM Cortex-M0+
  * Target Chip: RP2040
  */
 
-/* For ELFs this would set the entry, but for ucs it basically doesn't matter,
- * though it should tell the linker that the symbol is referenced and to not
- * optimize it away.
- */
 ENTRY(_entry_point);
 
 MEMORY
@@ -26,7 +20,6 @@ SECTIONS
 
   .text :
   {
-     /* Using microzig_flash_start here because we put the vector table here */
      KEEP(*(microzig_flash_start))
      *(.text*)
      *(.rodata*)
@@ -40,27 +33,13 @@ SECTIONS
       *(.ARM.exidx* .gnu.linkonce.armexidx.*)
   } > ram0
 
-  /* TODO: We would like to skip over the clearing of bss and writing of data since it's already in ram */
   .data :
   {
-     microzig_data_start = .;
-     KEEP(*(.time_critical*))
      *(.data*)
-     microzig_data_end = .;
   } > ram0
 
   .bss :
   {
-      microzig_bss_start = .;
       *(.bss*)
-      microzig_bss_end = .;
   } > ram0
-
-  .ram_vectors (NOLOAD) :
-  {
-    KEEP(*(ram_vectors))
-  } > ram0
-
-  /* Would not be used */
-  microzig_data_load_start = LOADADDR(.data);
 }

From bef5455e904d33a248c8e2a3d84baaa8d8057e9f Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 10:46:52 -0400
Subject: [PATCH 04/14] remove entry point setting in build.zig

---
 build.zig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/build.zig b/build.zig
index 10006bfd1..3f031881e 100644
--- a/build.zig
+++ b/build.zig
@@ -541,7 +541,6 @@ pub fn MicroBuild(port_select: PortSelect) type {
 
             fw.artifact.root_module.addImport("microzig", core_mod);
             fw.artifact.root_module.addImport("app", app_mod);
-            fw.artifact.entry = .{ .symbol_name = "_entry_point" };
 
             // If not specified then generate the linker script
             const linker_script = options.linker_script orelse target.linker_script orelse blk: {

From cfeb8f4739189bf6267aa7033547d308b5d6c653 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 10:53:23 -0400
Subject: [PATCH 05/14] define symbols in linker, even though unused

---
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index 2f095a4e3..30b3526fe 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -42,4 +42,11 @@ SECTIONS
   {
       *(.bss*)
   } > ram0
+
+  /* These symbols are not needed, but must be defined */
+  microzig_data_load_start = 0;
+  microzig_data_start = 0;
+  microzig_data_end = 0;
+  microzig_bss_start = 0;
+  microzig_bss_end = 0;
 }

From c8977296d37475eded750745ede11a845e70e088 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:00:11 -0400
Subject: [PATCH 06/14] rename microzig_flash_start section to .isr_vector

---
 core/src/cpus/cortex_m.zig                  | 2 +-
 port/raspberrypi/rp2xxx/rp2040.ld           | 2 +-
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index 91c9f4534..e6d51a82e 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -700,7 +700,7 @@ pub fn export_startup_logic() void {
 
     @export(&startup_logic._vector_table, .{
         .name = "_vector_table",
-        .section = "microzig_flash_start",
+        .section = ".isr_vector",
         .linkage = .strong,
     });
 }
diff --git a/port/raspberrypi/rp2xxx/rp2040.ld b/port/raspberrypi/rp2xxx/rp2040.ld
index 96bc53f02..1af1e86db 100644
--- a/port/raspberrypi/rp2xxx/rp2040.ld
+++ b/port/raspberrypi/rp2xxx/rp2040.ld
@@ -26,7 +26,7 @@ SECTIONS
 
   .text :
   {
-     KEEP(*(microzig_flash_start))
+     KEEP(*(.isr_vector))
      *(.text*)
      *(.rodata*)
   } > flash0
diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index 30b3526fe..db9e04a7e 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -20,7 +20,7 @@ SECTIONS
 
   .text :
   {
-     KEEP(*(microzig_flash_start))
+     KEEP(*(.isr_vector))
      *(.text*)
      *(.rodata*)
   } > ram0

From 7e2a1a0a7e440a335f1f38a97ab0aa34b8b365eb Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:12:53 -0400
Subject: [PATCH 07/14] use section not symbol?

---
 core/src/cpus/cortex_m.zig                  | 1 +
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index e6d51a82e..dc8e5f05a 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -691,6 +691,7 @@ pub fn export_startup_logic() void {
     if (is_ramimage())
         @export(&startup_logic.ram_image_entrypoint, .{
             .name = "_entry_point",
+            .section = ".entry",
             .linkage = .strong,
         });
 
diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index db9e04a7e..7d701e56b 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -15,7 +15,7 @@ SECTIONS
 {
   .entry :
   {
-     KEEP(*(_entry_point))
+     KEEP(*(.entry))
   } > entry
 
   .text :

From 480c8d93a1a23caf5b88e64192027b64637b1793 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:26:44 -0400
Subject: [PATCH 08/14] Revert "cleanup linker script"

This reverts commit 9dade70c28abc1e2a03645eef1bcd3dc66fbbe7e.
---
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index 7d701e56b..a5becd309 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -35,18 +35,24 @@ SECTIONS
 
   .data :
   {
+     microzig_data_start = .;
+     KEEP(*(.time_critical*))
      *(.data*)
+     microzig_data_end = .;
   } > ram0
 
   .bss :
   {
+      microzig_bss_start = .;
       *(.bss*)
+      microzig_bss_end = .;
   } > ram0
 
-  /* These symbols are not needed, but must be defined */
-  microzig_data_load_start = 0;
-  microzig_data_start = 0;
-  microzig_data_end = 0;
-  microzig_bss_start = 0;
-  microzig_bss_end = 0;
+  .ram_vectors (NOLOAD) :
+  {
+    KEEP(*(ram_vectors))
+  } > ram0
+
+  /* Would not be used */
+  microzig_data_load_start = LOADADDR(.data);
 }

From e4e5609deb72d03ffbabc0ed3654e07617b9d3c9 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:45:30 -0400
Subject: [PATCH 09/14] Combine both start functions

---
 core/src/cpus/cortex_m.zig | 80 ++++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 43 deletions(-)

diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
index dc8e5f05a..5421da9b6 100644
--- a/core/src/cpus/cortex_m.zig
+++ b/core/src/cpus/cortex_m.zig
@@ -606,66 +606,61 @@ pub const startup_logic = struct {
     }
 
     pub fn _start() callconv(.c) noreturn {
-        // fill .bss with zeroes
-        {
-            const bss_start: [*]u8 = @ptrCast(&microzig_bss_start);
-            const bss_end: [*]u8 = @ptrCast(&microzig_bss_end);
-            const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start);
+        if (comptime !is_ramimage()) {
+            // fill .bss with zeroes
+            {
+                const bss_start: [*]u8 = @ptrCast(&microzig_bss_start);
+                const bss_end: [*]u8 = @ptrCast(&microzig_bss_end);
+                const bss_len = @intFromPtr(bss_end) - @intFromPtr(bss_start);
+
+                @memset(bss_start[0..bss_len], 0);
+            }
 
-            @memset(bss_start[0..bss_len], 0);
-        }
+            // load .data from flash
+            {
+                const data_start: [*]u8 = @ptrCast(&microzig_data_start);
+                const data_end: [*]u8 = @ptrCast(&microzig_data_end);
+                const data_len = @intFromPtr(data_end) - @intFromPtr(data_start);
+                const data_src: [*]const u8 = @ptrCast(&microzig_data_load_start);
 
-        // load .data from flash
-        {
-            const data_start: [*]u8 = @ptrCast(&microzig_data_start);
-            const data_end: [*]u8 = @ptrCast(&microzig_data_end);
-            const data_len = @intFromPtr(data_end) - @intFromPtr(data_start);
-            const data_src: [*]const u8 = @ptrCast(&microzig_data_load_start);
+                @memcpy(data_start[0..data_len], data_src[0..data_len]);
+            }
 
-            @memcpy(data_start[0..data_len], data_src[0..data_len]);
-        }
+            // Move vector table to RAM if requested
+            if (interrupt.has_ram_vectors()) {
+                // Copy vector table to RAM and set VTOR to point to it
 
-        // Move vector table to RAM if requested
-        if (interrupt.has_ram_vectors()) {
-            // Copy vector table to RAM and set VTOR to point to it
-
-            if (comptime interrupt.has_ram_vectors_section()) {
-                @export(&ram_vectors, .{
-                    .name = "_ram_vectors",
-                    .section = "ram_vectors",
-                    .linkage = .strong,
-                });
-            } else {
-                @export(&ram_vectors, .{
-                    .name = "_ram_vectors",
-                    .linkage = .strong,
-                });
-            }
+                if (comptime interrupt.has_ram_vectors_section()) {
+                    @export(&ram_vectors, .{
+                        .name = "_ram_vectors",
+                        .section = "ram_vectors",
+                        .linkage = .strong,
+                    });
+                } else {
+                    @export(&ram_vectors, .{
+                        .name = "_ram_vectors",
+                        .linkage = .strong,
+                    });
+                }
 
-            const flash_vector: [*]const usize = @ptrCast(&_vector_table);
+                const flash_vector: [*]const usize = @ptrCast(&_vector_table);
 
-            @memcpy(ram_vectors[0..vector_count], flash_vector[0..vector_count]);
+                @memcpy(ram_vectors[0..vector_count], flash_vector[0..vector_count]);
 
-            peripherals.scb.VTOR = @intFromPtr(&ram_vectors);
+                peripherals.scb.VTOR = @intFromPtr(&ram_vectors);
+            }
         }
 
         microzig_main();
     }
 
-    pub fn ramimage_start() callconv(.c) noreturn {
-        microzig_main();
-    }
-
     const VectorTable = microzig.chip.VectorTable;
 
     // will be imported by microzig.zig to allow system startup.
     pub const _vector_table: VectorTable = blk: {
         var tmp: VectorTable = .{
             .initial_stack_pointer = microzig.config.end_of_stack,
-            .Reset = .{ .c = if (is_ramimage())
-                microzig.cpu.startup_logic.ramimage_start
-            else
-                microzig.cpu.startup_logic._start },
+            .Reset = .{ .c = microzig.cpu.startup_logic._start },
         };
 
         for (@typeInfo(@TypeOf(microzig_options.interrupts)).@"struct".fields) |field| {
@@ -691,7 +686,6 @@ pub fn export_startup_logic() void {
     if (is_ramimage())
         @export(&startup_logic.ram_image_entrypoint, .{
             .name = "_entry_point",
-            .section = ".entry",
             .linkage = .strong,
         });
 

From 5314cc18f47330e141b760375fbde71cc5930b2a Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:47:10 -0400
Subject: [PATCH 10/14] try to cleanup linker

---
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index a5becd309..efb70209b 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -35,24 +35,19 @@ SECTIONS
 
   .data :
   {
-     microzig_data_start = .;
      KEEP(*(.time_critical*))
      *(.data*)
-     microzig_data_end = .;
   } > ram0
 
   .bss :
   {
-      microzig_bss_start = .;
       *(.bss*)
-      microzig_bss_end = .;
   } > ram0
 
-  .ram_vectors (NOLOAD) :
-  {
-    KEEP(*(ram_vectors))
-  } > ram0
-
-  /* Would not be used */
-  microzig_data_load_start = LOADADDR(.data);
+  /* Unused, but set as extern in startup_logic */
+  microzig_data_start = .;
+  microzig_data_end = .;
+  microzig_bss_start = .;
+  microzig_bss_end = .;
+  microzig_data_load_start = .;
 }

From 168dbe317d1c367407ae783972a659b65bc4b45e Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 11:47:23 -0400
Subject: [PATCH 11/14] cleanup more

---
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 1 -
 1 file changed, 1 deletion(-)

diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index efb70209b..9d500415a 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -35,7 +35,6 @@ SECTIONS
 
   .data :
   {
-     KEEP(*(.time_critical*))
      *(.data*)
   } > ram0
 

From 6051dcbb6630924b41a1bb49937aaa196f987e46 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 12:45:52 -0400
Subject: [PATCH 12/14] convert ram image chip to flashless board

---
 examples/raspberrypi/rp2xxx/build.zig | 14 ++++----------
 port/raspberrypi/rp2xxx/build.zig     | 20 +++++++++-----------
 2 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig
index a2f68df2d..4fa403a2d 100644
--- a/examples/raspberrypi/rp2xxx/build.zig
+++ b/examples/raspberrypi/rp2xxx/build.zig
@@ -12,7 +12,7 @@ pub fn build(b: *std.Build) void {
     const mz_dep = b.dependency("microzig", .{});
     const mb = MicroBuild.init(b, mz_dep) orelse return;
 
-    const rp2040_only_examples: []const Example = &.{
+    const specific_examples: []const Example = &.{
         // RaspberryPi Boards:
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-program", .file = "src/rp2040_only/flash_program.zig" },
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_flash-id", .file = "src/rp2040_only/flash_id.zig" },
@@ -23,20 +23,15 @@ pub fn build(b: *std.Build) void {
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_hd44780", .file = "src/rp2040_only/hd44780.zig" },
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_pcf8574", .file = "src/rp2040_only/pcf8574.zig" },
         .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico, .name = "pico_i2c_slave", .file = "src/rp2040_only/i2c_slave.zig" },
-        // TODO: Fix
-        .{ .target = mb.ports.rp2xxx.chips.rp2040_ram_image, .name = "ram_blinky", .file = "src/blinky.zig" },
+        .{ .target = mb.ports.rp2xxx.boards.raspberrypi.pico_flashless, .name = "pico_flashless_blinky", .file = "src/blinky.zig" },
 
         // WaveShare Boards:
-        .{ .target = mb.ports.rp2xxx.boards.waveshare.rp2040_matrix, .name = "rp2040-matrix_tiles", .file = "src/rp2040_only/tiles.zig" },
+        .{ .target = mb.ports.rp2xxx.boards.waveshare.rp2040_matrix, .name = "rp2040_matrix_tiles", .file = "src/rp2040_only/tiles.zig" },
         // .{ .target = "board:waveshare/rp2040_eth", .name = "rp2040-eth" },
         // .{ .target = "board:waveshare/rp2040_plus_4m", .name = "rp2040-plus-4m" },
         // .{ .target = "board:waveshare/rp2040_plus_16m", .name = "rp2040-plus-16m" },
     };
 
-    const rp2350_only_examples: []const Example = &.{
-        // TODO: No RP2350 feature specific examples to show off yet
-    };
-
     const chip_agnostic_examples: []const ChipAgnosticExample = &.{
         .{ .name = "adc", .file = "src/adc.zig" },
         .{ .name = "i2c-bus-scan", .file = "src/i2c_bus_scan.zig" },
@@ -62,8 +57,7 @@ pub fn build(b: *std.Build) void {
     };
 
     var available_examples = std.ArrayList(Example).init(b.allocator);
-    available_examples.appendSlice(rp2040_only_examples) catch @panic("out of memory");
-    available_examples.appendSlice(rp2350_only_examples) catch @panic("out of memory");
+    available_examples.appendSlice(specific_examples) catch @panic("out of memory");
     for (chip_agnostic_examples) |example| {
         available_examples.append(.{
             .target = mb.ports.rp2xxx.boards.raspberrypi.pico,
diff --git a/port/raspberrypi/rp2xxx/build.zig b/port/raspberrypi/rp2xxx/build.zig
index 29a11e222..0e08f4f7f 100644
--- a/port/raspberrypi/rp2xxx/build.zig
+++ b/port/raspberrypi/rp2xxx/build.zig
@@ -5,7 +5,6 @@ const Self = @This();
 
 chips: struct {
     rp2040: *const microzig.Target,
-    rp2040_ram_image: *const microzig.Target,
     rp2350_arm: *const microzig.Target,
     rp2350_riscv: *const microzig.Target,
 },
@@ -16,6 +15,7 @@ boards: struct {
     },
     raspberrypi: struct {
         pico: *const microzig.Target,
+        pico_flashless: *const microzig.Target,
         pico2_arm: *const microzig.Target,
         pico2_riscv: *const microzig.Target,
     },
@@ -142,16 +142,6 @@ pub fn init(dep: *std.Build.Dependency) Self {
     return .{
         .chips = .{
             .rp2040 = chip_rp2040.derive(.{}),
-            // This should probably be a board? Here it's a mix of a flash-less pico, so rp2040 on
-            // its own, but with an external oscillator
-            .rp2040_ram_image = chip_rp2040.derive(.{
-                .linker_script = b.path("rp2040_ram_image.ld"),
-                .board = .{
-                    .name = "RaspberryPi Pico (ram image)",
-                    .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/",
-                    .root_source_file = b.path("src/boards/raspberry_pi_pico2.zig"),
-                },
-            }),
             .rp2350_arm = chip_rp2350_arm.derive(.{}),
             .rp2350_riscv = chip_rp2350_riscv.derive(.{}),
         },
@@ -174,6 +164,14 @@ pub fn init(dep: *std.Build.Dependency) Self {
                         .imports = rp2040_bootrom_imports,
                     },
                 }),
+                .pico_flashless = chip_rp2040.derive(.{
+                    .linker_script = b.path("rp2040_ram_image.ld"),
+                    .board = .{
+                        .name = "RaspberryPi Pico (ram image)",
+                        .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/",
+                        .root_source_file = b.path("src/boards/raspberry_pi_pico2.zig"),
+                    },
+                }),
                 .pico2_arm = chip_rp2350_arm.derive(.{
                     .board = .{
                         .name = "RaspberryPi Pico 2",

From 8d07e06460b28c8e193967fb9cd8f99640cc4e95 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 13:59:39 -0400
Subject: [PATCH 13/14] Allow firmware options and mz.Target to set entry point

---
 build-internals/build.zig | 5 +++++
 build.zig                 | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/build-internals/build.zig b/build-internals/build.zig
index ca7866944..8a157f522 100644
--- a/build-internals/build.zig
+++ b/build-internals/build.zig
@@ -57,6 +57,9 @@ pub const Target = struct {
     /// (optional) Provide a custom linker script for the hardware or define a custom generation.
     linker_script: ?LazyPath = null,
 
+    /// (Optional) Explicitly set the entry point
+    entry: ?Build.Step.Compile.Entry = null,
+
     /// (optional) Post processing step that will patch up and modify the elf file if necessary.
     patch_elf: ?*const fn (*Build.Dependency, LazyPath) LazyPath = null,
 
@@ -71,6 +74,7 @@ pub const Target = struct {
         hal: ?HardwareAbstractionLayer = null,
         board: ?Board = null,
         linker_script: ?LazyPath = null,
+        entry: ?Build.Step.Compile.Entry = null,
         patch_elf: ?*const fn (*Build.Dependency, LazyPath) LazyPath = null,
     };
 
@@ -88,6 +92,7 @@ pub const Target = struct {
             .hal = options.hal orelse from.hal,
             .board = options.board orelse from.board,
             .linker_script = options.linker_script orelse from.linker_script,
+            .entry = options.entry orelse from.entry,
             .patch_elf = options.patch_elf orelse from.patch_elf,
         };
         return ret;
diff --git a/build.zig b/build.zig
index 3f031881e..065a20429 100644
--- a/build.zig
+++ b/build.zig
@@ -332,6 +332,9 @@ pub fn MicroBuild(port_select: PortSelect) type {
             /// If set, overrides the `linker_script` property of the target.
             linker_script: ?LazyPath = null,
 
+            /// If set, overrides the default `entry` property of the arget.
+            entry: ?Build.Step.Compile.Entry = null,
+
             /// Strips stack trace info from final executable.
             strip: bool = false,
 
@@ -538,6 +541,7 @@ pub fn MicroBuild(port_select: PortSelect) type {
             fw.artifact.link_gc_sections = options.strip_unused_symbols;
             fw.artifact.link_function_sections = options.strip_unused_symbols;
             fw.artifact.link_data_sections = options.strip_unused_symbols;
+            fw.artifact.entry = options.entry orelse target.entry orelse .default;
 
             fw.artifact.root_module.addImport("microzig", core_mod);
             fw.artifact.root_module.addImport("app", app_mod);

From 697333982348e89a70aaff14eab6b34553ee3f11 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Wed, 14 May 2025 14:00:24 -0400
Subject: [PATCH 14/14] Explicitly set entry point for flashless board

---
 port/raspberrypi/rp2xxx/build.zig           | 1 +
 port/raspberrypi/rp2xxx/rp2040_ram_image.ld | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/port/raspberrypi/rp2xxx/build.zig b/port/raspberrypi/rp2xxx/build.zig
index 0e08f4f7f..b92965d18 100644
--- a/port/raspberrypi/rp2xxx/build.zig
+++ b/port/raspberrypi/rp2xxx/build.zig
@@ -165,6 +165,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
                     },
                 }),
                 .pico_flashless = chip_rp2040.derive(.{
+                    .entry = .{ .symbol_name = "_entry_point" },
                     .linker_script = b.path("rp2040_ram_image.ld"),
                     .board = .{
                         .name = "RaspberryPi Pico (ram image)",
diff --git a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
index 9d500415a..ed36bf7df 100644
--- a/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
+++ b/port/raspberrypi/rp2xxx/rp2040_ram_image.ld
@@ -3,8 +3,6 @@
  * Target Chip: RP2040
  */
 
-ENTRY(_entry_point);
-
 MEMORY
 {
   entry  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00000100