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Vadlamudi04Vadlamudi04
authoredDec 10, 2024
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‎sizing_sheets/135n_externalcompensated_heavyload.csv

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1+
Step 1: List Down the Specifications and classify them,,,,,,,,
2+
,,,,,,,,
3+
,Value,Units,Comments,,,,,
4+
,,,,,,,,
5+
Vin,1.4,V,,,,,,
6+
Vout,1,V,Relaxed,,,,,
7+
PSRR,60,dB,Aggressive,,,,,
8+
Iload|max,10,mA,Moderate,,,,,
9+
Cload,1,uF,Aggressive,,,,,
10+
Iquiescent,50,?A,Moderate,,,,,
11+
,,,,,,,,
12+
Step 2: Evaluate Interim Design Goals,,,,,,,,
13+
,,,,,,,,
14+
Low Freq Loop Gain,1000,V/V,,,,,Keep Loop Gain Margin vs. PSRR (PSRR will degrade),
15+
Drop Out Voltage,0.4,V,,,,,,
16+
,,,,,,,,
17+
Step 3: Power FET Sizing,,,,,,,,
18+
,,,,,,,,
19+
Power FET,,,,,,,,
20+
,Hand/Techplots Calculations,,,Comments,,,,
21+
gm/Id,10,1/V,,Assumption for Vov=200mV; Vov<Vdsat,,,,
22+
Id/W,24.86,A/m,24.86,From Id/W vs. gm/Id plot,,,,
23+
Id,0.01,A,,,,,,
24+
W,0.000402253,m,,,,,,
25+
gmro,73.125,V/V,73.125,,,,,
26+
ft,1.26E+10,Hz,12575424613,,,,,
27+
Length,0.135,?m,0.135,,,,,
28+
gm,1.00E-01,A/V,,,,,,
29+
ro,7.31E+02,Ohm,,,,,,
30+
Cgs+Cgd,1.27E-12,F,,,,,,
31+
,,,,,,,,
32+
Step 4: Revaluate Interim Design Parameters,,,,,,,,
33+
wp1,1.37E+03,,,,,,,
34+
wp2,1.37E+06,rad/s,,,gmpass/Cl,For >45 degrees phase margin,,
35+
fp1,2.18E+02,,,,gmn/Cc,,,
36+
Adiffamp_min,13.67521368,,,,gm*(ron||rop),,,
37+
Adiff_n_min,27.35042735,,,,gmron,,,
38+
rodiff,5.78E+05,,1.37E+06,,1/wp2/Cgg,,,
39+
fp2,2.18E+05,,2.74E+06,2.18E+05,,,,
40+
Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,,,,,
41+
,Hand Calculation.,,,,,,,
42+
gm/Iddiff,1.00E+01,,9.47E-01,,,,We want to make sure that the Bias fet has enough headroom,
43+
Id,0.000025,A,,,,,Taking all budget available and check later,
44+
gmro,27.35042735,,7.30E+01,,,,Vds for heavy load lower,
45+
Length,0.08,um,,,,,Get the length for the desired gain from the techplots (gmro vs. gm/Id),
46+
Id/W,60,A/m,80,,,,,
47+
W,4.16667E-07,um,,,,,,
48+
gm,0.00025,,,,,,,
49+
ro,109401.7094,,,,,,,
50+
,,,,,,,,
51+
Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,,,,,
52+
Id,0.000025,,,,,,,
53+
gm/Idload,10,,,,,,,
54+
gmro,27.35042735,73,27.35,36.82,73.125,,,
55+
Length,0.09,0.135,0.08,,,,Please simulate for Vds of 0.5 everything and you are good to go,
56+
gm,0.00025,,,,,,,
57+
Id/W,41.38,,36.78,,,,,
58+
W,6.04157E-07,,,,,,,
59+
ro,109401.7094,,,,,,,
60+
,,,,,,,,
61+
rocheck,54700.8547,,,,,,,
62+
,,,,,,,,
63+
,,,,,,,,
64+
Step 7: Performance Results,,,,,,,,
65+
,,Expected,Simulated,,,,,
66+
Low-Frequency Loop Gain,,60 dB,61 dB,,,,,
67+
fp1,,218 Hz,214H z,,,,,
68+
fp2,,218 kHz,214 kHz,,,,,
69+
Phase margin,,>45 deg,50 degrees,?,,,,

‎sizing_sheets/135n_externalcompensated_lightload.csv

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1+
Step 1: List Down the Specifications and classify them,,,,
2+
,,,,
3+
,,Value,,Notes
4+
,,,,
5+
Vin,,1.4,,
6+
Vout,,1,,
7+
PSRR,,60,,20*log(Vin/Vout) You can also have it as 20*log(Vout/Vin) and then report PSRR as negative
8+
Iload|min,,2,,
9+
Iload|max,,10,,
10+
Cload,,2,,
11+
Iquiescent,,50,,
12+
Transient duration,,1,,
13+
,,,,
14+
Step 2: Evaluate Interim Design Goals,,,,
15+
,,,,
16+
Low Freq Loop Gain (Alg),,1000,,
17+
Drop Out Voltage,,0.4,,Vin-Vout of the LDO
18+
?I (Load step),,0.008,,Imax-Imin
19+
,,,,
20+
wumin,,1000000,,1/tau or transient duration
21+
,,,,
22+
Step 3: Power FET Sizing,,,,
23+
,,,,
24+
Power FET,,,,
25+
,,Hand/Techplots Calculations,,
26+
gm/Id,,10,,Proxy for 200 mV Vov (You can change it later as long as you guarantee the transistor in saturation)
27+
Id/W,,24.8608,,From techplots of PMOS
28+
Id,,0.01,,Design for max load
29+
W,,0.00040224,,Id/(Id/W)
30+
Apass_heavy (gmro),,73.125,,From techplots
31+
ft,,1.26E+10,,From techplots
32+
Length,,0.135,,Minimum length to keep pass fet area low
33+
gm,,1.00E-01,,gm/Id * Id
34+
ro,,7.31E+02,,gmro/gm
35+
Cgs+Cgd,,1.27E-12,,ft/gm/2pi
36+
LIGHT LOAD,,,,Worst Case Stability Condition
37+
Id,,2.00E-03,,Imin
38+
Id/W,,4.97E+00,,Imin/Width derived above
39+
gm/Id,,18,,From techplots
40+
gmro,,83.53,,From techplots
41+
Low-frequency loop gain light load,,1142.290598,,Apass scales by gmro_light/gmro_heavy. Same scaling factor for Loop Gain : So 1000*(65/33)
42+
gmlight,,3.60E-02,,gm/Id*Id
43+
,,,,
44+
Step 4: Revaluate Interim Design Parameters,,,,
45+
,,,,
46+
wp2heavy,,5.00E+07,,gmpass_heavy/CL
47+
wp2light,,1.80E+07,,gmpass_light/CL
48+
fp2light,,2.86E+06,,gmpass_light/CL/2pi
49+
Adiffamp_min,,14,,Alg/Apass_heavy
50+
Adiff_n_min,,28,,Adiffamp_min*2 : Diffamp gain is gmro/2 so gmro is 2*Adiffamp_min
51+
wp1,,1.58E+04,,Adiffamp_min
52+
fp1,,2.51E+03,,
53+
Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,
54+
,,Hand Calculation.,,
55+
gm/Iddiff,,10,,"Again, proxy for 200 mV"
56+
Id,,0.000025,,Ibias/2
57+
gmro,,28,,"From NMOS techplots: Choose higher, a little overdesigned"
58+
Length,,0.08,,From NMOS techplots
59+
Id/W,,60,,From NMOS techplots
60+
W,,0.416666667,,Id/(Id/W)
61+
gm,,0.00025,,gm/Id * Id
62+
ro,,112000,,gmro/gm
63+
,,,,
64+
Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,
65+
Id,,0.000025,,Ibias/2
66+
gm/Iddiff,,10,,Match with the gm/Id of Pass FET for reduced Vds mismatch
67+
gmro,,28,,From PMOS Techplots
68+
Length,,0.09,,"If you don�t have exact Vds techplots, then choose the length accordingly. For us, we have techplots for Vds of 0.4 and Vds of Pload is Vt+Vov (>0.7V)"
69+
gm,,0.00025,,gm/Id*Id
70+
Id/W,,41.38,,From PMOS Techplots
71+
W,,6.04157E-07,,Id/(Id/W)
72+
ro,,112000,,gmro/gm
73+
,,,,
74+
,,,,
75+
,,,,
76+
Sizing CC,,,,
77+
rodiff,,56000,,rop||ron
78+
Cc+Cgd,,1.36E-11,,1/wp1/rodiff/Apass
79+
Cgg,,1.27E-12,,From gmpass fT
80+
Cgd,,4.18E-13,,For our technology Cgd is 0.33*Cgg in Saturation
81+
Cc,,1.31E-11,,(Cc+Cgd)-Cgd

‎sizing_sheets/135n_internalcompensated.csv

+69
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1+
,Step 1: List Down the Specifications and classify them,,,,,,,,
2+
,,,,,,,,,
3+
,,Value,Units,Comments,,,,,
4+
,,,,,,,,,
5+
,Vin,1.4,V,,,,,,
6+
,Vout,1,V,Relaxed,,,,,
7+
,PSRR,60,dB,Aggressive,,,,,
8+
,Iload|max,2,mA,Moderate,,,,,
9+
,Cload,1,uF,Aggressive,,,,,
10+
,Iquiescent,50,?A,Moderate,,,,,
11+
,,,,,,,,,
12+
,Step 2: Evaluate Interim Design Goals,,,,,,,,
13+
,,,,,,,,,
14+
,Low Freq Loop Gain,1000,V/V,,,,,Keep Loop Gain Margin vs. PSRR (PSRR will degrade),
15+
,Drop Out Voltage,0.4,V,,,,,,
16+
,,,,,,,,,
17+
,Step 3: Power FET Sizing,,,,,,,,
18+
,,,,,,,,,
19+
,Power FET,,,,,,,,
20+
,,Hand/Techplots Calculations,,,Comments,,,,
21+
,gm/Id,10,1/V,,Assumption for Vov=200mV; Vov<Vdsat,,,,
22+
,Id/W,24.86,A/m,24.86,From Id/W vs. gm/Id plot,,,,
23+
,Id,0.002,A,,,,,,
24+
,W,8.04505E-05,m,,,,,,
25+
,gmro,73.125,V/V,73.125,,,,,
26+
,ft,1.26E+10,Hz,12575424613,,,,,
27+
,Length,0.135,?m,0.135,,,,,
28+
,gm,2.00E-02,A/V,,,,,,
29+
,ro,3.66E+03,Ohm,,,,,,
30+
,Cgs+Cgd,2.53E-13,F,,,,,,
31+
,,,,,,,,,
32+
,Step 4: Revaluate Interim Design Parameters,,,,,,,,
33+
,wp1,2.74E+02,,,,,,,
34+
,wp2,2.74E+05,rad/s,,,gmpass/Cl,For >45 degrees phase margin,,
35+
,fp1,4.35E+01,,,,gmn/Cc,,,
36+
,Adiffamp_min,13.67521368,,,,gm*(ron||rop),,,
37+
,Adiff_n_min,27.35042735,,2.74E+05,,gmron,,,
38+
,rodiff,1.44E+07,,,,1/wp2/Cgg,,,
39+
,fp2,,,5.47E+05,4.36E+04,,,,
40+
,Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,,,,,
41+
,,Hand Calculation.,,,,,,,
42+
,gm/Iddiff,1.00E+01,,3.79E-02,,,,We want to make sure that the Bias fet has enough headroom,
43+
,Id,0.000025,A,,,,,Taking all budget available and check later,
44+
,gmro,27.35042735,,7.30E+01,,,,Vds for heavy load lower,
45+
,Length,0.08,um,,,,,Get the length for the desired gain from the techplots (gmro vs. gm/Id),
46+
,Id/W,60,A/m,80,,,,,
47+
,W,4.16667E-07,um,,,,,,
48+
,gm,0.00025,,,,,,,
49+
,ro,109401.7094,,,,,,,
50+
,,,,,,,,,
51+
,Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,,,,,
52+
,Id,0.000025,,,,,,,
53+
,gm/Idload,10,,,,,,,
54+
,gmro,27.35042735,73,27.35,36.82,73.125,,,
55+
,Length,0.09,0.135,0.08,,,,Please simulate for Vds of 0.5 everything and you are good to go,
56+
,gm,0.00025,,,,,,,
57+
,Id/W,41.38,,36.78,,,,,
58+
,W,6.04157E-07,,,,,,,
59+
,ro,109401.7094,,,,,,,
60+
,,,,,,,,,
61+
,rocheck,54700.8547,,,,,,,
62+
,,,,,,,,,
63+
,,,,,,,,,
64+
,Step 7: Performance Results,,,,,,,,
65+
,,,Expected,Simulated,,,,,
66+
,Low-Frequency Loop Gain,,60 dB,61 dB,,,,,
67+
,fp1,,218 Hz,214H z,,,,,
68+
,fp2,,218 kHz,214 kHz,,,,,
69+
,Phase margin,,>45 deg,50 degrees,?,,,,

‎sizing_sheets/90nm_externalcompensated_heavyload.csv

+71
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@@ -0,0 +1,71 @@
1+
Step 1: List Down the Specifications and classify them,,,,,,,,
2+
,,,,,,,,
3+
,Value,Units,Comments,,,,,
4+
,,,,,,,,
5+
Vin,1.4,V,,,,,,
6+
Vout,1,V,Relaxed,,,,,
7+
PSRR,60,dB,Aggressive,,,,,
8+
Iload|max,10,mA,Moderate,,,,,
9+
Cload,1,uF,Aggressive,,,,,
10+
Iquiescent,50,?A,Moderate,,,,,
11+
,,,,,,,,
12+
Step 2: Evaluate Interim Design Goals,,,,,,,,
13+
,,,,,,,,
14+
Low Freq Loop Gain,1000,V/V,,,,,Keep Loop Gain Margin vs. PSRR (PSRR will degrade),
15+
Drop Out Voltage,0.4,V,,,,,,
16+
,,,,,,,,
17+
Step 3: Power FET Sizing,,,,,,,,
18+
,,,,,,,,
19+
Power FET,,,,,,,,
20+
,Hand/Techplots Calculations,,,Comments,,,,
21+
gm/Id,10,1/V,,Assumption for Vov=200mV; Vov<Vdsat,,,,
22+
Id/W,41.38,A/m,,From Id/W vs. gm/Id plot,,,,
23+
Id,0.01,A,,,,,,
24+
W,0.000241663,m,,,,,,
25+
gmro,36.8,V/V,,,,,,
26+
ft,2.98E+10,Hz,,,,,,
27+
Length,0.09,?m,,,,,,
28+
gm,1.00E-01,A/V,,,,,,
29+
ro,3.68E+02,Ohm,,,,,,
30+
Cgs+Cgd,5.34E-13,F,,,,,,
31+
,,,,,,,,
32+
Step 4: Revaluate Interim Design Parameters,,,,,,,,
33+
wp1,2.72E+03,,,,,,,
34+
wp2,2.72E+06,rad/s,,,gmpass/Cl,For >45 degrees phase margin,,
35+
fp1,4.32E+02,,,,gmn/Cc,,,
36+
Adiffamp_min,27.17391304,,,,gm*(ron||rop),,,
37+
Adiff_n_min,54.34782609,,2.72E+06,,gmron,,,
38+
rodiff,6.89E+05,,,,1/wp2/Cgg,,,
39+
fp2,4.32E+05,8.61E+06,4.33E+05,,,,,
40+
Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,,,,,
41+
,Hand Calculation.,,,,,,,
42+
gm/Iddiff,1.00E+01,,1.58E+00,,,,We want to make sure that the Bias fet has enough headroom,
43+
Id,0.000025,A,,,,,Taking all budget available and check later,
44+
gmro,54.34782609,,7.30E+01,,,,Vds for heavy load lower,
45+
Length,0.09,um,,,,,Get the length for the desired gain from the techplots (gmro vs. gm/Id),
46+
Id/W,89.96,A/m,80,,,,,
47+
W,2.77901E-07,um,,,,,,
48+
gm,0.00025,,,,,,,
49+
ro,217391.3044,,,,,,,
50+
,,,,,,,,
51+
Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,,,,,
52+
Id,0.000025,,,,,,,
53+
gm/Idload,10,,,,,,,
54+
gmro,54.34782609,73,27.35,36.82,73.125,,,
55+
Length,0.09,0.135,0.08,,,,Please simulate for Vds of 0.5 everything and you are good to go,
56+
gm,0.00025,,,,,,,
57+
Id/W,41.38,,36.78,,,,,
58+
W,6.04157E-07,,,,,,,
59+
ro,217391.3043,,,,,,,
60+
,,,,,,,,
61+
rocheck,108695.6522,,,,,,,
62+
,,,,,,,,
63+
,,,,,,,,
64+
Step 7: Performance Results,,,,,,,,
65+
,,Expected,Simulated,,,,,
66+
Low-Frequency Loop Gain,,60 dB,61 dB,,,,,
67+
fp1,,218 Hz,214H z,,,,,
68+
fp2,,218 kHz,214 kHz,,,,,
69+
Phase margin,,>45 deg,50 degrees,?,,,,
70+
,,,,,,,,
71+
5.43E+06,,,,,,,,

‎sizing_sheets/90nm_externalcompensated_lightload.csv

+71
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@@ -0,0 +1,71 @@
1+
lowload,,,,,,,,,
2+
,,,,,,,,,
3+
,Step 1: List Down the Specifications and classify them,,,,,,,,
4+
,,,,,,,,,
5+
,,Value,Units,Comments,,,,,
6+
,,,,,,,,,
7+
,Vin,1.4,V,,,,,,
8+
,Vout,1,V,Relaxed,,,,,
9+
,PSRR,60,dB,Aggressive,,,,,
10+
,Iload|max,2,mA,Moderate,,,,,
11+
,Cload,1,uF,Aggressive,,,,,
12+
,Iquiescent,50,?A,Moderate,,,,,
13+
,,,,,,,,,
14+
,Step 2: Evaluate Interim Design Goals,,,,,,,,
15+
,,,,,,,,,
16+
,Low Freq Loop Gain,1000,V/V,,,,,Keep Loop Gain Margin vs. PSRR (PSRR will degrade),
17+
,Drop Out Voltage,0.4,V,,,,,,
18+
,,,,,,,,,
19+
,Step 3: Power FET Sizing,,,,,,,,
20+
,,,,,,,,,
21+
,Power FET,,,,,,,,
22+
,,Hand/Techplots Calculations,,,Comments,,,,
23+
,gm/Id,10,1/V,,Assumption for Vov=200mV; Vov<Vdsat,,,,
24+
,Id/W,41.38,A/m,,From Id/W vs. gm/Id plot,,,,
25+
,Id,0.002,A,,,,,,
26+
,W,4.83325E-05,m,,,,,,
27+
,gmro,36.8,V/V,,,,,,
28+
,ft,2.98E+10,Hz,,,,,,
29+
,Length,0.09,?m,,,,,,
30+
,gm,2.00E-02,A/V,,,,,,
31+
,ro,1.84E+03,Ohm,,,,,,
32+
,Cgs+Cgd,1.07E-13,F,,,,,,
33+
,,,,,,,,,
34+
,Step 4: Revaluate Interim Design Parameters,,,,,,,,
35+
,wp1,5.43E+02,,,,,,,
36+
,wp2,5.43E+05,rad/s,,,gmpass/Cl,For >45 degrees phase margin,,
37+
,fp1,8.65E+01,,,,gmn/Cc,,,
38+
,Adiffamp_min,27.17391304,,,,gm*(ron||rop),,,
39+
,Adiff_n_min,54.34782609,,,,gmron,,,
40+
,rodiff,1.72E+07,,,,1/wp2/Cgg,,,
41+
,fp2,,,5.43E+05,,,,,
42+
,Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,,,,,
43+
,,Hand Calculation.,,,,,,,
44+
,gm/Iddiff,1.00E+01,,6.31E-02,,,,We want to make sure that the Bias fet has enough headroom,
45+
,Id,0.000025,A,,,,,Taking all budget available and check later,
46+
,gmro,54.34782609,,7.30E+01,,,,Vds for heavy load lower,
47+
,Length,0.09,um,,,,,Get the length for the desired gain from the techplots (gmro vs. gm/Id),
48+
,Id/W,89.96,A/m,80,,,,,
49+
,W,2.77901E-07,um,,,,,,
50+
,gm,0.00025,,,,,,,
51+
,ro,217391.3044,,,,,,,
52+
,,,,,,,,,
53+
,Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,,,,,
54+
,Id,0.000025,,,,,,,
55+
,gm/Idload,10,,,,,,,
56+
,gmro,54.34782609,73,27.35,36.82,73.125,,,
57+
,Length,0.09,0.135,0.08,,,,Please simulate for Vds of 0.5 everything and you are good to go,
58+
,gm,0.00025,,,,,,,
59+
,Id/W,41.38,,36.78,,,,,
60+
,W,6.04157E-07,,,,,,,
61+
,ro,217391.3043,,,,,,,
62+
,,,,,,,,,
63+
,rocheck,108695.6522,,,,,,,
64+
,,,,,,,,,
65+
,,,,,,,,,
66+
,Step 7: Performance Results,,,,,,,,
67+
,,,Expected,Simulated,,,,,
68+
,Low-Frequency Loop Gain,,60 dB,61 dB,,,,,
69+
,fp1,,218 Hz,214H z,,,,,
70+
,fp2,,218 kHz,214 kHz,,,,,
71+
,Phase margin,,>45 deg,50 degrees,?,,,,

‎sizing_sheets/90nm_internalcompensated.csv

+81
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@@ -0,0 +1,81 @@
1+
Step 1: List Down the Specifications and classify them,,,,
2+
,,,,
3+
,,Value,,Notes
4+
,,,,
5+
Vin,,1.4,,
6+
Vout,,1,,
7+
PSRR,,60,,20*log(Vin/Vout) You can also have it as 20*log(Vout/Vin) and then report PSRR as negative
8+
Iload|min,,2,,
9+
Iload|max,,10,,
10+
Cload,,2,,
11+
Iquiescent,,50,,
12+
Transient duration,,1,,
13+
,,,,
14+
Step 2: Evaluate Interim Design Goals,,,,
15+
,,,,
16+
Low Freq Loop Gain (Alg),,1000,,
17+
Drop Out Voltage,,0.4,,Vin-Vout of the LDO
18+
?I (Load step),,0.008,,Imax-Imin
19+
,,,,
20+
wumin,,1000000,,1/tau or transient duration
21+
,,,,
22+
Step 3: Power FET Sizing,,,,
23+
,,,,
24+
Power FET,,,,
25+
,,Hand/Techplots Calculations,,
26+
gm/Id,,10,,Proxy for 200 mV Vov (You can change it later as long as you guarantee the transistor in saturation)
27+
Id/W,,41.3831,,From techplots of PMOS
28+
Id,,0.01,,Design for max load
29+
W,,0.000241645,,Id/(Id/W)
30+
Apass_heavy (gmro),,36.8,,From techplots
31+
ft,,2.98E+10,,From techplots
32+
Length,,0.09,,Minimum length to keep pass fet area low
33+
gm,,1.00E-01,,gm/Id * Id
34+
ro,,3.68E+02,,gmro/gm
35+
Cgs+Cgd,,5.34E-13,,ft/gm/2pi
36+
LIGHT LOAD,,,,Worst Case Stability Condition
37+
Id,,2.00E-03,,Imin
38+
Id/W,,8.28E+00,,Imin/Width derived above
39+
gm/Id,,17,,From techplots
40+
gmro,,40.36,,From techplots
41+
Low-frequency loop gain light load,,1096.73913,,Apass scales by gmro_light/gmro_heavy. Same scaling factor for Loop Gain : So 1000*(65/33)
42+
gmlight,,3.40E-02,,gm/Id*Id
43+
,,,,
44+
Step 4: Revaluate Interim Design Parameters,,,,
45+
,,,,
46+
wp2heavy,,5.00E+07,,gmpass_heavy/CL
47+
wp2light,,1.70E+07,,gmpass_light/CL
48+
fp2light,,2.71E+06,,gmpass_light/CL/2pi
49+
Adiffamp_min,,27,,Alg/Apass_heavy
50+
Adiff_n_min,,54,,Adiffamp_min*2 : Diffamp gain is gmro/2 so gmro is 2*Adiffamp_min
51+
wp1,,1.55E+04,,Adiffamp_min
52+
fp1,,2.47E+03,,
53+
Step 5: Diffamp Input Pair Sizing (Heavy load error will be higher than light load because we used light load Charts),,,,
54+
,,Hand Calculation.,,
55+
gm/Iddiff,,10,,"Again, proxy for 200 mV"
56+
Id,,0.000025,,Ibias/2
57+
gmro,,54,,"From NMOS techplots: Choose higher, a little overdesigned"
58+
Length,,0.09,,From NMOS techplots
59+
Id/W,,89.96,,From NMOS techplots
60+
W,,0.277901289,,Id/(Id/W)
61+
gm,,0.00025,,gm/Id * Id
62+
ro,,216000,,gmro/gm
63+
,,,,
64+
Step 6: PMOS Load sizing (Vds assumed to be 0.4 for techplots - which can change),,,,
65+
Id,,0.000025,,Ibias/2
66+
gm/Iddiff,,10,,Match with the gm/Id of Pass FET for reduced Vds mismatch
67+
gmro,,54,,From PMOS Techplots
68+
Length,,0.09,,"If you don�t have exact Vds techplots, then choose the length accordingly. For us, we have techplots for Vds of 0.4 and Vds of Pload is Vt+Vov (>0.7V)"
69+
gm,,0.00025,,gm/Id*Id
70+
Id/W,,41.38,,From PMOS Techplots
71+
W,,6.04157E-07,,Id/(Id/W)
72+
ro,,216000,,gmro/gm
73+
,,,,
74+
,,,,
75+
,,,,
76+
Sizing CC,,,,
77+
rodiff,,108000,,rop||ron
78+
Cc+Cgd,,1.48E-11,,1/wp1/rodiff/Apass
79+
Cgg,,5.34E-13,,From gmpass fT
80+
Cgd,,1.76E-13,,For our technology Cgd is 0.33*Cgg in Saturation
81+
Cc,,1.46E-11,,(Cc+Cgd)-Cgd

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