Lifting for PC-relative `vldr` instruction does not align PC when calculating address

[whitequark]

Version and Platform (required):

• Binary Ninja Version: 5.1.7598-test Ultimate (0e5168d7)
• Edition: Ultimate
• OS: Debian Linux
• OS Version: 13
• CPU Architecture: x86_64

Bug Description:
This vldr instruction:

Loads from 802808a:

However, consulting the ARM ARM for VLDR, it's clear that the base address is word aligned when PC is the base register:

Since the address expression is [pc, 0x58], where the displacement is a multiple of 4, the instruction cannot be loading anything from an address ending in ...a.

Steps To Reproduce:

1. Open attached BNDB

Expected Behavior:
Load from the correct address.

Binary:
bug_vfp.zip

[whitequark]

The actual literal it's loading is 100.0, from 8028088.

[plafosse]

Broken lifting is here:

Armv7:

binaryninja-api/arch/armv7/il.cpp

Line 4962 in 5320c69

case ARMV7_VLDR:

Thumb2:

binaryninja-api/arch/armv7/thumb2_disasm/il_thumb2.cpp

Line 2041 in 5320c69

case armv7::ARMV7_VLDR: