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verilator --lint-only --Wall --Wno-DECLFILENAME --Wno-EOFNEWLINE --top-module tt_um_openram_top /workspaces/tt25a_openram_testchip/runs/wokwi/01-verilator-lint/_deps.vlt /workspaces/tt25a_openram_testchip/runs/wokwi/tmp/48678ef3245f4d87a07c526d46588fac.bb.v /workspaces/tt25a_openram_testchip/runs/wokwi/tmp/679491210445499ba08cfc4ebf0bf9da.bb.v /workspaces/tt25a_openram_testchip/src/defs.v /workspaces/tt25a_openram_testchip/src/project.v /workspaces/tt25a_openram_testchip/src/scan_cell_2ph.v /workspaces/tt25a_openram_testchip/src/scan_chain_2ph.v /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v --Wno-fatal --relative-includes --Werror-LATCH +define+PDK_sky130A +define+SCL_sky130_fd_sc_hd +define+__openlane__ +define+__pnr__ +define+USE_POWER_PINS
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`verilator_config
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lint_off -rule DECLFILENAME
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lint_off -rule EOFNEWLINE
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lint_off -rule UNDRIVEN -file "/workspaces/tt25a_openram_testchip/runs/wokwi/tmp/48678ef3245f4d87a07c526d46588fac.bb.v"
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lint_off -rule UNUSEDSIGNAL -file "/workspaces/tt25a_openram_testchip/runs/wokwi/tmp/48678ef3245f4d87a07c526d46588fac.bb.v"
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lint_off -rule UNDRIVEN -file "/workspaces/tt25a_openram_testchip/runs/wokwi/tmp/679491210445499ba08cfc4ebf0bf9da.bb.v"
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lint_off -rule UNUSEDSIGNAL -file "/workspaces/tt25a_openram_testchip/runs/wokwi/tmp/679491210445499ba08cfc4ebf0bf9da.bb.v"
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{
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"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
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"VDD_PIN": "VPWR",
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"VDD_PIN_VOLTAGE": 1.8,
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"GND_PIN": "VGND",
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"WIRE_LENGTH_THRESHOLD": null,
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"TECH_LEFS": {
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"nom_*": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef",
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"min_*": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef",
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"max_*": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"
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},
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"GPIO_PADS_LEF": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"
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],
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"GPIO_PADS_LEF_CORE_SIDE": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"
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],
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"GPIO_PADS_VERILOG": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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],
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"GPIO_PAD_CELLS": [
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"sky130_fd_io*",
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"sky130_ef_io*"
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],
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"PRIMARY_GDSII_STREAMOUT_TOOL": "magic",
28+
"DEFAULT_MAX_TRAN": null,
29+
"SIGNAL_WIRE_RC_LAYERS": null,
30+
"CLOCK_WIRE_RC_LAYERS": null,
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"DEFAULT_CORNER": "nom_tt_025C_1v80",
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"STA_CORNERS": [
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"nom_tt_025C_1v80",
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"nom_ss_100C_1v60",
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"nom_ff_n40C_1v95",
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"min_tt_025C_1v80",
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"min_ss_100C_1v60",
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"min_ff_n40C_1v95",
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"max_tt_025C_1v80",
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"max_ss_100C_1v60",
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"max_ff_n40C_1v95"
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],
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"FP_TRACKS_INFO": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info",
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"FP_TAPCELL_DIST": 13,
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"FP_IO_HLAYER": "met3",
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"FP_IO_VLAYER": "met2",
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"RT_MIN_LAYER": "met1",
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"RT_MAX_LAYER": "met4",
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"SCL_GROUND_PINS": [
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"VGND",
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"VNB"
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],
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"SCL_POWER_PINS": [
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"VPWR",
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"VPB"
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],
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"TRISTATE_CELLS": [
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"sky130_fd_sc_hd__ebuf*"
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],
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"FILL_CELL": [
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"sky130_fd_sc_hd__fill*"
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],
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"DECAP_CELL": [
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"sky130_ef_sc_hd__decap_12",
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"sky130_fd_sc_hd__decap_8",
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"sky130_fd_sc_hd__decap_6",
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"sky130_fd_sc_hd__decap_4",
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"sky130_fd_sc_hd__decap_3"
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],
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"LIB": {
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"*_tt_025C_1v80": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
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],
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"*_ss_100C_1v60": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
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],
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"*_ff_n40C_1v95": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
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]
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},
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"CELL_LEFS": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef"
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],
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"CELL_GDS": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"
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],
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"CELL_VERILOG_MODELS": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
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],
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"CELL_BB_VERILOG_MODELS": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v"
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],
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"CELL_SPICE_MODELS": [
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice",
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"/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
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],
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"SYNTH_EXCLUDED_CELL_FILE": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells",
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"PNR_EXCLUDED_CELL_FILE": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells",
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"OUTPUT_CAP_LOAD": 33.442,
106+
"MAX_FANOUT_CONSTRAINT": 10,
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"MAX_TRANSITION_CONSTRAINT": 0.75,
108+
"MAX_CAPACITANCE_CONSTRAINT": 0.2,
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"CLOCK_UNCERTAINTY_CONSTRAINT": 0.25,
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"CLOCK_TRANSITION_CONSTRAINT": 0.15,
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"TIME_DERATING_CONSTRAINT": 5,
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"IO_DELAY_CONSTRAINT": 20,
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"SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2/Y",
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"SYNTH_CLK_DRIVING_CELL": null,
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"SYNTH_TIEHI_CELL": "sky130_fd_sc_hd__conb_1/HI",
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"SYNTH_TIELO_CELL": "sky130_fd_sc_hd__conb_1/LO",
117+
"SYNTH_BUFFER_CELL": "sky130_fd_sc_hd__buf_2/A/X",
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"WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1",
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"ENDCAP_CELL": "sky130_fd_sc_hd__decap_3",
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"PLACE_SITE": "unithd",
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"CELL_PAD_EXCLUDE": [
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"sky130_fd_sc_hd__tap*",
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"sky130_fd_sc_hd__decap*",
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"sky130_ef_sc_hd__decap*",
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"sky130_fd_sc_hd__fill*"
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],
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"DIODE_CELL": "sky130_fd_sc_hd__diode_2/DIODE",
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"DESIGN_DIR": "/workspaces/tt25a_openram_testchip/src",
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"PDK_ROOT": "/home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af",
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"DESIGN_NAME": "tt_um_openram_top",
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"PDK": "sky130A",
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"CLOCK_PERIOD": 10000,
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"CLOCK_PORT": [
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"ui_in[3]",
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"ui_in[4]"
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],
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"CLOCK_NET": [
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"ui_in[3]",
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"ui_in[4]"
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],
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"VDD_NETS": [
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"VPWR"
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],
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"GND_NETS": [
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"VGND"
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],
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"DIE_AREA": [
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0,
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0,
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334.88,
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225.76
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],
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"EXTRA_EXCLUDED_CELLS": null,
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"MACROS": {
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"sky130_sram_256B_1rw_32x64": {
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"gds": [
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"/workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.gds"
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],
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"lef": [
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"/workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.lef"
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],
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"instances": {
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"SRAM": {
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"location": [
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2,
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10
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],
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"orientation": "S"
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}
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},
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"vh": [],
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"nl": [
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"/workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v"
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],
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"pnl": [],
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"spef": {},
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"lib": {},
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"spice": [],
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"sdf": {},
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"json_h": null
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}
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},
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"EXTRA_LEFS": [
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"src/sky130_sram_256B_1rw_32x64.lef"
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],
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"EXTRA_VERILOG_MODELS": null,
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"EXTRA_SPICE_MODELS": null,
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"EXTRA_LIBS": null,
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"EXTRA_GDS_FILES": null,
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"FALLBACK_SDC_FILE": "src/project.sdc",
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"VERILOG_FILES": [
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"/workspaces/tt25a_openram_testchip/src/defs.v",
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"/workspaces/tt25a_openram_testchip/src/project.v",
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"/workspaces/tt25a_openram_testchip/src/scan_cell_2ph.v",
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"/workspaces/tt25a_openram_testchip/src/scan_chain_2ph.v",
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"/workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v"
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],
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"VERILOG_POWER_DEFINE": "USE_POWER_PINS",
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"LINTER_INCLUDE_PDK_MODELS": true,
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"LINTER_RELATIVE_INCLUDES": true,
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"LINTER_ERROR_ON_LATCH": true,
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"VERILOG_DEFINES": null,
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"LINTER_DEFINES": null,
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"meta": {
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"openlane_version": "2.2.9",
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"step": "Verilator.Lint"
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}
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}
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00:00:00.589
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{
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"nl": null,
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"pnl": null,
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"pnl-sdf-friendly": null,
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"pnl-npc": null,
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"def": null,
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"lef": null,
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"openroad-lef": null,
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"odb": null,
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"sdc": null,
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"sdf": null,
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"spef": null,
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"lib": null,
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"spice": null,
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"mag": null,
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"gds": null,
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"mag_gds": null,
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"klayout_gds": null,
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"json_h": null,
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"vh": null,
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"metrics": {}
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}
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{
2+
"nl": null,
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"pnl": null,
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"pnl-sdf-friendly": null,
5+
"pnl-npc": null,
6+
"def": null,
7+
"lef": null,
8+
"openroad-lef": null,
9+
"odb": null,
10+
"sdc": null,
11+
"sdf": null,
12+
"spef": null,
13+
"lib": null,
14+
"spice": null,
15+
"mag": null,
16+
"gds": null,
17+
"mag_gds": null,
18+
"klayout_gds": null,
19+
"json_h": null,
20+
"vh": null,
21+
"metrics": {
22+
"design__lint_error__count": 0,
23+
"design__lint_timing_construct__count": 0,
24+
"design__lint_warning__count": 4,
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"design__inferred_latch__count": 0
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}
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}
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%Warning-MODDUP: /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v:9:8: Duplicate declaration of module: 'sky130_sram_256B_1rw_32x64'
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/workspaces/tt25a_openram_testchip/src/project.v:9:1: ... note: In file included from 'project.v'
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/workspaces/tt25a_openram_testchip/runs/wokwi/tmp/679491210445499ba08cfc4ebf0bf9da.bb.v:3:8: ... Location of original declaration
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3 | module sky130_sram_256B_1rw_32x64(vccd1, vssd1, clk0, csb0, web0, wmask0, spare_wen0, addr0, din0, dout0);
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| ^~~~~~~~~~~~~~~~~~~~~~~~~~
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... For warning description see https://verilator.org/warn/MODDUP?v=5.018
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... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.
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%Warning-VARHIDDEN: /workspaces/tt25a_openram_testchip/src/scan_chain_2ph.v:22:27: Declaration of signal hides declaration in upper scope: 'scan_chain'
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/workspaces/tt25a_openram_testchip/src/project.v:10:1: ... note: In file included from 'project.v'
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/workspaces/tt25a_openram_testchip/src/project.v:76:30: ... Location of original declaration
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%Warning-UNUSEDSIGNAL: /workspaces/tt25a_openram_testchip/src/project.v:18:23: Bits of signal are not used: 'uio_in'[7:4]
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: ... note: In instance 'tt_um_openram_top'
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%Warning-UNUSEDSIGNAL: /workspaces/tt25a_openram_testchip/src/project.v:41:23: Bits of signal are not used: 'scan_data_out'[32:1]
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: ... note: In instance 'tt_um_openram_top'
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{
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"time": {
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"cpu_time_user": "00:00:00.030",
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"cpu_time_system": "00:00:00.000",
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"runtime": "00:00:00.201",
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"cpu_time_iowait": "00:00:00.000"
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},
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"peak_resources": {
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"cpu_percent": 29.9,
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"memory_rss": "12MiB",
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"memory_vms": "233MiB",
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"threads": 1
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},
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"avg_resources": {
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"cpu_percent": 7.475,
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"memory_rss": "3MiB",
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"memory_vms": "59MiB",
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"threads": 0.75
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}
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}

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