1+ {
2+ "STD_CELL_LIBRARY" : " sky130_fd_sc_hd" ,
3+ "VDD_PIN" : " VPWR" ,
4+ "VDD_PIN_VOLTAGE" : 1.8 ,
5+ "GND_PIN" : " VGND" ,
6+ "WIRE_LENGTH_THRESHOLD" : null ,
7+ "TECH_LEFS" : {
8+ "nom_*" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef" ,
9+ "min_*" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef" ,
10+ "max_*" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"
11+ },
12+ "GPIO_PADS_LEF" : [
13+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef" ,
14+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"
15+ ],
16+ "GPIO_PADS_LEF_CORE_SIDE" : [
17+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef" ,
18+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"
19+ ],
20+ "GPIO_PADS_VERILOG" : [
21+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
22+ ],
23+ "GPIO_PAD_CELLS" : [
24+ " sky130_fd_io*" ,
25+ " sky130_ef_io*"
26+ ],
27+ "PRIMARY_GDSII_STREAMOUT_TOOL" : " magic" ,
28+ "DEFAULT_MAX_TRAN" : null ,
29+ "SIGNAL_WIRE_RC_LAYERS" : null ,
30+ "CLOCK_WIRE_RC_LAYERS" : null ,
31+ "DEFAULT_CORNER" : " nom_tt_025C_1v80" ,
32+ "STA_CORNERS" : [
33+ " nom_tt_025C_1v80" ,
34+ " nom_ss_100C_1v60" ,
35+ " nom_ff_n40C_1v95" ,
36+ " min_tt_025C_1v80" ,
37+ " min_ss_100C_1v60" ,
38+ " min_ff_n40C_1v95" ,
39+ " max_tt_025C_1v80" ,
40+ " max_ss_100C_1v60" ,
41+ " max_ff_n40C_1v95"
42+ ],
43+ "FP_TRACKS_INFO" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info" ,
44+ "FP_TAPCELL_DIST" : 13 ,
45+ "FP_IO_HLAYER" : " met3" ,
46+ "FP_IO_VLAYER" : " met2" ,
47+ "RT_MIN_LAYER" : " met1" ,
48+ "RT_MAX_LAYER" : " met4" ,
49+ "SCL_GROUND_PINS" : [
50+ " VGND" ,
51+ " VNB"
52+ ],
53+ "SCL_POWER_PINS" : [
54+ " VPWR" ,
55+ " VPB"
56+ ],
57+ "TRISTATE_CELLS" : [
58+ " sky130_fd_sc_hd__ebuf*"
59+ ],
60+ "FILL_CELL" : [
61+ " sky130_fd_sc_hd__fill*"
62+ ],
63+ "DECAP_CELL" : [
64+ " sky130_ef_sc_hd__decap_12" ,
65+ " sky130_fd_sc_hd__decap_8" ,
66+ " sky130_fd_sc_hd__decap_6" ,
67+ " sky130_fd_sc_hd__decap_4" ,
68+ " sky130_fd_sc_hd__decap_3"
69+ ],
70+ "LIB" : {
71+ "*_tt_025C_1v80" : [
72+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
73+ ],
74+ "*_ss_100C_1v60" : [
75+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
76+ ],
77+ "*_ff_n40C_1v95" : [
78+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
79+ ]
80+ },
81+ "CELL_LEFS" : [
82+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef" ,
83+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef"
84+ ],
85+ "CELL_GDS" : [
86+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"
87+ ],
88+ "CELL_VERILOG_MODELS" : [
89+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v" ,
90+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
91+ ],
92+ "CELL_BB_VERILOG_MODELS" : [
93+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v" ,
94+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v"
95+ ],
96+ "CELL_SPICE_MODELS" : [
97+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice" ,
98+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice" ,
99+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice" ,
100+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice" ,
101+ " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
102+ ],
103+ "SYNTH_EXCLUDED_CELL_FILE" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells" ,
104+ "PNR_EXCLUDED_CELL_FILE" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells" ,
105+ "OUTPUT_CAP_LOAD" : 33.442 ,
106+ "MAX_FANOUT_CONSTRAINT" : 10 ,
107+ "MAX_TRANSITION_CONSTRAINT" : 0.75 ,
108+ "MAX_CAPACITANCE_CONSTRAINT" : 0.2 ,
109+ "CLOCK_UNCERTAINTY_CONSTRAINT" : 0.25 ,
110+ "CLOCK_TRANSITION_CONSTRAINT" : 0.15 ,
111+ "TIME_DERATING_CONSTRAINT" : 5 ,
112+ "IO_DELAY_CONSTRAINT" : 20 ,
113+ "SYNTH_DRIVING_CELL" : " sky130_fd_sc_hd__inv_2/Y" ,
114+ "SYNTH_CLK_DRIVING_CELL" : null ,
115+ "SYNTH_TIEHI_CELL" : " sky130_fd_sc_hd__conb_1/HI" ,
116+ "SYNTH_TIELO_CELL" : " sky130_fd_sc_hd__conb_1/LO" ,
117+ "SYNTH_BUFFER_CELL" : " sky130_fd_sc_hd__buf_2/A/X" ,
118+ "WELLTAP_CELL" : " sky130_fd_sc_hd__tapvpwrvgnd_1" ,
119+ "ENDCAP_CELL" : " sky130_fd_sc_hd__decap_3" ,
120+ "PLACE_SITE" : " unithd" ,
121+ "CELL_PAD_EXCLUDE" : [
122+ " sky130_fd_sc_hd__tap*" ,
123+ " sky130_fd_sc_hd__decap*" ,
124+ " sky130_ef_sc_hd__decap*" ,
125+ " sky130_fd_sc_hd__fill*"
126+ ],
127+ "DIODE_CELL" : " sky130_fd_sc_hd__diode_2/DIODE" ,
128+ "DESIGN_DIR" : " /workspaces/tt25a_openram_testchip/src" ,
129+ "PDK_ROOT" : " /home/vscode/ttsetup/pdk/volare/sky130/versions/0fe599b2afb6708d281543108caf8310912f54af" ,
130+ "DESIGN_NAME" : " tt_um_openram_top" ,
131+ "PDK" : " sky130A" ,
132+ "CLOCK_PERIOD" : 10000 ,
133+ "CLOCK_PORT" : [
134+ " ui_in[3]" ,
135+ " ui_in[4]"
136+ ],
137+ "CLOCK_NET" : [
138+ " ui_in[3]" ,
139+ " ui_in[4]"
140+ ],
141+ "VDD_NETS" : [
142+ " VPWR"
143+ ],
144+ "GND_NETS" : [
145+ " VGND"
146+ ],
147+ "DIE_AREA" : [
148+ 0 ,
149+ 0 ,
150+ 334.88 ,
151+ 225.76
152+ ],
153+ "EXTRA_EXCLUDED_CELLS" : null ,
154+ "MACROS" : {
155+ "sky130_sram_256B_1rw_32x64" : {
156+ "gds" : [
157+ " /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.gds"
158+ ],
159+ "lef" : [
160+ " /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.lef"
161+ ],
162+ "instances" : {
163+ "SRAM" : {
164+ "location" : [
165+ 2 ,
166+ 10
167+ ],
168+ "orientation" : " S"
169+ }
170+ },
171+ "vh" : [],
172+ "nl" : [
173+ " /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v"
174+ ],
175+ "pnl" : [],
176+ "spef" : {},
177+ "lib" : {},
178+ "spice" : [],
179+ "sdf" : {},
180+ "json_h" : null
181+ }
182+ },
183+ "EXTRA_LEFS" : [
184+ " src/sky130_sram_256B_1rw_32x64.lef"
185+ ],
186+ "EXTRA_VERILOG_MODELS" : null ,
187+ "EXTRA_SPICE_MODELS" : null ,
188+ "EXTRA_LIBS" : null ,
189+ "EXTRA_GDS_FILES" : null ,
190+ "FALLBACK_SDC_FILE" : " src/project.sdc" ,
191+ "VERILOG_FILES" : [
192+ " /workspaces/tt25a_openram_testchip/src/defs.v" ,
193+ " /workspaces/tt25a_openram_testchip/src/project.v" ,
194+ " /workspaces/tt25a_openram_testchip/src/scan_cell_2ph.v" ,
195+ " /workspaces/tt25a_openram_testchip/src/scan_chain_2ph.v" ,
196+ " /workspaces/tt25a_openram_testchip/src/sky130_sram_256B_1rw_32x64.v"
197+ ],
198+ "VERILOG_POWER_DEFINE" : " USE_POWER_PINS" ,
199+ "LINTER_INCLUDE_PDK_MODELS" : true ,
200+ "LINTER_RELATIVE_INCLUDES" : true ,
201+ "LINTER_ERROR_ON_LATCH" : true ,
202+ "VERILOG_DEFINES" : null ,
203+ "LINTER_DEFINES" : null ,
204+ "meta" : {
205+ "openlane_version" : " 2.2.9" ,
206+ "step" : " Verilator.Lint"
207+ }
208+ }
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