fix(style): Replace std::map by std::unordered map where possible

Signed-off-by: Steffen Vogel <[email protected]>

Author: stv0g

common/include/villas/graph/directed.hpp

@@ -10,11 +10,11 @@
 #include <algorithm>
 #include <fstream>
 #include <list>
-#include <map>
 #include <memory>
 #include <sstream>
 #include <stdexcept>
 #include <string>
+#include <unordered_map>
 
 #include <villas/graph/edge.hpp>
 #include <villas/graph/vertex.hpp>
@@ -245,8 +245,8 @@ class DirectedGraph {
   VertexIdentifier lastVertexId;
   EdgeIdentifier lastEdgeId;
 
-  std::map<VertexIdentifier, std::shared_ptr<VertexType>> vertices;
-  std::map<EdgeIdentifier, std::shared_ptr<EdgeType>> edges;
+  std::unordered_map<VertexIdentifier, std::shared_ptr<VertexType>> vertices;
+  std::unordered_map<EdgeIdentifier, std::shared_ptr<EdgeType>> edges;
 
   Logger logger;
 };

common/include/villas/memory.hpp

@@ -275,7 +275,8 @@ class HostDmaRam {
   static HostDmaRamAllocator &getAllocator(int num = 0);
 
 private:
-  static std::map<int, std::unique_ptr<HostDmaRamAllocator>> allocators;
+  static std::unordered_map<int, std::unique_ptr<HostDmaRamAllocator>>
+      allocators;
 
   static std::string getUdmaBufName(int num);
 

common/include/villas/memory_manager.hpp

@@ -8,9 +8,9 @@
 #pragma once
 
 #include <cstdint>
-#include <map>
 #include <stdexcept>
 #include <string>
+#include <unordered_map>
 
 #include <fmt/ostream.h>
 #include <unistd.h>
@@ -214,7 +214,7 @@ class MemoryManager {
   MemoryGraph memoryGraph;
 
   // Cache mapping of names to address space ids for fast lookup
-  std::map<std::string, AddressSpaceId> addrSpaceLookup;
+  std::unordered_map<std::string, AddressSpaceId> addrSpaceLookup;
 
   // Logger for universal access in this class
   Logger logger;

common/include/villas/popen.hpp

@@ -8,10 +8,10 @@
 #pragma once
 
 #include <istream>
-#include <map>
 #include <memory>
 #include <ostream>
 #include <string>
+#include <unordered_map>
 #include <vector>
 
 #include <ext/stdio_filebuf.h>
@@ -24,7 +24,7 @@ class Popen {
 
 public:
   using arg_list = std::vector<std::string>;
-  using env_map = std::map<std::string, std::string>;
+  using env_map = std::unordered_map<std::string, std::string>;
 
   using char_type = char;
   using stdio_buf = __gnu_cxx::stdio_filebuf<char_type>;

common/lib/log.cpp

@@ -7,7 +7,7 @@
 
 #include <algorithm>
 #include <list>
-#include <map>
+#include <unordered_map>
 
 #include <fnmatch.h>
 #include <spdlog/sinks/basic_file_sink.h>
@@ -19,7 +19,7 @@
 
 using namespace villas;
 
-static std::map<spdlog::level::level_enum, std::string> levelNames = {
+static std::unordered_map<spdlog::level::level_enum, std::string> levelNames = {
     {spdlog::level::trace, "trc"}, {spdlog::level::debug, "dbg"},
     {spdlog::level::info, "info"}, {spdlog::level::warn, "warn"},
     {spdlog::level::err, "err"},   {spdlog::level::critical, "crit"},

common/lib/memory.cpp

@@ -155,7 +155,7 @@ HostRam::HostRamAllocator::HostRamAllocator()
   };
 }
 
-std::map<int, std::unique_ptr<HostDmaRam::HostDmaRamAllocator>>
+std::unordered_map<int, std::unique_ptr<HostDmaRam::HostDmaRamAllocator>>
     HostDmaRam::allocators;
 
 HostDmaRam::HostDmaRamAllocator::HostDmaRamAllocator(int num)

fpga/include/villas/fpga/card.hpp

@@ -49,7 +49,8 @@ class Card {
 
 protected:
   // Keep a map of already mapped memory blocks
-  std::map<MemoryManager::AddressSpaceId, std::shared_ptr<MemoryBlock>>
+  std::unordered_map<MemoryManager::AddressSpaceId,
+                     std::shared_ptr<MemoryBlock>>
       memoryBlocksMapped;
 
   Logger logger;

fpga/include/villas/fpga/core.hpp

@@ -11,8 +11,8 @@
 #pragma once
 
 #include <list>
-#include <map>
 #include <memory>
+#include <unordered_map>
 
 #include <fmt/ostream.h>
 #include <jansson.h>
@@ -194,16 +194,18 @@ class Core {
   IpIdentifier id;
 
   // All interrupts of this IP with their associated interrupt controller
-  std::map<std::string, IrqPort> irqs;
+  std::unordered_map<std::string, IrqPort> irqs;
 
   // Cached translations from the process address space to each memory block
-  std::map<MemoryBlockName, MemoryTranslation> addressTranslations;
+  std::unordered_map<MemoryBlockName, MemoryTranslation> addressTranslations;
 
   // Lookup for IP's slave address spaces (= memory blocks)
-  std::map<MemoryBlockName, MemoryManager::AddressSpaceId> slaveAddressSpaces;
+  std::unordered_map<MemoryBlockName, MemoryManager::AddressSpaceId>
+      slaveAddressSpaces;
 
   // AXI bus master interfaces to access memory somewhere
-  std::map<std::string, MemoryManager::AddressSpaceId> busMasterInterfaces;
+  std::unordered_map<std::string, MemoryManager::AddressSpaceId>
+      busMasterInterfaces;
 
   size_t baseaddr = 0;
 };

fpga/include/villas/fpga/ips/pcie.hpp

@@ -38,8 +38,8 @@ class AxiPciExpressBridge : public Core {
     uintptr_t translation;
   };
 
-  std::map<std::string, AxiBar> axiToPcieTranslations;
-  std::map<std::string, PciBar> pcieToAxiTranslations;
+  std::unordered_map<std::string, AxiBar> axiToPcieTranslations;
+  std::unordered_map<std::string, PciBar> pcieToAxiTranslations;
 };
 
 class XDmaBridge : public AxiPciExpressBridge {

fpga/include/villas/fpga/ips/switch.hpp

@@ -10,7 +10,7 @@
 
 #pragma once
 
-#include <map>
+#include <unordered_map>
 
 #include <xilinx/xaxis_switch.h>
 
@@ -45,7 +45,7 @@ class AxiStreamSwitch : public Node {
   XAxis_Switch xSwitch;
   XAxis_Switch_Config xConfig;
 
-  std::map<std::string, std::string> portMapping;
+  std::unordered_map<std::string, std::string> portMapping;
 };
 
 class AxiStreamSwitchFactory : NodeFactory {