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Adjusted copyright test to "The PoC-Library Authors".
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‎docs/_extensions/DocumentMember.py‎

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#
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# License:
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# ==============================================================================
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# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany
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# Copryright 2017-2025 The PoC-Library Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.

‎poc.ps1‎

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#
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# License:
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# ==============================================================================
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# Copyright 2017-2018 Patrick Lehmann - Bötzingen, Germany
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# Copryright 2017-2025 The PoC-Library Authors
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# Copyright 2007-2016 Technische Universitaet Dresden - Germany
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# Chair of VLSI-Design, Diagnostics and Architecture
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#

‎poc.sh‎

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#
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# License:
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# ==============================================================================
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# Copyright 2017-2018 Patrick Lehmann - Bötzingen, Germany
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# Copryright 2017-2025 The PoC-Library Authors
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# Copyright 2007-2016 Technische Universitaet Dresden - Germany
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# Chair of VLSI-Design, Diagnostics and Architecture
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#

‎regression.tcl‎

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#
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# License:
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# =============================================================================
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# Copyright 2018-2019 PLC2 Design GmbH, Germany
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# Copryright 2017-2025 The PoC-Library Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.

‎src/arith/arith.pkg.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2024 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
2020
-- Chair of VLSI-Design, Diagnostics and Architecture
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--

‎src/arith/arith_prng.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2024 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--

‎src/bus/stream/stream.pkg.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2024 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--

‎src/bus/stream/stream_FrameGenerator.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2024-2025 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--

‎src/cache/cache_tagunit_seq.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2023 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--

‎src/common/components.vhdl‎

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--
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-- License:
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-- =============================================================================
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-- Copyright 2023 PLC2 Design GmbH, Endingen - Germany
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-- Copryright 2017-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--
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return cnt;
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end if;
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end function;
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function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed is
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begin
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if (rst = '1') then

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