Add ignored test for generic types from ports in maps

Author: Schottkyc137

vhdl_lang/src/analysis/tests/association_formal.rs

@@ -785,3 +785,41 @@ end architecture;
     );
     check_no_diagnostics(&builder.analyze());
 }
+
+#[test]
+#[ignore]
+fn generic_type_from_port_in_map() {
+    let mut builder = LibraryBuilder::new();
+    builder.code(
+        "libname",
+        "
+entity coyote_top is
+    generic (
+        type t
+    );
+    port (
+        clk: in t
+    );
+end entity coyote_top;
+
+architecture rtl of coyote_top is
+begin
+end architecture;
+
+entity te is
+end entity te;
+
+architecture rtl of te is
+begin
+    coyote_top_inst: entity work.coyote_top
+     generic map(
+        t => bit
+    )
+     port map(
+        clk => '1'
+    );
+end architecture;
+        ",
+    );
+    check_no_diagnostics(&builder.analyze());
+}