feat: update project tt_um_wokwi_446368563224770561 from ArigganKnight/TinyTapeout

Commit: 77791c8f57672e205dcfbdf2b7227af3ceb75f2c
Workflow: https://github.com/ArigganKnight/TinyTapeout/actions/runs/18990554424

Author: TinyTapeoutBot

projects/tt_um_wokwi_446368563224770561/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout main f77b61f7",
   "repo": "https://github.com/ArigganKnight/TinyTapeout",
-  "commit": "a73dc5c34ab392bf9974971127915de943454371",
-  "workflow_url": "https://github.com/ArigganKnight/TinyTapeout/actions/runs/18987441699",
+  "commit": "77791c8f57672e205dcfbdf2b7227af3ceb75f2c",
+  "workflow_url": "https://github.com/ArigganKnight/TinyTapeout/actions/runs/18990554424",
   "project_id": 3294,
   "sort_id": 1761953554437
 }

projects/tt_um_wokwi_446368563224770561/docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Give it two 4-bit inputs and it will give you a 4-bit output.
+It uses input 4-7 to populate a LUT to implement a simple logic function.
 
 ## How to test
 
-Pending...
+Configure it by presenting a truth table on inputs 4-7. Give it inputs on 0 and 1, and it'll give you the output on 0.
 
 ## External hardware
 
-Pending...
+There is none.

projects/tt_um_wokwi_446368563224770561/info.yaml

@@ -1,10 +1,10 @@
 # Tiny Tapeout project information (Wokwi project)
 project:
   wokwi_id:     446368563224770561       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "TinyTapeout1"      # Project title
+  title:        "TinyTapeout2"      # Project title
   author:       "Kevin"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "ALU WIP..."      # One line description of what your project does
+  description:  "Programmable Logic Function"      # One line description of what your project does
   language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -16,20 +16,20 @@ project:
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
 pinout:
   # Inputs
-  ui[0]: "a0"
-  ui[1]: "a1"
-  ui[2]: "a2"
-  ui[3]: "a3"
-  ui[4]: "b0"
-  ui[5]: "b1"
-  ui[6]: "b2"
-  ui[7]: "b3"
+  ui[0]: "a"
+  ui[1]: "b"
+  ui[2]: ""
+  ui[3]: ""
+  ui[4]: "v00"
+  ui[5]: "v01"
+  ui[6]: "v10"
+  ui[7]: "v11"
 
   # Outputs
-  uo[0]: "q0"
-  uo[1]: "q1"
-  uo[2]: "q2"
-  uo[3]: "q3"
+  uo[0]: "q"
+  uo[1]: ""
+  uo[2]: ""
+  uo[3]: ""
   uo[4]: ""
   uo[5]: ""
   uo[6]: ""

projects/tt_um_wokwi_446368563224770561/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,271
-design__instance__area,564.291
+design__instance__count,258
+design__instance__area,431.664
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,8.617585081083234E-7
-power__switching__total,0.0000017162913081847364
-power__leakage__total,1.4623517952117027E-9
-power__total,0.0000025795120563998353
+power__internal__total,9.002937417790235E-7
+power__switching__total,9.673613021732308E-7
+power__leakage__total,1.3230463391522562E-9
+power__total,0.0000018689781882130774
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,7.933998571587016
-timing__setup__ws__corner:nom_tt_025C_1v80,10.787536502746303
+timing__hold__ws__corner:nom_tt_025C_1v80,8.146742178117748
+timing__setup__ws__corner:nom_tt_025C_1v80,10.850110450540729
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.10807355316564
-timing__setup__ws__corner:nom_ss_100C_1v60,9.712153134398385
+timing__hold__ws__corner:nom_ss_100C_1v60,8.482684128550952
+timing__setup__ws__corner:nom_ss_100C_1v60,9.848516947388417
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,7.869980445641314
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.176810904255586
+timing__hold__ws__corner:nom_ff_n40C_1v95,8.015483614828538
+timing__setup__ws__corner:nom_ff_n40C_1v95,11.215478641029248
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,7.8685291620624795
-timing__setup__ws,9.710774681452024
+timing__hold__ws,8.014680701514422
+timing__setup__ws,9.84667664165075
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -84,18 +84,17 @@ design__core__bbox,2.76 2.72 158.24 108.8
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,271
-design__instance__area__stdcell,564.291
+design__instance__count__stdcell,258
+design__instance__area__stdcell,431.664
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0342133
-design__instance__utilization__stdcell,0.0342133
-design__instance__count__class:buffer,8
-design__instance__count__class:inverter,4
-design__instance__count__class:multi_input_combinational_cell,32
+design__instance__utilization,0.0261721
+design__instance__utilization__stdcell,0.0261721
+design__instance__count__class:buffer,1
+design__instance__count__class:multi_input_combinational_cell,26
 flow__warnings__count,1
 flow__errors__count,0
-design__instance__count__class:fill_cell,1463
+design__instance__count__class:fill_cell,1469
 design__instance__count__class:tap_cell,225
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
@@ -105,42 +104,40 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,602.104
+route__wirelength__estimated,232.969
 design__violations,0
-design__instance__count__class:timing_repair_buffer,2
+design__instance__count__class:timing_repair_buffer,6
 design__instance__count__setup_buffer,0
 design__instance__count__hold_buffer,0
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
 antenna_diodes_count,0
-route__net,65
+route__net,52
 route__net__special,2
-route__drc_errors__iter:1,4
-route__wirelength__iter:1,558
-route__drc_errors__iter:2,0
-route__wirelength__iter:2,546
+route__drc_errors__iter:1,0
+route__wirelength__iter:1,192
 route__drc_errors,0
-route__wirelength,546
-route__vias,231
-route__vias__singlecut,231
+route__wirelength,192
+route__vias,149
+route__vias__singlecut,149
 route__vias__multicut,0
 design__disconnected_pin__count,13
 design__critical_disconnected_pin__count,0
-route__wirelength__max,48.18
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,55
+route__wirelength__max,26.25
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,45
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,55
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,45
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,55
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,45
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,7.931993952837058
-timing__setup__ws__corner:min_tt_025C_1v80,10.7880853970252
+timing__hold__ws__corner:min_tt_025C_1v80,8.14574564190266
+timing__setup__ws__corner:min_tt_025C_1v80,10.85094000920819
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -151,15 +148,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,55
+timing__unannotated_net__count__corner:min_tt_025C_1v80,45
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.104234845927131
-timing__setup__ws__corner:min_ss_100C_1v60,9.713035983772535
+timing__hold__ws__corner:min_ss_100C_1v60,8.481223075009224
+timing__setup__ws__corner:min_ss_100C_1v60,9.849787930742954
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -170,15 +167,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,55
+timing__unannotated_net__count__corner:min_ss_100C_1v60,45
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,7.8685291620624795
-timing__setup__ws__corner:min_ff_n40C_1v95,11.177260322548664
+timing__hold__ws__corner:min_ff_n40C_1v95,8.014680701514422
+timing__setup__ws__corner:min_ff_n40C_1v95,11.216145663041308
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -189,15 +186,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,55
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,45
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,7.935085702003475
-timing__setup__ws__corner:max_tt_025C_1v80,10.786655429729043
+timing__hold__ws__corner:max_tt_025C_1v80,8.148124183777886
+timing__setup__ws__corner:max_tt_025C_1v80,10.848888317000657
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -208,15 +205,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,55
+timing__unannotated_net__count__corner:max_tt_025C_1v80,45
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.109854350947503
-timing__setup__ws__corner:max_ss_100C_1v60,9.710774681452024
+timing__hold__ws__corner:max_ss_100C_1v60,8.484649667449338
+timing__setup__ws__corner:max_ss_100C_1v60,9.84667664165075
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -227,15 +224,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,55
+timing__unannotated_net__count__corner:max_ss_100C_1v60,45
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,7.870856189587906
-timing__setup__ws__corner:max_ff_n40C_1v95,11.176060393469712
+timing__hold__ws__corner:max_ff_n40C_1v95,8.016614265988794
+timing__setup__ws__corner:max_ff_n40C_1v95,11.214477663921937
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -246,25 +243,25 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,55
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,45
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,55
+timing__unannotated_net__count,45
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000270698
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000268679
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,5.05518E-8
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000268679
-design_powergrid__voltage__worst,0.00000268679
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000256786
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000271848
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.59373E-8
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000271848
+design_powergrid__voltage__worst,0.00000271848
 design_powergrid__voltage__worst__net:VPWR,1.8
-design_powergrid__drop__worst,0.00000270698
-design_powergrid__drop__worst__net:VPWR,0.00000270698
-design_powergrid__voltage__worst__net:VGND,0.00000268679
-design_powergrid__drop__worst__net:VGND,0.00000268679
+design_powergrid__drop__worst,0.00000271848
+design_powergrid__drop__worst__net:VPWR,0.00000256786
+design_powergrid__voltage__worst__net:VGND,0.00000271848
+design_powergrid__drop__worst__net:VGND,0.00000271848
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,5.1100000000000000969881184913201632724621958914212882518768310546875E-8
-ir__drop__worst,0.00000270999999999999988795529488883051527636780519969761371612548828125
+ir__drop__avg,3.410000000000000094506989582222866719263265622430481016635894775390625E-8
+ir__drop__worst,0.0000025699999999999999578180302772789644905060413293540477752685546875
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0