From 5bb74978c81f8b01ead4bfc60a5c39cab30d90c0 Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Wed, 23 Oct 2024 01:38:23 +0300 Subject: [PATCH] feat: update project tt_um_MichaelBell_tinyQV from MichaelBell/ttihp-tinyQV Commit: d50edbb16e31183b5d1b4f469e997a3fb68c0982 Workflow: https://github.com/MichaelBell/ttihp-tinyQV/actions/runs/11469013367 --- projects/tt_um_MichaelBell_tinyQV/LICENSE | 201 + .../tt_um_MichaelBell_tinyQV/commit_id.json | 7 + .../tt_um_MichaelBell_tinyQV/docs/info.md | 97 + projects/tt_um_MichaelBell_tinyQV/info.yaml | 67 + .../stats/metrics.csv | 265 + .../stats/synthesis-stats.txt | 61 + .../tool_versions.json | 7 + .../tt_um_MichaelBell_tinyQV.gds | Bin 0 -> 8456720 bytes .../tt_um_MichaelBell_tinyQV.lef | 430 + .../tt_um_MichaelBell_tinyQV.spef | 303875 +++++++++++++++ .../tt_um_MichaelBell_tinyQV.v | 36114 ++ 11 files changed, 341124 insertions(+) create mode 100644 projects/tt_um_MichaelBell_tinyQV/LICENSE create mode 100644 projects/tt_um_MichaelBell_tinyQV/commit_id.json create mode 100644 projects/tt_um_MichaelBell_tinyQV/docs/info.md create mode 100644 projects/tt_um_MichaelBell_tinyQV/info.yaml create mode 100644 projects/tt_um_MichaelBell_tinyQV/stats/metrics.csv create mode 100644 projects/tt_um_MichaelBell_tinyQV/stats/synthesis-stats.txt create mode 100644 projects/tt_um_MichaelBell_tinyQV/tool_versions.json create mode 100644 projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.gds create mode 100644 projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.lef create mode 100644 projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.spef create mode 100644 projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.v diff --git a/projects/tt_um_MichaelBell_tinyQV/LICENSE b/projects/tt_um_MichaelBell_tinyQV/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/projects/tt_um_MichaelBell_tinyQV/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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The QSPI clock and data lines are shared between the flash and the RAM, so only one can be accessed simultaneously. + +Code can only be executed from flash. Data can be read from flash and RAM, and written to RAM. + +The SoC includes a UART and an SPI controller. + +## Address map + +| Address range | Device | +| ------------- | ------ | +| 0x0000000 - 0x0FFFFFF | Flash | +| 0x1000000 - 0x17FFFFF | RAM A | +| 0x1800000 - 0x1FFFFFF | RAM B | +| 0x8000000 - 0x8000007 | GPIO | +| 0x8000010 - 0x800001F | UART | +| 0x8000020 - 0x8000027 | SPI | + +### GPIO + +| Register | Address | Description | +| -------- | ------- | ----------- | +| OUT | 0x8000000 (W) | Control out0-7, if the corresponding bit in SEL is high | +| OUT | 0x8000000 (R) | Reads the current state of out0-7 | +| IN | 0x8000004 (R) | Reads the current state of in0-7 | +| SEL | 0x800000C (R/W) | Enables general purpose output on the corresponding bit on out0-7 | + +### UART + +| Register | Address | Description | +| -------- | ------- | ----------- | +| DATA | 0x8000010 (W) | Transmits the byte | +| DATA | 0x8000010 (R) | Reads any received byte | +| STATUS | 0x8000014 (R) | Bit 0 indicates whether the UART TX is busy, bytes should not be written to the data register while this bit is set. Bit 1 indicates whether a received byte is available to be read. | + +### Debug UART (Transmit only) + +| Register | Address | Description | +| -------- | ------- | ----------- | +| DATA | 0x8000018 (W) | Transmits the byte | +| STATUS | 0x800001C (R) | Bit 0 indicates whether the UART TX is busy, bytes should not be written to the data register while this bit is set. | + +### SPI + +| Register | Address | Description | +| -------- | ------- | ----------- | +| DATA | 0x8000020 (W) | Transmits the byte in bits 7-0, bit 8 is set if this is the last byte of the transaction, bit 9 controls Data/Command on out3 | +| DATA | 0x8000020 (R) | Reads the last received byte | +| CONFIG | 0x8000024 (W) | The low 2 bits set the clock divisor for the SPI clock to 2*(value + 1), bit 2 adds half a cycle to the read latency when set | +| STATUS | 0x8000024 (R) | Bit 0 indicates whether the SPI is busy, bytes should not be written or read from the data register while this bit is set. | + +# How to test + +Load an image into flash and then select the design. + +Reset the design as follows: + +* Set rst_n high and then low to ensure the design sees a falling edge of rst_n. The bidirectional IOs are all set to inputs while rst_n is low. +* Program the flash and leave flash in continuous read mode, and the PSRAMs in QPI mode +* Drive all the QSPI CS high and set SD2:SD0 to the read latency of the QSPI flash and PSRAM in cycles. +* Clock at least 8 times and stop with clock high +* Release all the QSPI lines +* Set rst_n high +* Set clock low +* Start clocking normally + +Based on the observed latencies from tt3p5 testing, at the target 64MHz clock a read latency of 2 or 3 is likely required. The maximum supported latency is currently 3, but should get up to 5 to have a chance at running at faster clock speeds. + +The above should all be handled by some MicroPython scripts for the RP2040 on the TT demo PC. + +Build programs using the riscv32-unknown-elf toolchain and the [tinyQV-sdk](https://github.com/MichaelBell/tinyQV-sdk), some examples are [here](https://github.com/MichaelBell/tinyQV-projects). + +# External hardware + +The design is intended to be used with this [QSPI PMOD](https://github.com/mole99/qspi-pmod) on the bidirectional PMOD. This has a 16MB flash and 2 8MB RAMs. + +The UART is on the correct pins to be used with the hardware UART on the RP2040 on the demo board. + +The SPI controller is intended to make it easy to drive an ST7789 LCD display (more details to be added). + +It may be useful to have buttons to use on the GPIO inputs. diff --git a/projects/tt_um_MichaelBell_tinyQV/info.yaml b/projects/tt_um_MichaelBell_tinyQV/info.yaml new file mode 100644 index 0000000..ffa4263 --- /dev/null +++ b/projects/tt_um_MichaelBell_tinyQV/info.yaml @@ -0,0 +1,67 @@ +# Tiny Tapeout project information +project: + title: "TinyQV Risc-V SoC" # Project title + author: "Michael Bell" # Your name + discord: "rebelmike" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) + description: "A Risc-V SoC for Tiny Tapeout" # One line description of what your project does + language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc + clock_hz: 64000000 # Clock frequency in Hz (or 0 if not applicable) + + # How many tiles your design occupies? A single tile is about 167x108 uM. + tiles: "2x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 + + # Your top module name must start with "tt_um_". Make it unique by including your github username: + top_module: "tt_um_MichaelBell_tinyQV" + + # List your project's source files here. + # Source files must be in ./src and you must list each source file separately, one per line. + # Don't forget to also update `PROJECT_SOURCES` in test/Makefile. + source_files: + - "project.v" + - "tinyQV/cpu/tinyqv.v" + - "tinyQV/cpu/alu.v" + - "tinyQV/cpu/core.v" + - "tinyQV/cpu/counter.v" + - "tinyQV/cpu/cpu.v" + - "tinyQV/cpu/decode.v" + - "tinyQV/cpu/mem_ctrl.v" + - "tinyQV/cpu/qspi_ctrl.v" + - "tinyQV/cpu/register.v" + - "tinyQV/peri/uart/uart_tx.v" + - "tinyQV/peri/uart/uart_rx.v" + - "tinyQV/peri/spi/spi.v" + +# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. +pinout: + # Inputs + ui[0]: "Interrupt 0" + ui[1]: "Interrupt 1" + ui[2]: "SPI MISO" + ui[3]: "GP in3" + ui[4]: "GP in4" + ui[5]: "GP in5" + ui[6]: "GP in6" + ui[7]: "UART RX" + + # Outputs + uo[0]: "UART TX" + uo[1]: "UART RTS" + uo[2]: "SPI DC" + uo[3]: "SPI MOSI" + uo[4]: "SPI CS" + uo[5]: "SPI SCK" + uo[6]: "Debug UART TX" + uo[7]: "Debug signal" + + # Bidirectional pins + uio[0]: "Flash CS" + uio[1]: "SD0" + uio[2]: "SD1" + uio[3]: "SCK" + uio[4]: "SD2" + uio[5]: "SD3" + uio[6]: "RAM A CS" + uio[7]: "RAM B CS" + +# Do not change! +yaml_version: 6 diff --git a/projects/tt_um_MichaelBell_tinyQV/stats/metrics.csv b/projects/tt_um_MichaelBell_tinyQV/stats/metrics.csv new file mode 100644 index 0000000..5658fba --- /dev/null +++ b/projects/tt_um_MichaelBell_tinyQV/stats/metrics.csv @@ -0,0 +1,265 @@ +Metric,Value +detailedplace__design__instance__displacement__total,39622.7 +detailedplace__design__instance__displacement__mean,5.346 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b/projects/tt_um_MichaelBell_tinyQV/stats/synthesis-stats.txt @@ -0,0 +1,61 @@ + +17. Printing statistics. + +=== tt_um_MichaelBell_tinyQV === + + Number of wires: 7079 + Number of wire bits: 7114 + Number of public wires: 1050 + Number of public wire bits: 1085 + Number of ports: 8 + Number of port bits: 43 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 6059 + sg13g2_a21o_1 70 + sg13g2_a21oi_1 398 + sg13g2_a21oi_2 2 + sg13g2_a221oi_1 86 + sg13g2_a22oi_1 134 + sg13g2_and2_1 130 + sg13g2_and2_2 1 + sg13g2_and3_1 37 + sg13g2_and3_2 1 + sg13g2_and4_1 17 + sg13g2_buf_1 612 + sg13g2_buf_16 2 + sg13g2_buf_2 84 + sg13g2_buf_4 32 + sg13g2_buf_8 23 + sg13g2_dfrbp_1 1036 + sg13g2_inv_1 135 + sg13g2_inv_2 5 + sg13g2_inv_4 1 + sg13g2_mux2_1 431 + sg13g2_mux4_1 69 + sg13g2_nand2_1 581 + sg13g2_nand2_2 4 + sg13g2_nand2b_1 141 + sg13g2_nand3_1 156 + sg13g2_nand3b_1 30 + sg13g2_nand4_1 58 + sg13g2_nor2_1 535 + sg13g2_nor2_2 5 + sg13g2_nor2b_1 132 + sg13g2_nor2b_2 4 + sg13g2_nor3_1 172 + sg13g2_nor3_2 3 + sg13g2_nor4_1 53 + sg13g2_nor4_2 7 + sg13g2_o21ai_1 531 + sg13g2_or2_1 57 + sg13g2_or3_1 16 + sg13g2_or4_1 4 + sg13g2_tiehi 1 + sg13g2_xnor2_1 181 + sg13g2_xor2_1 82 + + Chip area for module '\tt_um_MichaelBell_tinyQV': 100467.334800 + of which used for sequential elements: 48872.678400 (48.65%) + diff --git a/projects/tt_um_MichaelBell_tinyQV/tool_versions.json b/projects/tt_um_MichaelBell_tinyQV/tool_versions.json new file mode 100644 index 0000000..6c43b4d --- /dev/null +++ b/projects/tt_um_MichaelBell_tinyQV/tool_versions.json @@ -0,0 +1,7 @@ +{ + "yosys": "", + "openroad": "v2.0-16649-g40811f37f", + "klayout": "KLayout 0.29.7", + "orfs": "980de246ed15fde469d98bd2d88084b9559ea7f2", + "ihp_pdk": "ff292fcd5d1f1d54c68078ce23853058ce3c95cc" +} \ No newline at end of file diff --git a/projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.gds b/projects/tt_um_MichaelBell_tinyQV/tt_um_MichaelBell_tinyQV.gds new file mode 100644 index 0000000000000000000000000000000000000000..b1ffdae68e7e2e624623358e4f844234baffbd1b GIT binary patch literal 8456720 zcmeFa37lm|S@(bYcHi5#Z{O~o$z(WRi4}$v)Y`j@Sud9}x*c;6-QHA%?}UxFI&m zCgfE_K}EzCP!IwHjO^ebVMjo~03zBdQN*YiQ4s=pf8VP5-MY7@t1{gunE(6vzb)f8 z_o?$cPt{Y)Ij2sYb6VY2yM1YE*F<~ztF3-(hyHJ_b>!%Ow|edF-uqnCY8^h=x!Z-m zc!&Fa=(S(J)5Y&Nd*!zt_Mq0TPFZ(&xBKAxT)6MSPk6+6`yTqxOZGkW$*tB@uhr_# zwdJWh-)^;9d$vs8eDlq((7%hIERP=jXFF_7ZO!^)8|sf4)Bmpa|1|ykUHLvw|Mr=- z!{~pyb%
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