SIMD: Vector memory alignment can be optimized to support higher Quads

[SwayamInSync]

Current logic is based for the SIMD of 2x Sleef Quads, which has major support but for modern SIMD instructions set like AVX-512 or AVX it can go upto 128, this can be checked at compile time to set the proper ranges.

Algorithms also need to be modified to support different vector loads

#if defined(__AVX512F__)
    constexpr size_t ALIGNMENT = 128;  // For quadx8
    constexpr size_t VECTOR_SIZE = 8;
#elif defined(__AVX__)
    constexpr size_t ALIGNMENT = 64;   // For quadx4  
    constexpr size_t VECTOR_SIZE = 4;
#else
    constexpr size_t ALIGNMENT = 32;   // For quadx2
    constexpr size_t VECTOR_SIZE = 2;
#endif

[SwayamInSync]

On more exploration it seems on AArch64, there is only Sleef_quadx2 support (which make sense) but still resolving above can give major boost on x86-64 machines.
Also for AArch64, SVE might worth considering as well, it might can support higher vectorized types.