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| 1 | +//! `x86_64` intrinsics |
| 2 | +
|
| 3 | +use core::arch::asm; |
| 4 | + |
| 5 | +/// Unsigned integer addition of two operands with carry flag. |
| 6 | +/// |
| 7 | +/// Performs an unsigned addition of the destination operand (first operand), |
| 8 | +/// the source operand (second operand) and the carry-flag (CF) and stores the |
| 9 | +/// result in the destination operand. The destination operand is a |
| 10 | +/// general-purpose register, whereas the source operand can be a |
| 11 | +/// general-purpose register or memory location. The state of CF can represent |
| 12 | +/// a carry from a previous addition. The instruction sets the CF flag with the |
| 13 | +/// carry generated by the unsigned addition of the operands. |
| 14 | +/// |
| 15 | +/// The ADCX instruction is executed in the context of multi-precision addition |
| 16 | +/// where we add a series of operands with a carry-chain. At the beginning of a |
| 17 | +/// chain of additions, we need to make sure the CF is in a desired initial |
| 18 | +/// state. Often, this initial state needs to be 0, which can be achieved with |
| 19 | +/// an instruction to zero the CF (e.g. XOR). |
| 20 | +/// |
| 21 | +/// # Safety |
| 22 | +/// |
| 23 | +/// This function requires support for the Intel ADX (Multi-Precision Add-Carry |
| 24 | +/// Instruction) extension to the x86 instruction set. |
| 25 | +/// |
| 26 | +/// If called on a CPU which does not support this extension, it will crash the |
| 27 | +/// process with an illegal instruction exception (i.e. `SIGILL`) |
| 28 | +#[inline(always)] |
| 29 | +pub unsafe fn adcx(a: &mut u64, b: u64) { |
| 30 | + asm! { |
| 31 | + "adcx {0}, {1}", |
| 32 | + inout(reg) *a, |
| 33 | + in(reg) b |
| 34 | + }; |
| 35 | +} |
| 36 | + |
| 37 | +/// Unsigned integer addition of two operations with overflow flag. |
| 38 | +/// |
| 39 | +/// Performs an unsigned addition of the destination operand (first operand), |
| 40 | +/// the source operand (second operand) and the overflow-flag (OF) and stores |
| 41 | +/// the result in the destination operand. The destination operand is a |
| 42 | +/// general-purpose register, whereas the source operand can be a |
| 43 | +/// general-purpose register or memory location. The state of OF represents a |
| 44 | +/// carry from a previous addition. The instruction sets the OF flag with the |
| 45 | +/// carry generated by the unsigned addition of the operands. |
| 46 | +/// |
| 47 | +/// The ADOX instruction is executed in the context of multi-precision |
| 48 | +/// addition, where we add a series of operands with a carry-chain. At the |
| 49 | +/// beginning of a chain of additions, we execute an instruction to zero the OF |
| 50 | +/// (e.g. XOR). |
| 51 | +/// |
| 52 | +/// # Safety |
| 53 | +/// |
| 54 | +/// This function requires support for the Intel ADX (Multi-Precision Add-Carry |
| 55 | +/// Instruction) extension to the x86 instruction set. |
| 56 | +/// |
| 57 | +/// If called on a CPU which does not support this extension, it will crash the |
| 58 | +/// process with an illegal instruction exception (i.e. `SIGILL`) |
| 59 | +#[inline(always)] |
| 60 | +pub unsafe fn adox(a: &mut u64, b: u64) { |
| 61 | + asm! { |
| 62 | + "adox {0}, {1}", |
| 63 | + inout(reg) *a, |
| 64 | + in(reg) b |
| 65 | + }; |
| 66 | +} |
| 67 | + |
| 68 | +/// Move if zero. |
| 69 | +/// |
| 70 | +/// Uses a `test` instruction to check if the given `condition` value is |
| 71 | +/// equal to zero, then calls `cmovz` (a.k.a. `cmove`) to conditionally move |
| 72 | +/// `src` to `dst` when `condition` is equal to zero. |
| 73 | +#[inline(always)] |
| 74 | +pub fn cmovz(condition: u64, src: u64, dst: &mut u64) { |
| 75 | + unsafe { |
| 76 | + asm! { |
| 77 | + "test {0}, {0}", |
| 78 | + "cmovz {1}, {2}", |
| 79 | + in(reg) condition, |
| 80 | + inlateout(reg) *dst, |
| 81 | + in(reg) src |
| 82 | + }; |
| 83 | + } |
| 84 | +} |
| 85 | + |
| 86 | +/// Move if not zero. |
| 87 | +/// |
| 88 | +/// Uses a `test` instruction to check if the given `condition` value is not |
| 89 | +/// equal to zero, then calls `cmovnz` (a.k.a. `cmovne`) to conditionally move |
| 90 | +/// `src` to `dst` when `condition` is nonzero. |
| 91 | +#[inline(always)] |
| 92 | +pub fn cmovnz(condition: u64, src: u64, dst: &mut u64) { |
| 93 | + unsafe { |
| 94 | + asm! { |
| 95 | + "test {0}, {0}", |
| 96 | + "cmovnz {1}, {2}", |
| 97 | + in(reg) condition, |
| 98 | + inlateout(reg) *dst, |
| 99 | + in(reg) src |
| 100 | + }; |
| 101 | + } |
| 102 | +} |
| 103 | + |
| 104 | +/// Unsigned multiply without affecting flags. |
| 105 | +/// |
| 106 | +/// Performs an unsigned multiplication of the implicit source operand and the |
| 107 | +/// specified source operand (the third operand) and stores the low half of the |
| 108 | +/// result in the second destination (second operand), the high half of the |
| 109 | +/// result in the first destination operand (first operand), without reading or |
| 110 | +/// writing the arithmetic flags. |
| 111 | +/// |
| 112 | +/// This enables efficient programming where the software can interleave add |
| 113 | +/// with carry operations and multiplications. |
| 114 | +/// |
| 115 | +/// If the first and second operand are identical, it will contain the high |
| 116 | +/// half of the multiplication result. |
| 117 | +/// |
| 118 | +/// # Safety |
| 119 | +/// |
| 120 | +/// This function requires support for the Intel BMI2 (Bit Manipulation |
| 121 | +/// Instruction Set 2) extension to the x86 instruction set. |
| 122 | +/// |
| 123 | +/// If called on a CPU which does not support this extension, it will crash the |
| 124 | +/// process with an illegal instruction exception (i.e. `SIGILL`) |
| 125 | +#[target_feature(enable = "bmi2")] |
| 126 | +pub unsafe fn mulx(a: u64, b: u64, lo: &mut u64, hi: &mut u64) { |
| 127 | + asm! { |
| 128 | + "mulx {2}, {1}, {0}", |
| 129 | + in(reg) b, |
| 130 | + lateout(reg) *lo, |
| 131 | + lateout(reg) *hi, |
| 132 | + in("rdx") a |
| 133 | + }; |
| 134 | +} |
| 135 | + |
| 136 | +#[cfg(test)] |
| 137 | +mod tests { |
| 138 | + use super::*; |
| 139 | + |
| 140 | + #[test] |
| 141 | + fn cmovz_works() { |
| 142 | + let mut n = 24; |
| 143 | + cmovz(42, 42, &mut n); |
| 144 | + assert_eq!(n, 24); |
| 145 | + cmovz(0, 42, &mut n); |
| 146 | + assert_eq!(n, 42); |
| 147 | + } |
| 148 | + |
| 149 | + #[test] |
| 150 | + fn cmovnz_works() { |
| 151 | + let mut n = 24; |
| 152 | + cmovnz(0, 42, &mut n); |
| 153 | + assert_eq!(n, 24); |
| 154 | + cmovnz(42, 42, &mut n); |
| 155 | + assert_eq!(n, 42); |
| 156 | + } |
| 157 | +} |
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