From 03757983f837bd89bf08f18569b5ef13ea6c6d8d Mon Sep 17 00:00:00 2001
From: Wenshan-736 <736810738@qq.com>
Date: Wed, 4 Jun 2025 21:14:27 +0800
Subject: [PATCH 1/5] stm32h7r7-atk bsp
---
bsp/stm32/stm32h7r7-atk/.config | 1439 +++++++++++
bsp/stm32/stm32h7r7-atk/.config.old | 1454 +++++++++++
bsp/stm32/stm32h7r7-atk/.cproject | 245 ++
bsp/stm32/stm32h7r7-atk/.gitattributes | 36 +
bsp/stm32/stm32h7r7-atk/.gitignore | 37 +
bsp/stm32/stm32h7r7-atk/.project | 28 +
.../stm32h7r7-atk/EventRecorderStub.scvd | 9 +
bsp/stm32/stm32h7r7-atk/Kconfig | 32 +
bsp/stm32/stm32h7r7-atk/README.md | 130 +
bsp/stm32/stm32h7r7-atk/SConscript | 15 +
bsp/stm32/stm32h7r7-atk/SConstruct | 58 +
.../stm32h7r7-atk/applications/SConscript | 10 +
bsp/stm32/stm32h7r7-atk/applications/main.c | 39 +
.../board/CubeMX_Config/.mxproject | 105 +
.../board/CubeMX_Config/Appli/Core/Inc/main.h | 69 +
.../Appli/Core/Inc/stm32h7rsxx_hal_conf.h | 501 ++++
.../Appli/Core/Inc/stm32h7rsxx_it.h | 68 +
.../board/CubeMX_Config/Appli/Core/Src/main.c | 514 ++++
.../Appli/Core/Src/stm32h7rsxx_hal_msp.c | 605 +++++
.../Appli/Core/Src/stm32h7rsxx_it.c | 232 ++
.../Appli/Core/Src/system_stm32h7rsxx.c | 304 +++
.../board/CubeMX_Config/CubeMX_Config.ioc | 597 +++++
bsp/stm32/stm32h7r7-atk/board/SConscript | 23 +
bsp/stm32/stm32h7r7-atk/board/board.c | 44 +
bsp/stm32/stm32h7r7-atk/board/board.h | 96 +
bsp/stm32/stm32h7r7-atk/board/drv_mpu.c | 140 +
.../board/linker_scripts/link.lds | 215 ++
.../board/linker_scripts/link.sct | 29 +
bsp/stm32/stm32h7r7-atk/board/port/Kconfig | 62 +
bsp/stm32/stm32h7r7-atk/board/port/SConscript | 78 +
bsp/stm32/stm32h7r7-atk/board/port/drv_adc.c | 307 +++
.../stm32h7r7-atk/board/port/drv_common.c | 216 ++
bsp/stm32/stm32h7r7-atk/board/port/drv_dcmi.c | 220 ++
bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c | 697 +++++
.../stm32h7r7-atk/board/port/drv_fdcan.c | 907 +++++++
.../stm32h7r7-atk/board/port/drv_gc0328c.c | 551 ++++
bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c | 829 ++++++
bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.h | 45 +
.../stm32h7r7-atk/board/port/drv_hwtimer.c | 612 +++++
bsp/stm32/stm32h7r7-atk/board/port/drv_lcd.c | 409 +++
.../stm32h7r7-atk/board/port/drv_lptim.c | 127 +
.../stm32h7r7-atk/board/port/drv_ov2640.c | 692 +++++
bsp/stm32/stm32h7r7-atk/board/port/drv_pm.c | 253 ++
.../stm32h7r7-atk/board/port/drv_psram.c | 108 +
bsp/stm32/stm32h7r7-atk/board/port/drv_pwm.c | 570 +++++
bsp/stm32/stm32h7r7-atk/board/port/drv_qspi.c | 400 +++
.../stm32h7r7-atk/board/port/drv_qspi_flash.c | 72 +
bsp/stm32/stm32h7r7-atk/board/port/drv_rtc.c | 303 +++
.../stm32h7r7-atk/board/port/drv_sdmmc.c | 742 ++++++
.../stm32h7r7-atk/board/port/drv_soft_i2c.c | 222 ++
bsp/stm32/stm32h7r7-atk/board/port/drv_spi.c | 914 +++++++
.../board/port/drv_spi_ili9488.c | 1167 +++++++++
.../stm32h7r7-atk/board/port/drv_usart.c | 1294 ++++++++++
.../stm32h7r7-atk/board/port/drv_usart_v2.c | 1363 ++++++++++
bsp/stm32/stm32h7r7-atk/board/port/drv_usbd.c | 277 ++
bsp/stm32/stm32h7r7-atk/board/port/drv_usbh.c | 254 ++
bsp/stm32/stm32h7r7-atk/board/port/drv_wdt.c | 133 +
bsp/stm32/stm32h7r7-atk/board/port/drv_wlan.c | 259 ++
.../board/port/drv_xspi_norflash.c | 30 +
bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h | 53 +
.../stm32h7r7-atk/board/port/filesystem.c | 166 ++
.../board/port/include/config/adc_config.h | 93 +
.../board/port/include/config/dma_config.h | 174 ++
.../board/port/include/config/pwm_config.h | 68 +
.../board/port/include/config/qspi_config.h | 56 +
.../board/port/include/config/sdio_config.h | 44 +
.../board/port/include/config/spi_config.h | 194 ++
.../board/port/include/config/tim_config.h | 56 +
.../board/port/include/config/uart_config.h | 315 +++
.../board/port/include/config/usbd_config.h | 42 +
.../board/port/include/drv_common.h | 67 +
.../board/port/include/drv_config.h | 125 +
.../board/port/include/drv_dcmi.h | 34 +
.../board/port/include/drv_dma.h | 52 +
.../board/port/include/drv_eth.h | 116 +
.../board/port/include/drv_fdcan.h | 71 +
.../board/port/include/drv_flash.h | 31 +
.../board/port/include/drv_gc0328c.h | 521 ++++
.../board/port/include/drv_gpio.h | 45 +
.../board/port/include/drv_lcd_font.h | 795 ++++++
.../board/port/include/drv_log.h | 27 +
.../board/port/include/drv_lptim.h | 23 +
.../board/port/include/drv_ov2640.h | 553 ++++
.../board/port/include/drv_qspi.h | 17 +
.../board/port/include/drv_sdmmc.h | 72 +
.../board/port/include/drv_soft_i2c.h | 73 +
.../board/port/include/drv_spi.h | 62 +
.../board/port/include/drv_spi_ili9488.h | 64 +
.../board/port/include/drv_touch.h | 26 +
.../board/port/include/drv_usart.h | 81 +
.../board/port/include/drv_usart_v2.h | 83 +
.../board/port/include/drv_usbh.h | 21 +
.../board/port/include/lcd_port.h | 107 +
.../board/port/include/lcd_spi_port.h | 39 +
.../board/port/include/psram_port.h | 20 +
.../board/port/include/rttlogo.h | 2072 +++++++++++++++
.../board/port/include/sdram_port.h | 65 +
.../board/stldr/ATK-DNH7R7_XSPI_MULTIPLE.FLM | Bin 0 -> 352336 bytes
bsp/stm32/stm32h7r7-atk/exclude_list.json | 1 +
bsp/stm32/stm32h7r7-atk/figures/board.png | Bin 0 -> 1585335 bytes
bsp/stm32/stm32h7r7-atk/makefile.targets | 6 +
bsp/stm32/stm32h7r7-atk/mklinks.bat | 6 +
bsp/stm32/stm32h7r7-atk/project.uvoptx | 1454 +++++++++++
bsp/stm32/stm32h7r7-atk/project.uvprojx | 2274 +++++++++++++++++
bsp/stm32/stm32h7r7-atk/rtconfig.h | 436 ++++
bsp/stm32/stm32h7r7-atk/rtconfig.py | 135 +
bsp/stm32/stm32h7r7-atk/rtconfig_preinc.h | 15 +
bsp/stm32/stm32h7r7-atk/template.uvoptx | 194 ++
bsp/stm32/stm32h7r7-atk/template.uvprojx | 401 +++
109 files changed, 32632 insertions(+)
create mode 100644 bsp/stm32/stm32h7r7-atk/.config
create mode 100644 bsp/stm32/stm32h7r7-atk/.config.old
create mode 100644 bsp/stm32/stm32h7r7-atk/.cproject
create mode 100644 bsp/stm32/stm32h7r7-atk/.gitattributes
create mode 100644 bsp/stm32/stm32h7r7-atk/.gitignore
create mode 100644 bsp/stm32/stm32h7r7-atk/.project
create mode 100644 bsp/stm32/stm32h7r7-atk/EventRecorderStub.scvd
create mode 100644 bsp/stm32/stm32h7r7-atk/Kconfig
create mode 100644 bsp/stm32/stm32h7r7-atk/README.md
create mode 100644 bsp/stm32/stm32h7r7-atk/SConscript
create mode 100644 bsp/stm32/stm32h7r7-atk/SConstruct
create mode 100644 bsp/stm32/stm32h7r7-atk/applications/SConscript
create mode 100644 bsp/stm32/stm32h7r7-atk/applications/main.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc
create mode 100644 bsp/stm32/stm32h7r7-atk/board/SConscript
create mode 100644 bsp/stm32/stm32h7r7-atk/board/board.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/board.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/drv_mpu.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds
create mode 100644 bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/Kconfig
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/SConscript
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_adc.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_common.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_dcmi.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_fdcan.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_gc0328c.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_hwtimer.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_lcd.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_lptim.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_ov2640.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_pm.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_pwm.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_qspi.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_qspi_flash.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_rtc.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_spi.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_spi_ili9488.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_usbd.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_usbh.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_wdt.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_wlan.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/drv_xspi_norflash.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/filesystem.c
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/adc_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/pwm_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/qspi_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/spi_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/config/usbd_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_dcmi.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_flash.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_gc0328c.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_lcd_font.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_lptim.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_ov2640.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_qspi.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi_ili9488.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_touch.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/drv_usbh.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/lcd_port.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/lcd_spi_port.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/port/include/sdram_port.h
create mode 100644 bsp/stm32/stm32h7r7-atk/board/stldr/ATK-DNH7R7_XSPI_MULTIPLE.FLM
create mode 100644 bsp/stm32/stm32h7r7-atk/exclude_list.json
create mode 100644 bsp/stm32/stm32h7r7-atk/figures/board.png
create mode 100644 bsp/stm32/stm32h7r7-atk/makefile.targets
create mode 100644 bsp/stm32/stm32h7r7-atk/mklinks.bat
create mode 100644 bsp/stm32/stm32h7r7-atk/project.uvoptx
create mode 100644 bsp/stm32/stm32h7r7-atk/project.uvprojx
create mode 100644 bsp/stm32/stm32h7r7-atk/rtconfig.h
create mode 100644 bsp/stm32/stm32h7r7-atk/rtconfig.py
create mode 100644 bsp/stm32/stm32h7r7-atk/rtconfig_preinc.h
create mode 100644 bsp/stm32/stm32h7r7-atk/template.uvoptx
create mode 100644 bsp/stm32/stm32h7r7-atk/template.uvprojx
diff --git a/bsp/stm32/stm32h7r7-atk/.config b/bsp/stm32/stm32h7r7-atk/.config
new file mode 100644
index 00000000000..b774f73edcd
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.config
@@ -0,0 +1,1439 @@
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# end of kservice optimization
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_SMALL_MEM is not set
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=384
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50100
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=9
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=15
+CONFIG_FINSH_THREAD_STACK_SIZE=8192
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=10
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# CONFIG_RT_DFS_ELM_USE_EXFAT is not set
+# end of elm-chan's FatFs, Generic FAT Filesystem Module
+
+CONFIG_RT_USING_DFS_DEVFS=y
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_DFS_MQUEUE is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+# CONFIG_RT_USING_POSIX_DEVIO is not set
+# CONFIG_RT_USING_POSIX_STDIO is not set
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_EVENTFD is not set
+# CONFIG_RT_USING_POSIX_TIMERFD is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+CONFIG_RT_USING_SAL=y
+# CONFIG_SAL_INTERNET_CHECK is not set
+
+#
+# Docking with protocol stacks
+#
+# CONFIG_SAL_USING_LWIP is not set
+# CONFIG_SAL_USING_AT is not set
+# CONFIG_SAL_USING_TLS is not set
+# end of Docking with protocol stacks
+
+CONFIG_SAL_USING_POSIX=y
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_ULOG=y
+# CONFIG_ULOG_OUTPUT_LVL_A is not set
+# CONFIG_ULOG_OUTPUT_LVL_E is not set
+# CONFIG_ULOG_OUTPUT_LVL_W is not set
+# CONFIG_ULOG_OUTPUT_LVL_I is not set
+CONFIG_ULOG_OUTPUT_LVL_D=y
+CONFIG_ULOG_OUTPUT_LVL=7
+CONFIG_ULOG_USING_ISR_LOG=y
+CONFIG_ULOG_ASSERT_ENABLE=y
+CONFIG_ULOG_LINE_BUF_SIZE=128
+# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set
+
+#
+# log format
+#
+CONFIG_ULOG_OUTPUT_FLOAT=y
+CONFIG_ULOG_USING_COLOR=y
+CONFIG_ULOG_OUTPUT_TIME=y
+# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set
+CONFIG_ULOG_OUTPUT_LEVEL=y
+CONFIG_ULOG_OUTPUT_TAG=y
+# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set
+# end of log format
+
+CONFIG_ULOG_BACKEND_USING_CONSOLE=y
+# CONFIG_ULOG_BACKEND_USING_FILE is not set
+# CONFIG_ULOG_USING_FILTER is not set
+# CONFIG_ULOG_USING_SYSLOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+CONFIG_PKG_USING_RT_VSNPRINTF_FULL=y
+CONFIG_PKG_RT_VSNPRINTF_FULL_PATH="/packages/system/enhanced-kservice/rt_vsnprintf_full"
+CONFIG_PKG_VSNPRINTF_SUPPORT_DECIMAL_SPECIFIERS=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_EXPONENTIAL_SPECIFIERS=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_WRITEBACK_SPECIFIER=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_LONG_LONG=y
+CONFIG_PKG_VSNPRINTF_CHECK_FOR_NUL_IN_FORMAT_SPECIFIER=y
+# CONFIG_PKG_VSNPRINTF_SUPPORT_MSVC_STYLE_INTEGER_SPECIFIERS is not set
+CONFIG_PKG_VSNPRINTF_INTEGER_BUFFER_SIZE=32
+CONFIG_PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE=32
+CONFIG_PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION=6
+CONFIG_PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9
+CONFIG_PKG_VSNPRINTF_LOG10_TAYLOR_TERMS=4
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SNPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_PRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSNPRINTF is not set
+CONFIG_PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION=y
+CONFIG_PKG_RT_VSNPRINTF_FULL_VER="latest"
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+
+#
+# HC32 DDL Drivers
+#
+# end of HC32 DDL Drivers
+
+#
+# NXP HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
+# end of NXP HAL & SDK Drivers
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# CONFIG_PKG_USING_QMI8658 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
+# CONFIG_PKG_USING_SEAN_WS2812B is not set
+# CONFIG_PKG_USING_IC74HC165 is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32H7RS=y
+CONFIG_SOC_SERIES_STM32H7RS=y
+# CONFIG_RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT is not set
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_SCB_ENABLE_I_CACHE=y
+CONFIG_BSP_SCB_ENABLE_D_CACHE=y
+# CONFIG_BSP_USING_USB_TO_USART is not set
+# CONFIG_BSP_USING_XSPI_NORFLASH is not set
+# CONFIG_BSP_USING_WIFI is not set
+# CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_LVGL_DEMO is not set
+# CONFIG_BSP_USING_FS is not set
+# end of Onboard Peripheral Drivers
+
+#
+# On-chip Peripheral
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_UART1_TX_USING_DMA is not set
+CONFIG_BSP_UART1_RX_BUFSIZE=512
+CONFIG_BSP_UART1_TX_BUFSIZE=512
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART7 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SDIO is not set
+CONFIG_BSP_USING_PSRAM=y
+CONFIG_BSP_USING_PSRAM_TEST=y
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_DCMI is not set
+# CONFIG_BSP_USING_FDCAN is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_USBH is not set
+# CONFIG_BSP_USING_TIM is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# end of On-chip Peripheral
+# end of Hardware Drivers Config
+
+#
+# External Libraries
+#
+# CONFIG_ART_PI_USING_WIFI_6212_LIB is not set
+# CONFIG_ART_PI_TouchGFX_LIB is not set
+# end of External Libraries
+
+CONFIG_FIRMWARE_EXEC_USING_OSPI_FLASH=y
+CONFIG_RT_STUDIO_BUILT_IN=y
diff --git a/bsp/stm32/stm32h7r7-atk/.config.old b/bsp/stm32/stm32h7r7-atk/.config.old
new file mode 100644
index 00000000000..58c02c438b4
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.config.old
@@ -0,0 +1,1454 @@
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# end of kservice optimization
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_SMALL_MEM is not set
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=384
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50100
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=9
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=15
+CONFIG_FINSH_THREAD_STACK_SIZE=8192
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=10
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# CONFIG_RT_DFS_ELM_USE_EXFAT is not set
+# end of elm-chan's FatFs, Generic FAT Filesystem Module
+
+CONFIG_RT_USING_DFS_DEVFS=y
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_DFS_MQUEUE is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+# CONFIG_RT_USING_POSIX_DEVIO is not set
+# CONFIG_RT_USING_POSIX_STDIO is not set
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_EVENTFD is not set
+# CONFIG_RT_USING_POSIX_TIMERFD is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+CONFIG_RT_USING_SAL=y
+# CONFIG_SAL_INTERNET_CHECK is not set
+
+#
+# Docking with protocol stacks
+#
+# CONFIG_SAL_USING_LWIP is not set
+# CONFIG_SAL_USING_AT is not set
+# CONFIG_SAL_USING_TLS is not set
+# end of Docking with protocol stacks
+
+CONFIG_SAL_USING_POSIX=y
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_ULOG=y
+# CONFIG_ULOG_OUTPUT_LVL_A is not set
+# CONFIG_ULOG_OUTPUT_LVL_E is not set
+# CONFIG_ULOG_OUTPUT_LVL_W is not set
+# CONFIG_ULOG_OUTPUT_LVL_I is not set
+CONFIG_ULOG_OUTPUT_LVL_D=y
+CONFIG_ULOG_OUTPUT_LVL=7
+CONFIG_ULOG_USING_ISR_LOG=y
+CONFIG_ULOG_ASSERT_ENABLE=y
+CONFIG_ULOG_LINE_BUF_SIZE=128
+# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set
+
+#
+# log format
+#
+CONFIG_ULOG_OUTPUT_FLOAT=y
+CONFIG_ULOG_USING_COLOR=y
+CONFIG_ULOG_OUTPUT_TIME=y
+# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set
+CONFIG_ULOG_OUTPUT_LEVEL=y
+CONFIG_ULOG_OUTPUT_TAG=y
+# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set
+# end of log format
+
+CONFIG_ULOG_BACKEND_USING_CONSOLE=y
+# CONFIG_ULOG_BACKEND_USING_FILE is not set
+# CONFIG_ULOG_USING_FILTER is not set
+# CONFIG_ULOG_USING_SYSLOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+CONFIG_PKG_USING_NETUTILS=y
+CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils"
+# CONFIG_PKG_NETUTILS_TFTP is not set
+# CONFIG_PKG_NETUTILS_IPERF is not set
+CONFIG_PKG_NETUTILS_NTP=y
+CONFIG_NTP_USING_AUTO_SYNC=y
+CONFIG_NTP_AUTO_SYNC_FIRST_DELAY=30
+CONFIG_NTP_AUTO_SYNC_PERIOD=3600
+CONFIG_NETUTILS_NTP_HOSTNAME="cn.ntp.org.cn"
+CONFIG_NETUTILS_NTP_HOSTNAME2="ntp.rt-thread.org"
+CONFIG_NETUTILS_NTP_HOSTNAME3="edu.ntp.org.cn"
+# CONFIG_PKG_NETUTILS_TELNET is not set
+CONFIG_PKG_USING_NETUTILS_LATEST_VERSION=y
+# CONFIG_PKG_USING_NETUTILS_V133 is not set
+CONFIG_PKG_NETUTILS_VER="latest"
+CONFIG_PKG_NETUTILS_VER_NUM=0x99999
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+CONFIG_PKG_USING_RT_VSNPRINTF_FULL=y
+CONFIG_PKG_RT_VSNPRINTF_FULL_PATH="/packages/system/enhanced-kservice/rt_vsnprintf_full"
+CONFIG_PKG_VSNPRINTF_SUPPORT_DECIMAL_SPECIFIERS=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_EXPONENTIAL_SPECIFIERS=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_WRITEBACK_SPECIFIER=y
+CONFIG_PKG_VSNPRINTF_SUPPORT_LONG_LONG=y
+CONFIG_PKG_VSNPRINTF_CHECK_FOR_NUL_IN_FORMAT_SPECIFIER=y
+# CONFIG_PKG_VSNPRINTF_SUPPORT_MSVC_STYLE_INTEGER_SPECIFIERS is not set
+CONFIG_PKG_VSNPRINTF_INTEGER_BUFFER_SIZE=32
+CONFIG_PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE=32
+CONFIG_PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION=6
+CONFIG_PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9
+CONFIG_PKG_VSNPRINTF_LOG10_TAYLOR_TERMS=4
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SNPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_PRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSPRINTF is not set
+# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSNPRINTF is not set
+CONFIG_PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION=y
+CONFIG_PKG_RT_VSNPRINTF_FULL_VER="latest"
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+
+#
+# HC32 DDL Drivers
+#
+# end of HC32 DDL Drivers
+
+#
+# NXP HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
+# end of NXP HAL & SDK Drivers
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# CONFIG_PKG_USING_QMI8658 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
+# CONFIG_PKG_USING_SEAN_WS2812B is not set
+# CONFIG_PKG_USING_IC74HC165 is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32H7RS=y
+CONFIG_SOC_SERIES_STM32H7RS=y
+# CONFIG_RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT is not set
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_SCB_ENABLE_I_CACHE=y
+CONFIG_BSP_SCB_ENABLE_D_CACHE=y
+# CONFIG_BSP_USING_USB_TO_USART is not set
+# CONFIG_BSP_USING_XSPI_NORFLASH is not set
+# CONFIG_BSP_USING_WIFI is not set
+# CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_LVGL_DEMO is not set
+# CONFIG_BSP_USING_FS is not set
+# end of Onboard Peripheral Drivers
+
+#
+# On-chip Peripheral
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_UART1_TX_USING_DMA is not set
+CONFIG_BSP_UART1_RX_BUFSIZE=512
+CONFIG_BSP_UART1_TX_BUFSIZE=512
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART7 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SDIO is not set
+CONFIG_BSP_USING_PSRAM=y
+CONFIG_BSP_USING_PSRAM_TEST=y
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_DCMI is not set
+# CONFIG_BSP_USING_FDCAN is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_USBH is not set
+# CONFIG_BSP_USING_TIM is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# end of On-chip Peripheral
+# end of Hardware Drivers Config
+
+#
+# External Libraries
+#
+# CONFIG_ART_PI_USING_WIFI_6212_LIB is not set
+# CONFIG_ART_PI_TouchGFX_LIB is not set
+# end of External Libraries
+
+CONFIG_FIRMWARE_EXEC_USING_OSPI_FLASH=y
+CONFIG_RT_STUDIO_BUILT_IN=y
diff --git a/bsp/stm32/stm32h7r7-atk/.cproject b/bsp/stm32/stm32h7r7-atk/.cproject
new file mode 100644
index 00000000000..16ffe062dc7
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.cproject
@@ -0,0 +1,245 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/stm32/stm32h7r7-atk/.gitattributes b/bsp/stm32/stm32h7r7-atk/.gitattributes
new file mode 100644
index 00000000000..1f98e683d83
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.gitattributes
@@ -0,0 +1,36 @@
+# Sources
+*.c text diff=c
+*.cc text diff=cpp
+*.cxx text diff=cpp
+*.cpp text diff=cpp
+*.c++ text diff=cpp
+*.hpp text diff=cpp
+*.h text diff=c
+*.h++ text diff=cpp
+*.hh text diff=cpp
+
+# Compiled Object files
+*.slo binary
+*.lo binary
+*.o binary
+*.obj binary
+
+# Precompiled Headers
+*.gch binary
+*.pch binary
+
+# Compiled Dynamic libraries
+*.so binary
+*.dylib binary
+*.dll binary
+
+# Compiled Static libraries
+*.lai binary
+*.la binary
+*.a binary
+*.lib binary
+
+# Executables
+*.exe binary
+*.out binary
+*.app binary
diff --git a/bsp/stm32/stm32h7r7-atk/.gitignore b/bsp/stm32/stm32h7r7-atk/.gitignore
new file mode 100644
index 00000000000..34f7681a001
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.gitignore
@@ -0,0 +1,37 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.pdb
+*.idb
+*.ilk
+!*.old
+build
+Debug
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
diff --git a/bsp/stm32/stm32h7r7-atk/.project b/bsp/stm32/stm32h7r7-atk/.project
new file mode 100644
index 00000000000..855079d83dd
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/.project
@@ -0,0 +1,28 @@
+
+
+ project
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.rt-thread.studio.rttnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
diff --git a/bsp/stm32/stm32h7r7-atk/EventRecorderStub.scvd b/bsp/stm32/stm32h7r7-atk/EventRecorderStub.scvd
new file mode 100644
index 00000000000..2956b296838
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/bsp/stm32/stm32h7r7-atk/Kconfig b/bsp/stm32/stm32h7r7-atk/Kconfig
new file mode 100644
index 00000000000..e224ae7e92f
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/Kconfig
@@ -0,0 +1,32 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "rt-thread"
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+config PLATFORM_DIR
+ string
+ option env="PLATFORM_DIR"
+ default "F:/github/rtthread/workspace/rtthread-atk/platform"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$RTT_DIR/../libraries/Kconfig"
+
+config RT_STUDIO_BUILT_IN
+ bool
+ select ARCH_ARM_CORTEX_M7
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
diff --git a/bsp/stm32/stm32h7r7-atk/README.md b/bsp/stm32/stm32h7r7-atk/README.md
new file mode 100644
index 00000000000..90a8c3f8fc3
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/README.md
@@ -0,0 +1,130 @@
+# STM32H7r7-atk 开发板 BSP 说明
+
+## 简介
+
+本文档为 wenshan 为 STM32H7r7-atk开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+阿波罗 STM32H7r7 是正点原子推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H7r7 的芯片性能。
+
+开发板外观如下图所示：
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32H7r7l8h，主频 600MHz，128K FLASH ，620K RAM
+- 外部 HyperRam：W955K8MBYA，32MB
+- 外部 SD NAND：MKDV4GCL，2GB
+- 外部 HyperFlash：GD25LX256MEBFR，32MB
+- 常用外设
+ - LED：2个，DS0（红色，PB1），DS1（绿色，PB0）
+ - 按键：4个，KEY_UP（兼具唤醒功能，PA0），K0（PH3），K1（PH2），K2（PC13）
+- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口等
+- 调试接口，标准 SWD
+
+开发板更多详细信息请参考正点原子 [STM32阿波罗开发板介绍](https://eboard.taobao.com/index.htm)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注** |
+| :---------------- | :----------: | :------------------------------------------------------ |
+| USB 转串口 | 支持 | |
+| ESP32接口 | 支持 | |
+| hyperbus Flash | 支持 | |
+| 以太网 | 支持 | |
+| SD卡 | 支持 | |
+| HyperRAM | 支持 | |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持 | |
+| UART | 支持 | |
+| SPI | 支持 | |
+| I2C | 支持 | 软件iic |
+| ETH | 支持 | |
+| CAN-FD | 支持 | HDR暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+**请注意！！！**
+
+在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
+
+```bash
+pkgs --update
+```
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 DAP_LINK 仿真器下载程序，在通过 DAP_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.1.0 build Jun 2 2025 12:43:54
+ 2006 - 2024 Copyright by RT-Thread team
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+1. UART暂未完成对DMA的支持，同时开启uart7和uart1的dma会进入hardfault，只打开uart1的dma会有概率进入hardfault。
+2. 开发板连接正点原子的esp32模块可能会报execute command (AT+CIPDNS?) failed错误，这是因为esp32的at固件不支持这个at指令，需要升级esp32的固件版本，详情参照网上教程。
+3. 正点原子暂未提供可以用在rtthread studio上的stldr下载文件，故在rtthread studio上只能编译还不能下载，现在只有在keil上用的flm下载文件。
+4. 如果使用eth的话，hal库一定要是1.3版本以上！
+5. 核心板有四种，这里使用的是正点原子的h7r7的高配板。
+6. 需要先下载对应的bootloader，在[Wenshan-736/stm32h7r7-atk](https://github.com/Wenshan-736/stm32h7r7-atk/tree/main)里面
+
+## 联系人信息
+
+维护人:[Wenshan-736](https://github.com/Wenshan-736), 邮箱：<736810738@qq.com>
diff --git a/bsp/stm32/stm32h7r7-atk/SConscript b/bsp/stm32/stm32h7r7-atk/SConscript
new file mode 100644
index 00000000000..20f7689c53c
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/stm32/stm32h7r7-atk/SConstruct b/bsp/stm32/stm32h7r7-atk/SConstruct
new file mode 100644
index 00000000000..2104b127bb1
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/SConstruct
@@ -0,0 +1,58 @@
+import os
+import sys
+import rtconfig
+
+if os.path.exists('rt-thread'):
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except Exception as e:
+ print("Error message:", e.message)
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ sys.exit(-1)
+
+TARGET = 'rt-thread.elf'
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+env.AppendUnique(CPPDEFINES = [])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+if os.path.exists('libraries'):
+ libraries_path_prefix = 'libraries'
+else:
+ libraries_path_prefix = '../../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32H7RSxx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+if not os.path.exists('libraries'):
+ # include libraries
+ objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript')))
+
+ # include applications
+ #objs.extend(SConscript(os.path.join(APP_ROOT, 'applications', 'SConscript')))
+
+#objs += PrepareBuilding(env, LIB_ROOT, has_libcpu=False)
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/stm32/stm32h7r7-atk/applications/SConscript b/bsp/stm32/stm32h7r7-atk/applications/SConscript
new file mode 100644
index 00000000000..114bfbabf21
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/applications/SConscript
@@ -0,0 +1,10 @@
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+path = [cwd]
+src = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/stm32/stm32h7r7-atk/applications/main.c b/bsp/stm32/stm32h7r7-atk/applications/main.c
new file mode 100644
index 00000000000..0474f868d15
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/applications/main.c
@@ -0,0 +1,39 @@
+/*
+ * @Author : wenshan
+ * @Date : 2025-05-14 20:21:24
+ * @LastEditors : wenshan
+ * @LastEditTime : 2025-06-02 21:53:35
+ * @Description :
+ * @FilePath : \rtthread-atk\applications\main.c
+ */
+
+#include
+#include
+#include "drv_common.h"
+
+
+#define LED_PIN GET_PIN(D, 14)
+
+int main(void)
+{
+ rt_uint32_t count = 1;
+
+ while(count++)
+ {
+ rt_thread_mdelay(500);
+ rt_pin_write(LED_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED_PIN, PIN_LOW);
+ }
+ return RT_EOK;
+}
+
+#include "stm32h7rsxx.h"
+static int vtor_config(void)
+{
+ /* Vector Table Relocation in Internal XSPI1_BASE */
+ SCB->VTOR = XSPI1_BASE;
+ return 0;
+}
+INIT_BOARD_EXPORT(vtor_config);
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject
new file mode 100644
index 00000000000..dbd6af51bdd
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject
@@ -0,0 +1,105 @@
+[Boot:PreviousLibFiles]
+LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[Boot:PreviousUsedKeilFiles]
+SourceFiles=..\Boot\Core\Src\main.c;..\Boot\Core\Src\stm32h7rsxx_it.c;..\Boot\Core\Src\stm32h7rsxx_hal_msp.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;;
+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Boot\Core\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;
+CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[Appli:PreviousLibFiles]
+LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[Appli:PreviousUsedKeilFiles]
+SourceFiles=..\Appli\Core\Src\main.c;..\Appli\Core\Src\stm32h7rsxx_it.c;..\Appli\Core\Src\stm32h7rsxx_hal_msp.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;;
+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Appli\Core\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;
+CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[Eloader:PreviousLibFiles]
+LibFiles=Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7s7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[Eloader:PreviousUsedKeilFiles]
+SourceFiles=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;;
+HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include;
+CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousLibFiles]
+LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[PreviousUsedKeilFiles]
+SourceFiles=..\Appli\Core\Src\main.c;..\Boot\Core\Src\main.c;..\Boot\Core\Src\stm32h7rsxx_it.c;..\Boot\Core\Src\stm32h7rsxx_hal_msp.c;..\Appli\Core\Src\stm32h7rsxx_it.c;..\Appli\Core\Src\stm32h7rsxx_hal_msp.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;..\Src\system_stm32h7rsxx.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;..\Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;..\Src\system_stm32h7rsxx.c;..\Boot\Core\Src\system_stm32h7rsxx.c;..\Appli\Core\Src\system_stm32h7rsxx.c;..\ExtMemLoader\Core\Src\system_stm32h7rsxx.c;;;
+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Boot\Core\Inc;..\Appli\Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[Eloader:PreviousGenFiles]
+SourceFiles=;
+
+[ExtMemLoader:PreviousLibFiles]
+LibFiles=Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[ExtMemLoader:PreviousUsedKeilFiles]
+SourceFiles=..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;;
+HeaderPath=..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;
+CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[Boot:PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=..\Boot\Core\Inc\stm32h7rsxx_it.h
+HeaderFiles#1=..\Boot\Core\Inc\stm32h7rsxx_hal_conf.h
+HeaderFiles#2=..\Boot\Core\Inc\main.h
+HeaderFolderListSize=1
+HeaderPath#0=..\Boot\Core\Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=..\Boot\Core\Src\stm32h7rsxx_it.c
+SourceFiles#1=..\Boot\Core\Src\stm32h7rsxx_hal_msp.c
+SourceFiles#2=..\Boot\Core\Src\main.c
+SourceFolderListSize=1
+SourcePath#0=..\Boot\Core\Src
+SourceFiles=;
+
+[Appli:PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=..\Appli\Core\Inc\stm32h7rsxx_it.h
+HeaderFiles#1=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h
+HeaderFiles#2=..\Appli\Core\Inc\main.h
+HeaderFolderListSize=1
+HeaderPath#0=..\Appli\Core\Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=..\Appli\Core\Src\stm32h7rsxx_it.c
+SourceFiles#1=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c
+SourceFiles#2=..\Appli\Core\Src\main.c
+SourceFolderListSize=1
+SourcePath#0=..\Appli\Core\Src
+SourceFiles=;
+
+[ExtMemLoader:PreviousGenFiles]
+SourceFiles=;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=6
+HeaderFiles#0=..\Boot\Core\Inc\stm32h7rsxx_it.h
+HeaderFiles#1=..\Boot\Core\Inc\stm32h7rsxx_hal_conf.h
+HeaderFiles#2=..\Boot\Core\Inc\main.h
+HeaderFiles#3=..\Appli\Core\Inc\stm32h7rsxx_it.h
+HeaderFiles#4=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h
+HeaderFiles#5=..\Appli\Core\Inc\main.h
+HeaderFolderListSize=2
+HeaderPath#0=..\Boot\Core\Inc
+HeaderPath#1=..\Appli\Core\Inc
+HeaderFiles=;
+SourceFileListSize=6
+SourceFiles#0=..\Boot\Core\Src\stm32h7rsxx_it.c
+SourceFiles#1=..\Boot\Core\Src\stm32h7rsxx_hal_msp.c
+SourceFiles#2=..\Boot\Core\Src\main.c
+SourceFiles#3=..\Appli\Core\Src\stm32h7rsxx_it.c
+SourceFiles#4=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c
+SourceFiles#5=..\Appli\Core\Src\main.c
+SourceFolderListSize=2
+SourcePath#0=..\Boot\Core\Src
+SourcePath#1=..\Appli\Core\Src
+SourceFiles=;
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h
new file mode 100644
index 00000000000..439921be213
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7rsxx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "drv_common.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h
new file mode 100644
index 00000000000..bc8de5225ea
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h
@@ -0,0 +1,501 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7rsxx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32h7rsxx_hal_conf.h.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7RSxx_HAL_CONF_H
+#define STM32H7RSxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_CORDIC_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DCMIPP_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_DTS_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+/* #define HAL_GFXMMU_MODULE_ENABLED */
+/* #define HAL_GFXTIM_MODULE_ENABLED */
+/* #define HAL_GPU2D_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_I3C_MODULE_ENABLED */
+/* #define HAL_ICACHE_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_JPEG_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_MCE_MODULE_ENABLED */
+/* #define HAL_MDF_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_PKA_MODULE_ENABLED */
+/* #define HAL_PSSI_MODULE_ENABLED */
+/* #define HAL_RAMECC_MODULE_ENABLED */
+/* #define HAL_RCC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+#define HAL_XSPI_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low-power oscillator (CSI) default value.
+ * This value is the default CSI range value after Reset.
+ */
+#if !defined (CSI_VALUE)
+#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG.
+ * This internal oscillator is mainly dedicated to provide a high precision clock to
+ * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ * which is subject to manufacturing process variations.
+ */
+ #if !defined (HSI48_VALUE)
+ #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz.
+ The real value my vary depending on manufacturing process variations. */
+ #endif /* HSI48_VALUE */
+
+/**
+* @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz.
+ Value of the Internal Low Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+#endif /* LSI_VALUE */
+
+/**
+* @brief External Low Speed oscillator (LSE) value.
+*/
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF
+ * This value is used by the RCC HAL module to provide the digital audio interfaces
+ * frequency. This clock source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0U
+
+/* ########################## Assert Selection ############################## */
+/**
+* @brief Uncomment the line below to expanse the "assert_param" macro in the
+* HAL drivers code
+*/
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+* @brief Set below the peripheral configuration to "1U" to add the support
+* of HAL callback registration/unregistration feature for the HAL
+* driver(s). This allows user application to provide specific callback
+* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file
+* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+* for each PPP peripheral).
+*/
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
+#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
+#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_MDF_REGISTER_CALLBACKS 0U
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
+#define USE_HAL_PKA_REGISTER_CALLBACKS 0U
+#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
+#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME 0U
+
+/* ################## HASH peripheral configuration ########################## */
+
+#define USE_HAL_HASH_SUSPEND_RESUME 0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DCMIPP_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_dcmipp.h"
+#endif /* HAL_DCMIPP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_GFXTIM_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_gfxtim.h"
+#endif /* HAL_GFXTIM_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_I3C_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_i3c.h"
+#endif /* HAL_I3C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MCE_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_mce.h"
+#endif /* HAL_MCE_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_ramecc.h"
+#endif /* HAL_RAMECC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t *file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7RSxx_HAL_CONF_H */
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h
new file mode 100644
index 00000000000..2803bc38798
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7rsxx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7RSxx_IT_H
+#define __STM32H7RSxx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void ETH_IRQHandler(void);
+void SDMMC1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7RSxx_IT_H */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c
new file mode 100644
index 00000000000..e05d2b5223b
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c
@@ -0,0 +1,514 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "string.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+#pragma location=0x24020000
+ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+#pragma location=0x24020080
+ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+
+#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
+
+__attribute__((at(0x24020000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+__attribute__((at(0x24020080))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+
+#elif (defined ( __GNUC__ ) || defined ( __ARMCC_VERSION )) /* GNU Compiler */
+
+ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDescripSection"))); /* Ethernet Rx DMA Descriptors */
+ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDescripSection"))); /* Ethernet Tx DMA Descriptors */
+#endif
+
+ETH_TxPacketConfigTypeDef TxConfig;
+
+ETH_HandleTypeDef heth;
+
+FDCAN_HandleTypeDef hfdcan1;
+
+SD_HandleTypeDef hsd1;
+
+UART_HandleTypeDef huart7;
+UART_HandleTypeDef huart1;
+
+PCD_HandleTypeDef hpcd_USB_OTG_HS;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void MPU_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_FLASH_Init(void);
+static void MX_USB_OTG_HS_PCD_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_FDCAN1_Init(void);
+static void MX_ETH_Init(void);
+static void MX_SDMMC1_SD_Init(void);
+static void MX_UART7_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+ /* MPU Configuration--------------------------------------------------------*/
+ MPU_Config();
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Update SystemCoreClock variable according to RCC registers values. */
+ SystemCoreClockUpdate();
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_FLASH_Init();
+ MX_USB_OTG_HS_PCD_Init();
+ MX_USART1_UART_Init();
+ MX_FDCAN1_Init();
+ MX_ETH_Init();
+ MX_SDMMC1_SD_Init();
+ MX_UART7_Init();
+ /* USER CODE BEGIN 2 */
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief ETH Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ETH_Init(void)
+{
+
+ /* USER CODE BEGIN ETH_Init 0 */
+
+ /* USER CODE END ETH_Init 0 */
+
+ static uint8_t MACAddr[6];
+
+ /* USER CODE BEGIN ETH_Init 1 */
+
+ /* USER CODE END ETH_Init 1 */
+ heth.Instance = ETH;
+ MACAddr[0] = 0x00;
+ MACAddr[1] = 0x80;
+ MACAddr[2] = 0xE1;
+ MACAddr[3] = 0x00;
+ MACAddr[4] = 0x00;
+ MACAddr[5] = 0x00;
+ heth.Init.MACAddr = &MACAddr[0];
+ heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
+ heth.Init.TxDesc = DMATxDscrTab;
+ heth.Init.RxDesc = DMARxDscrTab;
+ heth.Init.RxBuffLen = 1524;
+
+ /* USER CODE BEGIN MACADDRESS */
+
+ /* USER CODE END MACADDRESS */
+
+ if (HAL_ETH_Init(&heth) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfigTypeDef));
+ TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+ TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+ TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+ /* USER CODE BEGIN ETH_Init 2 */
+
+ /* USER CODE END ETH_Init 2 */
+
+}
+
+/**
+ * @brief FDCAN1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_FDCAN1_Init(void)
+{
+
+ /* USER CODE BEGIN FDCAN1_Init 0 */
+
+ /* USER CODE END FDCAN1_Init 0 */
+
+ /* USER CODE BEGIN FDCAN1_Init 1 */
+
+ /* USER CODE END FDCAN1_Init 1 */
+ hfdcan1.Instance = FDCAN1;
+ hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV6;
+ hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+ hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
+ hfdcan1.Init.AutoRetransmission = DISABLE;
+ hfdcan1.Init.TransmitPause = DISABLE;
+ hfdcan1.Init.ProtocolException = DISABLE;
+ hfdcan1.Init.NominalPrescaler = 2;
+ hfdcan1.Init.NominalSyncJumpWidth = 1;
+ hfdcan1.Init.NominalTimeSeg1 = 19;
+ hfdcan1.Init.NominalTimeSeg2 = 5;
+ hfdcan1.Init.DataPrescaler = 1;
+ hfdcan1.Init.DataSyncJumpWidth = 1;
+ hfdcan1.Init.DataTimeSeg1 = 1;
+ hfdcan1.Init.DataTimeSeg2 = 1;
+ hfdcan1.Init.StdFiltersNbr = 0;
+ hfdcan1.Init.ExtFiltersNbr = 0;
+ hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN FDCAN1_Init 2 */
+
+ /* USER CODE END FDCAN1_Init 2 */
+
+}
+
+/**
+ * @brief FLASH Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_FLASH_Init(void)
+{
+
+ /* USER CODE BEGIN FLASH_Init 0 */
+
+ /* USER CODE END FLASH_Init 0 */
+
+ /* USER CODE BEGIN FLASH_Init 1 */
+
+ /* USER CODE END FLASH_Init 1 */
+ /* USER CODE BEGIN FLASH_Init 2 */
+
+ /* USER CODE END FLASH_Init 2 */
+
+}
+
+/**
+ * @brief SDMMC1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_SDMMC1_SD_Init(void)
+{
+
+ /* USER CODE BEGIN SDMMC1_Init 0 */
+
+ /* USER CODE END SDMMC1_Init 0 */
+
+ /* USER CODE BEGIN SDMMC1_Init 1 */
+
+ /* USER CODE END SDMMC1_Init 1 */
+ hsd1.Instance = SDMMC1;
+ hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+ hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+ hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+ hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+ hsd1.Init.ClockDiv = 0;
+ if (HAL_SD_Init(&hsd1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN SDMMC1_Init 2 */
+
+ /* USER CODE END SDMMC1_Init 2 */
+
+}
+
+/**
+ * @brief UART7 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_UART7_Init(void)
+{
+
+ /* USER CODE BEGIN UART7_Init 0 */
+
+ /* USER CODE END UART7_Init 0 */
+
+ /* USER CODE BEGIN UART7_Init 1 */
+
+ /* USER CODE END UART7_Init 1 */
+ huart7.Instance = UART7;
+ huart7.Init.BaudRate = 115200;
+ huart7.Init.WordLength = UART_WORDLENGTH_8B;
+ huart7.Init.StopBits = UART_STOPBITS_1;
+ huart7.Init.Parity = UART_PARITY_NONE;
+ huart7.Init.Mode = UART_MODE_TX_RX;
+ huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart7.Init.OverSampling = UART_OVERSAMPLING_16;
+ huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ if (HAL_UART_Init(&huart7) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN UART7_Init 2 */
+
+ /* USER CODE END UART7_Init 2 */
+
+}
+
+/**
+ * @brief USART1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART1_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART1_Init 0 */
+
+ /* USER CODE END USART1_Init 0 */
+
+ /* USER CODE BEGIN USART1_Init 1 */
+
+ /* USER CODE END USART1_Init 1 */
+ huart1.Instance = USART1;
+ huart1.Init.BaudRate = 115200;
+ huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ huart1.Init.StopBits = UART_STOPBITS_1;
+ huart1.Init.Parity = UART_PARITY_NONE;
+ huart1.Init.Mode = UART_MODE_TX_RX;
+ huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ if (HAL_UART_Init(&huart1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART1_Init 2 */
+
+ /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+ * @brief USB_OTG_HS Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USB_OTG_HS_PCD_Init(void)
+{
+
+ /* USER CODE BEGIN USB_OTG_HS_Init 0 */
+
+ /* USER CODE END USB_OTG_HS_Init 0 */
+
+ /* USER CODE BEGIN USB_OTG_HS_Init 1 */
+
+ /* USER CODE END USB_OTG_HS_Init 1 */
+ hpcd_USB_OTG_HS.Instance = USB_OTG_HS;
+ hpcd_USB_OTG_HS.Init.dev_endpoints = 9;
+ hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_HIGH;
+ hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
+ hpcd_USB_OTG_HS.Init.dma_enable = DISABLE;
+ hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE;
+ hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE;
+ hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE;
+ hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE;
+ hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE;
+ if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USB_OTG_HS_Init 2 */
+
+ /* USER CODE END USB_OTG_HS_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOM_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ __HAL_RCC_GPION_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOP_CLK_ENABLE();
+ __HAL_RCC_GPIOO_CLK_ENABLE();
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+ /* MPU Configuration */
+
+static void MPU_Config(void)
+{
+ MPU_Region_InitTypeDef MPU_InitStruct = {0};
+
+ /* Disables the MPU */
+ HAL_MPU_Disable();
+
+ /** Initializes and configures the Region and the memory to be protected
+ */
+ MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+ MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+ MPU_InitStruct.BaseAddress = 0x0;
+ MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
+ MPU_InitStruct.SubRegionDisable = 0x87;
+ MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+ MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+ MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+ MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+
+ HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ /* Enables the MPU */
+ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c
new file mode 100644
index 00000000000..3e6d03b1553
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c
@@ -0,0 +1,605 @@
+
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7rsxx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+#include
+#include
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ /* System interrupt init*/
+
+ /* Enable the XSPIM_P1 interface */
+ HAL_PWREx_EnableXSPIM1();
+
+ /* Enable the XSPIM_P2 interface */
+ HAL_PWREx_EnableXSPIM2();
+
+ /* Enable USB Voltage detector */
+ if(HAL_PWREx_EnableUSBVoltageDetector() != HAL_OK)
+ {
+ /* Initialization error */
+ Error_Handler();
+ }
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ETH MSP Initialization
+* This function configures the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(heth->Instance==ETH)
+ {
+ /* USER CODE BEGIN ETH_MspInit 0 */
+
+ /* USER CODE END ETH_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH1REF|RCC_PERIPHCLK_ETH1PHY;
+ PeriphClkInit.Eth1RefClockSelection = RCC_ETH1REFCLKSOURCE_PHY;
+ PeriphClkInit.Eth1PhyClockSelection = RCC_ETH1PHYCLKSOURCE_PLL3S;
+
+ /* USER CODE BEGIN MACADDRESS */
+
+ /* USER CODE END MACADDRESS */
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_ETH1MAC_CLK_ENABLE();
+ __HAL_RCC_ETH1TX_CLK_ENABLE();
+ __HAL_RCC_ETH1RX_CLK_ENABLE();
+
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**ETH GPIO Configuration
+ PD7 ------> ETH_RMII_REF_CLK
+ PG14 ------> ETH_RMII_TXD1
+ PG11 ------> ETH_RMII_TX_EN
+ PG13 ------> ETH_RMII_TXD0
+ PC1 ------> ETH_MDC
+ PC4 ------> ETH_RMII_RXD0
+ PA4 ------> ETH_MDIO
+ PA7 ------> ETH_RMII_CRS_DV
+ PC5 ------> ETH_RMII_RXD1
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF4_ETH;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_11|GPIO_PIN_13;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* ETH interrupt Init */
+ HAL_NVIC_SetPriority(ETH_IRQn, 7, 0);
+ HAL_NVIC_EnableIRQ(ETH_IRQn);
+ /* USER CODE BEGIN ETH_MspInit 1 */
+
+ /* USER CODE END ETH_MspInit 1 */
+
+ }
+
+}
+
+/**
+* @brief ETH MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
+{
+ if(heth->Instance==ETH)
+ {
+ /* USER CODE BEGIN ETH_MspDeInit 0 */
+
+ /* USER CODE END ETH_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_ETH1MAC_CLK_DISABLE();
+ __HAL_RCC_ETH1TX_CLK_DISABLE();
+ __HAL_RCC_ETH1RX_CLK_DISABLE();
+
+ /**ETH GPIO Configuration
+ PD7 ------> ETH_RMII_REF_CLK
+ PG14 ------> ETH_RMII_TXD1
+ PG11 ------> ETH_RMII_TX_EN
+ PG13 ------> ETH_RMII_TXD0
+ PC1 ------> ETH_MDC
+ PC4 ------> ETH_RMII_RXD0
+ PA4 ------> ETH_MDIO
+ PA7 ------> ETH_RMII_CRS_DV
+ PC5 ------> ETH_RMII_RXD1
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_11|GPIO_PIN_13);
+
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
+
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_7);
+
+ /* ETH interrupt DeInit */
+ HAL_NVIC_DisableIRQ(ETH_IRQn);
+ /* USER CODE BEGIN ETH_MspDeInit 1 */
+
+ /* USER CODE END ETH_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief FDCAN MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hfdcan->Instance==FDCAN1)
+ {
+ /* USER CODE BEGIN FDCAN1_MspInit 0 */
+
+ /* USER CODE END FDCAN1_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL1Q;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_FDCAN_CLK_ENABLE();
+
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /**FDCAN1 GPIO Configuration
+ PD1 ------> FDCAN1_TX
+ PD0 ------> FDCAN1_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN FDCAN1_MspInit 1 */
+
+ /* USER CODE END FDCAN1_MspInit 1 */
+
+ }
+
+}
+
+/**
+* @brief FDCAN MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
+{
+ if(hfdcan->Instance==FDCAN1)
+ {
+ /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
+
+ /* USER CODE END FDCAN1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_FDCAN_CLK_DISABLE();
+
+ /**FDCAN1 GPIO Configuration
+ PD1 ------> FDCAN1_TX
+ PD0 ------> FDCAN1_RX
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_1|GPIO_PIN_0);
+
+ /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
+
+ /* USER CODE END FDCAN1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hsd->Instance==SDMMC1)
+ {
+ /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+ /* USER CODE END SDMMC1_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12;
+ PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL2T;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ /**SDMMC1 GPIO Configuration
+ PD2 ------> SDMMC1_CMD
+ PC10 ------> SDMMC1_D2
+ PC11 ------> SDMMC1_D3
+ PC12 ------> SDMMC1_CK
+ PC8 ------> SDMMC1_D0
+ PC9 ------> SDMMC1_D1
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_2;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC1;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC1;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* SDMMC1 interrupt Init */
+ HAL_NVIC_SetPriority(SDMMC1_IRQn, 6, 0);
+ HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+ /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+ /* USER CODE END SDMMC1_MspInit 1 */
+
+ }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+ if(hsd->Instance==SDMMC1)
+ {
+ /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+ /* USER CODE END SDMMC1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+ /**SDMMC1 GPIO Configuration
+ PD2 ------> SDMMC1_CMD
+ PC10 ------> SDMMC1_D2
+ PC11 ------> SDMMC1_D3
+ PC12 ------> SDMMC1_CK
+ PC8 ------> SDMMC1_D0
+ PC9 ------> SDMMC1_D1
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8
+ |GPIO_PIN_9);
+
+ /* SDMMC1 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+ /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+ /* USER CODE END SDMMC1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(huart->Instance==UART7)
+ {
+ /* USER CODE BEGIN UART7_MspInit 0 */
+
+ /* USER CODE END UART7_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART234578;
+ PeriphClkInit.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PCLK1;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_UART7_CLK_ENABLE();
+
+ __HAL_RCC_GPIOM_CLK_ENABLE();
+ /**UART7 GPIO Configuration
+ PM9 ------> UART7_TX
+ PM8 ------> UART7_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_UART7;
+ HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN UART7_MspInit 1 */
+
+ /* USER CODE END UART7_MspInit 1 */
+ }
+ else if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspInit 0 */
+
+ /* USER CODE END USART1_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_USART1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**USART1 GPIO Configuration
+ PB14 ------> USART1_TX
+ PB15 ------> USART1_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART1_MspInit 1 */
+
+ /* USER CODE END USART1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==UART7)
+ {
+ /* USER CODE BEGIN UART7_MspDeInit 0 */
+
+ /* USER CODE END UART7_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_UART7_CLK_DISABLE();
+
+ /**UART7 GPIO Configuration
+ PM9 ------> UART7_TX
+ PM8 ------> UART7_RX
+ */
+ HAL_GPIO_DeInit(GPIOM, GPIO_PIN_9|GPIO_PIN_8);
+
+ /* USER CODE BEGIN UART7_MspDeInit 1 */
+
+ /* USER CODE END UART7_MspDeInit 1 */
+ }
+ else if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+ /* USER CODE END USART1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART1_CLK_DISABLE();
+
+ /**USART1 GPIO Configuration
+ PB14 ------> USART1_TX
+ PB15 ------> USART1_RX
+ */
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
+
+ /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+ /* USER CODE END USART1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief PCD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hpcd->Instance==USB_OTG_HS)
+ {
+ /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */
+
+ /* USER CODE END USB_OTG_HS_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHYC;
+ PeriphClkInit.UsbPhycClockSelection = RCC_USBPHYCCLKSOURCE_HSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Enable USB Voltage detector
+ */
+ HAL_PWREx_EnableUSBVoltageDetector();
+
+ /* Peripheral clock enable */
+ __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+ __HAL_RCC_USBPHYC_CLK_ENABLE();
+ /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */
+
+ /* USER CODE END USB_OTG_HS_MspInit 1 */
+
+ }
+
+}
+
+/**
+* @brief PCD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
+{
+ if(hpcd->Instance==USB_OTG_HS)
+ {
+ /* USER CODE BEGIN USB_OTG_HS_MspDeInit 0 */
+
+ /* USER CODE END USB_OTG_HS_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USB_OTG_HS_CLK_DISABLE();
+ __HAL_RCC_USBPHYC_CLK_DISABLE();
+ /* USER CODE BEGIN USB_OTG_HS_MspDeInit 1 */
+
+ /* USER CODE END USB_OTG_HS_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c
new file mode 100644
index 00000000000..bab87928214
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c
@@ -0,0 +1,232 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7rsxx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7rsxx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern ETH_HandleTypeDef heth;
+extern SD_HandleTypeDef hsd1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7RSxx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32h7rsxx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles Ethernet global interrupt.
+ */
+void ETH_IRQHandler(void)
+{
+ /* USER CODE BEGIN ETH_IRQn 0 */
+
+ /* USER CODE END ETH_IRQn 0 */
+ HAL_ETH_IRQHandler(&heth);
+ /* USER CODE BEGIN ETH_IRQn 1 */
+
+ /* USER CODE END ETH_IRQn 1 */
+}
+
+/**
+ * @brief This function handles SDMMC1 global interrupt.
+ */
+void SDMMC1_IRQHandler(void)
+{
+ /* USER CODE BEGIN SDMMC1_IRQn 0 */
+
+ /* USER CODE END SDMMC1_IRQn 0 */
+ HAL_SD_IRQHandler(&hsd1);
+ /* USER CODE BEGIN SDMMC1_IRQn 1 */
+
+ /* USER CODE END SDMMC1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c
new file mode 100644
index 00000000000..bc00435139d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c
@@ -0,0 +1,304 @@
+/**
+ ******************************************************************************
+ * @file system_stm32h7rsxx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7rsxx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can
+ * be used by the user application to setup the
+ * SysTick timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the HSI (64 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to
+ * optionally configure the system clock before to branch to main program.
+ *
+ *=============================================================================
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32H7RSxx_System
+ * @{
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7rsxx.h"
+#include
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 24000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */
+#endif /* CSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line or define USER_VECT_TAB_ADDRESS at compiler level if you need
+ to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at
+ the automatic remap of the selected boot address */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line or define VECT_TAB_SRAM at compiler level if you need
+ to relocate your vector Table in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+
+#if defined(VECT_TAB_SRAM)
+#if !defined(VECT_TAB_BASE_ADDRESS)
+#define VECT_TAB_BASE_ADDRESS ITCM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#endif
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif
+#else
+#if !defined(VECT_TAB_BASE_ADDRESS)
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#endif
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in two ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the first function listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = HSI_VALUE;
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7RSxx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#endif
+
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to RCC registers values.
+ * The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*)
+ * or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
+ * 24 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc;
+ float_t pllfracn, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case 0x00: /* HSI used as system clock source (default after reset) */
+ sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
+ break;
+
+ case 0x08: /* CSI used as system clock source */
+ sysclk = CSI_VALUE;
+ break;
+
+ case 0x10: /* HSE used as system clock source */
+ sysclk = HSE_VALUE;
+ break;
+
+ case 0x18: /* PLL1 used as system clock source */
+ /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL1_VCO / PLL1R
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ;
+ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U)
+ {
+ pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos));
+ }
+ else
+ {
+ pllfracn = (float_t)0U;
+ }
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case 0x02: /* HSE used as PLL1 clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case 0x01: /* CSI used as PLL1 clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case 0x00: /* HSI used as PLL1 clock source */
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ;
+ sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ sysclk = 0U;
+ }
+ break;
+
+ default: /* Unexpected, default to HSI used as system clock source (default after reset) */
+ sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
+ break;
+ }
+
+ /* system clock frequency : CM7 CPU frequency */
+ core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
+ if (core_presc >= 8U)
+ {
+ SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
+ }
+ else
+ {
+ SystemCoreClock = sysclk;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc
new file mode 100644
index 00000000000..4ff2224a309
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc
@@ -0,0 +1,597 @@
+#MicroXplorer Configuration settings - do not modify
+Appli.IPs=CORTEX_M7_APPLI\:I,GPDMA1\:I,HPDMA1\:I,LINKEDLIST\:I,RCC\:I,GPIO,NVIC2\:I,FLASH,USB_OTG_HS,GFXTIM,USART1,XSPI1,XSPI2,FDCAN1,ETH,SDMMC1,UART7
+Boot.IPs=CORTEX_M7_BOOT\:I,GPDMA1,HPDMA1,LINKEDLIST,RCC,GPIO,NVIC1\:I,MEMORYMAP\:I,USB_OTG_HS
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+CORTEX_M7_APPLI.IPParameters=default_mode_Activation
+CORTEX_M7_APPLI.default_mode_Activation=1
+CORTEX_M7_BOOT.IPParameters=default_mode_Activation
+CORTEX_M7_BOOT.default_mode_Activation=1
+ETH.IPParameters=MediaInterface,TxDescAddress,RxBufferAddress
+ETH.MediaInterface=HAL_ETH_RMII_MODE
+ETH.RxBufferAddress=0x24020200
+ETH.TxDescAddress=0x24020080
+ExtMemLoader.IPs=EXTMEM_LOADER\:I,EXTMEM_MANAGER\:I,GPIO\:I
+FDCAN1.CalculateBaudRateNominal=2000000
+FDCAN1.CalculateTimeBitNominal=500
+FDCAN1.CalculateTimeQuantumNominal=20.0
+FDCAN1.ClockDivider=FDCAN_CLOCK_DIV6
+FDCAN1.FrameFormat=FDCAN_FRAME_CLASSIC
+FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,FrameFormat,ClockDivider
+FDCAN1.NominalPrescaler=2
+FDCAN1.NominalTimeSeg1=19
+FDCAN1.NominalTimeSeg2=5
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+MMTAppReg1.MEMORYMAP.AppRegionName=DTCM
+MMTAppReg1.MEMORYMAP.ContextName=Boot
+MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg1.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name
+MMTAppReg1.MEMORYMAP.Name=DTCM
+MMTAppReg1.MEMORYMAP.Size=65536
+MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
+MMTAppReg2.MEMORYMAP.AppRegionName=RAM
+MMTAppReg2.MEMORYMAP.ContextName=Boot
+MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg2.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name
+MMTAppReg2.MEMORYMAP.Name=RAM
+MMTAppReg2.MEMORYMAP.Size=465920
+MMTAppReg2.MEMORYMAP.StartAddress=0x24000000
+MMTAppReg3.MEMORYMAP.AppRegionName=ITCM
+MMTAppReg3.MEMORYMAP.Cacheability=WTRA
+MMTAppReg3.MEMORYMAP.ContextName=Boot
+MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg3.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,Cacheability
+MMTAppReg3.MEMORYMAP.Name=ITCM
+MMTAppReg3.MEMORYMAP.Size=65536
+MMTAppReg3.MEMORYMAP.StartAddress=0x00000000
+MMTAppReg4.MEMORYMAP.AP=RO_priv_only
+MMTAppReg4.MEMORYMAP.AppRegionName=FLASH
+MMTAppReg4.MEMORYMAP.Cacheability=WTRA
+MMTAppReg4.MEMORYMAP.ContextName=Boot
+MMTAppReg4.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg4.MEMORYMAP.DefaultCodeRegion=true
+MMTAppReg4.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg4.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
+MMTAppReg4.MEMORYMAP.MemType=ROM
+MMTAppReg4.MEMORYMAP.Name=FLASH
+MMTAppReg4.MEMORYMAP.Size=65536
+MMTAppReg4.MEMORYMAP.StartAddress=0x08000000
+MMTAppReg5.MEMORYMAP.AppRegionName=DTCM
+MMTAppReg5.MEMORYMAP.ContextName=Appli
+MMTAppReg5.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg5.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg5.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name
+MMTAppReg5.MEMORYMAP.Name=DTCM
+MMTAppReg5.MEMORYMAP.Size=65536
+MMTAppReg5.MEMORYMAP.StartAddress=0x20000000
+MMTAppReg6.MEMORYMAP.AppRegionName=RAM
+MMTAppReg6.MEMORYMAP.ContextName=Appli
+MMTAppReg6.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg6.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg6.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name
+MMTAppReg6.MEMORYMAP.Name=RAM
+MMTAppReg6.MEMORYMAP.Size=465920
+MMTAppReg6.MEMORYMAP.StartAddress=0x24000000
+MMTAppReg7.MEMORYMAP.AppRegionName=ITCM
+MMTAppReg7.MEMORYMAP.Cacheability=WTRA
+MMTAppReg7.MEMORYMAP.ContextName=Appli
+MMTAppReg7.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg7.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg7.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,Cacheability
+MMTAppReg7.MEMORYMAP.Name=ITCM
+MMTAppReg7.MEMORYMAP.Size=65536
+MMTAppReg7.MEMORYMAP.StartAddress=0x00000000
+MMTAppReg8.MEMORYMAP.AP=RO_priv_only
+MMTAppReg8.MEMORYMAP.AppRegionName=FLASH
+MMTAppReg8.MEMORYMAP.Cacheability=WTRA
+MMTAppReg8.MEMORYMAP.ContextName=Appli
+MMTAppReg8.MEMORYMAP.CoreName=ARM Cortex-M7
+MMTAppReg8.MEMORYMAP.DefaultCodeRegion=true
+MMTAppReg8.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg8.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
+MMTAppReg8.MEMORYMAP.MemType=ROM
+MMTAppReg8.MEMORYMAP.Name=FLASH
+MMTAppReg8.MEMORYMAP.Size=65536
+MMTAppReg8.MEMORYMAP.StartAddress=0x08000000
+MMTAppRegionsCount=8
+MMTConfigApplied=false
+Mcu.CPN=STM32H7R7L8H6H
+Mcu.Context0=Boot
+Mcu.Context1=Appli
+Mcu.Context2=ExtMemLoader
+Mcu.ContextNb=3
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7_APPLI
+Mcu.IP1=CORTEX_M7_BOOT
+Mcu.IP10=UART7
+Mcu.IP11=USART1
+Mcu.IP12=USB_OTG_HS
+Mcu.IP13=XSPI1
+Mcu.IP14=XSPI2
+Mcu.IP2=ETH
+Mcu.IP3=FDCAN1
+Mcu.IP4=FLASH
+Mcu.IP5=MEMORYMAP
+Mcu.IP6=NVIC2
+Mcu.IP7=NVIC1
+Mcu.IP8=RCC
+Mcu.IP9=SDMMC1
+Mcu.IPNb=15
+Mcu.Name=STM32H7R7L8HxH
+Mcu.Package=TFBGA225 HEXA SMPS
+Mcu.Pin0=PM6
+Mcu.Pin1=PD2
+Mcu.Pin10=PC15-OSC32_OUT(OSC32_OUT)
+Mcu.Pin11=PC14-OSC32_IN(OSC32_IN)
+Mcu.Pin12=PC12
+Mcu.Pin13=PC8
+Mcu.Pin14=PD6
+Mcu.Pin15=PC9
+Mcu.Pin16=PG14
+Mcu.Pin17=PG11
+Mcu.Pin18=PN1
+Mcu.Pin19=PG13
+Mcu.Pin2=PD7
+Mcu.Pin20=PN3
+Mcu.Pin21=PN0
+Mcu.Pin22=PN11
+Mcu.Pin23=PN10
+Mcu.Pin24=PN9
+Mcu.Pin25=PN2
+Mcu.Pin26=PF10
+Mcu.Pin27=PN7
+Mcu.Pin28=PN6
+Mcu.Pin29=PH0-OSC_IN(PH0)
+Mcu.Pin3=PM9
+Mcu.Pin30=PH1-OSC_OUT(PH1)
+Mcu.Pin31=PN8
+Mcu.Pin32=PN4
+Mcu.Pin33=PN5
+Mcu.Pin34=PC1
+Mcu.Pin35=PC4
+Mcu.Pin36=PD14
+Mcu.Pin37=PN12
+Mcu.Pin38=PA4
+Mcu.Pin39=PA7
+Mcu.Pin4=PM5
+Mcu.Pin40=PB14
+Mcu.Pin41=PB15
+Mcu.Pin42=PC5
+Mcu.Pin43=PP2
+Mcu.Pin44=PP5
+Mcu.Pin45=PO2
+Mcu.Pin46=PP1
+Mcu.Pin47=PP3
+Mcu.Pin48=PP0
+Mcu.Pin49=PP7
+Mcu.Pin5=PD1
+Mcu.Pin50=PP4
+Mcu.Pin51=PO4
+Mcu.Pin52=PP6
+Mcu.Pin53=PO0
+Mcu.Pin54=VP_FLASH_SIG_Activate_FlashIP
+Mcu.Pin55=VP_RCC_VS_RMII
+Mcu.Pin56=VP_XSPI1_VS_octo
+Mcu.Pin57=VP_XSPI2_VS_octo
+Mcu.Pin58=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin6=PC10
+Mcu.Pin7=PC11
+Mcu.Pin8=PM8
+Mcu.Pin9=PD0
+Mcu.PinsNb=59
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H7R7L8HxH
+MxCube.Version=6.12.0
+MxDb.Version=DB.6.0.120
+NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.ForceEnableDMAVector=true
+NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.ETH_IRQn=true\:7\:0\:true\:false\:true\:true\:true\:true
+NVIC2.ForceEnableDMAVector=true
+NVIC2.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC2.SDMMC1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
+NVIC2.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC2.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC2.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA4.GPIOParameters=PinAttribute
+PA4.Locked=true
+PA4.Mode=RMII
+PA4.PinAttribute=Appli
+PA4.Signal=ETH_MDIO
+PA7.GPIOParameters=PinAttribute
+PA7.Mode=RMII
+PA7.PinAttribute=Appli
+PA7.Signal=ETH_RMII_CRS_DV
+PB14.GPIOParameters=PinAttribute
+PB14.Locked=true
+PB14.Mode=Asynchronous
+PB14.PinAttribute=Appli
+PB14.Signal=USART1_TX
+PB15.GPIOParameters=PinAttribute
+PB15.Locked=true
+PB15.Mode=Asynchronous
+PB15.PinAttribute=Appli
+PB15.Signal=USART1_RX
+PC1.GPIOParameters=PinAttribute
+PC1.Mode=RMII
+PC1.PinAttribute=Appli
+PC1.Signal=ETH_MDC
+PC10.GPIOParameters=PinAttribute
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.PinAttribute=Appli
+PC10.Signal=SDMMC1_D2
+PC11.GPIOParameters=PinAttribute
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.PinAttribute=Appli
+PC11.Signal=SDMMC1_D3
+PC12.GPIOParameters=PinAttribute
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.PinAttribute=Appli
+PC12.Signal=SDMMC1_CK
+PC14-OSC32_IN(OSC32_IN).Mode=LSE-External-Oscillator
+PC14-OSC32_IN(OSC32_IN).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT(OSC32_OUT).Mode=LSE-External-Oscillator
+PC15-OSC32_OUT(OSC32_OUT).Signal=RCC_OSC32_OUT
+PC4.GPIOParameters=PinAttribute
+PC4.Mode=RMII
+PC4.PinAttribute=Appli
+PC4.Signal=ETH_RMII_RXD0
+PC5.GPIOParameters=PinAttribute
+PC5.Mode=RMII
+PC5.PinAttribute=Appli
+PC5.Signal=ETH_RMII_RXD1
+PC8.GPIOParameters=PinAttribute
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.PinAttribute=Appli
+PC8.Signal=SDMMC1_D0
+PC9.GPIOParameters=PinAttribute
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.PinAttribute=Appli
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=PinAttribute
+PD0.Locked=true
+PD0.Mode=FDCAN_Activate
+PD0.PinAttribute=Appli
+PD0.Signal=FDCAN1_RX
+PD1.GPIOParameters=PinAttribute
+PD1.Locked=true
+PD1.Mode=FDCAN_Activate
+PD1.PinAttribute=Appli
+PD1.Signal=FDCAN1_TX
+PD14.GPIOParameters=GPIO_PuPd,GPIO_Label,PinAttribute
+PD14.GPIO_Label=LED0
+PD14.GPIO_PuPd=GPIO_PULLDOWN
+PD14.Locked=true
+PD14.PinAttribute=Free
+PD14.Signal=GPIO_Output
+PD2.GPIOParameters=PinAttribute
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.PinAttribute=Appli
+PD2.Signal=SDMMC1_CMD
+PD6.GPIOParameters=PinAttribute
+PD6.Mode=Digital_ClockEthClk
+PD6.PinAttribute=Free
+PD6.Signal=ETH_CLK
+PD7.GPIOParameters=PinAttribute
+PD7.Mode=RMII
+PD7.PinAttribute=Appli
+PD7.Signal=ETH_RMII_REF_CLK
+PF10.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,PinAttribute
+PF10.GPIO_Label=ETH_RESET
+PF10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PF10.Locked=true
+PF10.PinAttribute=Free
+PF10.PinState=GPIO_PIN_SET
+PF10.Signal=GPIO_Output
+PG11.GPIOParameters=PinAttribute
+PG11.Mode=RMII
+PG11.PinAttribute=Appli
+PG11.Signal=ETH_RMII_TX_EN
+PG13.GPIOParameters=PinAttribute
+PG13.Mode=RMII
+PG13.PinAttribute=Appli
+PG13.Signal=ETH_RMII_TXD0
+PG14.GPIOParameters=PinAttribute
+PG14.Locked=true
+PG14.Mode=RMII
+PG14.PinAttribute=Appli
+PG14.Signal=ETH_RMII_TXD1
+PH0-OSC_IN(PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN(PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT(PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT(PH1).Signal=RCC_OSC_OUT
+PM5.GPIOParameters=PinAttribute
+PM5.Locked=true
+PM5.Mode=Internal_Phy_Device
+PM5.PinAttribute=Appli
+PM5.Signal=USB_OTG_HS_DM
+PM6.GPIOParameters=PinAttribute
+PM6.Locked=true
+PM6.Mode=Internal_Phy_Device
+PM6.PinAttribute=Appli
+PM6.Signal=USB_OTG_HS_DP
+PM8.GPIOParameters=PinAttribute
+PM8.Locked=true
+PM8.Mode=Asynchronous
+PM8.PinAttribute=Appli
+PM8.Signal=UART7_RX
+PM9.GPIOParameters=PinAttribute
+PM9.Mode=Asynchronous
+PM9.PinAttribute=Appli
+PM9.Signal=UART7_TX
+PN0.GPIOParameters=PinAttribute
+PN0.Mode=XSPI2_Port2Octo
+PN0.PinAttribute=Appli
+PN0.Signal=XSPIM_P2_DQS0
+PN1.GPIOParameters=PinAttribute
+PN1.Mode=XSPI2_NCS1_Port2
+PN1.PinAttribute=Appli
+PN1.Signal=XSPIM_P2_NCS1
+PN10.GPIOParameters=PinAttribute
+PN10.Mode=XSPI2_Port2Octo
+PN10.PinAttribute=Appli
+PN10.Signal=XSPIM_P2_IO6
+PN11.GPIOParameters=PinAttribute
+PN11.Mode=XSPI2_Port2Octo
+PN11.PinAttribute=Appli
+PN11.Signal=XSPIM_P2_IO7
+PN12.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,PinAttribute
+PN12.GPIO_Label=HyperRam_RST
+PN12.GPIO_PuPd=GPIO_PULLUP
+PN12.Locked=true
+PN12.PinAttribute=Free
+PN12.PinState=GPIO_PIN_SET
+PN12.Signal=GPIO_Output
+PN2.GPIOParameters=PinAttribute
+PN2.Mode=XSPI2_Port2Octo
+PN2.PinAttribute=Appli
+PN2.Signal=XSPIM_P2_IO0
+PN3.GPIOParameters=PinAttribute
+PN3.Mode=XSPI2_Port2Octo
+PN3.PinAttribute=Appli
+PN3.Signal=XSPIM_P2_IO1
+PN4.GPIOParameters=PinAttribute
+PN4.Mode=XSPI2_Port2Octo
+PN4.PinAttribute=Appli
+PN4.Signal=XSPIM_P2_IO2
+PN5.GPIOParameters=PinAttribute
+PN5.Mode=XSPI2_Port2Octo
+PN5.PinAttribute=Appli
+PN5.Signal=XSPIM_P2_IO3
+PN6.GPIOParameters=PinAttribute
+PN6.Mode=XSPI2_Port2Octo
+PN6.PinAttribute=Appli
+PN6.Signal=XSPIM_P2_CLK
+PN7.GPIOParameters=PinAttribute
+PN7.Mode=XSPI2_Port2_NCLK
+PN7.PinAttribute=Appli
+PN7.Signal=XSPIM_P2_NCLK
+PN8.GPIOParameters=PinAttribute
+PN8.Mode=XSPI2_Port2Octo
+PN8.PinAttribute=Appli
+PN8.Signal=XSPIM_P2_IO4
+PN9.GPIOParameters=PinAttribute
+PN9.Mode=XSPI2_Port2Octo
+PN9.PinAttribute=Appli
+PN9.Signal=XSPIM_P2_IO5
+PO0.GPIOParameters=PinAttribute
+PO0.Mode=XSPI1_NCS1_Port1
+PO0.PinAttribute=Appli
+PO0.Signal=XSPIM_P1_NCS1
+PO2.GPIOParameters=PinAttribute
+PO2.Locked=true
+PO2.Mode=XSPI1_Port1Octo
+PO2.PinAttribute=Appli
+PO2.Signal=XSPIM_P1_DQS0
+PO4.GPIOParameters=PinAttribute
+PO4.Locked=true
+PO4.Mode=XSPI1_Port1Octo
+PO4.PinAttribute=Appli
+PO4.Signal=XSPIM_P1_CLK
+PP0.GPIOParameters=PinAttribute
+PP0.Locked=true
+PP0.Mode=XSPI1_Port1Octo
+PP0.PinAttribute=Appli
+PP0.Signal=XSPIM_P1_IO0
+PP1.GPIOParameters=PinAttribute
+PP1.Locked=true
+PP1.Mode=XSPI1_Port1Octo
+PP1.PinAttribute=Appli
+PP1.Signal=XSPIM_P1_IO1
+PP2.GPIOParameters=PinAttribute
+PP2.Locked=true
+PP2.Mode=XSPI1_Port1Octo
+PP2.PinAttribute=Appli
+PP2.Signal=XSPIM_P1_IO2
+PP3.GPIOParameters=PinAttribute
+PP3.Locked=true
+PP3.Mode=XSPI1_Port1Octo
+PP3.PinAttribute=Appli
+PP3.Signal=XSPIM_P1_IO3
+PP4.GPIOParameters=PinAttribute
+PP4.Locked=true
+PP4.Mode=XSPI1_Port1Octo
+PP4.PinAttribute=Appli
+PP4.Signal=XSPIM_P1_IO4
+PP5.GPIOParameters=PinAttribute
+PP5.Locked=true
+PP5.Mode=XSPI1_Port1Octo
+PP5.PinAttribute=Appli
+PP5.Signal=XSPIM_P1_IO5
+PP6.GPIOParameters=PinAttribute
+PP6.Locked=true
+PP6.Mode=XSPI1_Port1Octo
+PP6.PinAttribute=Appli
+PP6.Signal=XSPIM_P1_IO6
+PP7.GPIOParameters=PinAttribute
+PP7.Locked=true
+PP7.Mode=XSPI1_Port1Octo
+PP7.PinAttribute=Appli
+PP7.Signal=XSPIM_P1_IO7
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerLinker=GCC
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H7R7L8HxH
+ProjectManager.FirmwarePackage=STM32Cube FW_H7RS V1.1.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=App-0x200,Boot-0x200,ExtMemLoader-0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.ProjectStructure=Boot\:Boot Project\:true;App\:Appli Project\:true;ExtMemLoader\:ExtMemLoader Project\:false;
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=App-0x400,Boot-0x400,ExtMemLoader-0x400
+ProjectManager.TargetToolchain=MDK-ARM V5.37
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-Boot,2-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true-Boot,1-SystemClock_Config-RCC-false-HAL-false-Appli,2-MX_GPIO_Init-GPIO-false-HAL-true-Appli,3-MX_FLASH_Init-FLASH-false-HAL-true-Appli,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true-Appli,5-MX_USART1_UART_Init-USART1-false-HAL-true-Appli,false-6-MX_XSPI1_Init-XSPI1-false-HAL-true-Appli,false-7-MX_XSPI2_Init-XSPI2-false-HAL-true-Appli,8-MX_FDCAN1_Init-FDCAN1-false-HAL-true-Appli,9-MX_ETH_Init-ETH-false-HAL-true-Appli,10-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true-Appli,0-MX_CORTEX_M7_BOOT_Init-CORTEX_M7_BOOT-false-HAL-true-Boot,0-MX_CORTEX_M7_APPLI_Init-CORTEX_M7_APPLI-false-HAL-true-Appli,1-SystemClock_Config-RCC-false-HAL-false-ExtMemLoader
+RCC.ADCFreq_Value=600000000
+RCC.ADFFreq_Value=300000000
+RCC.AHB1234Freq_Value=300000000
+RCC.AHB5ClockFreq_Value=300000000
+RCC.APB1Freq_Value=150000000
+RCC.APB2Freq_Value=150000000
+RCC.APB4Freq_Value=150000000
+RCC.APB5Freq_Value=150000000
+RCC.AXIClockFreq_Value=300000000
+RCC.BMPRE=RCC_HCLK_DIV2
+RCC.CECFreq_Value=32768
+RCC.CKPERFreq_Value=64000000
+RCC.CPREFreq_Value=600000000
+RCC.CortexFreq_Value=600000000
+RCC.CpuClockFreq_Value=600000000
+RCC.DIVM1=6
+RCC.DIVM2=6
+RCC.DIVM3=18
+RCC.DIVN1=300
+RCC.DIVN2=300
+RCC.DIVN3=300
+RCC.DIVP1Freq_Value=600000000
+RCC.DIVP2Freq_Value=600000000
+RCC.DIVP3Freq_Value=200000000
+RCC.DIVQ1Freq_Value=600000000
+RCC.DIVQ2Freq_Value=600000000
+RCC.DIVQ3Freq_Value=200000000
+RCC.DIVR1Freq_Value=600000000
+RCC.DIVR2Freq_Value=600000000
+RCC.DIVR3=1
+RCC.DIVR3Freq_Value=400000000
+RCC.DIVS1Freq_Value=600000000
+RCC.DIVS2Freq_Value=600000000
+RCC.DIVS3=8
+RCC.DIVS3Freq_Value=50000000
+RCC.DIVT1Freq_Value=600000000
+RCC.DIVT2=6
+RCC.DIVT2Freq_Value=200000000
+RCC.DIVT3Freq_Value=200000000
+RCC.DTSFreq_Value=32768
+RCC.ETH1Freq_Value=50000000
+RCC.ETHPHYCLockSelection=RCC_ETH1PHYCLKSOURCE_PLL3S
+RCC.ETHPHYFreq_Value=50000000
+RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL1Q
+RCC.FDCANFreq_Value=600000000
+RCC.FMCFreq_Value=300000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=300000000
+RCC.I2C23Freq_Value=150000000
+RCC.I2CI3C1Freq_Value=150000000
+RCC.IPParameters=ADCFreq_Value,ADFFreq_Value,AHB1234Freq_Value,AHB5ClockFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,BMPRE,CECFreq_Value,CKPERFreq_Value,CPREFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,DIVS1Freq_Value,DIVS2Freq_Value,DIVS3,DIVS3Freq_Value,DIVT1Freq_Value,DIVT2,DIVT2Freq_Value,DIVT3Freq_Value,DTSFreq_Value,ETH1Freq_Value,ETHPHYCLockSelection,ETHPHYFreq_Value,FDCANCLockSelection,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLKFreq_Value,I2C23Freq_Value,I2CI3C1Freq_Value,LPTIM1Freq_Value,LPTIM23Freq_Value,LPTIM45Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,OSPI1Freq_Value,OSPI2Freq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSource,PPRE1,PPRE2,PPRE4,PPRE5,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI1Freq_Value,SPI23Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TPIUFreq_Value,Tim1OutputFreq_Value,Tim2OutputFreq_Value,UCPDFreq_Value,USART1Freq_Value,USART234578Freq_Value,USBOFSFreq_Value,USBPHYFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,Xspi1ClockSelection,Xspi2ClockSelection
+RCC.LPTIM1Freq_Value=150000000
+RCC.LPTIM23Freq_Value=150000000
+RCC.LPTIM45Freq_Value=150000000
+RCC.LPUART1Freq_Value=150000000
+RCC.LTDCFreq_Value=400000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=600000000
+RCC.OSPI1Freq_Value=600000000
+RCC.OSPI2Freq_Value=600000000
+RCC.PLL2FRACN=0
+RCC.PLL3FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSource=RCC_PLLSOURCE_HSE
+RCC.PPRE1=RCC_APB1_DIV2
+RCC.PPRE2=RCC_APB2_DIV2
+RCC.PPRE4=RCC_APB4_DIV2
+RCC.PPRE5=RCC_APB5_DIV2
+RCC.PSSIFreq_Value=400000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=600000000
+RCC.SAI2Freq_Value=600000000
+RCC.SDMMC1CLockSelection=RCC_SDMMC12CLKSOURCE_PLL2T
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=600000000
+RCC.SPI1Freq_Value=600000000
+RCC.SPI23Freq_Value=600000000
+RCC.SPI45Freq_Value=150000000
+RCC.SPI6Freq_Value=150000000
+RCC.SYSCLKFreq_VALUE=600000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TPIUFreq_Value=200000000
+RCC.Tim1OutputFreq_Value=300000000
+RCC.Tim2OutputFreq_Value=300000000
+RCC.UCPDFreq_Value=16000000
+RCC.USART1Freq_Value=150000000
+RCC.USART234578Freq_Value=150000000
+RCC.USBOFSFreq_Value=48000000
+RCC.USBPHYFreq_Value=24000000
+RCC.VCO1OutputFreq_Value=1200000000
+RCC.VCO2OutputFreq_Value=1200000000
+RCC.VCO3OutputFreq_Value=400000000
+RCC.VCOInput1Freq_Value=4000000
+RCC.VCOInput2Freq_Value=4000000
+RCC.VCOInput3Freq_Value=1333333.3333333333
+RCC.Xspi1ClockSelection=RCC_XSPI1CLKSOURCE_PLL2S
+RCC.Xspi2ClockSelection=RCC_XSPI2CLKSOURCE_PLL2S
+USART1.IPParameters=VirtualMode
+USART1.VirtualMode=VM_ASYNC
+USB_OTG_HS.IPParameters=VirtualMode
+USB_OTG_HS.VirtualMode=Device_HS
+VP_FLASH_SIG_Activate_FlashIP.Mode=Activate_FlashIP
+VP_FLASH_SIG_Activate_FlashIP.Signal=FLASH_SIG_Activate_FlashIP
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
+VP_RCC_VS_RMII.Mode=Digital_ClockIn
+VP_RCC_VS_RMII.Signal=RCC_VS_RMII
+VP_XSPI1_VS_octo.Mode=octo_mode
+VP_XSPI1_VS_octo.Signal=XSPI1_VS_octo
+VP_XSPI2_VS_octo.Mode=hyperbus_mode
+VP_XSPI2_VS_octo.Signal=XSPI2_VS_octo
+board=custom
diff --git a/bsp/stm32/stm32h7r7-atk/board/SConscript b/bsp/stm32/stm32h7r7-atk/board/SConscript
new file mode 100644
index 00000000000..062dac808a0
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/SConscript
@@ -0,0 +1,23 @@
+import os
+from building import *
+
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+src = Glob('*.c')
+
+src += Split('''
+CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c
+''')
+
+path = [cwd]
+path += [cwd + '/port']
+path += [cwd + '/CubeMX_Config/Appli/Core/Inc']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+for item in list:
+ if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+ group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/stm32/stm32h7r7-atk/board/board.c b/bsp/stm32/stm32h7r7-atk/board/board.c
new file mode 100644
index 00000000000..0dc22f10f28
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/board.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-29 RealThread first version
+ */
+
+#include "board.h"
+
+#define DBG_TAG "board"
+#define DBG_LVL DBG_LOG
+#include
+
+#ifdef RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
+#define RT_NVIC_PRO_BITS __NVIC_PRIO_BITS
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+ rt_base_t level = __get_BASEPRI();
+ __set_BASEPRI(RT_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - RT_NVIC_PRO_BITS));
+
+ __ISB();
+ __DSB();
+
+ return level;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+ __set_BASEPRI(level);
+}
+#endif /* RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT */
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+*/
+void SystemClock_Config(void)
+{
+ return;
+}
diff --git a/bsp/stm32/stm32h7r7-atk/board/board.h b/bsp/stm32/stm32h7r7-atk/board/board.h
new file mode 100644
index 00000000000..31a93bcd1f8
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/board.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-29 RealThread first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*-------------------------- CHIP CONFIG BEGIN --------------------------*/
+
+#define CHIP_FAMILY_STM32
+#define CHIP_SERIES_STM32H7RS
+#define CHIP_NAME_STM32H750XBHX
+
+/*-------------------------- CHIP CONFIG END --------------------------*/
+
+/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/
+/**
+ * @brief H7RS7 SRAM MEMORY Layout
+ * 0x24060000 - 0x23071FFF AXI SRAM shared with ECC
+ * 0x24040000 - 0x2305FFFF AXI SRAM shared with DTCM
+ * 0x24020000 - 0x2403FFFF AXI SRAM
+ * 0x24000000 - 0x2401FFFF AXI SRAM shared with ITCM
+ */
+#define ROM_START ((uint32_t)0x90000000)
+#define ROM_SIZE (131072)
+#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE * 1024))
+
+#define RAM_START (0x24000000)
+#define RAM_SIZE (456)
+#define RAM_END (RAM_START + RAM_SIZE * 1024)
+
+/*-------------------------- ROM/RAM CONFIG END --------------------------*/
+
+/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/
+
+#define BSP_CLOCK_SOURCE ("HSE")
+#define BSP_CLOCK_SOURCE_FREQ_MHZ ((int32_t)0)
+#define BSP_CLOCK_SYSTEM_FREQ_MHZ ((int32_t)480)
+
+/*-------------------------- CLOCK CONFIG END --------------------------*/
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+ *
+ * STEP 1, define macro define related to the serial port opening based on the serial port number
+ * such as #define BSP_USING_UATR1
+ *
+ * STEP 2, according to the corresponding pin of serial port, define the related serial port information macro
+ * such as #define BSP_UART1_TX_PIN "PA9"
+ * #define BSP_UART1_RX_PIN "PA10"
+ *
+ * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+ * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+ *
+ * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+ * such as #define BSP_UART1_RX_USING_DMA
+ *
+ */
+
+#ifdef BSP_USING_UART1
+#define BSP_UART1_TX_PIN "PA9"
+#define BSP_UART1_RX_PIN "PA10"
+#endif
+
+#ifdef BSP_USING_UART4
+#define BSP_UART4_TX_PIN "PD0"
+#define BSP_UART4_RX_PIN "PD1"
+#endif
+
+
+void SystemClock_Config(void);
+void SystemClock_ReConfig(uint8_t mode);
+
+/*-------------------------- UART CONFIG END --------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c b/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c
new file mode 100644
index 00000000000..3554e08a3ba
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-04-14 whj4674672 first version
+ */
+#include
+#include "stm32h7rsxx.h"
+#include "board.h"
+
+int mpu_init(void)
+{
+ MPU_Region_InitTypeDef mpu_region_init_struct = {0};
+ uint32_t region_index = 0;
+
+ /* 关闭MPU */
+ HAL_MPU_Disable();
+
+ /* 配置背景域（0x00000000~0xFFFFFFFF，4GB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x00000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_4GB;
+ mpu_region_init_struct.SubRegionDisable = 0x87;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL0;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_NO_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置ITCM对应区域（0x00000000~0x0000FFFF，64KB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x00000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_64KB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置DTCM对应区域（0x20000000~0x2000FFFF，64KB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x20000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_64KB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置AXI-SRAM1~4对应区域（0x24000000~0x24071FFF，456KB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x24000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_512KB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置AHB-SRAM1~2对应区域（0x30000000~0x30007FFF，32KB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x30000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_32KB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置FMC LCD对应区域（0x60000000~0x63FFFFFF，64MB） */
+// mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+// mpu_region_init_struct.Number = region_index++;
+// mpu_region_init_struct.BaseAddress = 0x60000000;
+// mpu_region_init_struct.Size = MPU_REGION_SIZE_64MB;
+// mpu_region_init_struct.SubRegionDisable = 0x00;
+// mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL0;
+// mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+// mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+// mpu_region_init_struct.IsShareable = MPU_ACCESS_SHAREABLE;
+// mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+// mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+// HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置XSPI NOR Flash对应区域（0x90000000~0x91FFFFFF，32MB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x90000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_32MB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 配置XSPI HyperRAM对应区域（0x70000000~0x71FFFFFF，32MB） */
+ mpu_region_init_struct.Enable = MPU_REGION_ENABLE;
+ mpu_region_init_struct.Number = region_index++;
+ mpu_region_init_struct.BaseAddress = 0x70000000;
+ mpu_region_init_struct.Size = MPU_REGION_SIZE_32MB;
+ mpu_region_init_struct.SubRegionDisable = 0x00;
+ mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1;
+ mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+ mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ HAL_MPU_ConfigRegion(&mpu_region_init_struct);
+
+ /* 使能MPU */
+ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+ return RT_EOK;
+
+}
+INIT_BOARD_EXPORT(mpu_init);
diff --git a/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds
new file mode 100644
index 00000000000..75ae499f2d1
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds
@@ -0,0 +1,215 @@
+/*
+ * linker script for STM32H750XBHx with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ROM (rx) : ORIGIN =0x08000000,LENGTH =64k
+QFLASH (rx) : ORIGIN =0x90000000,LENGTH =8192k
+RAM (rw) : ORIGIN =0x24000000,LENGTH =456k
+RxDecripSection (rw) : ORIGIN =0x24020000,LENGTH =32k
+TxDecripSection (rw) : ORIGIN =0x24020200,LENGTH =32k
+RxArraySection (rw) : ORIGIN =0x24020400,LENGTH =32k
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .onchip_rom :
+ {
+ . = ALIGN(4);
+ KEEP(*bootloader_img.o(.rodata*))
+ . = ALIGN(4);
+ } > ROM
+
+
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+
+ /* section information for utest */
+ . = ALIGN(4);
+ __rt_utest_tc_tab_start = .;
+ KEEP(*(UtestTcTab))
+ __rt_utest_tc_tab_end = .;
+
+ /* section information for at server */
+ . = ALIGN(4);
+ __rtatcmdtab_start = .;
+ KEEP(*(RtAtCmdTab))
+ __rtatcmdtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for modules */
+ . = ALIGN(4);
+ __rtmsymtab_start = .;
+ KEEP(*(RTMSymTab))
+ __rtmsymtab_end = .;
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+
+ . = ALIGN(4);
+
+ PROVIDE(__ctors_start__ = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE(__ctors_end__ = .);
+
+ . = ALIGN(4);
+
+ _etext = .;
+ } > QFLASH = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > QFLASH
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+ .stack :
+ {
+ . = ALIGN(4);
+ _sstack = .;
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >RAM
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > RAM
+ __bss_end = .;
+
+ .RxDecripSection (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.RxDecripSection)
+ *(.RxDecripSection.*)
+ . = ALIGN(4);
+ __RxDecripSection_free__ = .;
+ } > RxDecripSection
+
+ .TxDecripSection (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.TxDecripSection)
+ *(.TxDecripSection.*)
+ . = ALIGN(4);
+ __TxDecripSection_free__ = .;
+ } > TxDecripSection
+
+ .RxArraySection (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.RxArraySection)
+ *(.RxArraySection.*)
+ . = ALIGN(4);
+ __RxArraySection_free__ = .;
+ } > RxArraySection
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct
new file mode 100644
index 00000000000..ca8f610f3da
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct
@@ -0,0 +1,29 @@
+LR_EROM1 0x90000000 0x02000000 {
+ ER_IROM1 0x90000000 0x02000000 { ; ڲ64KBflash
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+XO)
+ .ANY (+RO)
+ }
+ RW_IDTCM 0x20000000 0x00010000 { ; ڲDTCM64KBӳչ2*32bit
+ .ANY (.RAM_DTCM)
+ *(STACK)
+ *(HEAP)
+ }
+
+ RW_IITCM 0x00000000 0x00010000 { ; ڲITCM64KBӳչ,64bit
+ .ANY (.RAM_ITCM)
+ }
+
+ RW_IRAM1 0x24000000 0x00072000 { ; ڲAXIϹ456KBSRAMĿڴͳһʹãӳ
+ .ANY (+RW +ZI)
+ }
+
+ RW_IRAM2 0x30000000 0x00008000 { ; ڲAHBϹ32KBSRAMڴͳһʹ
+ .ANY (.RAM_SRAM2)
+ }
+
+ RW_ERAM1 0x70000000 UNINIT 0x02000000 { ; ⲿչ32MBHyperBusӿڵRAM
+ .ANY (.RAM_HPRAM)
+ }
+}
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/Kconfig b/bsp/stm32/stm32h7r7-atk/board/port/Kconfig
new file mode 100644
index 00000000000..0a918c1ccd3
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/Kconfig
@@ -0,0 +1,62 @@
+if BSP_USING_USBD
+ config BSP_USBD_TYPE_FS
+ bool
+ # "USB Full Speed (FS) Core"
+ config BSP_USBD_TYPE_HS
+ bool
+ # "USB High Speed (HS) Core"
+
+ config BSP_USBD_SPEED_HS
+ bool
+ # "USB High Speed (HS) Mode"
+ config BSP_USBD_SPEED_HSINFS
+ bool
+ # "USB High Speed (HS) Core in FS mode"
+
+ config BSP_USBD_PHY_EMBEDDED
+ bool
+ # "Using Embedded phy interface"
+ config BSP_USBD_PHY_UTMI
+ bool
+ # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+ config BSP_USBD_PHY_ULPI
+ bool
+ # "ULPI: UTMI+ Low Pin Interface"
+endif
+
+config BSP_USING_CRC
+ bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_CRC
+ # "Crypto device frame dose not support above 8-bits granularity"
+ # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
+ depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
+ default n
+
+config BSP_USING_RNG
+ bool "Enable RNG (Random Number Generator)"
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_RNG
+ depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
+ SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
+ default n
+
+config BSP_USING_HASH
+ bool "Enable HASH (Hash House Harriers)"
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_HASH
+ depends on (SOC_SERIES_STM32MP1)
+ default n
+
+config BSP_USING_CRYP
+ bool "Enable CRYP (Encrypt And Decrypt Data)"
+ select RT_USING_HWCRYPTO
+ select RT_HWCRYPTO_USING_CRYP
+ depends on (SOC_SERIES_STM32MP1)
+ default n
+
+config BSP_USING_UDID
+ bool "Enable UDID (Unique Device Identifier)"
+ select RT_USING_HWCRYPTO
+ default n
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/SConscript b/bsp/stm32/stm32h7r7-atk/board/port/SConscript
new file mode 100644
index 00000000000..c715d19153d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/SConscript
@@ -0,0 +1,78 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+# add general drivers
+src = Split('''
+drv_common.c
+drv_gpio.c
+drv_spi.c
+drv_psram.c
+''')
+#CubeMX_Config/Src/stm32h7xx_hal_msp.c
+
+if GetDepend(['RT_USING_SERIAL']):
+ if GetDepend(['RT_USING_SERIAL_V2']):
+ src += ['drv_usart_v2.c']
+ else:
+ src += ['drv_usart.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+ src += Glob('drv_sdmmc.c')
+
+if GetDepend(['BSP_USING_ETH']):
+ src += Glob('drv_eth.c')
+
+if GetDepend(['BSP_USING_DCMI']):
+ src += Glob('drv_dcmi.c')
+
+if GetDepend(['BSP_USING_LCD']):
+ src += Glob('drv_lcd.c')
+
+if GetDepend(['BSP_USING_TIM']):
+ src += Glob('drv_hwtimer.c')
+
+if GetDepend(['RT_USING_PM']):
+ src += ['drv_pm.c']
+ src += ['drv_lptim.c']
+
+if GetDepend(['BSP_USING_SPI_LCD_ILI9488']):
+ src += Glob('drv_spi_ili9488.c')
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+ if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+ src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+ src += Glob('drv_rtc.c')
+
+if GetDepend(['BSP_USING_USBD']):
+ src += Glob('drv_usbd.c')
+
+if GetDepend(['BSP_USING_USBH']):
+ src += ['drv_usbh.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['drv_fdcan.c']
+
+if GetDepend(['RT_USING_PWM']):
+ src += ['drv_pwm.c']
+
+if GetDepend(['BSP_USING_XSPI_NORFLASH']):
+ src += ['drv_xspi_norflash.c']
+
+path = [cwd]
+path += [cwd + '/include']
+path += [cwd + '/include/config']
+
+startup_path_prefix = SDK_LIB
+
+# STM32H7S7xx
+# You can select chips from the list above
+CPPDEFINES = ['STM32H7S7xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_adc.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_adc.c
new file mode 100644
index 00000000000..4bf3290cf59
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_adc.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-05 zylx first version
+ * 2018-12-12 greedyhao Porting for stm32f7xx
+ * 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
+ */
+
+#include
+#include
+#include
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.adc"
+#include
+
+static ADC_HandleTypeDef adc_config[] =
+{
+#ifdef BSP_USING_ADC1
+ ADC1_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC2
+ ADC2_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC3
+ ADC3_CONFIG,
+#endif
+};
+
+struct stm32_adc
+{
+ ADC_HandleTypeDef ADC_Handler;
+ struct rt_adc_device stm32_adc_device;
+};
+
+static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
+
+static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+ ADC_HandleTypeDef *stm32_adc_handler;
+ RT_ASSERT(device != RT_NULL);
+ stm32_adc_handler = device->parent.user_data;
+
+ if (enabled)
+ {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
+ ADC_Enable(stm32_adc_handler);
+#else
+ __HAL_ADC_ENABLE(stm32_adc_handler);
+#endif
+ }
+ else
+ {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
+ ADC_Disable(stm32_adc_handler);
+#else
+ __HAL_ADC_DISABLE(stm32_adc_handler);
+#endif
+ }
+
+ return RT_EOK;
+}
+
+static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
+{
+ rt_uint32_t stm32_channel = 0;
+
+ switch (channel)
+ {
+ case 0:
+ stm32_channel = ADC_CHANNEL_0;
+ break;
+ case 1:
+ stm32_channel = ADC_CHANNEL_1;
+ break;
+ case 2:
+ stm32_channel = ADC_CHANNEL_2;
+ break;
+ case 3:
+ stm32_channel = ADC_CHANNEL_3;
+ break;
+ case 4:
+ stm32_channel = ADC_CHANNEL_4;
+ break;
+ case 5:
+ stm32_channel = ADC_CHANNEL_5;
+ break;
+ case 6:
+ stm32_channel = ADC_CHANNEL_6;
+ break;
+ case 7:
+ stm32_channel = ADC_CHANNEL_7;
+ break;
+ case 8:
+ stm32_channel = ADC_CHANNEL_8;
+ break;
+ case 9:
+ stm32_channel = ADC_CHANNEL_9;
+ break;
+ case 10:
+ stm32_channel = ADC_CHANNEL_10;
+ break;
+ case 11:
+ stm32_channel = ADC_CHANNEL_11;
+ break;
+ case 12:
+ stm32_channel = ADC_CHANNEL_12;
+ break;
+ case 13:
+ stm32_channel = ADC_CHANNEL_13;
+ break;
+ case 14:
+ stm32_channel = ADC_CHANNEL_14;
+ break;
+ case 15:
+ stm32_channel = ADC_CHANNEL_15;
+ break;
+#ifdef ADC_CHANNEL_16
+ case 16:
+ stm32_channel = ADC_CHANNEL_16;
+ break;
+#endif
+ case 17:
+ stm32_channel = ADC_CHANNEL_17;
+ break;
+#ifdef ADC_CHANNEL_18
+ case 18:
+ stm32_channel = ADC_CHANNEL_18;
+ break;
+#endif
+#ifdef ADC_CHANNEL_19
+ case 19:
+ stm32_channel = ADC_CHANNEL_19;
+ break;
+#endif
+ }
+
+ return stm32_channel;
+}
+
+static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+ ADC_ChannelConfTypeDef ADC_ChanConf;
+ ADC_HandleTypeDef *stm32_adc_handler;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(value != RT_NULL);
+
+ stm32_adc_handler = device->parent.user_data;
+
+ rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
+
+#ifndef ADC_CHANNEL_16
+ if (channel == 16)
+ {
+ LOG_E("ADC channel must not be 16.");
+ return -RT_ERROR;
+ }
+#endif
+
+/* ADC channel number is up to 17 */
+#if !defined(ADC_CHANNEL_18)
+ if (channel <= 17)
+/* ADC channel number is up to 19 */
+#elif defined(ADC_CHANNEL_19)
+ if (channel <= 19)
+/* ADC channel number is up to 18 */
+#else
+ if (channel <= 18)
+#endif
+ {
+ /* set stm32 ADC channel */
+ ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
+ }
+ else
+ {
+#if !defined(ADC_CHANNEL_18)
+ LOG_E("ADC channel must be between 0 and 17.");
+#elif defined(ADC_CHANNEL_19)
+ LOG_E("ADC channel must be between 0 and 19.");
+#else
+ LOG_E("ADC channel must be between 0 and 18.");
+#endif
+ return -RT_ERROR;
+ }
+#if defined(SOC_SERIES_STM32H7)
+ ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
+#else
+ ADC_ChanConf.Rank = 1;
+#endif
+
+#if defined(SOC_SERIES_STM32F0)
+ ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
+#elif defined(SOC_SERIES_STM32F1)
+ ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
+#elif defined(SOC_SERIES_STM32L4)
+ ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
+#elif defined(SOC_SERIES_STM32H7)
+ ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+#endif
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
+ ADC_ChanConf.Offset = 0;
+#endif
+#ifdef SOC_SERIES_STM32L4
+ ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
+ ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
+#elif defined(SOC_SERIES_STM32H7)
+ ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; /* ADC channel affected to offset number */
+ ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */
+#endif
+
+#if defined(SOC_SERIES_STM32H7)
+ /* Run the ADC linear calibration in single-ended mode */
+ if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK)
+ {
+ LOG_E("ADC open linear calibration error!\n");
+ /* Calibration Error */
+ return -RT_ERROR;
+ }
+#endif
+
+ HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
+
+ /* start ADC */
+ HAL_ADC_Start(stm32_adc_handler);
+
+ /* Wait for the ADC to convert */
+ HAL_ADC_PollForConversion(stm32_adc_handler, 100);
+
+ /* get ADC value */
+ *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
+
+ return RT_EOK;
+}
+
+static const struct rt_adc_ops stm_adc_ops =
+{
+ .enabled = stm32_adc_enabled,
+ .convert = stm32_get_adc_value,
+};
+
+static int stm32_adc_init(void)
+{
+ int result = RT_EOK;
+ /* save adc name */
+ char name_buf[5] = {'a', 'd', 'c', '0', 0};
+ int i = 0;
+
+ for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
+ {
+ /* ADC init */
+ name_buf[3] = '0';
+ stm32_adc_obj[i].ADC_Handler = adc_config[i];
+#if defined(ADC1)
+ if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
+ {
+ name_buf[3] = '1';
+ }
+#endif
+#if defined(ADC2)
+ if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
+ {
+ name_buf[3] = '2';
+ }
+#endif
+#if defined(ADC3)
+ if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
+ {
+ name_buf[3] = '3';
+ }
+#endif
+ if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
+ {
+ LOG_E("%s init failed", name_buf);
+ result = -RT_ERROR;
+ }
+ else
+ {
+ /* register ADC device */
+ if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
+ {
+ LOG_D("%s init success", name_buf);
+ }
+ else
+ {
+ LOG_E("%s register failed", name_buf);
+ result = -RT_ERROR;
+ }
+ }
+ }
+
+ return result;
+}
+INIT_BOARD_EXPORT(stm32_adc_init);
+
+#endif /* BSP_USING_ADC */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c
new file mode 100644
index 00000000000..81f7c60a4b2
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-7 SummerGift first version
+ */
+#include "drv_common.h"
+#include
+
+#ifdef RT_USING_PIN
+ #include
+#endif
+
+#ifdef RT_USING_SERIAL
+ #ifdef RT_USING_SERIAL_V2
+ #include
+ #else
+ #include
+ #endif /* RT_USING_SERIAL */
+#endif /* RT_USING_SERIAL_V2 */
+
+#define DBG_TAG "drv_common"
+#define DBG_LVL DBG_INFO
+#include
+
+#ifdef RT_USING_FINSH
+#include
+static void reboot(uint8_t argc, char **argv)
+{
+ rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+extern __IO uint32_t uwTick;
+static uint32_t _systick_ms = 1;
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+ // Updates the variable SystemCoreClock
+ SystemCoreClockUpdate();
+
+ HAL_SYSTICK_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ NVIC_SetPriority(SysTick_IRQn, 0xFF);
+
+ _systick_ms = 1000u / RT_TICK_PER_SECOND;
+ if (_systick_ms == 0)
+ _systick_ms = 1;
+}
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+ HAL_IncTick();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+uint32_t HAL_GetTick(void)
+{
+ if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+ HAL_IncTick();
+
+ return uwTick;
+}
+
+void HAL_IncTick(void)
+{
+ uwTick += _systick_ms;
+}
+
+void HAL_SuspendTick(void)
+{
+}
+
+void HAL_ResumeTick(void)
+{
+}
+
+void HAL_Delay(__IO uint32_t Delay)
+{
+ if (rt_thread_self())
+ {
+ rt_thread_mdelay(Delay);
+ }
+ else
+ {
+ for (rt_uint32_t count = 0; count < Delay; count++)
+ {
+ rt_hw_us_delay(1000);
+ }
+ }
+}
+
+/* re-implement tick interface for STM32 HAL */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ rt_hw_systick_init();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void _Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+ rt_uint64_t ticks;
+ rt_uint32_t told, tnow, tcnt = 0;
+ rt_uint32_t reload = SysTick->LOAD;
+
+ ticks = us * (reload / (1000000 / RT_TICK_PER_SECOND));
+ told = SysTick->VAL;
+ while (1)
+ {
+ tnow = SysTick->VAL;
+ if (tnow != told)
+ {
+ if (tnow < told)
+ {
+ tcnt += told - tnow;
+ }
+ else
+ {
+ tcnt += reload - tnow + told;
+ }
+ told = tnow;
+ if (tcnt >= ticks)
+ {
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+rt_weak void rt_hw_board_init(void)
+{
+ /* HAL_Init() function is called at the beginning of the program */
+ HAL_Init();
+
+ /* System clock initialization */
+ SystemClock_Config();
+
+#if defined(RT_USING_HEAP)
+ /* Heap initialization */
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_PIN
+ rt_hw_pin_init();
+#endif
+
+#ifdef RT_USING_SERIAL
+ rt_hw_usart_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+ /* Set the shell console output device */
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO)
+ extern void rt_hw_console_init(void);
+ rt_hw_console_init();
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+ /* Board underlying hardware initialization */
+ rt_components_board_init();
+#endif
+
+#ifdef BSP_SCB_ENABLE_I_CACHE
+ /* Enable I-Cache---------------------------------------------------------*/
+ SCB_EnableICache();
+#endif
+
+#ifdef BSP_SCB_ENABLE_D_CACHE
+ /* Enable D-Cache---------------------------------------------------------*/
+ SCB_EnableDCache();
+#endif
+}
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_dcmi.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_dcmi.c
new file mode 100644
index 00000000000..506944682cb
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_dcmi.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-27 thread-liu the first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_DCMI)
+
+#include
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.dcmi"
+#include
+
+struct stm32_dcmi
+{
+ DCMI_HandleTypeDef DCMI_Handle;
+ struct rt_dcmi_device dev;
+};
+static struct stm32_dcmi rt_dcmi = {0};
+
+DMA_HandleTypeDef hdma_dcmi;
+
+static void rt_hw_dcmi_dma_init(void)
+{
+ __HAL_RCC_DMA2_CLK_ENABLE();
+
+ hdma_dcmi.Instance = DMA2_Stream1;
+ hdma_dcmi.Init.Request = DMA_REQUEST_DCMI;
+ hdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_dcmi.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_dcmi.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_dcmi.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+ hdma_dcmi.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+ hdma_dcmi.Init.Mode = DMA_CIRCULAR;
+ hdma_dcmi.Init.Priority = DMA_PRIORITY_HIGH;
+ hdma_dcmi.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
+ hdma_dcmi.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+ hdma_dcmi.Init.MemBurst = DMA_MBURST_SINGLE;
+ hdma_dcmi.Init.PeriphBurst = DMA_PBURST_SINGLE;
+
+ HAL_DMA_Init(&hdma_dcmi);
+
+ __HAL_LINKDMA(&rt_dcmi.DCMI_Handle, DMA_Handle, hdma_dcmi);
+
+ HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0x00, 0x00);
+ HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);;
+}
+
+void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len)
+{
+ HAL_DMAEx_MultiBufferStart(&hdma_dcmi, (rt_uint32_t)&DCMI->DR, dst_addr1, dst_addr2, len);
+
+ __HAL_DMA_ENABLE_IT(&hdma_dcmi, DMA_IT_TC);
+}
+
+static rt_err_t rt_hw_dcmi_init(DCMI_HandleTypeDef *device)
+{
+ RT_ASSERT(device != RT_NULL);
+
+ device->Instance = DCMI;
+ device->Init.SynchroMode = DCMI_SYNCHRO_HARDWARE;
+ device->Init.PCKPolarity = DCMI_PCKPOLARITY_RISING;
+ device->Init.VSPolarity = DCMI_VSPOLARITY_LOW;
+ device->Init.HSPolarity = DCMI_HSPOLARITY_LOW;
+ device->Init.CaptureRate = DCMI_CR_ALL_FRAME;
+ device->Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B;
+ device->Init.JPEGMode = DCMI_JPEG_ENABLE;
+ device->Init.ByteSelectMode = DCMI_BSM_ALL;
+ device->Init.ByteSelectStart = DCMI_OEBS_ODD;
+ device->Init.LineSelectMode = DCMI_LSM_ALL;
+ device->Init.LineSelectStart = DCMI_OELS_ODD;
+
+ if (HAL_DCMI_Init(device) != HAL_OK)
+ {
+ LOG_E("dcmi init error!");
+ return RT_ERROR;
+ }
+
+ DCMI->IER = 0x0;
+
+ __HAL_DCMI_ENABLE_IT(device, DCMI_IT_FRAME);
+ __HAL_DCMI_ENABLE(device);
+
+ return RT_EOK;
+}
+
+void DCMI_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DCMI_IRQHandler(&rt_dcmi.DCMI_Handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void DCMI_Start(void)
+{
+ __HAL_DMA_ENABLE(&hdma_dcmi);
+ DCMI->CR |= DCMI_CR_CAPTURE;
+}
+
+void DCMI_Stop(void)
+{
+ DCMI->CR &= ~(DCMI_CR_CAPTURE);
+ while (DCMI->CR & 0x01);
+ __HAL_DMA_DISABLE(&hdma_dcmi);
+}
+
+/* Capture a frame of the image */
+void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+ extern void camera_frame_data_process(void);
+ /* enter interrupt */
+ rt_interrupt_enter();
+ /* move frame data to buffer */
+ camera_frame_data_process();
+ __HAL_DCMI_ENABLE_IT(&rt_dcmi.DCMI_Handle, DCMI_IT_FRAME);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void DMA2_Stream1_IRQHandler(void)
+{
+ extern void camera_dma_data_process(void);
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ if (__HAL_DMA_GET_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5) != RESET)
+ {
+ __HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF1_5);
+ /* move dma data to buffer */
+ camera_dma_data_process();
+ SCB_CleanInvalidateDCache();
+ }
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static rt_err_t rt_dcmi_init(rt_device_t dev)
+{
+ RT_ASSERT(dev != RT_NULL);
+ rt_err_t result = RT_EOK;
+
+ result = rt_hw_dcmi_init(&rt_dcmi.DCMI_Handle);
+ if (result != RT_EOK)
+ {
+ return result;
+ }
+
+ rt_hw_dcmi_dma_init();
+
+ return result;
+}
+
+static rt_err_t rt_dcmi_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_dcmi_close(rt_device_t dev)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_dcmi_control(rt_device_t dev, int cmd, void *args)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_size_t rt_dcmi_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_size_t rt_dcmi_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+int dcmi_init(void)
+{
+ rt_dcmi.dev.parent.type = RT_Device_Class_Miscellaneous;
+ rt_dcmi.dev.parent.init = rt_dcmi_init;
+ rt_dcmi.dev.parent.open = rt_dcmi_open;
+ rt_dcmi.dev.parent.close = rt_dcmi_close;
+ rt_dcmi.dev.parent.read = rt_dcmi_read;
+ rt_dcmi.dev.parent.write = rt_dcmi_write;
+ rt_dcmi.dev.parent.control = rt_dcmi_control;
+ rt_dcmi.dev.parent.user_data = RT_NULL;
+
+ rt_device_register(&rt_dcmi.dev.parent, "dcmi", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
+
+ LOG_I("dcmi init success!");
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(dcmi_init);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c
new file mode 100644
index 00000000000..0a95c837373
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c
@@ -0,0 +1,697 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-19 SummerGift first version
+ * 2018-12-25 zylx fix some bugs
+ * 2019-06-10 SummerGift optimize PHY state detection process
+ * 2019-09-03 xiaofan optimize link change detection process
+ * 2020-07-17 wanghaijing support h7
+ * 2020-11-30 wanghaijing add phy reset
+ */
+
+#include
+#include
+#include "board.h"
+#include "drv_config.h"
+
+#ifdef BSP_USING_ETH
+
+#include
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+/*
+* Emac driver uses CubeMX tool to generate emac and phy's configuration,
+* the configuration files can be found in CubeMX_Config folder.
+*/
+
+/* debug option */
+//#define ETH_RX_DUMP
+//#define ETH_TX_DUMP
+//#define DRV_DEBUG
+#define LOG_TAG "drv_eth.c"
+#include
+
+#define MAX_ADDR_LEN (6)
+
+
+
+struct rt_stm32_eth
+{
+ /* inherit from ethernet device */
+ struct eth_device parent;
+#ifndef PHY_USING_INTERRUPT_MODE
+ rt_timer_t poll_link_timer;
+#endif
+
+ /* interface address info, hw address */
+ rt_uint8_t dev_addr[MAX_ADDR_LEN];
+ /* ETH_Speed */
+ uint32_t ETH_Speed;
+ /* ETH_Duplex_Mode */
+ uint32_t ETH_Mode;
+};
+
+typedef struct
+{
+ struct pbuf pbuf;
+ uint8_t buff[ETH_RX_BUFFER_SIZE];
+} RxBuff_t;
+
+static ETH_HandleTypeDef EthHandle = {0};
+static ETH_TxPacketConfig TxConfig;
+static struct rt_stm32_eth stm32_eth_device;
+static uint8_t PHY_ADDR = BSP_ETH_PHY_ADDR;
+static rt_uint32_t reset_pin = 0;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+#pragma location=0x24020000
+ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+#pragma location=0x24020100
+ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+#pragma location=0x24020200
+uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */
+
+#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
+__attribute__((at(0x24020000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+__attribute__((at(0x24020100))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+__attribute__((at(0x24020200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */
+
+#elif defined ( __GNUC__ ) /* GNU Compiler */
+ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
+ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */
+RxBuff_t Rx_Buff[ETH_RX_DESC_CNT] __attribute__((section(".RxArraySection")))__attribute__((aligned(32))); /* Ethernet Receive Buffers */
+#endif
+
+#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+ unsigned char *buf = (unsigned char *)ptr;
+ int i, j;
+
+ for (i = 0; i < buflen; i += 16)
+ {
+ rt_kprintf("%08X: ", i);
+
+ for (j = 0; j < 16; j++)
+ if (i + j < buflen)
+ rt_kprintf("%02X ", buf[i + j]);
+ else
+ rt_kprintf(" ");
+ rt_kprintf(" ");
+
+ for (j = 0; j < 16; j++)
+ if (i + j < buflen)
+ rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+ rt_kprintf("\n");
+ }
+}
+#endif
+
+static void phy_reset(void)
+{
+ rt_pin_write(reset_pin, PIN_LOW);
+ rt_thread_mdelay(50);
+ rt_pin_write(reset_pin, PIN_HIGH);
+}
+
+
+/* EMAC initialization function */
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+ ETH_MACConfigTypeDef MACConf;
+ uint32_t regvalue = 0;
+ uint8_t status = RT_EOK;
+
+
+ /* ETHERNET Configuration */
+ EthHandle.Instance = ETH;
+ EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
+ EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE;
+ EthHandle.Init.TxDesc = DMATxDscrTab;
+ EthHandle.Init.RxDesc = DMARxDscrTab;
+ EthHandle.Init.RxBuffLen = ETH_MAX_PACKET_SIZE;
+
+ SCB_InvalidateDCache();
+
+ HAL_ETH_DeInit(&EthHandle);
+
+ /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
+ if (HAL_ETH_Init(&EthHandle) != HAL_OK)
+ {
+ LOG_E("eth hardware init failed");
+ }
+ else
+ {
+ LOG_D("eth hardware init success");
+ }
+
+ phy_reset();
+
+ rt_memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
+ TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+ TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+ TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+
+// for (int idx = 0; idx < ETH_RX_DESC_CNT; idx++)
+// {
+// HAL_ETH_DescAssignMemory(&EthHandle, idx, &Rx_Buff[idx][0], NULL);
+// }
+
+ HAL_ETH_SetMDIOClockRange(&EthHandle);
+
+ /* 自己找phy的地址 */
+// for(int i = 0; i <= PHY_ADDR; i ++)
+// {
+// if(HAL_ETH_ReadPHYRegister(&EthHandle, i, PHY_SPECIAL_MODES_REG, ®value) != HAL_OK)
+// {
+// status = RT_ERROR;
+// /* Can't read from this device address continue with next address */
+// continue;
+// }
+//
+// if((regvalue & PHY_BASIC_STATUS_REG) == i)
+// {
+// PHY_ADDR = i;
+// status = RT_EOK;
+// LOG_D("Found a phy, address:0x%02X", PHY_ADDR);
+// break;
+// }
+// }
+ PHY_ADDR = BSP_ETH_PHY_ADDR;
+
+ /* 软复位 */
+ if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK)
+ {
+ HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value);
+
+ uint32_t tickstart = rt_tick_get();
+
+ /* wait until software reset is done or timeout occured */
+ while(regvalue & PHY_RESET_MASK)
+ {
+ if((rt_tick_get() - tickstart) <= 500)
+ {
+ if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) != HAL_OK)
+ {
+ status = RT_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = RT_ETIMEOUT;
+ }
+ }
+ }
+
+ rt_thread_delay(2000);
+
+ /* 启动自动协商 */
+ if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) == HAL_OK)
+ {
+ regvalue |= PHY_AUTO_NEGOTIATION_MASK;
+ HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, regvalue);
+
+ eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+ HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
+ MACConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+ MACConf.Speed = ETH_SPEED_100M;
+ HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
+
+ HAL_ETH_Start_IT(&EthHandle);
+ SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef));
+ }
+ else
+ {
+ status = RT_ERROR;
+ }
+
+ return status;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ LOG_D("emac open");
+ return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+ LOG_D("emac close");
+ return RT_EOK;
+}
+
+static rt_ssize_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+ LOG_D("emac read");
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_ssize_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+ LOG_D("emac write");
+ rt_set_errno(-RT_ENOSYS);
+ return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
+{
+ switch (cmd)
+ {
+ case NIOCTL_GADDR:
+ /* get mac address */
+ if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+ else return -RT_ERROR;
+ break;
+
+ default :
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit data*/
+rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+ rt_err_t ret = RT_ERROR;
+ HAL_StatusTypeDef state;
+ uint32_t i = 0, framelen = 0;
+ struct pbuf *q;
+ ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};
+
+ rt_memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef));
+
+ for (q = p; q != NULL; q = q->next)
+ {
+ if (i >= ETH_TX_DESC_CNT)
+ return ERR_IF;
+
+ Txbuffer[i].buffer = q->payload;
+ Txbuffer[i].len = q->len;
+ framelen += q->len;
+
+ if (i > 0)
+ {
+ Txbuffer[i - 1].next = &Txbuffer[i];
+ }
+
+ if (q->next == NULL)
+ {
+ Txbuffer[i].next = NULL;
+ }
+
+ i++;
+ }
+
+ TxConfig.Length = framelen;
+ TxConfig.TxBuffer = Txbuffer;
+ TxConfig.pData = p;
+
+#ifdef ETH_TX_DUMP
+ rt_kprintf("Tx dump, len= %d\r\n", framelen);
+ dump_hex(&Txbuffer[0]);
+#endif
+
+ if (stm32_eth_device.parent.link_status)
+ {
+ SCB_CleanInvalidateDCache();
+ state = HAL_ETH_Transmit(&EthHandle, &TxConfig, 1000);
+ if (state != HAL_OK)
+ {
+ LOG_W("eth transmit frame faild: %d", EthHandle.ErrorCode);
+ EthHandle.ErrorCode = HAL_ETH_STATE_READY;
+ EthHandle.gState = HAL_ETH_STATE_READY;
+ }
+ }
+ else
+ {
+ LOG_E("eth transmit frame faild, netif not up");
+ }
+ HAL_ETH_ReleaseTxPacket(&EthHandle);
+ ret = ERR_OK;
+
+ return ret;
+}
+
+/* receive data*/
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+ uint32_t framelength = 0;
+ rt_uint16_t l;
+ struct pbuf *p = RT_NULL;
+ uint32_t alignedAddr;
+ RxBuff_t *pStart = RT_NULL, *q;
+
+ SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef));
+ /* 这里pStart指向的其实是RxBuff_t的地址 */
+ if(HAL_ETH_ReadData(&EthHandle, (void**)&pStart) == HAL_OK)
+ {
+ SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef));
+ framelength = EthHandle.RxDescList.RxDataLength;
+ /* Invalidate data cache for ETH Rx Buffers */
+ /* pStart指向的Rx_Buff定义时候已经是32对齐过了 */
+ SCB_InvalidateDCache_by_Addr((uint32_t *)pStart->buff, framelength);
+
+ p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
+ if (p != NULL)
+ {
+ for (q = pStart, l = 0; q != NULL; q = (RxBuff_t *)q->pbuf.next)
+ {
+
+ // memcpy((rt_uint8_t *)q->payload, (rt_uint8_t *)&RxBuff.buffer[l], q->len);
+ rt_memcpy(&(((rt_uint8_t*)(p->payload))[l]), q->buff, q->pbuf.len);
+ l = l + q->pbuf.len;
+ }
+#ifdef BSP_ETH_USING_DEBUG
+ // memcpy((rt_uint8_t *)p->payload, (rt_uint8_t *)pStart->buff, framelength);
+ LOG_I("eth_rx rece data = %d", framelength);
+#endif
+ }
+ }
+
+ return p;
+}
+
+/* interrupt service routine */
+void ETH_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_ETH_IRQHandler(&EthHandle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void HAL_ETH_TxFreeCallback(uint32_t * buff)
+{
+/* USER CODE BEGIN HAL ETH TxFreeCallback */
+
+ pbuf_free((struct pbuf *)buff);
+
+/* USER CODE END HAL ETH TxFreeCallback */
+}
+
+void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+{
+ /* *
+ * ppstart是描述符列表里的pRxStart成员，在这里
+ * 定义为pbuf的地址也是RxBuff_t的地址，buff是
+ * 以太网frame保存的地址，这个函数主要是把相关
+ * 的pbuf都连接起来。
+ */
+ struct pbuf **ppStart = (struct pbuf **)pStart;
+ struct pbuf **ppEnd = (struct pbuf **)pEnd;
+ struct pbuf *p = NULL;
+
+ /* Get the struct pbuf from the buff address. */
+ p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff));
+ p->next = NULL;
+ p->tot_len = 0;
+ p->len = Length;
+
+ /* Chain the buffer. */
+ /* 正常来说新包的第一次进这里pstart都应该是空的 */
+ if (!*ppStart)
+ {
+ /* 第一个buffer设置pstart. */
+ *ppStart = p;
+ }
+ else
+ {
+ /* 这里的pEnd指向上次进HAL_ETH_RxLinkCallback的pbuf，也是RX_BUFF_T */
+ (*ppEnd)->next = p;
+ }
+ /* pEnd设置为当前pbuf */
+ *ppEnd = p;
+
+ /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len
+ * set to its own length, plus the length of all the following pbufs in the chain. */
+ for (p = *ppStart; p != NULL; p = p->next)
+ {
+ p->tot_len += Length;
+ }
+
+ /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */
+ SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length);
+
+}
+
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ rt_err_t result;
+ result = eth_device_ready(&(stm32_eth_device.parent));
+ if (result != RT_EOK)
+ LOG_I("RxCpltCallback err = %d", result);
+}
+
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+ if ((HAL_ETH_GetDMAError(heth) & ETH_DMACSR_RBU) == ETH_DMACSR_RBU)
+ {
+ LOG_E("eth err:ETH_DMACSR_RBU");
+ }
+
+ if((HAL_ETH_GetDMAError(heth) & ETH_DMACSR_TBU) == ETH_DMACSR_TBU)
+ {
+ LOG_E("eth err:ETH_DMACSR_TBU");
+ }
+ LOG_E("eth err");
+}
+
+
+/* -----------------------------------以下皆为测试----------------------------------------- */
+
+void HAL_ETH_RxAllocateCallback(uint8_t **buff)
+{
+// static uint16_t buf_index = 0;
+// *buff = Rx_Buff[buf_index];
+// buf_index++;
+// if(buf_index >= ETH_RX_DESC_CNT) buf_index = 0;
+
+ /* 使用环形缓冲区索引 */
+ static uint16_t buf_index = 0;
+#ifdef BSP_ETH_USING_DEBUG
+ uint16_t i = 0,j = 0;
+#endif
+
+ /* 更新索引前检查描述符所有权 */
+ if((DMARxDscrTab[buf_index].DESC3 & ETH_DMARXNDESCRF_OWN) == 0) {
+ *buff = Rx_Buff[buf_index].buff;
+ buf_index = (buf_index + 1) % ETH_RX_DESC_CNT;
+
+#ifdef BSP_ETH_USING_DEBUG
+ LOG_I("RxAlloCB buf_index = %d", buf_index);
+ for(i=0;i
+#include
+
+#ifdef RT_USING_CAN
+
+#if defined(BSP_USING_FDCAN1) || defined(BSP_USING_FDCAN2)
+
+#include "drv_fdcan.h"
+
+#define LOG_TAG "drv_can"
+#define DBG_LVL LOG_LVL_DBG
+#include
+
+#ifdef BSP_USING_FDCAN1
+static _stm32_fdcan_t st_DrvCan1 = {0};
+#endif
+
+#ifdef BSP_USING_FDCAN2
+static _stm32_fdcan_t st_DrvCan2 = {0};
+#endif
+
+
+/*
+ * note:经过分频后，fdcan工作时钟为100mhz
+ */
+static const _stm32_fdcan_NTconfig_t st_CanNTconfig[]=
+/*baud brp sjw tseg1 tseg2*/
+{
+ {BSP_FDCAN_BAUD_DATA_5M, 1,8,15,4}, /* 这四个只有数据段可以使用 */
+ {BSP_FDCAN_BAUD_DATA_4M, 1,8,19,5},
+ {BSP_FDCAN_BAUD_DATA_2M5, 2,8,15,4},
+ {BSP_FDCAN_BAUD_DATA_2M, 2,8,19,5},
+ {CAN1MBaud, 5,8,15,4}, /* 下面都可以 */
+ {CAN800kBaud, 1,8,99,25},
+ {CAN500kBaud, 10,8,15,4},
+ {CAN250kBaud, 10,8,35,4},
+ {CAN125kBaud, 20,8,35,4},
+ {CAN100kBaud, 20,8,44,5},
+ {CAN50kBaud, 40,8,44,5},
+ {CAN20kBaud, 100,8,44,5},
+ {CAN10kBaud, 200,8,44,5}
+};
+
+/*
+*function name:_inline_get_NTbaud_index
+*Inf: 根据传入的波特率大小返回上面st_CanNTconfig这个
+*Inf: timing配置结构体数组的索引值。
+*
+*#param: 波特率:十进制数字
+*
+*#return: 索引值;如果没找到就返回0xff
+*/
+static uint32_t _inline_get_NTbaud_index(uint32_t baud_rate)
+{
+ uint32_t len, index;
+
+ len = sizeof(st_CanNTconfig) / sizeof(st_CanNTconfig[0]);
+
+ for (index = 0; index < len; index++)
+ {
+ if (st_CanNTconfig[index].u32NBaudrate == baud_rate)
+
+ return index;
+ }
+
+ return 0xff;
+}
+
+static void _inline_can_tx_header_init(_stm32_fdcan_t *pCan)
+{
+ /* Prepare Tx Header */
+ pCan->TxHeader.Identifier = 0x000000;
+ pCan->TxHeader.IdType = FDCAN_EXTENDED_ID;
+ pCan->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
+ pCan->TxHeader.DataLength = FDCAN_DLC_BYTES_8;
+ pCan->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
+ pCan->TxHeader.BitRateSwitch = FDCAN_BRS_OFF;
+ pCan->TxHeader.FDFormat = FDCAN_CLASSIC_CAN;
+ pCan->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
+ pCan->TxHeader.MessageMarker = 0;
+}
+
+
+/*
+ * note:这里输入时钟时pll1q，600mhz，进去先分频到100m，正点原子说最大125m，但没翻到，暂且相信
+ */
+static rt_err_t _inline_can_config(struct rt_can_device *can, struct can_configure *cfg)
+{
+ _stm32_fdcan_t *pdrv_can;
+ rt_uint32_t tmp_u32Index;
+ FDCAN_FilterTypeDef canx_rxfilter = {0};
+
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
+
+ pdrv_can = (_stm32_fdcan_t *)can->parent.user_data;
+
+ RT_ASSERT(pdrv_can);
+ /* 外设时钟输入600MHZ，经过6分频为100MHZ */
+ pdrv_can->fdcanHandle.Init.ClockDivider = FDCAN_CLOCK_DIV6;
+
+ /* 配置FrameFormat */
+ if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_CLASSIC)
+ {
+ pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+ pdrv_can->fdcanHandle.Init.AutoRetransmission = DISABLE;
+ }else if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS)
+ {
+ pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_NO_BRS;
+ pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE;
+ }else if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_BRS)
+ {
+ pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+ pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE;
+ }else return -RT_ERROR;
+
+ pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+ pdrv_can->fdcanHandle.Init.TransmitPause = DISABLE;
+ pdrv_can->fdcanHandle.Init.ProtocolException = DISABLE;
+
+ switch (cfg->mode)
+ {
+ case RT_CAN_MODE_NORMAL:
+ pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+ break;
+ case RT_CAN_MODE_LISTEN:
+ pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_BUS_MONITORING;
+ break;
+ case RT_CAN_MODE_LOOPBACK:
+ pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK;
+ break;
+ default:
+ pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+ break;
+ }
+
+ /* 配置经典CAN或者仲裁段速率 */
+ tmp_u32Index = _inline_get_NTbaud_index(cfg->baud_rate);
+
+ /* 数据段速率不能超过1M */
+ if(tmp_u32Index <= 3 || tmp_u32Index == 0xff)
+ return -RT_ERROR;
+
+ pdrv_can->fdcanHandle.Init.NominalPrescaler = st_CanNTconfig[tmp_u32Index].u16Nbrp;
+ pdrv_can->fdcanHandle.Init.NominalSyncJumpWidth = st_CanNTconfig[tmp_u32Index].u8Nsjw;
+ pdrv_can->fdcanHandle.Init.NominalTimeSeg1 = st_CanNTconfig[tmp_u32Index].u8Ntseg1;
+ pdrv_can->fdcanHandle.Init.NominalTimeSeg2 = st_CanNTconfig[tmp_u32Index].u8Ntseg2;
+
+ /* 配置数据段速率 */
+ if(cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_BRS)
+ {
+ tmp_u32Index = _inline_get_NTbaud_index(cfg->baud_rate_fd);
+ /* 数据段速率因为当前timing设置的问题，速率不能1M以下 */
+ if(tmp_u32Index > 4 || tmp_u32Index == 0xff)
+ return -RT_ERROR;
+
+ pdrv_can->fdcanHandle.Init.DataPrescaler = st_CanNTconfig[tmp_u32Index].u16Nbrp;
+ pdrv_can->fdcanHandle.Init.DataSyncJumpWidth = st_CanNTconfig[tmp_u32Index].u8Nsjw;
+ pdrv_can->fdcanHandle.Init.DataTimeSeg1 = st_CanNTconfig[tmp_u32Index].u8Ntseg1;
+ pdrv_can->fdcanHandle.Init.DataTimeSeg2 = st_CanNTconfig[tmp_u32Index].u8Ntseg2;
+ }
+
+ /* h7r的fdcan和h7用的有些不一样,消息ram被砍了不少,这里可以直接配置成最大 */
+ pdrv_can->fdcanHandle.Init.StdFiltersNbr = 28;
+ pdrv_can->fdcanHandle.Init.ExtFiltersNbr = 8;
+
+ if (HAL_FDCAN_Init(&pdrv_can->fdcanHandle) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ /* 安装过滤器 */
+#if defined(RT_CAN_USING_HDR)
+ HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig);
+#else/* 没开HDR支持，就默认全收 */
+
+ /* 配置CAN过滤器 */
+ canx_rxfilter.IdType = FDCAN_STANDARD_ID; /* 标准ID */
+ canx_rxfilter.FilterIndex = 0; /* 滤波器索引 */
+ canx_rxfilter.FilterType = FDCAN_FILTER_MASK; /* 滤波器类型 */
+ canx_rxfilter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; /* 过滤器0关联到FIFO0 */
+ canx_rxfilter.FilterID1 = 0x0000; /* 第一个可被接受的32位ID */
+ canx_rxfilter.FilterID2 = 0x0000; /* 第二个可被接受的32位ID，如果FDCAN配置为传统模式的话，这里是32位掩码 */
+ /* 过滤器配置 */
+ if (HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &canx_rxfilter) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ /* 扩展ID */
+ canx_rxfilter.IdType = FDCAN_EXTENDED_ID;
+ if (HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &canx_rxfilter) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+#endif
+
+ if (HAL_FDCAN_ConfigGlobalFilter(&pdrv_can->fdcanHandle, FDCAN_REJECT, FDCAN_REJECT, FDCAN_FILTER_REMOTE, FDCAN_FILTER_REMOTE) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ /* 初始化发送头 */
+ _inline_can_tx_header_init(pdrv_can);
+
+ /* 启动外围设备 */
+ HAL_FDCAN_Start(&pdrv_can->fdcanHandle);
+ return RT_EOK;
+}
+
+/*
+ * brief: 这个函数的过滤表模式只做了掩码mask模式，
+ * stm32还支持范围和双值模式，这里没做支持,
+ * 默认就是掩码模式
+ *
+ * 暂不支持hdr-bank为负,IdType不一样用的是
+ * 两套索引//hdr暂未支持
+ */
+/* 暂时有问题 */
+#ifdef RT_CAN_USING_HDR
+static rt_err_t _inline_can_filter_config(_stm32_fdcan_t *pdrv_can,struct rt_can_filter_config *puser_can_filter_config)
+{
+ int tmp_i32IndexCount;
+
+ RT_ASSERT(pdrv_can);
+ RT_ASSERT(puser_can_filter_config);
+
+ pdrv_can->ext_filter_num = 0;
+ pdrv_can->std_filter_num = 0;
+
+ /* get default filter */
+ for (tmp_i32IndexCount = 0; tmp_i32IndexCount < puser_can_filter_config->count; tmp_i32IndexCount++)
+ {
+
+ if(puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank < 0) continue;
+
+
+ _FilterIndex = (rt_uint32_t)puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank;
+
+ if(puser_can_filter_config->items[tmp_i32IndexCount].ide == RT_CAN_EXTID)
+ {
+ pdrv_can->FilterConfig.IdType = FDCAN_EXTENDED_ID;
+ if(_FilterIndex > 7) return -RT_ERROR;
+ }
+ else
+ {
+ pdrv_can->FilterConfig.IdType = FDCAN_STANDARD_ID;
+ if(_FilterIndex > 27) return -RT_ERROR;
+ }
+
+
+
+
+ pdrv_can->FilterConfig.FilterIndex = _FilterIndex;
+ pdrv_can->FilterConfig.FilterID1 = puser_can_filter_config->items[tmp_i32IndexCount].id;
+ pdrv_can->FilterConfig.FilterID2 = puser_can_filter_config->items[tmp_i32IndexCount].mask;
+
+
+ /* filter-item里面的rtr过滤stm32不能设置 */
+ pdrv_can->FilterConfig.FilterType = FDCAN_FILTER_MASK;
+ pdrv_can->FilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+ if(HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+ }
+ return RT_EOK;
+}
+#endif
+
+static rt_err_t _inline_can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+
+ rt_uint32_t argval;
+ _stm32_fdcan_t *pdrv_can;
+ rt_uint32_t tmp_u32Errcount;
+ rt_uint32_t tmp_u32status;
+// struct rt_can_filter_config *filter_cfg;
+
+ RT_ASSERT(can != RT_NULL);
+ pdrv_can = (_stm32_fdcan_t *)can->parent.user_data;
+ RT_ASSERT(pdrv_can != RT_NULL);
+
+ switch (cmd)
+ {
+
+ case RT_DEVICE_CTRL_CLR_INT:
+ argval = (rt_uint32_t) arg;
+ if (argval == RT_DEVICE_FLAG_INT_RX)
+ {
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE);
+ }
+ else if (argval == RT_DEVICE_FLAG_INT_TX)
+ {
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_FIFO_EMPTY);
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE);
+ }
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING);
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE);
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_LOGGING_OVERFLOW);
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF);
+ HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR);
+ }
+ break;
+ case RT_DEVICE_CTRL_SET_INT:
+ argval = (rt_uint32_t) arg;
+ if (argval == RT_DEVICE_FLAG_INT_RX)
+ {
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, FDCAN_INTERRUPT_LINE0);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0);
+
+ if(FDCAN1 == pdrv_can->fdcanHandle.Instance)
+ {
+ HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 1);
+ HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+ }
+ else
+ {
+ HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 1);
+ HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+ }
+
+ }
+ else if (argval == RT_DEVICE_FLAG_INT_TX)
+ {
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_INTERRUPT_LINE1);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER0);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER1);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER2);
+
+ if(FDCAN1 == pdrv_can->fdcanHandle.Instance)
+ {
+ HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
+ HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
+ }
+ else
+ {
+ HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
+ HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
+ }
+ }
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, FDCAN_INTERRUPT_LINE1);
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, FDCAN_INTERRUPT_LINE1);
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, FDCAN_INTERRUPT_LINE1);
+ HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, FDCAN_INTERRUPT_LINE1);
+
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, 0);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, 0);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, 0);
+ HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, 0);
+ if(FDCAN1 == pdrv_can->fdcanHandle.Instance)
+ {
+ HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
+ HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
+ }
+ else
+ {
+ HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
+ HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
+ }
+ }
+ break;
+
+#ifdef RT_CAN_USING_HDR
+ case RT_CAN_CMD_SET_FILTER:
+ if (RT_NULL == arg)
+ {
+ /* default filter config */
+ HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig);
+ }
+ else
+ {
+ filter_cfg = (struct rt_can_filter_config *)arg;
+ _inline_can_filter_config(pdrv_can, filter_cfg);
+ }
+ break;
+#endif
+
+ case RT_CAN_CMD_SET_MODE:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_NORMAL &&
+ argval != RT_CAN_MODE_LISTEN &&
+ argval != RT_CAN_MODE_LOOPBACK &&
+ argval != RT_CAN_MODE_LOOPBACKANLISTEN)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pdrv_can->device.config.mode)
+ {
+ pdrv_can->device.config.mode = argval;
+ return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+ }
+ break;
+ case RT_CAN_CMD_SET_BAUD:
+ argval = (rt_uint32_t ) arg;
+ /*just low to 50kbit/s*/
+ if (argval != CAN1MBaud &&
+ argval != CAN800kBaud &&
+ argval != CAN500kBaud &&
+ argval != CAN250kBaud &&
+ argval != CAN125kBaud &&
+ argval != CAN100kBaud &&
+ argval != CAN50kBaud &&
+ argval != CAN20kBaud &&
+ argval != CAN10kBaud)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pdrv_can->device.config.baud_rate)
+ {
+ pdrv_can->device.config.baud_rate = argval;
+ return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+ }
+ break;
+
+ case RT_CAN_CMD_SET_PRIV:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_PRIV &&
+ argval != RT_CAN_MODE_NOPRIV)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pdrv_can->device.config.privmode)
+ {
+ pdrv_can->device.config.privmode = argval;
+
+ return RT_EOK;
+ }
+ break;
+
+ case RT_CAN_CMD_GET_STATUS:
+ tmp_u32Errcount = pdrv_can->fdcanHandle.Instance->ECR;
+ tmp_u32status = pdrv_can->fdcanHandle.Instance->PSR;
+
+ pdrv_can->device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
+ pdrv_can->device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
+ pdrv_can->device.status.lasterrtype = tmp_u32status&0x000000007;
+
+ rt_memcpy(arg, &pdrv_can->device.status, sizeof(pdrv_can->device.status));
+ break;
+
+ case BSP_CAN_CMD_SET_BRS_BAUD:
+ argval = (rt_uint32_t ) arg;
+ /*just low to 50kbit/s*/
+ if (argval != BSP_FDCAN_BAUD_DATA_2M &&
+ argval != BSP_FDCAN_BAUD_DATA_2M5 &&
+ argval != BSP_FDCAN_BAUD_DATA_4M &&
+ argval != BSP_FDCAN_BAUD_DATA_5M)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pdrv_can->device.config.baud_rate_fd)
+ {
+ pdrv_can->device.config.baud_rate_fd = argval;
+ return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+ }
+ break;
+ }
+
+ return RT_EOK;
+}
+
+static rt_ssize_t _inline_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+
+ _stm32_fdcan_t *pdrv_can;
+ struct rt_can_msg *pmsg;
+ uint32_t tmp_u32DataLen;
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pdrv_can = (_stm32_fdcan_t *)can->parent.user_data;
+
+ RT_ASSERT(pdrv_can);
+
+ pmsg = (struct rt_can_msg *) buf;
+
+ /* Check the parameters */
+ tmp_u32DataLen = pmsg->len;
+#ifndef RT_CAN_USING_CANFD
+ if(pmsg->len > 8)
+ {
+ tmp_u32DataLen = 8;
+ }
+#else
+ if(pmsg->len > 64)
+ {
+ tmp_u32DataLen = 64;
+ }
+#endif
+ /* id */
+ pdrv_can->TxHeader.Identifier = pmsg->id;
+
+ /* id-type */
+ if(pmsg->ide == RT_CAN_EXTID)
+ {
+ pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID;
+ }
+ else
+ {
+ pdrv_can->TxHeader.IdType = FDCAN_STANDARD_ID;
+ }
+
+ /* tx-frame-type */
+ if (pmsg->rtr == RT_CAN_DTR)
+ {
+ pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
+ }
+ else
+ {
+ pdrv_can->TxHeader.TxFrameType = FDCAN_REMOTE_FRAME;
+ }
+
+ /* data-length */
+ if(tmp_u32DataLen <= 8){
+ pdrv_can->TxHeader.DataLength = tmp_u32DataLen;
+ }else if (tmp_u32DataLen <= 12) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_12;
+ }else if (tmp_u32DataLen <= 16) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_16;
+ }else if (tmp_u32DataLen <= 20) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_20;
+ }else if (tmp_u32DataLen <= 24) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_24;
+ }else if (tmp_u32DataLen <= 32) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_32;
+ }else if (tmp_u32DataLen <= 48) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_48;
+ }else if (tmp_u32DataLen <= 64) {
+ pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_64;
+ }
+
+ /* brs */
+ if (pmsg->brs == 1)
+ {
+ pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_ON;
+ }
+ else
+ {
+ pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_OFF;
+ }
+
+ /* FDFormat */
+ if (pmsg->fd_frame == 1)
+ {
+ pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN;
+ }
+ else
+ {
+ pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN;
+ }
+
+ pdrv_can->TxHeader.MessageMarker = 0;
+ pdrv_can->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
+ pdrv_can->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
+
+ if(HAL_FDCAN_AddMessageToTxFifoQ(&pdrv_can->fdcanHandle, &pdrv_can->TxHeader, pmsg->data) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+static rt_ssize_t _inline_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+
+ struct rt_can_msg *pmsg;
+ _stm32_fdcan_t *pdrv_can;
+
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pdrv_can = (_stm32_fdcan_t *)can->parent.user_data;
+ pmsg = (struct rt_can_msg *) buf;
+ if(HAL_FDCAN_GetRxMessage(&pdrv_can->fdcanHandle, FDCAN_RX_FIFO0, &pdrv_can->RxHeader, pmsg->data) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+ else
+ {
+ pmsg->id = pdrv_can->RxHeader.Identifier;
+ if(pdrv_can->RxHeader.IdType == FDCAN_EXTENDED_ID)
+ {
+ pmsg->ide = RT_CAN_EXTID;
+ }
+ else
+ {
+ pmsg->ide = RT_CAN_STDID;
+ }
+
+ if(pdrv_can->RxHeader.RxFrameType == FDCAN_DATA_FRAME)
+ {
+ pmsg->rtr = RT_CAN_DTR;
+ }
+ else
+ {
+ pmsg->rtr = RT_CAN_RTR;
+ }
+
+ /* 长度 */
+ if(pdrv_can->RxHeader.DataLength <= 8)
+ {
+ pmsg->len = pdrv_can->RxHeader.DataLength;
+ }
+ else
+ {
+ switch(pdrv_can->RxHeader.DataLength)
+ {
+ case FDCAN_DLC_BYTES_12:
+ pmsg->len = 12;
+ break;
+
+ case FDCAN_DLC_BYTES_16:
+ pmsg->len = 16;
+ break;
+
+ case FDCAN_DLC_BYTES_20:
+ pmsg->len = 20;
+ break;
+
+ case FDCAN_DLC_BYTES_24:
+ pmsg->len = 24;
+ break;
+
+ case FDCAN_DLC_BYTES_32:
+ pmsg->len = 32;
+ break;
+
+ case FDCAN_DLC_BYTES_48:
+ pmsg->len = 48;
+ break;
+
+ case FDCAN_DLC_BYTES_64:
+ pmsg->len = 64;
+ break;
+
+ default:
+ pmsg->len = 0;
+ break;
+ }
+ }
+
+
+ if(pdrv_can->RxHeader.FDFormat == FDCAN_FD_CAN)
+ {
+ pmsg->fd_frame = 1;
+ }else pmsg->fd_frame = 0;
+
+ if(pdrv_can->RxHeader.BitRateSwitch == FDCAN_BRS_ON)
+ {
+ pmsg->brs = 1;
+ }else pmsg->brs = 0;
+
+ pmsg->hdr_index = pdrv_can->RxHeader.FilterIndex;
+ return RT_EOK;
+
+ }
+}
+
+static const struct rt_can_ops _can_ops =
+{
+ _inline_can_config,
+ _inline_can_control,
+ _inline_can_sendmsg,
+ _inline_can_recvmsg,
+};
+
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+ if((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET)
+ {
+ if(hfdcan->Instance == FDCAN1)
+ {
+#ifdef BSP_USING_FDCAN1
+ //CAN1
+ /* Retreive Rx messages from RX FIFO0 */
+ rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_RX_IND | 0 << 8);
+#endif
+ }
+ else
+ {
+#ifdef BSP_USING_FDCAN2
+ //CAN2
+ /* Retreive Rx messages from RX FIFO0 */
+ rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_RX_IND | 0 << 8);
+#endif
+ }
+ }
+}
+
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ if(hfdcan->Instance == FDCAN1)
+ {
+#ifdef BSP_USING_FDCAN1
+ //can1
+ // LOG_D("tx buffer can1 complete,buffer index:%x", BufferIndexes);
+ rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE | (((0) << 8)));
+#endif
+ }
+ else
+ {
+ // LOG_D("tx buffer can2 complete");
+#ifdef BSP_USING_FDCAN2
+ //can2
+ rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8));
+#endif
+ }
+
+}
+
+
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ if(hfdcan->Instance == FDCAN1)
+ {
+ //can1
+ // LOG_D("tx fifo can1 empty");
+ }
+ else
+ {
+ //can2
+ // LOG_D("tx fifo can2 empty");
+ }
+}
+
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+
+}
+
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ rt_uint32_t tmp_u32Errcount;
+ rt_uint32_t tmp_u32status;
+ uint32_t ret = HAL_FDCAN_GetError(hfdcan);
+
+ if(hfdcan->Instance == FDCAN1)
+ {
+#ifdef BSP_USING_FDCAN1
+ //can1
+ if( (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
+ (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
+ {
+ //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
+ hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
+ st_DrvCan1.device.status.errcode = 0xff;
+ }
+ else
+ {
+ tmp_u32Errcount = st_DrvCan1.fdcanHandle.Instance->ECR;
+ tmp_u32status = st_DrvCan1.fdcanHandle.Instance->PSR;
+
+ st_DrvCan1.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
+ st_DrvCan1.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
+ st_DrvCan1.device.status.lasterrtype = tmp_u32status&0x000000007;
+ }
+#endif /*BSP_USING_FDCAN1*/
+ }
+ else
+ {
+#ifdef BSP_USING_FDCAN2
+ if( (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
+ (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
+ {
+ //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
+ hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
+ st_DrvCan2.device.status.errcode = 0xff;
+ }
+ else
+ {
+ //can2
+ tmp_u32Errcount = st_DrvCan2.fdcanHandle.Instance->ECR;
+ tmp_u32status = st_DrvCan2.fdcanHandle.Instance->PSR;
+ st_DrvCan2.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
+ st_DrvCan2.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
+ st_DrvCan2.device.status.lasterrtype = tmp_u32status&0x000000007;
+ }
+#endif /*BSP_USING_FDCAN2*/
+ }
+}
+
+#ifdef BSP_USING_FDCAN1
+
+void FDCAN1_IT0_IRQHandler(void) /* FDCAN2 interrupt line 0 */
+{
+ rt_interrupt_enter();
+ HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
+ rt_interrupt_leave();
+}
+
+void FDCAN1_IT1_IRQHandler(void) /* FDCAN2 interrupt line 1 */
+{
+ rt_interrupt_enter();
+ HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
+ rt_interrupt_leave();
+}
+
+#endif /*BSP_USING_FDCAN1*/
+
+#ifdef BSP_USING_FDCAN2
+void FDCAN2_IT0_IRQHandler(void) /* FDCAN2 interrupt line 0 */
+{
+ rt_interrupt_enter();
+ HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
+ rt_interrupt_leave();
+}
+
+void FDCAN2_IT1_IRQHandler(void) /* FDCAN2 interrupt line 1 */
+{
+ rt_interrupt_enter();
+ HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
+ rt_interrupt_leave();
+}
+#endif/*BSP_USING_FDCAN2*/
+
+
+static int rt_hw_can_init(void)
+{
+ struct can_configure config;
+ config.baud_rate = CAN500kBaud;
+ config.msgboxsz = 30;
+ config.sndboxnumber = 1;
+ config.mode = RT_CAN_MODE_NORMAL;
+ config.privmode = RT_CAN_MODE_NOPRIV;
+ config.ticks = 50;
+ config.baud_rate_fd = BSP_FDCAN_BAUD_DATA_2M;
+ config.use_bit_timing = 0; // 不用config里面的timing
+
+#ifdef RT_CAN_USING_HDR
+ /* 这个成员不知道咋整，扩展过滤8个 ，普通的28个*/
+ config.maxhdr = 36;
+
+ /* 配置默认过滤器，标准id全放fifo1 */
+ FDCAN_FilterTypeDef sFilterConfig;
+ sFilterConfig.IdType = FDCAN_STANDARD_ID;
+ sFilterConfig.FilterIndex = 0;
+ sFilterConfig.FilterType = FDCAN_FILTER_MASK;
+ sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+ sFilterConfig.FilterID1 = 0;
+ sFilterConfig.FilterID2 = 0;
+#endif
+
+#ifdef BSP_USING_FDCAN1
+#if defined(BSP_FDCAN1_FRAME_CLASSIC)
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_CLASSIC;
+#elif defined(BSP_FDCAN1_FRAME_FD)
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS;
+#else
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_BRS;
+#endif
+
+#ifdef RT_CAN_USING_HDR
+ st_DrvCan1.FilterConfig = sFilterConfig;
+#endif
+
+ st_DrvCan1.name = "can1";
+ st_DrvCan1.fdcanHandle.Instance = FDCAN1;
+ st_DrvCan1.device.config = config;
+
+ /* register FDCAN1 device */
+ rt_hw_can_register(&st_DrvCan1.device, st_DrvCan1.name, &_can_ops, &st_DrvCan1);
+#endif /* BSP_USING_FDCAN1 */
+
+#ifdef BSP_USING_FDCAN2
+#if defined(BSP_FDCAN2_FRAME_CLASSIC)
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_CLASSIC;
+#elif defined(BSP_FDCAN2_FRAME_FD)
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS;
+#else
+ config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_BRS;
+#endif
+
+#ifdef RT_CAN_USING_HDR
+ st_DrvCan2.FilterConfig = sFilterConfig;
+#endif
+ st_DrvCan2.name = "can2";
+ st_DrvCan2.fdcanHandle.Instance = FDCAN2;
+ st_DrvCan2.device.config = config;
+
+ /* register FDCAN1 device */
+ rt_hw_can_register(&st_DrvCan2.device, st_DrvCan2.name, &_can_ops, &st_DrvCan2);
+#endif /* BSP_USING_FDCAN2 */
+
+ return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+#endif /* BSP_USING_FDCAN1 || BSP_USING_FDCAN2 */
+#endif /* RT_USING_CAN */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_gc0328c.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_gc0328c.c
new file mode 100644
index 00000000000..a45ed0e3fde
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_gc0328c.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-08-03 thread-liu the first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_GC0328C)
+
+#include
+#include
+#include
+#include
+
+#define DRV_DEBUG
+//#define CAMERA_DUMP
+#define LOG_TAG "drv.gc0328c"
+#include
+
+#define DEV_ADDRESS 0x21 /* gc0328c address */
+#define I2C_NAME "i2c2"
+
+volatile rt_uint32_t jpeg_data_len = 0;
+volatile rt_uint8_t jpeg_data_ok = 0;
+struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+#define JPEG_BUF_SIZE (320 * 240 *2)
+#define JPEG_LINE_SIZE (38400)
+#define RESET_PIN GET_PIN(A, 3)
+
+#define RGB565_RED 0xf800
+#define RGB565_GREEN 0x07e0
+#define RGB565_BLUE 0x001f
+
+typedef enum {
+ QVGA_320_240 = 0,
+ VGA_640_480,
+ PPI_MAX
+} PPI_TYPE; // Pixel per inch
+
+typedef enum {
+ TYPE_5FPS = 0,
+ TYPE_10FPS,
+ TYPE_20FPS,
+ FPS_MAX
+} FPS_TYPE; // frame per second
+
+static rt_uint8_t *jpeg_data_buf = RT_NULL;
+static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE];
+static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE];
+rt_uint8_t model_input_data_rgb[96*96*3];
+rt_uint8_t model_input_data_gray[96*96];
+//rt_uint32_t *JPEG_LINE0_BUF;
+//rt_uint32_t *JPEG_LINE1_BUF;
+extern struct drv_lcd_device _lcd;
+extern struct rt_event ov2640_event;
+
+#if defined(CAMERA_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+ unsigned char *buf = (unsigned char *)ptr;
+ int i, j;
+
+ for (i = 0; i < buflen; i += 16)
+ {
+ rt_kprintf("%08x:", i);
+
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < buflen)
+ {
+ rt_kprintf("%02x", buf[i + j]);
+ }
+ else
+ {
+ rt_kprintf(" ");
+ }
+ }
+ rt_kprintf(" ");
+
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < buflen)
+ {
+ rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+ }
+ }
+ rt_kprintf("\n");
+ }
+}
+#endif
+
+#define RANGE_LIMIT(x) (x > 255 ? 255 : (x < 0 ? 0 : x))
+
+/*
+* YUV422打包数据,UYVY,转换为RGB565,
+* inBuf -- YUV data
+* outBuf -- RGB565 data
+* imgWidth,imgHeight -- image width and height
+* cvtMethod -- 无效参数
+*/
+int convert_uyvy_to_rgb(unsigned char *inBuf, unsigned char *outBuf, int imgWidth, int imgHeight)
+{
+ int rows ,cols; /* 行列标志 */
+ int y, u, v, r, g, b; /* yuv rgb 相关分量 */
+ unsigned char *YUVdata, *RGBdata; /* YUV和RGB数据指针 */
+ int Ypos, Upos, Vpos; /* Y U V在数据缓存中的偏移 */
+ unsigned int i = 0;
+
+ YUVdata = inBuf;
+ RGBdata = outBuf;
+#if 1
+// /* YUYV */
+// Ypos = 0;
+// Upos = Ypos + 1;
+// Vpos = Upos + 2;
+
+ /* YVYU */
+ Ypos = 0;
+ Vpos = Ypos + 1;
+ Upos = Vpos + 2;
+#endif
+
+#if 0 /* UYVY */
+ Ypos = 1;
+ Upos = Ypos - 1;
+ Vpos = Ypos + 1;
+#endif
+
+ /* 每个像素两个字节 */
+ for(rows = 0; rows < imgHeight; rows++)
+ {
+ for(cols = 0; cols < imgWidth; cols++)
+ {
+ /* 矩阵推到，百度 */
+ y = YUVdata[Ypos];
+ u = YUVdata[Upos] - 128;
+ v = YUVdata[Vpos] - 128;
+
+ r = y + v + ((v * 103) >> 8);
+ g = y - ((u * 88) >> 8) - ((v * 183) >> 8);
+ b = y + u + ((u * 198) >> 8);
+
+ r = r > 255?255:(r < 0?0:r);
+ g = g > 255?255:(g < 0?0:g);
+ b = b > 255?255:(b < 0?0:b);
+
+ /* 从低到高r g b */
+ *(RGBdata ++) = (((g & 0x1c) << 3) | (b >> 3)); /* g低5位，b高5位 */
+ *(RGBdata ++) = ((r & 0xf8) | (g >> 5)); /* r高5位，g高3位 */
+
+ /* 两个字节数据中包含一个Y */
+ Ypos += 2;
+ //Ypos++;
+ i++;
+ /* 每两个Y更新一次UV */
+ if(!(i & 0x01))
+ {
+ Upos = Ypos - 1;
+ Vpos = Ypos + 1;
+ }
+
+ }
+ }
+
+ return 0;
+}
+
+static void rgb565_to_rgb888(rt_uint16_t *rgb565Color, rt_uint8_t *rgb888Color, int size)
+{
+ rt_uint16_t color;
+ rt_uint32_t i, n;
+
+ for (i=0, n=0; i> 11) <<3;
+ rgb888Color[n+1] = ((color & RGB565_GREEN) >> 5) <<2;
+ rgb888Color[n+2] = (color & RGB565_BLUE) <<3;
+ }
+}
+
+static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf)
+{
+ struct rt_i2c_msg msg[2];
+
+ RT_ASSERT(bus != RT_NULL);
+
+ msg[0].addr = DEV_ADDRESS;
+ msg[0].flags = RT_I2C_WR;
+ msg[0].buf = ®
+ msg[0].len = 1;
+
+ msg[1].addr = DEV_ADDRESS;
+ msg[1].flags = RT_I2C_RD;
+ msg[1].len = len;
+ msg[1].buf = buf;
+
+ if (rt_i2c_transfer(bus, msg, 2) == 2)
+ {
+ return RT_EOK;
+ }
+
+ return RT_ERROR;
+}
+
+/* i2c write reg */
+static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data)
+{
+ rt_uint8_t buf[2];
+ struct rt_i2c_msg msgs;
+
+ RT_ASSERT(bus != RT_NULL);
+
+ buf[0] = reg ;
+ buf[1] = data;
+
+ msgs.addr = DEV_ADDRESS;
+ msgs.flags = RT_I2C_WR;
+ msgs.buf = buf;
+ msgs.len = 2;
+
+ if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+ {
+ return RT_EOK;
+ }
+
+ return RT_ERROR;
+}
+
+static rt_err_t gc0328c_read_id(struct rt_i2c_bus_device *bus)
+{
+ rt_uint8_t id = 0;
+ read_reg(bus, 0xf0, 1, &id);
+
+ if (id != GC0328C_ID)
+ {
+ LOG_E("GC0328C init error, pid: 0x%04x", id);
+ return RT_ERROR;
+ }
+ LOG_I("GC0328C read hid success, pid: 0x%04x", id);
+
+ return RT_EOK;
+}
+
+static rt_err_t camera_inf_cfg_gc0328c_ppi(rt_uint8_t ppi_type)
+{
+ rt_err_t ret;
+ rt_uint32_t i, size = 0;
+ rt_uint8_t *addr, *data;
+
+ switch (ppi_type)
+ {
+ case QVGA_320_240:
+ size = sizeof(gc0328c_QVGA_320_240_talbe) / 2;
+ addr = &gc0328c_QVGA_320_240_talbe[0][0];
+ data = &gc0328c_QVGA_320_240_talbe[0][1];
+ break;
+ case VGA_640_480:
+ size = sizeof(gc0328c_VGA_640_480_talbe) / 2;
+ addr = &gc0328c_VGA_640_480_talbe[0][0];
+ data = &gc0328c_VGA_640_480_talbe[0][1];
+ break;
+ default:
+ LOG_E("set PPI unknown\r\n");
+ break;
+ }
+
+ for(i=0; iCR & (1<<19))
+// {
+// for (i = 0; i < JPEG_LINE_SIZE; i++)
+// {
+// pbuf[i] = JPEG_LINE0_BUF[i];
+// }
+// _lcd.lcd_info.framebuffer
+// jpeg_data_len += JPEG_LINE_SIZE;
+// }
+// else
+// {
+// for (i = 0; i < JPEG_LINE_SIZE; i++)
+// {
+// pbuf[i] = JPEG_LINE1_BUF[i];
+// }
+// jpeg_data_len += JPEG_LINE_SIZE;
+// }
+}
+
+/* After a frame of picture data has been collected. */
+void camera_frame_data_process(void)
+{
+ DCMI_Stop();
+ rt_uint32_t i , j , num = 0 , n = 0;
+ rt_uint8_t *pbuf;
+ rt_uint8_t *dbuf = _lcd.lcd_info.framebuffer;
+ rt_uint8_t w = 0 , h = 0;
+ rt_uint16_t color;
+
+ if (DMA2_Stream1->CR & (1<<19))
+ {
+ pbuf = (rt_uint8_t *)JPEG_LINE1_BUF;
+ }
+ else
+ {
+ pbuf = (rt_uint8_t *)JPEG_LINE0_BUF;
+ }
+ SCB_CleanInvalidateDCache();
+ //convert_uyvy_to_rgb(pbuf, jpeg_data_buf, 320, 240);
+ //pbuf = jpeg_data_buf;
+ for(i=0; i<240; i++)
+ {
+ //rt_memcpy(dbuf+ (i*320*2), pbuf + (i*320*2), 320*2);
+ rgb565_to_rgb888((rt_uint16_t *)(pbuf + (i*320*2)), dbuf+ (i*320*3), 320);
+ }
+ //convert to 96*96*3
+ for(j=0 ; j<240 ; j++)
+ {
+ if(h == 4)
+ {
+ h = 0;
+ continue;
+ }
+ if(h != 1 && h!= 3)
+ {
+ h = h + 1;
+ continue;
+ }
+ for(i=40 ; i<280 ; i++)
+ {
+ if(w == 4)
+ {
+ w = 0;
+ continue;
+ }
+ if(w != 1 && w != 3)
+ {
+ w = w + 1;
+ continue;
+ }
+ //96*96 rgb
+ model_input_data_rgb[num] = dbuf[j*320*3+i*3];
+ model_input_data_rgb[num+1] = dbuf[j*320*3+i*3+1];
+ model_input_data_rgb[num+2] = dbuf[j*320*3+i*3+2];
+ num = num + 3;
+
+ //96*96 gray
+ color = (rt_uint16_t *)(pbuf + (j*320*2) + i*2);
+ model_input_data_gray[n] = ((((color>>11)&0xff)<<3)*299+(((color>>5)&0x3f)<<2)*587+((color & 0x1f)<<2)*114+500)/1000;
+ n = n + 1;
+
+ w = w + 1;
+ }
+ h = h + 1;
+ }
+ rt_event_send(&ov2640_event, 1);
+}
+
+int rt_gc0328c_init(void)
+{
+ rt_uint16_t i = 0;
+ rt_err_t result = RT_EOK;
+ rt_device_t dcmi_dev = RT_NULL;
+
+ /* ov2640 reset */
+// rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
+// rt_pin_write(RESET_PIN, PIN_LOW);
+// rt_thread_delay(20);
+// rt_pin_write(RESET_PIN, PIN_HIGH);
+// rt_thread_delay(20);
+
+ i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
+ if (i2c_bus == RT_NULL)
+ {
+ LOG_E("can't find %s deivce", I2C_NAME);
+ return RT_ERROR;
+ }
+
+ result = gc0328c_read_id(i2c_bus);
+ if (result != RT_EOK)
+ {
+ LOG_E("gc0328c read id error!");
+ return RT_ERROR;
+ }
+
+ for (i = 0; i < sizeof(gc0328c_init_talbe) / 2; i++)
+ {
+ write_reg(i2c_bus, gc0328c_init_talbe[i][0], gc0328c_init_talbe[i][1]);
+ }
+
+ result = camera_inf_cfg_gc0328c_ppi(QVGA_320_240);
+ if(result != RT_EOK)
+ {
+ LOG_E("camera_inf_cfg_gc0328c_ppi iic err\n");
+ return RT_ERROR;
+ }
+
+ result = camera_inf_cfg_gc0328c_fps(TYPE_10FPS);
+ if(result != RT_EOK)
+ {
+ LOG_E("camera_inf_cfg_gc0328c_fps iic err\n");
+ return RT_ERROR;
+ }
+
+ dcmi_dev = rt_device_find("dcmi");
+ if (dcmi_dev == RT_NULL)
+ {
+ LOG_E("can't find dcmi device!");
+ return RT_ERROR;
+ }
+ rt_device_open(dcmi_dev, RT_DEVICE_FLAG_RDWR);
+
+// JPEG_LINE0_BUF = rt_malloc(JPEG_BUF_SIZE);
+// if (RT_NULL == JPEG_LINE0_BUF)
+// {
+// rt_kprintf("jpeg data buf0 malloc error!\n");
+// return RT_ERROR;
+// }
+//
+// JPEG_LINE1_BUF = rt_malloc(JPEG_BUF_SIZE);
+// if (RT_NULL == JPEG_LINE1_BUF)
+// {
+// rt_kprintf("jpeg data buf1 malloc error!\n");
+// return RT_ERROR;
+// }
+//
+ jpeg_data_buf = rt_malloc(JPEG_BUF_SIZE);
+ if (RT_NULL == jpeg_data_buf)
+ {
+ rt_kprintf("jpeg data buf2 malloc error!\n");
+ return RT_ERROR;
+ }
+ /* start dcmi capture */
+ rt_hw_dcmi_dma_config((rt_uint32_t)JPEG_LINE0_BUF, (rt_uint32_t)JPEG_LINE1_BUF, JPEG_LINE_SIZE);
+
+ rt_kprintf("camera init success!\n");
+ return RT_EOK;
+}
+//INIT_APP_EXPORT(rt_gc0328c_init);
+
+int camera_sample(int argc, char **argv)
+{
+ rt_err_t result = RT_EOK;
+
+ if (argc != 1)
+ {
+ rt_kprintf("Usage:\n");
+ rt_kprintf("camera_sample file.jpg\n");
+ return -1;
+ }
+ rt_gc0328c_init();
+ DCMI_Start();
+ return result;;
+}
+MSH_CMD_EXPORT(camera_sample, record picture to a jpg file);
+
+int read_camera(int argc, char **argv)
+{
+ rt_err_t result = RT_EOK;
+ rt_uint8_t data;
+ rt_uint8_t reg;
+
+ reg = atoi(argv[1]);
+ read_reg(i2c_bus, reg, 1, &data);
+
+ rt_kprintf("camera reg=0x%02x data=0x%02x\n", reg, data);
+ return result;
+}
+MSH_CMD_EXPORT(read_camera, record picture to a jpg file);
+
+int write_camera(int argc, char **argv)
+{
+ rt_err_t result = RT_EOK;
+ rt_uint8_t data;
+ rt_uint8_t reg;
+
+ reg = atoi(argv[1]);
+ data = atoi(argv[2]);
+ write_reg(i2c_bus, reg, data);
+
+ rt_kprintf("camera reg=0x%02x data=0x%02x\n", reg, data);
+ return result;
+}
+MSH_CMD_EXPORT(write_camera, record picture to a jpg file);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c
new file mode 100644
index 00000000000..704b106d202
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c
@@ -0,0 +1,829 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 balanceTWK first version
+ * 2019-04-23 WillianChan Fix GPIO serial number disorder
+ * 2020-06-16 thread-liu add STM32MP1
+ * 2020-09-01 thread-liu add GPIOZ
+ * 2020-09-18 geniusgogo optimization design pin-index algorithm
+ */
+
+#include
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_GPIO
+
+#define PIN_NUM(port, no) (((((port)&0xFu) << 4) | ((no)&0xFu)))
+#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO(pin) ((uint8_t)((pin)&0xFu))
+
+#if defined(SOC_SERIES_STM32MP1)
+#if defined(GPIOZ)
+#define gpioz_port_base (175) /* PIN_STPORT_MAX * 16 - 16 */
+#define PIN_STPORT(pin) ((pin > gpioz_port_base) ? ((GPIO_TypeDef *)(GPIOZ_BASE)) : ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin)))))
+#else
+#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin))))
+#endif /* GPIOZ */
+#else
+#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
+#endif /* SOC_SERIES_STM32MP1 */
+
+#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
+
+#if defined(GPIOZ)
+#define __STM32_PORT_MAX 16u
+#elif defined(GPIOP)
+#define __STM32_PORT_MAX 15u
+#elif defined(GPIOO)
+#define __STM32_PORT_MAX 14u
+#elif defined(GPION)
+#define __STM32_PORT_MAX 13u
+#elif defined(GPIOM)
+#define __STM32_PORT_MAX 12u
+#elif defined(GPIOK)
+#define __STM32_PORT_MAX 11u
+#elif defined(GPIOJ)
+#define __STM32_PORT_MAX 10u
+#elif defined(GPIOI)
+#define __STM32_PORT_MAX 9u
+#elif defined(GPIOH)
+#define __STM32_PORT_MAX 8u
+#elif defined(GPIOG)
+#define __STM32_PORT_MAX 7u
+#elif defined(GPIOF)
+#define __STM32_PORT_MAX 6u
+#elif defined(GPIOE)
+#define __STM32_PORT_MAX 5u
+#elif defined(GPIOD)
+#define __STM32_PORT_MAX 4u
+#elif defined(GPIOC)
+#define __STM32_PORT_MAX 3u
+#elif defined(GPIOB)
+#define __STM32_PORT_MAX 2u
+#elif defined(GPIOA)
+#define __STM32_PORT_MAX 1u
+#else
+#define __STM32_PORT_MAX 0u
+#error Unsupported STM32 GPIO peripheral.
+#endif
+
+#define PIN_STPORT_MAX __STM32_PORT_MAX
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0)
+ {GPIO_PIN_0, EXTI0_1_IRQn},
+ {GPIO_PIN_1, EXTI0_1_IRQn},
+ {GPIO_PIN_2, EXTI2_3_IRQn},
+ {GPIO_PIN_3, EXTI2_3_IRQn},
+ {GPIO_PIN_4, EXTI4_15_IRQn},
+ {GPIO_PIN_5, EXTI4_15_IRQn},
+ {GPIO_PIN_6, EXTI4_15_IRQn},
+ {GPIO_PIN_7, EXTI4_15_IRQn},
+ {GPIO_PIN_8, EXTI4_15_IRQn},
+ {GPIO_PIN_9, EXTI4_15_IRQn},
+ {GPIO_PIN_10, EXTI4_15_IRQn},
+ {GPIO_PIN_11, EXTI4_15_IRQn},
+ {GPIO_PIN_12, EXTI4_15_IRQn},
+ {GPIO_PIN_13, EXTI4_15_IRQn},
+ {GPIO_PIN_14, EXTI4_15_IRQn},
+ {GPIO_PIN_15, EXTI4_15_IRQn},
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) \
+ || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
+ {GPIO_PIN_0, EXTI0_IRQn},
+ {GPIO_PIN_1, EXTI1_IRQn},
+ {GPIO_PIN_2, EXTI2_IRQn},
+ {GPIO_PIN_3, EXTI3_IRQn},
+ {GPIO_PIN_4, EXTI4_IRQn},
+ {GPIO_PIN_5, EXTI5_IRQn},
+ {GPIO_PIN_6, EXTI6_IRQn},
+ {GPIO_PIN_7, EXTI7_IRQn},
+ {GPIO_PIN_8, EXTI8_IRQn},
+ {GPIO_PIN_9, EXTI9_IRQn},
+ {GPIO_PIN_10, EXTI10_IRQn},
+ {GPIO_PIN_11, EXTI11_IRQn},
+ {GPIO_PIN_12, EXTI12_IRQn},
+ {GPIO_PIN_13, EXTI13_IRQn},
+ {GPIO_PIN_14, EXTI14_IRQn},
+ {GPIO_PIN_15, EXTI15_IRQn},
+#elif defined(SOC_SERIES_STM32F3)
+ {GPIO_PIN_0, EXTI0_IRQn},
+ {GPIO_PIN_1, EXTI1_IRQn},
+ {GPIO_PIN_2, EXTI2_TSC_IRQn},
+ {GPIO_PIN_3, EXTI3_IRQn},
+ {GPIO_PIN_4, EXTI4_IRQn},
+ {GPIO_PIN_5, EXTI9_5_IRQn},
+ {GPIO_PIN_6, EXTI9_5_IRQn},
+ {GPIO_PIN_7, EXTI9_5_IRQn},
+ {GPIO_PIN_8, EXTI9_5_IRQn},
+ {GPIO_PIN_9, EXTI9_5_IRQn},
+ {GPIO_PIN_10, EXTI15_10_IRQn},
+ {GPIO_PIN_11, EXTI15_10_IRQn},
+ {GPIO_PIN_12, EXTI15_10_IRQn},
+ {GPIO_PIN_13, EXTI15_10_IRQn},
+ {GPIO_PIN_14, EXTI15_10_IRQn},
+ {GPIO_PIN_15, EXTI15_10_IRQn},
+#else
+ {GPIO_PIN_0, EXTI0_IRQn},
+ {GPIO_PIN_1, EXTI1_IRQn},
+ {GPIO_PIN_2, EXTI2_IRQn},
+ {GPIO_PIN_3, EXTI3_IRQn},
+ {GPIO_PIN_4, EXTI4_IRQn},
+ {GPIO_PIN_5, EXTI9_5_IRQn},
+ {GPIO_PIN_6, EXTI9_5_IRQn},
+ {GPIO_PIN_7, EXTI9_5_IRQn},
+ {GPIO_PIN_8, EXTI9_5_IRQn},
+ {GPIO_PIN_9, EXTI9_5_IRQn},
+ {GPIO_PIN_10, EXTI15_10_IRQn},
+ {GPIO_PIN_11, EXTI15_10_IRQn},
+ {GPIO_PIN_12, EXTI15_10_IRQn},
+ {GPIO_PIN_13, EXTI15_10_IRQn},
+ {GPIO_PIN_14, EXTI15_10_IRQn},
+ {GPIO_PIN_15, EXTI15_10_IRQn},
+#endif
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0]))
+
+/* e.g. PE.7 */
+static rt_base_t stm32_pin_get(const char *name)
+{
+ rt_base_t pin = 0;
+ int hw_port_num, hw_pin_num = 0;
+ int i, name_len;
+
+ name_len = rt_strlen(name);
+
+ if ((name_len < 4) || (name_len >= 6))
+ {
+ goto out;
+ }
+ if ((name[0] != 'P') || (name[2] != '.'))
+ {
+ goto out;
+ }
+
+ if ((name[1] >= 'A') && (name[1] <= 'Z'))
+ {
+ hw_port_num = (int)(name[1] - 'A');
+ }
+ else
+ {
+ goto out;
+ }
+
+ for (i = 3; i < name_len; i++)
+ {
+ hw_pin_num *= 10;
+ hw_pin_num += name[i] - '0';
+ }
+
+ pin = PIN_NUM(hw_port_num, hw_pin_num);
+
+ return pin;
+
+out:
+ rt_kprintf("Px.y x:A~Z y:0-15, e.g. PA.0\n");
+ return -RT_EINVAL;
+}
+
+static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+{
+ GPIO_TypeDef *gpio_port;
+ uint16_t gpio_pin;
+
+ if (PIN_PORT(pin) < PIN_STPORT_MAX)
+ {
+ gpio_port = PIN_STPORT(pin);
+ gpio_pin = PIN_STPIN(pin);
+
+ HAL_GPIO_WritePin(gpio_port, gpio_pin, (GPIO_PinState)value);
+ }
+}
+
+static rt_ssize_t stm32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+ GPIO_TypeDef *gpio_port;
+ uint16_t gpio_pin;
+ GPIO_PinState state = GPIO_PIN_RESET;
+
+ if (PIN_PORT(pin) < PIN_STPORT_MAX)
+ {
+ gpio_port = PIN_STPORT(pin);
+ gpio_pin = PIN_STPIN(pin);
+ state = HAL_GPIO_ReadPin(gpio_port, gpio_pin);
+ }
+ else
+ {
+ return -RT_EINVAL;
+ }
+
+ return (state == GPIO_PIN_RESET) ? PIN_LOW : PIN_HIGH;
+}
+
+static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+ {
+ return;
+ }
+
+ /* Configure GPIO_InitStructure */
+ GPIO_InitStruct.Pin = PIN_STPIN(pin);
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+
+ if (mode == PIN_MODE_OUTPUT)
+ {
+ /* output setting */
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ }
+ else if (mode == PIN_MODE_INPUT)
+ {
+ /* input setting: not pull. */
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ }
+ else if (mode == PIN_MODE_INPUT_PULLUP)
+ {
+ /* input setting: pull up. */
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ }
+ else if (mode == PIN_MODE_INPUT_PULLDOWN)
+ {
+ /* input setting: pull down. */
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ }
+ else if (mode == PIN_MODE_OUTPUT_OD)
+ {
+ /* output setting: od. */
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ }
+
+ HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+ rt_int32_t i;
+ for (i = 0; i < 32; i++)
+ {
+ if (((rt_uint32_t)0x01 << i) == bit)
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+ rt_int32_t mapindex = bit2bitno(pinbit);
+ if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
+ {
+ return RT_NULL;
+ }
+ return &pin_irq_map[mapindex];
+};
+
+static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+ rt_uint8_t mode, void (*hdr)(void *args), void *args)
+{
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+
+ if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+
+ irqindex = bit2bitno(PIN_STPIN(pin));
+ if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqindex].pin == pin &&
+ pin_irq_hdr_tab[irqindex].hdr == hdr &&
+ pin_irq_hdr_tab[irqindex].mode == mode &&
+ pin_irq_hdr_tab[irqindex].args == args)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+ if (pin_irq_hdr_tab[irqindex].pin != -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return -RT_EBUSY;
+ }
+ pin_irq_hdr_tab[irqindex].pin = pin;
+ pin_irq_hdr_tab[irqindex].hdr = hdr;
+ pin_irq_hdr_tab[irqindex].mode = mode;
+ pin_irq_hdr_tab[irqindex].args = args;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
+{
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+
+ if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+
+ irqindex = bit2bitno(PIN_STPIN(pin));
+ if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqindex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+ pin_irq_hdr_tab[irqindex].pin = -1;
+ pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+ pin_irq_hdr_tab[irqindex].mode = 0;
+ pin_irq_hdr_tab[irqindex].args = RT_NULL;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+ rt_uint8_t enabled)
+{
+ const struct pin_irq_map *irqmap;
+ rt_base_t level;
+ rt_int32_t irqindex = -1;
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+
+ if (enabled == PIN_IRQ_ENABLE)
+ {
+ irqindex = bit2bitno(PIN_STPIN(pin));
+ if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+
+ if (pin_irq_hdr_tab[irqindex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return -RT_ENOSYS;
+ }
+
+ irqmap = &pin_irq_map[irqindex];
+
+ /* Configure GPIO_InitStructure */
+ GPIO_InitStruct.Pin = PIN_STPIN(pin);
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ switch (pin_irq_hdr_tab[irqindex].mode)
+ {
+ case PIN_IRQ_MODE_RISING:
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ break;
+ case PIN_IRQ_MODE_FALLING:
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ break;
+ case PIN_IRQ_MODE_RISING_FALLING:
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
+ break;
+ }
+ HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
+
+ HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
+ HAL_NVIC_EnableIRQ(irqmap->irqno);
+ pin_irq_enable_mask |= irqmap->pinbit;
+
+ rt_hw_interrupt_enable(level);
+ }
+ else if (enabled == PIN_IRQ_DISABLE)
+ {
+ irqmap = get_pin_irq_map(PIN_STPIN(pin));
+ if (irqmap == RT_NULL)
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+
+ HAL_GPIO_DeInit(PIN_STPORT(pin), PIN_STPIN(pin));
+
+ pin_irq_enable_mask &= ~irqmap->pinbit;
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1))
+ {
+ if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1)))
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+ }
+ else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3))
+ {
+ if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3)))
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+ }
+ else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15))
+ {
+ if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
+ GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+ }
+ else
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+#else
+ if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
+ {
+ if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+ }
+ else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
+ {
+ if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+ }
+ else
+ {
+ HAL_NVIC_DisableIRQ(irqmap->irqno);
+ }
+#endif
+ rt_hw_interrupt_enable(level);
+ }
+ else
+ {
+ return -RT_ENOSYS;
+ }
+
+ return RT_EOK;
+}
+static const struct rt_pin_ops _stm32_pin_ops =
+{
+ stm32_pin_mode,
+ stm32_pin_write,
+ stm32_pin_read,
+ stm32_pin_attach_irq,
+ stm32_pin_dettach_irq,
+ stm32_pin_irq_enable,
+ stm32_pin_get,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+ if (pin_irq_hdr_tab[irqno].hdr)
+ {
+ pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+ }
+}
+
+#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5)
+void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+ pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+
+void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+ pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+#else
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+#endif
+
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32L0)
+void EXTI0_1_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
+ rt_interrupt_leave();
+}
+
+void EXTI2_3_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+ rt_interrupt_leave();
+}
+void EXTI4_15_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+ rt_interrupt_leave();
+}
+
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS)
+void EXTI0_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+ rt_interrupt_leave();
+}
+
+void EXTI1_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
+ rt_interrupt_leave();
+}
+
+void EXTI2_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+ rt_interrupt_leave();
+}
+
+void EXTI3_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+ rt_interrupt_leave();
+}
+
+void EXTI4_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
+ rt_interrupt_leave();
+}
+
+void EXTI5_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
+ rt_interrupt_leave();
+}
+
+void EXTI6_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
+ rt_interrupt_leave();
+}
+
+void EXTI7_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
+ rt_interrupt_leave();
+}
+
+void EXTI8_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+ rt_interrupt_leave();
+}
+
+void EXTI9_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
+ rt_interrupt_leave();
+}
+
+void EXTI10_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+ rt_interrupt_leave();
+}
+
+void EXTI11_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+ rt_interrupt_leave();
+}
+
+void EXTI12_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+ rt_interrupt_leave();
+}
+
+void EXTI13_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+ rt_interrupt_leave();
+}
+
+void EXTI14_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+ rt_interrupt_leave();
+}
+
+void EXTI15_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+ rt_interrupt_leave();
+}
+
+#else
+
+void EXTI0_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+ rt_interrupt_leave();
+}
+
+void EXTI1_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
+ rt_interrupt_leave();
+}
+
+void EXTI2_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+ rt_interrupt_leave();
+}
+
+void EXTI3_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+ rt_interrupt_leave();
+}
+
+void EXTI4_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
+ rt_interrupt_leave();
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
+ rt_interrupt_leave();
+}
+
+void EXTI15_10_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+ rt_interrupt_leave();
+}
+#endif
+
+int rt_hw_pin_init(void)
+{
+#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOB_CLK_ENABLE)
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOC_CLK_ENABLE)
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOD_CLK_ENABLE)
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOE_CLK_ENABLE)
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOF_CLK_ENABLE)
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOG_CLK_ENABLE)
+#ifdef SOC_SERIES_STM32L4
+ HAL_PWREx_EnableVddIO2();
+#endif
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOH_CLK_ENABLE)
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOI_CLK_ENABLE)
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE)
+ __HAL_RCC_GPIOJ_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOK_CLK_ENABLE)
+ __HAL_RCC_GPIOK_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOM_CLK_ENABLE)
+ __HAL_RCC_GPIOM_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPION_CLK_ENABLE)
+ __HAL_RCC_GPION_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOO_CLK_ENABLE)
+ __HAL_RCC_GPIOO_CLK_ENABLE();
+#endif
+
+#if defined(__HAL_RCC_GPIOP_CLK_ENABLE)
+ __HAL_RCC_GPIOP_CLK_ENABLE();
+#endif
+
+ return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
+}
+
+#endif /* BSP_USING_GPIO */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.h b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.h
new file mode 100644
index 00000000000..47989928566
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 balanceTWK first version
+ * 2020-06-16 thread-liu add stm32mp1
+ * 2020-09-01 thread-liu add GPIOZ
+ * 2020-09-18 geniusgogo optimization design pin-index algorithm
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __STM32_PORT(port) GPIO##port##_BASE
+
+#if defined(SOC_SERIES_STM32MP1)
+#define GET_PIN(PORTx,PIN) (GPIO##PORTx == GPIOZ) ? (176 + PIN) : ((rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN))
+#else
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+#endif
+
+struct pin_irq_map
+{
+ rt_uint16_t pinbit;
+ IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_hwtimer.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_hwtimer.c
new file mode 100644
index 00000000000..e66326442a6
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_hwtimer.c
@@ -0,0 +1,612 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-10 zylx first version
+ * 2020-06-16 thread-liu Porting for stm32mp1
+ * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
+ */
+
+#include
+#include
+#include
+
+#ifdef BSP_USING_TIM
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.hwtimer"
+#include
+
+#ifdef RT_USING_HWTIMER
+enum
+{
+#ifdef BSP_USING_TIM1
+ TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM2
+ TIM2_INDEX,
+#endif
+#ifdef BSP_USING_TIM3
+ TIM3_INDEX,
+#endif
+#ifdef BSP_USING_TIM4
+ TIM4_INDEX,
+#endif
+#ifdef BSP_USING_TIM5
+ TIM5_INDEX,
+#endif
+#ifdef BSP_USING_TIM6
+ TIM6_INDEX,
+#endif
+#ifdef BSP_USING_TIM7
+ TIM7_INDEX,
+#endif
+#ifdef BSP_USING_TIM8
+ TIM8_INDEX,
+#endif
+#ifdef BSP_USING_TIM9
+ TIM9_INDEX,
+#endif
+#ifdef BSP_USING_TIM10
+ TIM10_INDEX,
+#endif
+#ifdef BSP_USING_TIM11
+ TIM11_INDEX,
+#endif
+#ifdef BSP_USING_TIM12
+ TIM12_INDEX,
+#endif
+#ifdef BSP_USING_TIM13
+ TIM13_INDEX,
+#endif
+#ifdef BSP_USING_TIM14
+ TIM14_INDEX,
+#endif
+#ifdef BSP_USING_TIM15
+ TIM15_INDEX,
+#endif
+#ifdef BSP_USING_TIM16
+ TIM16_INDEX,
+#endif
+#ifdef BSP_USING_TIM17
+ TIM17_INDEX,
+#endif
+};
+
+struct stm32_hwtimer
+{
+ rt_hwtimer_t time_device;
+ TIM_HandleTypeDef tim_handle;
+ IRQn_Type tim_irqn;
+ char *name;
+};
+
+static struct stm32_hwtimer stm32_hwtimer_obj[] =
+{
+#ifdef BSP_USING_TIM1
+ TIM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM2
+ TIM2_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM3
+ TIM3_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM4
+ TIM4_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM5
+ TIM5_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM6
+ TIM6_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM7
+ TIM7_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM8
+ TIM8_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM9
+ TIM9_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM10
+ TIM10_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM11
+ TIM11_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM12
+ TIM12_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM13
+ TIM13_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM14
+ TIM14_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM15
+ TIM15_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM16
+ TIM16_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM17
+ TIM17_CONFIG,
+#endif
+};
+
+/* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
+static void pclkx_doubler_get(uint32_t *pclk1_doubler, uint32_t *pclk2_doubler)
+{
+ uint32_t flatency = 0;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ RT_ASSERT(pclk1_doubler != RT_NULL);
+ RT_ASSERT(pclk1_doubler != RT_NULL);
+
+ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
+
+ *pclk1_doubler = 1;
+ *pclk2_doubler = 1;
+
+#if defined(SOC_SERIES_STM32MP1)
+ if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
+ {
+ *pclk1_doubler = 2;
+ }
+ if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
+ {
+ *pclk2_doubler = 2;
+ }
+#elif defined(SOC_SERIES_STM32H7)
+ if (RCC_ClkInitStruct.APB1CLKDivider != RCC_APB1_DIV1)
+ {
+ *pclk1_doubler = 2;
+ }
+ if (RCC_ClkInitStruct.APB2CLKDivider != RCC_APB2_DIV1)
+ {
+ *pclk2_doubler = 2;
+ }
+#else
+ if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
+ {
+ *pclk1_doubler = 2;
+ }
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
+ if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
+ {
+ *pclk2_doubler = 2;
+ }
+#endif
+#endif
+}
+
+static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
+{
+ uint32_t prescaler_value = 0;
+ uint32_t pclk1_doubler, pclk2_doubler;
+ TIM_HandleTypeDef *tim = RT_NULL;
+ struct stm32_hwtimer *tim_device = RT_NULL;
+
+ RT_ASSERT(timer != RT_NULL);
+ if (state)
+ {
+ tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+ tim_device = (struct stm32_hwtimer *)timer;
+
+ pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
+
+ /* time init */
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+ if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32MP1)
+ if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32H7)
+ if (tim->Instance == TIM13 || tim->Instance == TIM14)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ if (0)
+#endif
+ {
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7)
+ prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
+#endif
+ }
+ else
+ {
+ prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
+ }
+ tim->Init.Period = 10000 - 1;
+ tim->Init.Prescaler = prescaler_value;
+ tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
+ {
+ tim->Init.CounterMode = TIM_COUNTERMODE_UP;
+ }
+ else
+ {
+ tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
+ }
+ tim->Init.RepetitionCounter = 0;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || \
+ defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+ tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+ if (HAL_TIM_Base_Init(tim) != HAL_OK)
+ {
+ LOG_E("%s init failed", tim_device->name);
+ return;
+ }
+ else
+ {
+ /* set the TIMx priority */
+ HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
+
+ /* enable the TIMx global Interrupt */
+ HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
+
+ /* clear update flag */
+ __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
+ /* enable update request source */
+ __HAL_TIM_URS_ENABLE(tim);
+
+ LOG_D("%s init success", tim_device->name);
+ }
+ }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+ rt_err_t result = RT_EOK;
+ TIM_HandleTypeDef *tim = RT_NULL;
+
+ RT_ASSERT(timer != RT_NULL);
+
+ tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+ /* set tim cnt */
+ __HAL_TIM_SET_COUNTER(tim, 0);
+ /* set tim arr */
+ __HAL_TIM_SET_AUTORELOAD(tim, t - 1);
+
+ if (opmode == HWTIMER_MODE_ONESHOT)
+ {
+ /* set timer to single mode */
+ tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
+ }
+ else
+ {
+ tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
+ }
+
+ /* start timer */
+ if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
+ {
+ LOG_E("TIM start failed");
+ result = -RT_ERROR;
+ }
+
+ return result;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+ TIM_HandleTypeDef *tim = RT_NULL;
+
+ RT_ASSERT(timer != RT_NULL);
+
+ tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+ /* stop timer */
+ HAL_TIM_Base_Stop_IT(tim);
+
+ /* set tim cnt */
+ __HAL_TIM_SET_COUNTER(tim, 0);
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+ TIM_HandleTypeDef *tim = RT_NULL;
+ rt_err_t result = RT_EOK;
+ uint32_t pclk1_doubler, pclk2_doubler;
+
+ RT_ASSERT(timer != RT_NULL);
+ RT_ASSERT(arg != RT_NULL);
+
+ tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+ switch (cmd)
+ {
+ case HWTIMER_CTRL_FREQ_SET:
+ {
+ rt_uint32_t freq;
+ rt_uint16_t val;
+
+ /* set timer frequence */
+ freq = *((rt_uint32_t *)arg);
+
+ pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+ if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32MP1)
+ if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32H7)
+ if (tim->Instance == TIM13 || tim->Instance == TIM14)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ if (0)
+#endif
+ {
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
+ val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
+#endif
+ }
+ else
+ {
+ val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
+ }
+ __HAL_TIM_SET_PRESCALER(tim, val - 1);
+
+ /* Update frequency value */
+ tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
+ }
+ break;
+ default:
+ {
+ result = -RT_ENOSYS;
+ }
+ break;
+ }
+
+ return result;
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+ TIM_HandleTypeDef *tim = RT_NULL;
+
+ RT_ASSERT(timer != RT_NULL);
+
+ tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+ return tim->Instance->CNT;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static const struct rt_hwtimer_ops _ops =
+{
+ .init = timer_init,
+ .start = timer_start,
+ .stop = timer_stop,
+ .count_get = timer_counter_get,
+ .control = timer_ctrl,
+};
+
+#ifdef BSP_USING_TIM2
+void TIM2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM3
+void TIM3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM4
+void TIM4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM5
+void TIM5_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM11
+void TIM1_TRG_COM_TIM11_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM13
+void TIM8_UP_TIM13_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM14
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ void TIM8_TRG_COM_TIM14_IRQHandler(void)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+ void TIM14_IRQHandler(void)
+#endif
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM15
+void TIM1_BRK_TIM15_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM16
+#if defined(SOC_SERIES_STM32L4)
+ void TIM1_UP_TIM16_IRQHandler(void)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
+ void TIM16_IRQHandler(void)
+#endif
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM17
+#if defined(SOC_SERIES_STM32L4)
+ void TIM1_TRG_COM_TIM17_IRQHandler(void)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
+ void TIM17_IRQHandler(void)
+#endif
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+#ifdef BSP_USING_TIM2
+ if (htim->Instance == TIM2)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM3
+ if (htim->Instance == TIM3)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM4
+ if (htim->Instance == TIM4)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM5
+ if (htim->Instance == TIM5)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM11
+ if (htim->Instance == TIM11)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM13
+ if (htim->Instance == TIM13)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM14
+ if (htim->Instance == TIM14)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM15
+ if (htim->Instance == TIM15)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM16
+ if (htim->Instance == TIM16)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
+ }
+#endif
+#ifdef BSP_USING_TIM17
+ if (htim->Instance == TIM17)
+ {
+ rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
+ }
+#endif
+}
+
+static int stm32_hwtimer_init(void)
+{
+ int i = 0;
+ int result = RT_EOK;
+
+ for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
+ {
+ stm32_hwtimer_obj[i].time_device.info = &_info;
+ stm32_hwtimer_obj[i].time_device.ops = &_ops;
+ if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
+ {
+ LOG_D("%s register success", stm32_hwtimer_obj[i].name);
+ }
+ else
+ {
+ LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
+ result = -RT_ERROR;
+ }
+ }
+
+ return result;
+}
+INIT_BOARD_EXPORT(stm32_hwtimer_init);
+
+#endif /* RT_USING_HWTIMER */
+#endif /* BSP_USING_TIM */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_lcd.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_lcd.c
new file mode 100644
index 00000000000..b42e187bebb
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_lcd.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-01-08 zylx first version
+ */
+
+#include
+
+#ifdef BSP_USING_LCD
+#include
+#include
+#include
+
+#if !defined(RT_USING_MEMHEAP_AS_HEAP)
+ #error "Please define RT_USING_MEMHEAP_AS_HEAP"
+#endif
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.lcd"
+#include
+
+#define LCD_DEVICE(dev) (struct drv_lcd_device*)(dev)
+
+LTDC_HandleTypeDef hltdc = {0};
+
+struct drv_lcd_device _lcd;
+
+static rt_err_t drv_lcd_init(struct rt_device *device)
+{
+ struct drv_lcd_device *lcd = LCD_DEVICE(device);
+ /* nothing, right now */
+ lcd = lcd;
+ return RT_EOK;
+}
+
+static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args)
+{
+ struct drv_lcd_device *lcd = LCD_DEVICE(device);
+
+ switch (cmd)
+ {
+ case RTGRAPHIC_CTRL_RECT_UPDATE:
+ {
+ /* update */
+ if (_lcd.cur_buf)
+ {
+ /* back_buf is being used */
+ memcpy(_lcd.front_buf, _lcd.lcd_info.framebuffer, LCD_BUF_SIZE);
+ /* Configure the color frame buffer start address */
+ LTDC_LAYER(&hltdc, 0)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+ LTDC_LAYER(&hltdc, 0)->CFBAR = (uint32_t)(_lcd.front_buf);
+ _lcd.cur_buf = 0;
+ }
+ else
+ {
+ /* front_buf is being used */
+ memcpy(_lcd.back_buf, _lcd.lcd_info.framebuffer, LCD_BUF_SIZE);
+ /* Configure the color frame buffer start address */
+ LTDC_LAYER(&hltdc, 0)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+ LTDC_LAYER(&hltdc, 0)->CFBAR = (uint32_t)(_lcd.back_buf);
+ _lcd.cur_buf = 1;
+ }
+ rt_sem_take(&_lcd.lcd_lock, RT_TICK_PER_SECOND / 20);
+ HAL_LTDC_Relaod(&hltdc, LTDC_SRCR_VBR);
+ }
+ break;
+
+ case RTGRAPHIC_CTRL_GET_INFO:
+ {
+ struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args;
+
+ RT_ASSERT(info != RT_NULL);
+ info->pixel_format = lcd->lcd_info.pixel_format;
+ info->bits_per_pixel = 16;
+ info->width = lcd->lcd_info.width;
+ info->height = lcd->lcd_info.height;
+ info->framebuffer = lcd->lcd_info.framebuffer;
+ }
+ break;
+
+ default:
+ return -RT_EINVAL;
+ }
+
+ return RT_EOK;
+}
+
+void LTDC_IRQHandler(void)
+{
+ rt_interrupt_enter();
+
+ HAL_LTDC_IRQHandler(&hltdc);
+
+ rt_interrupt_leave();
+}
+
+rt_err_t stm32_lcd_init(struct drv_lcd_device *lcd)
+{
+ LTDC_LayerCfgTypeDef pLayerCfg = {0};
+
+ /* LTDC Initialization -------------------------------------------------------*/
+
+ /* Polarity configuration */
+ /* Initialize the horizontal synchronization polarity as active low */
+ hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
+ /* Initialize the vertical synchronization polarity as active low */
+ hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
+ /* Initialize the data enable polarity as active low */
+ hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
+ /* Initialize the pixel clock polarity as input pixel clock */
+ hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
+
+ /* Timing configuration */
+ /* Horizontal synchronization width = Hsync - 1 */
+ hltdc.Init.HorizontalSync = LCD_HSYNC_WIDTH - 1;
+ /* Vertical synchronization height = Vsync - 1 */
+ hltdc.Init.VerticalSync = LCD_VSYNC_HEIGHT - 1;
+ /* Accumulated horizontal back porch = Hsync + HBP - 1 */
+ hltdc.Init.AccumulatedHBP = LCD_HSYNC_WIDTH + LCD_HBP - 1;
+ /* Accumulated vertical back porch = Vsync + VBP - 1 */
+ hltdc.Init.AccumulatedVBP = LCD_VSYNC_HEIGHT + LCD_VBP - 1;
+ /* Accumulated active width = Hsync + HBP + Active Width - 1 */
+ hltdc.Init.AccumulatedActiveW = LCD_HSYNC_WIDTH + LCD_HBP + lcd->lcd_info.width - 1 ;
+ /* Accumulated active height = Vsync + VBP + Active Heigh - 1 */
+ hltdc.Init.AccumulatedActiveH = LCD_VSYNC_HEIGHT + LCD_VBP + lcd->lcd_info.height - 1;
+ /* Total height = Vsync + VBP + Active Heigh + VFP - 1 */
+ hltdc.Init.TotalHeigh = hltdc.Init.AccumulatedActiveH + LCD_VFP;
+ /* Total width = Hsync + HBP + Active Width + HFP - 1 */
+ hltdc.Init.TotalWidth = hltdc.Init.AccumulatedActiveW + LCD_HFP;
+
+ /* Configure R,G,B component values for LCD background color */
+ hltdc.Init.Backcolor.Blue = 0;
+ hltdc.Init.Backcolor.Green = 0;
+ hltdc.Init.Backcolor.Red = 0;
+
+ hltdc.Instance = LTDC;
+
+ /* Layer1 Configuration ------------------------------------------------------*/
+
+ /* Windowing configuration */
+ pLayerCfg.WindowX0 = 0;
+ pLayerCfg.WindowX1 = lcd->lcd_info.width;
+ pLayerCfg.WindowY0 = 0;
+ pLayerCfg.WindowY1 = lcd->lcd_info.height;
+
+ /* Pixel Format configuration*/
+ if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565)
+ {
+ pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
+ }
+ else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888)
+ {
+ pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
+ }
+ else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB888)
+ {
+ pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888;
+ }
+ else
+ {
+ LOG_E("unsupported pixel format");
+ return -RT_ERROR;
+ }
+
+ /* Start Address configuration : frame buffer is located at FLASH memory */
+ pLayerCfg.FBStartAdress = (uint32_t)lcd->front_buf;
+
+ /* Alpha constant (255 totally opaque) */
+ pLayerCfg.Alpha = 255;
+
+ /* Default Color configuration (configure A,R,G,B component values) */
+ pLayerCfg.Alpha0 = 0;
+ pLayerCfg.Backcolor.Blue = 0;
+ pLayerCfg.Backcolor.Green = 0;
+ pLayerCfg.Backcolor.Red = 0;
+
+ /* Configure blending factors */
+ /* Constant Alpha value: pLayerCfg.Alpha / 255
+ C: Current Layer Color
+ Cs: Background color
+ BC = Constant Alpha x C + (1 - Constant Alpha ) x Cs */
+ /* BlendingFactor1: Pixel Alpha x Constant Alpha */
+ pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
+ /* BlendingFactor2: 1 - (Pixel Alpha x Constant Alpha) */
+ pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
+
+ /* Configure the number of lines and number of pixels per line */
+ pLayerCfg.ImageWidth = lcd->lcd_info.width;
+ pLayerCfg.ImageHeight = lcd->lcd_info.height;
+
+ /* Configure the LTDC */
+ if (HAL_LTDC_Init(&hltdc) != HAL_OK)
+ {
+ LOG_E("LTDC init failed");
+ return -RT_ERROR;
+ }
+
+ /* Configure the Background Layer*/
+ if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
+ {
+ LOG_E("LTDC layer init failed");
+ return -RT_ERROR;
+ }
+ else
+ {
+ /* enable LTDC interrupt */
+ HAL_NVIC_SetPriority(LTDC_IRQn, 1, 0);
+ HAL_NVIC_EnableIRQ(LTDC_IRQn);
+ LOG_D("LTDC init success");
+ return RT_EOK;
+ }
+}
+
+#if defined(LCD_BACKLIGHT_USING_PWM)
+void turn_on_lcd_backlight(void)
+{
+ struct rt_device_pwm *pwm_dev;
+
+ /* turn on the LCD backlight */
+ pwm_dev = (struct rt_device_pwm *)rt_device_find(LCD_PWM_DEV_NAME);
+ /* pwm frequency:100K = 10000ns */
+ rt_pwm_set(pwm_dev, LCD_PWM_DEV_CHANNEL, 10000, 10000);
+ rt_pwm_enable(pwm_dev, LCD_PWM_DEV_CHANNEL);
+}
+#elif defined(LCD_BACKLIGHT_USING_GPIO)
+void turn_on_lcd_backlight(void)
+{
+ rt_pin_mode(LCD_BL_GPIO_NUM, PIN_MODE_OUTPUT);
+ rt_pin_write(LCD_BL_GPIO_NUM, PIN_HIGH);
+}
+#else
+#error "No screen backlight enabled!"
+#endif
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops lcd_ops =
+{
+ drv_lcd_init,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ drv_lcd_control
+};
+#endif
+
+int drv_lcd_hw_init(void)
+{
+ rt_err_t result = RT_EOK;
+ struct rt_device *device = &_lcd.parent;
+
+ /* memset _lcd to zero */
+ memset(&_lcd, 0x00, sizeof(_lcd));
+
+ /* init lcd_lock semaphore */
+ result = rt_sem_init(&_lcd.lcd_lock, "lcd_lock", 0, RT_IPC_FLAG_FIFO);
+ if (result != RT_EOK)
+ {
+ LOG_E("init semaphore failed!\n");
+ result = -RT_ENOMEM;
+ goto __exit;
+ }
+
+ /* config LCD dev info */
+ _lcd.lcd_info.height = LCD_HEIGHT;
+ _lcd.lcd_info.width = LCD_WIDTH;
+ _lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
+ _lcd.lcd_info.pixel_format = LCD_PIXEL_FORMAT;
+
+ /* malloc memory for Triple Buffering */
+ _lcd.front_buf = _lcd.lcd_info.framebuffer = rt_malloc_align(LCD_BUF_SIZE, 32);
+ _lcd.back_buf = rt_malloc_align(LCD_BUF_SIZE, LCD_BUF_SIZE);
+ _lcd.front_buf = rt_malloc_align(LCD_BUF_SIZE, LCD_BUF_SIZE);
+ if (_lcd.lcd_info.framebuffer == RT_NULL || _lcd.back_buf == RT_NULL || _lcd.front_buf == RT_NULL)
+ {
+ LOG_E("init frame buffer failed!\n");
+ result = -RT_ENOMEM;
+ goto __exit;
+ }
+ /* memset buff to 0xFF */
+ memset(_lcd.lcd_info.framebuffer, 0xFF, LCD_BUF_SIZE);
+ memset(_lcd.back_buf, 0xFF, LCD_BUF_SIZE);
+ memset(_lcd.front_buf, 0xFF, LCD_BUF_SIZE);
+
+ rt_kprintf("_lcd.framebuffer:%#x\n", _lcd.lcd_info.framebuffer);
+ rt_kprintf("_lcd.back_buf:%#x\n", _lcd.back_buf);
+ rt_kprintf("_lcd.front_buf:%#x\n", _lcd.front_buf);
+
+ device->type = RT_Device_Class_Graphic;
+#ifdef RT_USING_DEVICE_OPS
+ device->ops = &lcd_ops;
+#else
+ device->init = drv_lcd_init;
+ device->control = drv_lcd_control;
+#endif
+
+ /* register lcd device */
+ rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR);
+
+ /* init stm32 LTDC */
+ if (stm32_lcd_init(&_lcd) != RT_EOK)
+ {
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ else
+ {
+ turn_on_lcd_backlight();
+ }
+
+__exit:
+ if (result != RT_EOK)
+ {
+ rt_sem_delete(&_lcd.lcd_lock);
+
+ if (_lcd.lcd_info.framebuffer)
+ {
+ rt_free(_lcd.lcd_info.framebuffer);
+ }
+
+ if (_lcd.back_buf)
+ {
+ rt_free(_lcd.back_buf);
+ }
+
+ if (_lcd.front_buf)
+ {
+ rt_free(_lcd.front_buf);
+ }
+ }
+ return result;
+}
+INIT_DEVICE_EXPORT(drv_lcd_hw_init);
+
+#ifdef DRV_DEBUG
+#ifdef FINSH_USING_MSH
+int lcd_test()
+{
+ struct drv_lcd_device *lcd;
+ lcd = (struct drv_lcd_device *)rt_device_find("lcd");
+
+ while (1)
+ {
+ if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565)
+ {
+ /* red */
+ for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
+ {
+ lcd->lcd_info.framebuffer[2 * i] = 0x00;
+ lcd->lcd_info.framebuffer[2 * i + 1] = 0xF8;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+ rt_thread_mdelay(1000);
+ /* green */
+ for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
+ {
+ lcd->lcd_info.framebuffer[2 * i] = 0xE0;
+ lcd->lcd_info.framebuffer[2 * i + 1] = 0x07;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+ rt_thread_mdelay(1000);
+ /* blue */
+ for (int i = 0; i < LCD_BUF_SIZE / 2; i++)
+ {
+ lcd->lcd_info.framebuffer[2 * i] = 0x1F;
+ lcd->lcd_info.framebuffer[2 * i + 1] = 0x00;
+ }
+ }
+ else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB888)
+ {
+ /* red */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0xff;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+ rt_thread_mdelay(1000);
+ /* green */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0xff;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0x00;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+ rt_thread_mdelay(1000);
+ /* blue */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0xff;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0x00;
+ }
+ }
+
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+ rt_thread_mdelay(1000);
+ }
+}
+MSH_CMD_EXPORT(lcd_test, lcd_test);
+#endif /* DRV_DEBUG */
+#endif /* BSP_USING_LCD */
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_lptim.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_lptim.c
new file mode 100644
index 00000000000..ff2c9c24d39
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_lptim.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-05-06 Zero-Free first version
+ */
+
+#ifdef RT_USING_PM
+
+#include
+#include
+
+static LPTIM_HandleTypeDef LptimHandle;
+
+void LPTIM1_IRQHandler(void)
+{
+ HAL_LPTIM_IRQHandler(&LptimHandle);
+}
+
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function get current count value of LPTIM
+ *
+ * @return the count vlaue
+ */
+rt_uint32_t stm32h7_lptim_get_current_tick(void)
+{
+ return HAL_LPTIM_ReadCounter(&LptimHandle);
+}
+
+/**
+ * This function get the max value that LPTIM can count
+ *
+ * @return the max count
+ */
+rt_uint32_t stm32h7_lptim_get_tick_max(void)
+{
+ return (0xFFFF);
+}
+
+/**
+ * This function start LPTIM with reload value
+ *
+ * @param reload The value that LPTIM count down from
+ *
+ * @return RT_EOK
+ */
+rt_err_t stm32h7_lptim_start(rt_uint32_t reload)
+{
+ HAL_LPTIM_TimeOut_Start_IT(&LptimHandle, 0xFFFF, reload);
+
+ return (RT_EOK);
+}
+
+/**
+ * This function stop LPTIM
+ */
+void stm32h7_lptim_stop(void)
+{
+ rt_uint32_t _ier;
+
+ _ier = LptimHandle.Instance->IER;
+ LptimHandle.Instance->ICR = LptimHandle.Instance->ISR & _ier;
+}
+
+/**
+ * This function get the count clock of LPTIM
+ *
+ * @return the count clock frequency in Hz
+ */
+rt_uint32_t stm32h7_lptim_get_countfreq(void)
+{
+ return 32000 / 32;
+}
+
+/**
+ * This function initialize the lptim
+ */
+int stm32h7_hw_lptim_init(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
+
+ /* Enable LSI clock */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ /* Select the LSI clock as LPTIM peripheral clock */
+ RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
+ RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
+ HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+
+ LptimHandle.Instance = LPTIM1;
+ LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
+ LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV32;
+ LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
+ LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
+ LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
+ LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
+ if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK)
+ {
+ return -1;
+ }
+
+ NVIC_ClearPendingIRQ(LPTIM1_IRQn);
+ NVIC_SetPriority(LPTIM1_IRQn, 0);
+ NVIC_EnableIRQ(LPTIM1_IRQn);
+
+ return 0;
+}
+
+INIT_DEVICE_EXPORT(stm32h7_hw_lptim_init);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_ov2640.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_ov2640.c
new file mode 100644
index 00000000000..1cf9f9d1cb4
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_ov2640.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-08-03 thread-liu the first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_OV2640)
+
+#include
+#include
+#include
+
+#define DRV_DEBUG
+//#define CAMERA_DUMP
+#define LOG_TAG "drv.ov2640"
+#include
+
+#define DEV_ADDRESS 0x30 /* OV2640 address */
+#define I2C_NAME "i2c2"
+
+volatile rt_uint32_t jpeg_data_len = 0;
+volatile rt_uint8_t jpeg_data_ok = 0;
+struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+#define JPEG_BUF_SIZE 32 * 1024
+#define JPEG_LINE_SIZE 1 * 1024
+
+#define RESET_PIN GET_PIN(A, 3)
+
+static rt_uint32_t *jpeg_data_buf = RT_NULL;
+static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE * 2];
+static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE * 2];
+
+#if defined(CAMERA_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+ unsigned char *buf = (unsigned char *)ptr;
+ int i, j;
+
+ for (i = 0; i < buflen; i += 16)
+ {
+ rt_kprintf("%08x:", i);
+
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < buflen)
+ {
+ rt_kprintf("%02x", buf[i + j]);
+ }
+ else
+ {
+ rt_kprintf(" ");
+ }
+ }
+ rt_kprintf(" ");
+
+ for (j = 0; j < 16; j++)
+ {
+ if (i + j < buflen)
+ {
+ rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+ }
+ }
+ rt_kprintf("\n");
+ }
+}
+#endif
+
+static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf)
+{
+ struct rt_i2c_msg msg[2];
+
+ RT_ASSERT(bus != RT_NULL);
+
+ msg[0].addr = DEV_ADDRESS;
+ msg[0].flags = RT_I2C_WR;
+ msg[0].buf = ®
+ msg[0].len = 2;
+
+ msg[1].addr = DEV_ADDRESS;
+ msg[1].flags = RT_I2C_RD;
+ msg[1].len = len;
+ msg[1].buf = buf;
+
+ if (rt_i2c_transfer(bus, msg, 2) == 2)
+ {
+ return RT_EOK;
+ }
+
+ return RT_ERROR;
+}
+
+/* i2c write reg */
+static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t data)
+{
+ rt_uint8_t buf[2];
+ struct rt_i2c_msg msgs;
+
+ RT_ASSERT(bus != RT_NULL);
+
+ buf[0] = reg ;
+ buf[1] = data;
+
+ msgs.addr = DEV_ADDRESS;
+ msgs.flags = RT_I2C_WR;
+ msgs.buf = buf;
+ msgs.len = 2;
+
+ if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+ {
+ return RT_EOK;
+ }
+
+ return RT_ERROR;
+}
+
+static rt_err_t ov2640_read_id(struct rt_i2c_bus_device *bus)
+{
+ rt_uint8_t read_value[2];
+ rt_uint16_t id = 0;
+ read_reg(bus, OV2640_SENSOR_MIDH, 1, &read_value[0]);
+ read_reg(bus, OV2640_SENSOR_MIDL, 1, &read_value[1]);
+ id = ((rt_uint16_t)(read_value[0] << 8) & 0xFF00);
+ id |= ((rt_uint16_t)(read_value[1]) & 0x00FF);
+
+ if (id != OV2640_MID)
+ {
+ LOG_E("ov2640 init error, mid: 0x%04x", id);
+ return RT_ERROR;
+ }
+
+ LOG_I("ov2640 read mid success, mid: 0x%04x", id);
+
+ read_reg(bus, OV2640_SENSOR_PIDH, 1, &read_value[0]);
+ read_reg(bus, OV2640_SENSOR_PIDL, 1, &read_value[1]);
+ id = ((rt_uint16_t)(read_value[0] << 8) & 0xFF00);
+ id |= ((rt_uint16_t)(read_value[1]) & 0x00FF);
+
+ if (id != OV2640_PID)
+ {
+ LOG_E("ov2640 init error, pid: 0x%04x", id);
+ return RT_ERROR;
+ }
+
+ LOG_I("ov2640 read hid success, pid: 0x%04x", id);
+
+ return RT_EOK;
+}
+
+/* change ov2640 to jpeg mode */
+void ov2640_jpeg_mode(void)
+{
+ rt_uint16_t i=0;
+ /* set yun422 mode */
+ for (i = 0; i < (sizeof(ov2640_yuv422_reg_tbl) / 2); i++)
+ {
+ write_reg(i2c_bus, ov2640_yuv422_reg_tbl[i][0],ov2640_yuv422_reg_tbl[i][1]);
+ }
+
+ /* set jpeg mode */
+ for(i=0;i<(sizeof(ov2640_jpeg_reg_tbl)/2);i++)
+ {
+ write_reg(i2c_bus, ov2640_jpeg_reg_tbl[i][0],ov2640_jpeg_reg_tbl[i][1]);
+ }
+}
+
+/* change ov2640 to rgb565 mode */
+void ov2640_rgb565_mode(void)
+{
+ rt_uint16_t i=0;
+ for (i = 0; i < (sizeof(ov2640_rgb565_reg_tbl) / 2); i++)
+ {
+ write_reg(i2c_bus, ov2640_rgb565_reg_tbl[i][0],ov2640_rgb565_reg_tbl[i][1]);
+ }
+}
+
+/* set auto exposure */
+void ov2640_set_auto_exposure(rt_uint8_t level)
+{
+ rt_uint8_t i = 0;
+ rt_uint8_t *p = (rt_uint8_t*)OV2640_AUTOEXPOSURE_LEVEL[level];
+ for (i = 0; i < 4; i++)
+ {
+ write_reg(i2c_bus, p[i*2],p[i*2+1]);
+ }
+}
+
+/* set light mode
+ * 0: auto
+ * 1: sunny
+ * 2: cloudy
+ * 3: office
+ * 4: home
+ * */
+void ov2640_set_light_mode(rt_uint8_t mode)
+{
+ rt_uint8_t regccval, regcdval, regceval;
+
+ switch(mode)
+ {
+ case 0:
+ write_reg(i2c_bus, 0xFF, 0x00);
+ write_reg(i2c_bus, 0xC7, 0x10);
+ return;
+
+ case 2:
+ regccval = 0x65;
+ regcdval = 0x41;
+ regceval = 0x4F;
+ break;
+
+ case 3:
+ regccval = 0x52;
+ regcdval = 0x41;
+ regceval = 0x66;
+ break;
+
+ case 4:
+ regccval = 0x42;
+ regcdval = 0x3F;
+ regceval = 0x71;
+ break;
+
+ default:
+ regccval = 0x5E;
+ regcdval = 0x41;
+ regceval = 0x54;
+ break;
+ }
+
+ write_reg(i2c_bus, 0xFF, 0x00);
+ write_reg(i2c_bus, 0xC7, 0x40);
+ write_reg(i2c_bus, 0xCC, regccval);
+ write_reg(i2c_bus, 0xCD, regcdval);
+ write_reg(i2c_bus, 0xCE, regceval);
+}
+
+/* set color saturation
+ * 0: -2
+ * 1: -1
+ * 2: 0
+ * 3: +1
+ * 4: +2
+ * */
+void ov2640_set_color_saturation(rt_uint8_t sat)
+{
+ rt_uint8_t reg7dval = ((sat+2)<<4) | 0x08;
+ write_reg(i2c_bus, 0xFF, 0X00);
+ write_reg(i2c_bus, 0x7C, 0X00);
+ write_reg(i2c_bus, 0x7D, 0X02);
+ write_reg(i2c_bus, 0x7C, 0X03);
+ write_reg(i2c_bus, 0x7D, reg7dval);
+ write_reg(i2c_bus, 0x7D, reg7dval);
+}
+
+/* set brightness
+ * 0: -2
+ * 1: -1
+ * 2: 0
+ * 3: 1
+ * 4: 2
+ * */
+void ov2640_set_brightness(rt_uint8_t bright)
+{
+ write_reg(i2c_bus, 0xff, 0x00);
+ write_reg(i2c_bus, 0x7c, 0x00);
+ write_reg(i2c_bus, 0x7d, 0x04);
+ write_reg(i2c_bus, 0x7c, 0x09);
+ write_reg(i2c_bus, 0x7d, bright << 4);
+ write_reg(i2c_bus, 0x7d, 0x00);
+}
+
+/* set contrast
+ * 0: -2
+ * 1: -1
+ * 2: 0
+ * 3: 1
+ * 4: 2
+ * */
+void ov2640_set_contrast(rt_uint8_t contrast)
+{
+ rt_uint8_t reg7d0val, reg7d1val;
+
+ switch(contrast)
+ {
+ case 0:
+ reg7d0val = 0x18;
+ reg7d1val = 0x34;
+ break;
+
+ case 1:
+ reg7d0val = 0x1C;
+ reg7d1val = 0x2A;
+ break;
+
+ case 3:
+ reg7d0val = 0x24;
+ reg7d1val = 0x16;
+ break;
+
+ case 4:
+ reg7d0val = 0x28;
+ reg7d1val = 0x0C;
+ break;
+
+ default:
+ reg7d0val = 0x20;
+ reg7d1val = 0x20;
+ break;
+ }
+ write_reg(i2c_bus, 0xff, 0x00);
+ write_reg(i2c_bus, 0x7c, 0x00);
+ write_reg(i2c_bus, 0x7d, 0x04);
+ write_reg(i2c_bus, 0x7c, 0x07);
+ write_reg(i2c_bus, 0x7d, 0x20);
+ write_reg(i2c_bus, 0x7d, reg7d0val);
+ write_reg(i2c_bus, 0x7d, reg7d1val);
+ write_reg(i2c_bus, 0x7d, 0x06);
+}
+
+/* set special effects
+ * 0: noraml
+ * 1: negative film
+ * 2: black-and-white
+ * 3: the red
+ * 4: the green
+ * 5: the blue
+ * 6: Retro
+*/
+void ov2640_set_special_effects(rt_uint8_t eft)
+{
+ rt_uint8_t reg7d0val, reg7d1val, reg7d2val;
+
+ switch(eft)
+ {
+ case 1:
+ reg7d0val = 0x40;
+ break;
+ case 2:
+ reg7d0val = 0x18;
+ break;
+ case 3:
+ reg7d0val = 0x18;
+ reg7d1val = 0x40;
+ reg7d2val = 0xC0;
+ break;
+ case 4:
+ reg7d0val = 0x18;
+ reg7d1val = 0x40;
+ reg7d2val = 0x40;
+ break;
+ case 5:
+ reg7d0val = 0x18;
+ reg7d1val = 0xA0;
+ reg7d2val = 0x40;
+ break;
+ case 6:
+ reg7d0val = 0x18;
+ reg7d1val = 0x40;
+ reg7d2val = 0xA6;
+ break;
+ default:
+ reg7d0val = 0x00;
+ reg7d1val = 0x80;
+ reg7d2val = 0x80;
+ break;
+ }
+ write_reg(i2c_bus, 0xff, 0x00);
+ write_reg(i2c_bus, 0x7c, 0x00);
+ write_reg(i2c_bus, 0x7d, reg7d0val);
+ write_reg(i2c_bus, 0x7c, 0x05);
+ write_reg(i2c_bus, 0x7d, reg7d1val);
+ write_reg(i2c_bus, 0x7d, reg7d2val);
+}
+
+/* set the image output window */
+void ov2640_set_window_size(rt_uint16_t sx,rt_uint16_t sy,rt_uint16_t width,rt_uint16_t height)
+{
+ rt_uint16_t endx;
+ rt_uint16_t endy;
+ rt_uint8_t temp;
+ endx = sx + width / 2;
+ endy = sy + height / 2;
+
+ write_reg(i2c_bus, 0xFF, 0x01);
+ read_reg(i2c_bus, 0x03, 1, &temp);
+ temp &= 0xF0;
+ temp |= ((endy & 0x03) << 2) | (sy & 0x03);
+ write_reg(i2c_bus, 0x03, temp);
+ write_reg(i2c_bus, 0x19, sy>>2);
+ write_reg(i2c_bus, 0x1A, endy>>2);
+
+ read_reg(i2c_bus, 0x32, 1, &temp);
+ temp &= 0xC0;
+ temp |= ((endx & 0x07) << 3) | (sx & 0x07);
+ write_reg(i2c_bus, 0x32, temp);
+ write_reg(i2c_bus, 0x17, sx>>3);
+ write_reg(i2c_bus, 0x18, endx>>3);
+}
+
+/* set the image output size */
+rt_uint8_t ov2640_set_image_out_size(rt_uint16_t width,rt_uint16_t height)
+{
+ rt_uint16_t outh, outw;
+ rt_uint8_t temp;
+
+ if(width%4)return 1;
+ if(height%4)return 2;
+ outw = width / 4;
+ outh = height / 4;
+ write_reg(i2c_bus, 0xFF, 0x00);
+ write_reg(i2c_bus, 0xE0, 0x04);
+ write_reg(i2c_bus, 0x5A, outw & 0XFF);
+ write_reg(i2c_bus, 0x5B, outh & 0XFF);
+ temp = (outw >> 8) & 0x03;
+ temp |= (outh >> 6) & 0x04;
+ write_reg(i2c_bus, 0x5C, temp);
+ write_reg(i2c_bus, 0xE0, 0X00);
+
+ return RT_EOK;
+}
+
+/* set the image window size */
+rt_uint8_t ov2640_set_image_window_size(rt_uint16_t offx, rt_uint16_t offy, rt_uint16_t width, rt_uint16_t height)
+{
+ rt_uint16_t hsize, vsize;
+ rt_uint8_t temp;
+ if ((width % 4) || (height%4))
+ {
+ return RT_ERROR;
+ }
+ hsize = width / 4;
+ vsize = height / 4;
+ write_reg(i2c_bus, 0XFF,0X00);
+ write_reg(i2c_bus, 0XE0,0X04);
+ write_reg(i2c_bus, 0X51,hsize&0XFF);
+ write_reg(i2c_bus, 0X52,vsize&0XFF);
+ write_reg(i2c_bus, 0X53,offx&0XFF);
+ write_reg(i2c_bus, 0X54,offy&0XFF);
+ temp=(vsize>>1)&0X80;
+ temp|=(offy>>4)&0X70;
+ temp|=(hsize>>5)&0X08;
+ temp|=(offx>>8)&0X07;
+ write_reg(i2c_bus, 0X55,temp);
+ write_reg(i2c_bus, 0X57,(hsize>>2)&0X80);
+ write_reg(i2c_bus, 0XE0,0X00);
+ return 0;
+}
+
+/* set output resolution */
+rt_uint8_t ov2640_set_image_size(rt_uint16_t width ,rt_uint16_t height)
+{
+ rt_uint8_t temp;
+ write_reg(i2c_bus, 0xFF, 0x00);
+ write_reg(i2c_bus, 0xE0, 0x04);
+ write_reg(i2c_bus, 0xC0, (width >>3) & 0xFF);
+ write_reg(i2c_bus, 0xC1, (height >> 3) & 0xFF);
+ temp = (width & 0x07) << 3;
+ temp |= height & 0x07;
+ temp |= (width >> 4) & 0x80;
+ write_reg(i2c_bus, 0x8C, temp);
+ write_reg(i2c_bus, 0xE0, 0x00);
+
+ return RT_EOK;
+}
+
+void camera_dma_data_process(void)
+{
+ rt_uint16_t i;
+ rt_uint32_t *pbuf;
+ pbuf = jpeg_data_buf + jpeg_data_len;
+
+ if (DMA2_Stream1->CR & (1<<19))
+ {
+ for (i = 0; i < JPEG_LINE_SIZE; i++)
+ {
+ pbuf[i] = JPEG_LINE0_BUF[i];
+ }
+ jpeg_data_len += JPEG_LINE_SIZE;
+ }
+ else
+ {
+ for (i = 0; i < JPEG_LINE_SIZE; i++)
+ {
+ pbuf[i] = JPEG_LINE1_BUF[i];
+ }
+ jpeg_data_len += JPEG_LINE_SIZE;
+ }
+ SCB_CleanInvalidateDCache();
+}
+
+/* After a frame of picture data has been collected. */
+void camera_frame_data_process(void)
+{
+ rt_uint16_t i, rlen;
+ rt_uint32_t *pbuf = RT_NULL;
+
+ if (jpeg_data_ok == 0)
+ {
+ __HAL_DMA_DISABLE(&hdma_dcmi);
+ while(DMA2_Stream1->CR & 0x01);
+
+ rlen = JPEG_LINE_SIZE - __HAL_DMA_GET_COUNTER(&hdma_dcmi);
+ pbuf = jpeg_data_buf + jpeg_data_len;
+
+ if (DMA2_Stream1->CR & (1<<19))
+ {
+ for (i = 0; i < rlen; i++)
+ {
+ pbuf[i] = JPEG_LINE1_BUF[i];
+ }
+ }
+ else
+ {
+ for (i = 0; i < rlen; i++)
+ {
+ pbuf[i] = JPEG_LINE0_BUF[i];
+ }
+ }
+ jpeg_data_len += rlen;
+ jpeg_data_ok = 1;
+ }
+ if (jpeg_data_ok==2)
+ {
+ DMA2_Stream1->NDTR = JPEG_LINE_SIZE;
+ DMA2_Stream1->CR |= 1<<0;
+ jpeg_data_ok = 0;
+ jpeg_data_len = 0;
+ }
+}
+
+int rt_ov2640_init(void)
+{
+ rt_uint16_t i = 0;
+ rt_err_t result = RT_EOK;
+ rt_device_t dcmi_dev = RT_NULL;
+
+ /* ov2640 reset */
+ rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
+ rt_pin_write(RESET_PIN, PIN_LOW);
+ rt_thread_delay(20);
+ rt_pin_write(RESET_PIN, PIN_HIGH);
+ rt_thread_delay(20);
+
+ i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
+ if (i2c_bus == RT_NULL)
+ {
+ LOG_E("can't find %s deivce", I2C_NAME);
+ return RT_ERROR;
+ }
+ /* Prepare the camera to be configured */
+ result = write_reg(i2c_bus, OV2640_DSP_RA_DLMT, 0x01);
+ if (result != RT_EOK )
+ {
+ LOG_E("ov2640 write reg error!");
+ return RT_ERROR;
+ }
+ rt_thread_delay(10);
+ result = write_reg(i2c_bus, OV2640_SENSOR_COM7, 0x80);
+ if (result != RT_EOK)
+ {
+ LOG_E("ov2640 soft reset error!");
+ return RT_ERROR;
+ }
+ rt_thread_delay(200);
+
+ result = ov2640_read_id(i2c_bus);
+ if (result != RT_EOK )
+ {
+ LOG_E("ov2640 read id error!");
+ return RT_ERROR;
+ }
+
+ for (i = 0; i < sizeof(ov2640_svga_init_reg_tbl) / 2; i++)
+ {
+ write_reg(i2c_bus, ov2640_svga_init_reg_tbl[i][0], ov2640_svga_init_reg_tbl[i][1]);
+ }
+
+ ov2640_rgb565_mode();
+ ov2640_set_light_mode(0);
+ ov2640_set_color_saturation(3);
+ ov2640_set_brightness(4);
+ ov2640_set_contrast(3);
+ ov2640_jpeg_mode();
+ ov2640_set_image_window_size(0, 0, 320, 240);
+ ov2640_set_image_out_size(320, 240);
+
+ dcmi_dev = rt_device_find("dcmi");
+ if (dcmi_dev == RT_NULL)
+ {
+ LOG_E("can't find dcmi device!");
+ return RT_ERROR;
+ }
+ rt_device_open(dcmi_dev, RT_DEVICE_FLAG_RDWR);
+
+ jpeg_data_buf = rt_malloc(JPEG_BUF_SIZE);
+ if (RT_NULL == jpeg_data_buf)
+ {
+ rt_kprintf("jpeg data buf malloc error!\n");
+ return RT_ERROR;
+ }
+
+ /* start dcmi capture */
+ rt_hw_dcmi_dma_config((rt_uint32_t)JPEG_LINE0_BUF, (rt_uint32_t)JPEG_LINE1_BUF, JPEG_LINE_SIZE);
+
+ rt_kprintf("camera init success!\n");
+
+ return RT_EOK;
+}
+INIT_APP_EXPORT(rt_ov2640_init);
+
+int camera_sample(int argc, char **argv)
+{
+ rt_err_t result = RT_EOK;
+ int fd = -1;
+ rt_uint32_t i, jpg_start, jpg_len;
+ rt_uint8_t jpg_head = 0;
+ rt_uint8_t *p = RT_NULL;
+
+ if (argc != 2)
+ {
+ rt_kprintf("Usage:\n");
+ rt_kprintf("camera_sample file.jpg\n");
+ return -1;
+ }
+
+ DCMI_Start();
+
+ while (1)
+ {
+ while (jpeg_data_ok != 1);
+ jpeg_data_ok = 2;
+ while (jpeg_data_ok != 1);
+ DCMI_Stop();
+
+ p = (rt_uint8_t *)jpeg_data_buf;
+ jpg_len = 0;
+ jpg_head = 0;
+ for (i = 0; i < jpeg_data_len * 4; i++)
+ {
+ /* jpg head */
+ if ((p[i] == 0xFF) && (p[i + 1] == 0xD8))
+ {
+ jpg_start = i;
+ jpg_head = 1;
+ }
+ /* jpg end */
+ if ((p[i] == 0xFF) && (p[i + 1] == 0xD9) && jpg_head)
+ {
+ jpg_len = i - jpg_start + 2; /* a picture len */
+ break;
+ }
+ }
+ if (jpg_len)
+ {
+ p += jpg_start;
+ fd = open(argv[1], O_WRONLY | O_CREAT);
+ if (fd < 0)
+ {
+ rt_kprintf("open file for recording failed!\n");
+ result = -RT_ERROR;
+ goto _exit;
+ }
+ else
+ {
+ write(fd, p, jpg_len);
+ close(fd);
+ rt_kprintf("%s picture capture complate!\n", argv[1]);
+ break;
+ }
+ }
+ else
+ {
+ rt_kprintf("jpg_len error!\n");
+ result = -RT_ERROR;
+ goto _exit;
+ }
+ }
+
+_exit:
+ return result;
+}
+MSH_CMD_EXPORT(camera_sample, record picture to a jpg file);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_pm.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_pm.c
new file mode 100644
index 00000000000..67a9b3348f3
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_pm.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-05-06 Zero-Free first version
+ */
+
+#ifdef RT_USING_PM
+
+#include
+#include
+#include
+
+static void uart_console_reconfig(void)
+{
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+ rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
+}
+
+/**
+ * This function will put STM32L4xx into sleep mode.
+ *
+ * @param pm pointer to power manage structure
+ */
+static void sleep(struct rt_pm *pm, uint8_t mode)
+{
+ switch (mode)
+ {
+ case PM_SLEEP_MODE_NONE:
+ break;
+
+ case PM_SLEEP_MODE_IDLE:
+ // __WFI();
+ break;
+
+ case PM_SLEEP_MODE_LIGHT:
+ if (pm->run_mode == PM_RUN_MODE_LOW_SPEED)
+ {
+ /* Enter LP SLEEP Mode, Enable low-power regulator */
+ HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+ }
+ else
+ {
+ /* Enter SLEEP Mode, Main regulator is ON */
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+ }
+ break;
+
+ case PM_SLEEP_MODE_DEEP:
+ /* Enter STOP mode */
+ HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON,PWR_STOPENTRY_WFI);
+ /* Re-configure the system clock */
+ SystemClock_ReConfig(pm->run_mode);
+ break;
+
+ case PM_SLEEP_MODE_STANDBY:
+ /* Enter STANDBY mode */
+ HAL_PWR_EnterSTANDBYMode();
+ break;
+
+// case PM_SLEEP_MODE_SHUTDOWN:
+// /* Enter SHUTDOWNN mode */
+// HAL_PWREx_EnterSHUTDOWNMode();
+// break;
+
+ default:
+ RT_ASSERT(0);
+ break;
+ }
+}
+
+static uint8_t run_speed[PM_RUN_MODE_MAX][2] =
+{
+ {80, 0},
+ {80, 1},
+ {24, 2},
+ {2, 3},
+};
+
+static void run(struct rt_pm *pm, uint8_t mode)
+{
+ static uint8_t last_mode;
+ static char *run_str[] = PM_RUN_MODE_NAMES;
+
+ if (mode == last_mode)
+ return;
+ last_mode = mode;
+
+ switch (mode)
+ {
+ case PM_RUN_MODE_HIGH_SPEED:
+ HAL_RCC_DeInit();
+// SystemClock_480M();
+ /* Configure the main internal regulator output voltage (Range1 by default)*/
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ break;
+ case PM_RUN_MODE_NORMAL_SPEED:
+ HAL_RCC_DeInit();
+// SystemClock_240M();
+ /* Configure the main internal regulator output voltage (Range1 by default)*/
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ break;
+ case PM_RUN_MODE_MEDIUM_SPEED:
+ HAL_RCC_DeInit();
+// SystemClock_120M();
+ /* Configure the main internal regulator output voltage */
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ break;
+ case PM_RUN_MODE_LOW_SPEED:
+ HAL_RCC_DeInit();
+// SystemClock_60M();
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+ /* Enter LP RUN mode */
+ break;
+ default:
+ break;
+ }
+
+ uart_console_reconfig();
+ /* Re-Configure the Systick time */
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
+ /* Re-Configure the Systick */
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+ rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]);
+}
+
+/**
+ * This function caculate the PM tick from OS tick
+ *
+ * @param tick OS tick
+ *
+ * @return the PM tick
+ */
+static rt_tick_t stm32h7_pm_tick_from_os_tick(rt_tick_t tick)
+{
+ rt_uint32_t freq = stm32h7_lptim_get_countfreq();
+
+ return (freq * tick / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This function caculate the OS tick from PM tick
+ *
+ * @param tick PM tick
+ *
+ * @return the OS tick
+ */
+static rt_tick_t stm32h7_os_tick_from_pm_tick(rt_uint32_t tick)
+{
+ static rt_uint32_t os_tick_remain = 0;
+ rt_uint32_t ret, freq;
+
+ freq = stm32h7_lptim_get_countfreq();
+ ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq;
+
+ os_tick_remain += (tick * RT_TICK_PER_SECOND);
+ os_tick_remain %= freq;
+
+ return ret;
+}
+
+/**
+ * This function start the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ * @param timeout How many OS Ticks that MCU can sleep
+ */
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+ RT_ASSERT(pm != RT_NULL);
+ RT_ASSERT(timeout > 0);
+
+ if (timeout != RT_TICK_MAX)
+ {
+ /* Convert OS Tick to pmtimer timeout value */
+ timeout = stm32h7_pm_tick_from_os_tick(timeout);
+ if (timeout > stm32h7_lptim_get_tick_max())
+ {
+ timeout = stm32h7_lptim_get_tick_max();
+ }
+
+ /* Enter PM_TIMER_MODE */
+ stm32h7_lptim_start(timeout);
+ }
+}
+
+/**
+ * This function stop the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ */
+static void pm_timer_stop(struct rt_pm *pm)
+{
+ RT_ASSERT(pm != RT_NULL);
+
+ /* Reset pmtimer status */
+ stm32h7_lptim_stop();
+}
+
+/**
+ * This function calculate how many OS Ticks that MCU have suspended
+ *
+ * @param pm Pointer to power manage structure
+ *
+ * @return OS Ticks
+ */
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm)
+{
+ rt_uint32_t timer_tick;
+
+ RT_ASSERT(pm != RT_NULL);
+
+ timer_tick = stm32h7_lptim_get_current_tick();
+
+ return stm32h7_os_tick_from_pm_tick(timer_tick);
+}
+
+/**
+ * This function initialize the power manager
+ */
+int drv_pm_hw_init(void)
+{
+ static const struct rt_pm_ops _ops =
+ {
+ sleep,
+ run,
+ pm_timer_start,
+ pm_timer_stop,
+ pm_timer_get_tick
+ };
+
+ rt_uint8_t timer_mask = 0;
+
+ /* Enable Power Clock */
+// __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* initialize timer mask */
+ timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
+
+ /* initialize system pm module */
+ rt_system_pm_init(&_ops, timer_mask, RT_NULL);
+
+ return 0;
+}
+
+INIT_BOARD_EXPORT(drv_pm_hw_init);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c
new file mode 100644
index 00000000000..a8a369dd17b
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-01-24 yuanjie first version
+ */
+
+#include
+#include
+
+#ifdef BSP_USING_PSRAM
+#include
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.psram"
+#include
+
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+struct rt_memheap system_heap;
+#endif
+
+static int PSRAM_Init(void)
+{
+ LOG_D("hyperram init success, mapped at 0x%X, size is %d bytes, data width is %d", PSRAM_BANK_ADDR, PSRAM_SIZE, PSRAM_DATA_WIDTH);
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+ /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
+ rt_memheap_init(&system_heap, "hyperram", (void *)PSRAM_BANK_ADDR, PSRAM_SIZE);
+#endif
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(PSRAM_Init);
+
+// #ifdef DRV_DEBUG
+#if (defined(FINSH_USING_MSH) && defined(BSP_USING_PSRAM_TEST))
+int psram_test(void)
+{
+ int i = 0;
+ uint32_t start_time = 0, time_cast = 0;
+#if PSRAM_DATA_WIDTH == 8
+ char data_width = 1;
+ uint8_t data = 0;
+#elif PSRAM_DATA_WIDTH == 16
+ char data_width = 2;
+ uint16_t data = 0;
+#else
+ char data_width = 4;
+ uint32_t data = 0;
+#endif
+
+ /* write data */
+ LOG_D("Writing the %ld bytes data, waiting....", PSRAM_SIZE);
+ start_time = rt_tick_get();
+ for (i = 0; i < PSRAM_SIZE / data_width; i++)
+ {
+#if PSRAM_DATA_WIDTH == 8
+ *(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint8_t)0x5A;
+#elif PSRAM_DATA_WIDTH == 16
+ *(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5AA5;
+#else
+ *(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint32_t)0x5AA55AA5;
+#endif
+ }
+ time_cast = rt_tick_get() - start_time;
+ LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
+ time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
+
+ /* read data */
+ LOG_D("start Reading and verifying data, waiting....");
+ for (i = 0; i < PSRAM_SIZE / data_width; i++)
+ {
+#if PSRAM_DATA_WIDTH == 8
+ data = *(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width);
+ if (data != 0x5A)
+ {
+ LOG_E("PSRAM test failed!");
+ break;
+ }
+#elif PSRAM_DATA_WIDTH == 16
+ data = *(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width);
+ if (data != 0x5AA5)
+ {
+ LOG_E("PSRAM test failed!");
+ break;
+ }
+#else
+ data = *(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width);
+ if (data != 0x5AA55AA5)
+ {
+ LOG_E("PSRAM test failed!");
+ break;
+ }
+#endif
+ }
+
+ if (i >= PSRAM_SIZE / data_width)
+ {
+ LOG_D("PSRAM test success!");
+ }
+
+ return RT_EOK;
+}
+MSH_CMD_EXPORT(psram_test, psram test)
+#endif /* FINSH_USING_MSH */
+#endif /* BSP_USING_PSRAM */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_pwm.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_pwm.c
new file mode 100644
index 00000000000..2fa3adbf6f2
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_pwm.c
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-13 zylx first version
+ */
+
+#include
+#include
+#include
+
+#ifdef RT_USING_PWM
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.pwm"
+#include
+
+#define MAX_PERIOD 65535
+#define MIN_PERIOD 3
+#define MIN_PULSE 2
+
+extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+enum
+{
+#ifdef BSP_USING_PWM1
+ PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+ PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+ PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+ PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+ PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+ PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+ PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+ PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+ PWM9_INDEX,
+#endif
+#ifdef BSP_USING_PWM10
+ PWM10_INDEX,
+#endif
+#ifdef BSP_USING_PWM11
+ PWM11_INDEX,
+#endif
+#ifdef BSP_USING_PWM12
+ PWM12_INDEX,
+#endif
+#ifdef BSP_USING_PWM13
+ PWM13_INDEX,
+#endif
+#ifdef BSP_USING_PWM14
+ PWM14_INDEX,
+#endif
+#ifdef BSP_USING_PWM15
+ PWM15_INDEX,
+#endif
+#ifdef BSP_USING_PWM16
+ PWM16_INDEX,
+#endif
+#ifdef BSP_USING_PWM17
+ PWM17_INDEX,
+#endif
+};
+
+struct stm32_pwm
+{
+ struct rt_device_pwm pwm_device;
+ TIM_HandleTypeDef tim_handle;
+ rt_uint8_t channel;
+ char *name;
+};
+
+static struct stm32_pwm stm32_pwm_obj[] =
+{
+#ifdef BSP_USING_PWM1
+ PWM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM2
+ PWM2_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM3
+ PWM3_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM4
+ PWM4_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM5
+ PWM5_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM6
+ PWM6_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM7
+ PWM7_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM8
+ PWM8_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM9
+ PWM9_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM10
+ PWM10_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM11
+ PWM11_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM12
+ PWM12_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM13
+ PWM13_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM14
+ PWM14_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM15
+ PWM15_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM16
+ PWM16_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM17
+ PWM17_CONFIG,
+#endif
+};
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+static struct rt_pwm_ops drv_ops =
+{
+ drv_pwm_control
+};
+
+static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+ /* Converts the channel number to the channel number of Hal library */
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+
+ if (!enable)
+ {
+ HAL_TIM_PWM_Stop(htim, channel);
+ }
+ else
+ {
+ HAL_TIM_PWM_Start(htim, channel);
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
+{
+ /* Converts the channel number to the channel number of Hal library */
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+ rt_uint64_t tim_clock;
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+ if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ if (0)
+#elif defined(SOC_SERIES_STM32H7)
+ if (htim->Instance == TIM5)
+#endif
+ {
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
+ tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
+#endif
+ }
+ else
+ {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ tim_clock = HAL_RCC_GetPCLK1Freq();
+#else
+ tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
+#endif
+ }
+
+ if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
+ {
+ tim_clock = tim_clock / 2;
+ }
+ else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
+ {
+ tim_clock = tim_clock / 4;
+ }
+
+ /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+ tim_clock /= 1000000UL;
+ configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
+ configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
+
+ return RT_EOK;
+}
+
+static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
+{
+ rt_uint32_t period, pulse;
+ rt_uint64_t tim_clock, psc;
+ /* Converts the channel number to the channel number of Hal library */
+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+ if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ if (0)
+#elif defined(SOC_SERIES_STM32H7)
+ if (htim->Instance == TIM5)
+#endif
+ {
+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
+ tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
+#endif
+ }
+ else
+ {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ tim_clock = HAL_RCC_GetPCLK1Freq();
+#else
+ tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
+#endif
+ }
+
+ /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+ tim_clock /= 1000000UL;
+ period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
+ psc = period / MAX_PERIOD + 1;
+ period = period / psc;
+ __HAL_TIM_SET_PRESCALER(htim, psc - 1);
+
+ if (period < MIN_PERIOD)
+ {
+ period = MIN_PERIOD;
+ }
+ __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
+
+ pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
+ if (pulse < MIN_PULSE)
+ {
+ pulse = MIN_PULSE;
+ }
+ else if (pulse > period)
+ {
+ pulse = period;
+ }
+ __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
+ __HAL_TIM_SET_COUNTER(htim, 0);
+
+ /* Update frequency value */
+ HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE);
+
+ return RT_EOK;
+}
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+ struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
+
+ switch (cmd)
+ {
+ case PWM_CMD_ENABLE:
+ return drv_pwm_enable(htim, configuration, RT_TRUE);
+ case PWM_CMD_DISABLE:
+ return drv_pwm_enable(htim, configuration, RT_FALSE);
+ case PWM_CMD_SET:
+ return drv_pwm_set(htim, configuration);
+ case PWM_CMD_GET:
+ return drv_pwm_get(htim, configuration);
+ default:
+ return RT_EINVAL;
+ }
+}
+
+static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
+{
+ rt_err_t result = RT_EOK;
+ TIM_HandleTypeDef *tim = RT_NULL;
+ TIM_OC_InitTypeDef oc_config = {0};
+ TIM_MasterConfigTypeDef master_config = {0};
+ TIM_ClockConfigTypeDef clock_config = {0};
+
+ RT_ASSERT(device != RT_NULL);
+
+ tim = (TIM_HandleTypeDef *)&device->tim_handle;
+
+ /* configure the timer to pwm mode */
+ tim->Init.Prescaler = 0;
+ tim->Init.CounterMode = TIM_COUNTERMODE_UP;
+ tim->Init.Period = 0;
+ tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
+ tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+
+ if (HAL_TIM_PWM_Init(tim) != HAL_OK)
+ {
+ LOG_E("%s pwm init failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+
+ clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
+ {
+ LOG_E("%s clock init failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+
+ master_config.MasterOutputTrigger = TIM_TRGO_RESET;
+ master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
+ {
+ LOG_E("%s master config failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+
+ oc_config.OCMode = TIM_OCMODE_PWM1;
+ oc_config.Pulse = 0;
+ oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ oc_config.OCFastMode = TIM_OCFAST_DISABLE;
+ oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
+
+ /* config pwm channel */
+ if (device->channel & 0x01)
+ {
+ if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
+ {
+ LOG_E("%s channel1 config failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ }
+
+ if (device->channel & 0x02)
+ {
+ if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
+ {
+ LOG_E("%s channel2 config failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ }
+
+ if (device->channel & 0x04)
+ {
+ if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
+ {
+ LOG_E("%s channel3 config failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ }
+
+ if (device->channel & 0x08)
+ {
+ if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
+ {
+ LOG_E("%s channel4 config failed", device->name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ }
+
+ /* pwm pin configuration */
+ HAL_TIM_MspPostInit(tim);
+
+ /* enable update request source */
+ __HAL_TIM_URS_ENABLE(tim);
+
+__exit:
+ return result;
+}
+
+static void pwm_get_channel(void)
+{
+#ifdef BSP_USING_PWM1_CH1
+ stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM1_CH2
+ stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM1_CH3
+ stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM1_CH4
+ stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM2_CH1
+ stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM2_CH2
+ stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM2_CH3
+ stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM2_CH4
+ stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM3_CH1
+ stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM3_CH2
+ stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM3_CH3
+ stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM3_CH4
+ stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM4_CH1
+ stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM4_CH2
+ stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM4_CH3
+ stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM4_CH4
+ stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM5_CH1
+ stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM5_CH2
+ stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM5_CH3
+ stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM5_CH4
+ stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM6_CH1
+ stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM6_CH2
+ stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM6_CH3
+ stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM6_CH4
+ stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM7_CH1
+ stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM7_CH2
+ stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM7_CH3
+ stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM7_CH4
+ stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM8_CH1
+ stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM8_CH2
+ stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM8_CH3
+ stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM8_CH4
+ stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM9_CH1
+ stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM9_CH2
+ stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM9_CH3
+ stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM9_CH4
+ stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM12_CH1
+ stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM12_CH2
+ stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
+#endif
+}
+
+static int stm32_pwm_init(void)
+{
+ int i = 0;
+ int result = RT_EOK;
+
+ pwm_get_channel();
+
+ for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
+ {
+ /* pwm init */
+ if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
+ {
+ LOG_E("%s init failed", stm32_pwm_obj[i].name);
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ else
+ {
+ LOG_D("%s init success", stm32_pwm_obj[i].name);
+
+ /* register pwm device */
+ if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
+ {
+ LOG_D("%s register success", stm32_pwm_obj[i].name);
+ }
+ else
+ {
+ LOG_E("%s register failed", stm32_pwm_obj[i].name);
+ result = -RT_ERROR;
+ }
+ }
+ }
+
+__exit:
+ return result;
+}
+INIT_DEVICE_EXPORT(stm32_pwm_init);
+#endif /* RT_USING_PWM */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi.c
new file mode 100644
index 00000000000..a9e4a7fcaf8
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-27 zylx first version
+ */
+
+#include "board.h"
+#include
+#include
+#include "drv_qspi.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_QSPI
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.qspi"
+#include
+
+#if defined(BSP_USING_QSPI)
+
+struct stm32_hw_spi_cs
+{
+ uint16_t Pin;
+};
+
+struct stm32_qspi_bus
+{
+ QSPI_HandleTypeDef QSPI_Handler;
+ char *bus_name;
+#ifdef BSP_QSPI_USING_DMA
+ DMA_HandleTypeDef hdma_quadspi;
+#endif
+};
+
+struct rt_spi_bus _qspi_bus1;
+struct stm32_qspi_bus _stm32_qspi_bus;
+
+static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
+{
+ int result = RT_EOK;
+ unsigned int i = 1;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(qspi_cfg != RT_NULL);
+
+ struct rt_spi_configuration *cfg = &qspi_cfg->parent;
+ struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
+ rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
+
+ QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
+ qspi_bus->QSPI_Handler = QSPI_Handler_config;
+
+ while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
+ {
+ i++;
+ if (i == 255)
+ {
+ LOG_E("QSPI init failed, QSPI frequency(%d) is too low.", cfg->max_hz);
+ return -RT_ERROR;
+ }
+ }
+ /* 80/(1+i) */
+ qspi_bus->QSPI_Handler.Init.ClockPrescaler = i;
+
+ if (!(cfg->mode & RT_SPI_CPOL))
+ {
+ /* QSPI MODE0 */
+ qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_0;
+ }
+ else
+ {
+ /* QSPI MODE3 */
+ qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_3;
+ }
+
+ /* flash size */
+ qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
+
+ result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
+ if (result == HAL_OK)
+ {
+ LOG_D("qspi init success!");
+ }
+ else
+ {
+ LOG_E("qspi init failed (%d)!", result);
+ }
+
+#ifdef BSP_QSPI_USING_DMA
+ /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
+ HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(QSPI_IRQn);
+ HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0);
+ HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ);
+
+ /* init QSPI DMA */
+ if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN)
+ {
+ __HAL_RCC_DMA1_CLK_ENABLE();
+ }
+ else
+ {
+ __HAL_RCC_DMA2_CLK_ENABLE();
+ }
+
+ HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
+ DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
+ qspi_bus->hdma_quadspi = hdma_quadspi_config;
+
+ if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK)
+ {
+ LOG_E("qspi dma init failed (%d)!", result);
+ }
+
+ __HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi);
+#endif /* BSP_QSPI_USING_DMA */
+
+ return result;
+}
+
+static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_message *message)
+{
+ RT_ASSERT(qspi_bus != RT_NULL);
+ RT_ASSERT(message != RT_NULL);
+
+ QSPI_CommandTypeDef Cmdhandler;
+
+ /* set QSPI cmd struct */
+ Cmdhandler.Instruction = message->instruction.content;
+ Cmdhandler.Address = message->address.content;
+ Cmdhandler.DummyCycles = message->dummy_cycles;
+ if (message->instruction.qspi_lines == 0)
+ {
+ Cmdhandler.InstructionMode = QSPI_INSTRUCTION_NONE;
+ }
+ else if (message->instruction.qspi_lines == 1)
+ {
+ Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
+ }
+ else if (message->instruction.qspi_lines == 2)
+ {
+ Cmdhandler.InstructionMode = QSPI_INSTRUCTION_2_LINES;
+ }
+ else if (message->instruction.qspi_lines == 4)
+ {
+ Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES;
+ }
+ if (message->address.qspi_lines == 0)
+ {
+ Cmdhandler.AddressMode = QSPI_ADDRESS_NONE;
+ }
+ else if (message->address.qspi_lines == 1)
+ {
+ Cmdhandler.AddressMode = QSPI_ADDRESS_1_LINE;
+ }
+ else if (message->address.qspi_lines == 2)
+ {
+ Cmdhandler.AddressMode = QSPI_ADDRESS_2_LINES;
+ }
+ else if (message->address.qspi_lines == 4)
+ {
+ Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
+ }
+ if (message->address.size == 24)
+ {
+ Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
+ }
+ else
+ {
+ Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS;
+ }
+ if (message->qspi_data_lines == 0)
+ {
+ Cmdhandler.DataMode = QSPI_DATA_NONE;
+ }
+ else if (message->qspi_data_lines == 1)
+ {
+ Cmdhandler.DataMode = QSPI_DATA_1_LINE;
+ }
+ else if (message->qspi_data_lines == 2)
+ {
+ Cmdhandler.DataMode = QSPI_DATA_2_LINES;
+ }
+ else if (message->qspi_data_lines == 4)
+ {
+ Cmdhandler.DataMode = QSPI_DATA_4_LINES;
+ }
+
+ Cmdhandler.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
+ Cmdhandler.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+ Cmdhandler.DdrMode = QSPI_DDR_MODE_DISABLE;
+ Cmdhandler.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
+ Cmdhandler.NbData = message->parent.length;
+ HAL_QSPI_Command(&qspi_bus->QSPI_Handler, &Cmdhandler, 5000);
+}
+
+static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+ rt_size_t len = 0;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(device->bus != RT_NULL);
+
+ struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
+ struct stm32_qspi_bus *qspi_bus = device->bus->parent.user_data;
+#ifdef BSP_QSPI_USING_SOFTCS
+ struct stm32_hw_spi_cs *cs = device->parent.user_data;
+#endif
+
+ const rt_uint8_t *sndb = message->send_buf;
+ rt_uint8_t *rcvb = message->recv_buf;
+ rt_int32_t length = message->length;
+
+#ifdef BSP_QSPI_USING_SOFTCS
+ if (message->cs_take)
+ {
+ rt_pin_write(cs->pin, 0);
+ }
+#endif
+
+ /* send data */
+ if (sndb)
+ {
+ qspi_send_cmd(qspi_bus, qspi_message);
+ if (qspi_message->parent.length != 0)
+ {
+ if (HAL_QSPI_Transmit(&qspi_bus->QSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK)
+ {
+ len = length;
+ }
+ else
+ {
+ LOG_E("QSPI send data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
+ qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
+ goto __exit;
+ }
+ }
+ else
+ {
+ len = 1;
+ }
+ }
+ else if (rcvb)/* recv data */
+ {
+ qspi_send_cmd(qspi_bus, qspi_message);
+#ifdef BSP_QSPI_USING_DMA
+ if (HAL_QSPI_Receive_DMA(&qspi_bus->QSPI_Handler, rcvb) == HAL_OK)
+#else
+ if (HAL_QSPI_Receive(&qspi_bus->QSPI_Handler, rcvb, 5000) == HAL_OK)
+#endif
+ {
+ len = length;
+#ifdef BSP_QSPI_USING_DMA
+ while (qspi_bus->QSPI_Handler.RxXferCount != 0);
+#endif
+ }
+ else
+ {
+ LOG_E("QSPI recv data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
+ qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
+ goto __exit;
+ }
+ }
+
+__exit:
+#ifdef BSP_QSPI_USING_SOFTCS
+ if (message->cs_release)
+ {
+ rt_pin_write(cs->pin, 1);
+ }
+#endif
+ return len;
+}
+
+static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
+{
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
+
+ struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
+ return stm32_qspi_init(qspi_device, &qspi_device->config);
+}
+
+static const struct rt_spi_ops stm32_qspi_ops =
+{
+ .configure = qspi_configure,
+ .xfer = qspixfer,
+};
+
+static int stm32_qspi_register_bus(struct stm32_qspi_bus *qspi_bus, const char *name)
+{
+ RT_ASSERT(qspi_bus != RT_NULL);
+ RT_ASSERT(name != RT_NULL);
+
+ _qspi_bus1.parent.user_data = qspi_bus;
+ return rt_qspi_bus_register(&_qspi_bus1, name, &stm32_qspi_ops);
+}
+
+/**
+ * @brief This function attach device to QSPI bus.
+ * @param device_name QSPI device name
+ * @param pin QSPI cs pin number
+ * @param data_line_width QSPI data lines width, such as 1, 2, 4
+ * @param enter_qspi_mode Callback function that lets FLASH enter QSPI mode
+ * @param exit_qspi_mode Callback function that lets FLASH exit QSPI mode
+ * @retval 0 : success
+ * -1 : failed
+ */
+rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
+{
+ struct rt_qspi_device *qspi_device = RT_NULL;
+ struct stm32_hw_spi_cs *cs_pin = RT_NULL;
+ rt_err_t result = RT_EOK;
+
+ RT_ASSERT(bus_name != RT_NULL);
+ RT_ASSERT(device_name != RT_NULL);
+ RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
+
+ qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
+ if (qspi_device == RT_NULL)
+ {
+ LOG_E("no memory, qspi bus attach device failed!");
+ result = RT_ENOMEM;
+ goto __exit;
+ }
+ cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
+ if (qspi_device == RT_NULL)
+ {
+ LOG_E("no memory, qspi bus attach device failed!");
+ result = RT_ENOMEM;
+ goto __exit;
+ }
+
+ qspi_device->enter_qspi_mode = enter_qspi_mode;
+ qspi_device->exit_qspi_mode = exit_qspi_mode;
+ qspi_device->config.qspi_dl_width = data_line_width;
+
+ cs_pin->Pin = pin;
+#ifdef BSP_QSPI_USING_SOFTCS
+ rt_pin_mode(pin, PIN_MODE_OUTPUT);
+ rt_pin_write(pin, 1);
+#endif
+
+ result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, (void *)cs_pin);
+
+__exit:
+ if (result != RT_EOK)
+ {
+ if (qspi_device)
+ {
+ rt_free(qspi_device);
+ }
+
+ if (cs_pin)
+ {
+ rt_free(cs_pin);
+ }
+ }
+
+ return result;
+}
+
+#ifdef BSP_QSPI_USING_DMA
+void QSPI_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_QSPI_IRQHandler(&_stm32_qspi_bus.QSPI_Handler);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void QSPI_DMA_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&_stm32_qspi_bus.hdma_quadspi);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_QSPI_USING_DMA */
+
+static int rt_hw_qspi_bus_init(void)
+{
+ return stm32_qspi_register_bus(&_stm32_qspi_bus, "qspi1");
+}
+#ifndef FIRMWARE_EXEC_USING_QEMU
+INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
+#endif
+
+#endif /* BSP_USING_QSPI */
+#endif /* RT_USING_QSPI */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi_flash.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi_flash.c
new file mode 100644
index 00000000000..c113d7de262
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_qspi_flash.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-01-19 wanghaijing the first version
+ */
+
+#include
+#include
+#include
+#include
+
+#ifdef BSP_USING_QSPI_FLASH
+
+char w25qxx_read_status_register2(struct rt_qspi_device *device)
+{
+ /* 0x35 read status register2 */
+ char instruction = 0x35, status;
+
+ rt_qspi_send_then_recv(device, &instruction, 1, &status, 1);
+
+ return status;
+}
+
+void w25qxx_write_enable(struct rt_qspi_device *device)
+{
+ /* 0x06 write enable */
+ char instruction = 0x06;
+
+ rt_qspi_send(device, &instruction, 1);
+}
+
+void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
+{
+ char status = 0;
+ /* 0x38 enter qspi mode */
+ char instruction = 0x38;
+ char write_status2_buf[2] = {0};
+
+ /* 0x31 write status register2 */
+ write_status2_buf[0] = 0x31;
+
+ status = w25qxx_read_status_register2(device);
+ if (!(status & 0x02))
+ {
+ status |= 1 << 1;
+ w25qxx_write_enable(device);
+ write_status2_buf[1] = status;
+ rt_qspi_send(device, &write_status2_buf, 2);
+ rt_qspi_send(device, &instruction, 1);
+ rt_kprintf("flash already enter qspi mode\n");
+ rt_thread_mdelay(10);
+ }
+}
+
+static int rt_qspi_flash_init(void)
+{
+ extern rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name);
+
+ stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
+ if (RT_NULL == rt_sfud_flash_probe("norflash1", "qspi10"))
+ {
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+INIT_ENV_EXPORT(rt_qspi_flash_init);
+
+#endif/* BSP_USING_QSPI_FLASH */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_rtc.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_rtc.c
new file mode 100644
index 00000000000..4d0dd503570
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_rtc.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-04 balanceTWK first version
+ * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
+ * 2021-02-05 Meco Man fix the problem of mixing local time and UTC time
+ * 2021-07-05 iysheng implement RTC framework V2.0
+ */
+
+#include "board.h"
+#include
+#include
+
+#ifdef BSP_USING_ONCHIP_RTC
+
+#ifndef RTC_BKP_DR1
+#define RTC_BKP_DR1 RT_NULL
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.rtc"
+#include
+
+#define BKUP_REG_DATA 0xA5A5
+
+static RTC_HandleTypeDef RTC_Handler;
+
+RT_WEAK uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ return (~BKUP_REG_DATA);
+}
+
+RT_WEAK void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ return;
+}
+
+static rt_err_t stm32_rtc_get_timeval(struct timeval *tv)
+{
+ RTC_TimeTypeDef RTC_TimeStruct = {0};
+ RTC_DateTypeDef RTC_DateStruct = {0};
+ struct tm tm_new = {0};
+
+ HAL_RTC_GetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN);
+ HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
+
+ tm_new.tm_sec = RTC_TimeStruct.Seconds;
+ tm_new.tm_min = RTC_TimeStruct.Minutes;
+ tm_new.tm_hour = RTC_TimeStruct.Hours;
+ tm_new.tm_mday = RTC_DateStruct.Date;
+ tm_new.tm_mon = RTC_DateStruct.Month - 1;
+ tm_new.tm_year = RTC_DateStruct.Year + 100;
+
+ tv->tv_sec = timegm(&tm_new);
+
+#if defined(SOC_SERIES_STM32H7)
+ tv->tv_usec = (255.0 - RTC_TimeStruct.SubSeconds * 1.0) / 256.0 * 1000.0 * 1000.0;
+#endif
+
+ return RT_EOK;
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+ RTC_TimeTypeDef RTC_TimeStruct = {0};
+ RTC_DateTypeDef RTC_DateStruct = {0};
+ struct tm tm = {0};
+
+ gmtime_r(&time_stamp, &tm);
+ if (tm.tm_year < 100)
+ {
+ return -RT_ERROR;
+ }
+
+ RTC_TimeStruct.Seconds = tm.tm_sec ;
+ RTC_TimeStruct.Minutes = tm.tm_min ;
+ RTC_TimeStruct.Hours = tm.tm_hour;
+ RTC_DateStruct.Date = tm.tm_mday;
+ RTC_DateStruct.Month = tm.tm_mon + 1 ;
+ RTC_DateStruct.Year = tm.tm_year - 100;
+ RTC_DateStruct.WeekDay = tm.tm_wday + 1;
+
+ if (HAL_RTC_SetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+ if (HAL_RTC_SetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ LOG_D("set rtc time.");
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
+
+#ifdef SOC_SERIES_STM32F1
+ /* F1 series does't save year/month/date datas. so keep those datas to bkp reg */
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR2, RTC_DateStruct.Year);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR3, RTC_DateStruct.Month);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR4, RTC_DateStruct.Date);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR5, RTC_DateStruct.WeekDay);
+#endif
+
+ return RT_EOK;
+}
+
+#ifdef SOC_SERIES_STM32F1
+/* update RTC_BKP_DRx*/
+static void rt_rtc_f1_bkp_update(void)
+{
+ RTC_DateTypeDef RTC_DateStruct = {0};
+
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_BKP_CLK_ENABLE();
+
+ RTC_DateStruct.Year = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR2);
+ RTC_DateStruct.Month = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR3);
+ RTC_DateStruct.Date = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR4);
+ RTC_DateStruct.WeekDay = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR5);
+ if (HAL_RTC_SetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
+ if (HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR4) != RTC_DateStruct.Date)
+ {
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR2, RTC_DateStruct.Year);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR3, RTC_DateStruct.Month);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR4, RTC_DateStruct.Date);
+ HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR5, RTC_DateStruct.WeekDay);
+ }
+}
+#endif
+
+static rt_err_t rt_rtc_config(void)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ HAL_PWR_EnableBkUpAccess();
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+#ifdef BSP_RTC_USING_LSI
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#else
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#endif
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+#if defined(SOC_SERIES_STM32WL)
+ __HAL_RCC_RTCAPB_CLK_ENABLE();
+#endif
+
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+
+ RTC_Handler.Instance = RTC;
+ if (HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR1) != BKUP_REG_DATA)
+ {
+ LOG_I("RTC hasn't been configured, please use command to config.");
+
+#if defined(SOC_SERIES_STM32F1)
+ RTC_Handler.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
+ RTC_Handler.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+#elif defined(SOC_SERIES_STM32F0)
+
+ /* set the frequency division */
+#ifdef BSP_RTC_USING_LSI
+ RTC_Handler.Init.AsynchPrediv = 0XA0;
+ RTC_Handler.Init.SynchPrediv = 0xFA;
+#else
+ RTC_Handler.Init.AsynchPrediv = 0X7F;
+ RTC_Handler.Init.SynchPrediv = 0x0130;
+#endif /* BSP_RTC_USING_LSI */
+
+ RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
+ RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
+
+ /* set the frequency division */
+#ifdef BSP_RTC_USING_LSI
+ RTC_Handler.Init.AsynchPrediv = 0X7D;
+#else
+ RTC_Handler.Init.AsynchPrediv = 0X7F;
+#endif /* BSP_RTC_USING_LSI */
+ RTC_Handler.Init.SynchPrediv = 0XFF;
+
+ RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
+ RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
+ RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+#endif
+ if (HAL_RTC_Init(&RTC_Handler) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+ }
+#ifdef SOC_SERIES_STM32F1
+ else
+ {
+ /* F1 series need update by bkp reg datas */
+ rt_rtc_f1_bkp_update();
+ }
+#endif
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_rtc_init(void)
+{
+#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32WB)
+ __HAL_RCC_PWR_CLK_ENABLE();
+#endif
+
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+#ifdef BSP_RTC_USING_LSI
+#ifdef SOC_SERIES_STM32WB
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+#else
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+#endif
+#else
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+#endif
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ if (rt_rtc_config() != RT_EOK)
+ {
+ LOG_E("rtc init failed.");
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_rtc_get_secs(time_t *sec)
+{
+ struct timeval tv;
+
+ stm32_rtc_get_timeval(&tv);
+ *(time_t *) sec = tv.tv_sec;
+ LOG_D("RTC: get rtc_time %d", *sec);
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_rtc_set_secs(time_t *sec)
+{
+ rt_err_t result = RT_EOK;
+
+ if (set_rtc_time_stamp(*sec))
+ {
+ result = -RT_ERROR;
+ }
+ LOG_D("RTC: set rtc_time %d", *sec);
+
+ return result;
+}
+
+static const struct rt_rtc_ops stm32_rtc_ops =
+{
+ stm32_rtc_init,
+ stm32_rtc_get_secs,
+ stm32_rtc_set_secs,
+ RT_NULL,
+ RT_NULL,
+ stm32_rtc_get_timeval,
+ RT_NULL,
+};
+
+static rt_rtc_dev_t stm32_rtc_dev;
+
+static int rt_hw_rtc_init(void)
+{
+ rt_err_t result;
+
+ stm32_rtc_dev.ops = &stm32_rtc_ops;
+ result = rt_hw_rtc_register(&stm32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
+ if (result != RT_EOK)
+ {
+ LOG_E("rtc register err code: %d", result);
+ return result;
+ }
+ LOG_D("rtc init success");
+
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif /* BSP_USING_ONCHIP_RTC */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c
new file mode 100644
index 00000000000..8016d4086e0
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-10-30 Evlers first version
+ */
+
+#include "board.h"
+
+#ifdef RT_USING_SDIO
+
+#if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2)
+ #error "Please define at least one BSP_USING_SDIOx"
+#endif
+
+#include "drv_sdmmc.h"
+
+#define DBG_TAG "drv.sdmmc"
+#ifdef DRV_DEBUG
+ #define DBG_LVL DBG_LOG
+#else
+ #define DBG_LVL DBG_INFO
+#endif /* DRV_DEBUG */
+#include
+
+static struct rt_mmcsd_host *host1;
+static struct rt_mmcsd_host *host2;
+
+#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000)
+
+#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
+#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
+
+struct sdio_pkg
+{
+ struct rt_mmcsd_cmd *cmd;
+ void *buff;
+ rt_uint32_t flag;
+};
+
+struct rthw_sdio
+{
+ struct rt_mmcsd_host *host;
+ struct stm32_sdio_des sdio_des;
+ struct rt_event event;
+ struct rt_mutex mutex;
+ rt_uint8_t *cache_buf;
+ struct sdio_pkg *pkg;
+};
+
+#ifdef BSP_USING_SDIO1
+rt_align(SDIO_ALIGN_LEN)
+static rt_uint8_t cache_buf1[SDIO_BUFF_SIZE];
+#endif
+
+#ifdef BSP_USING_SDIO2
+rt_align(SDIO_ALIGN_LEN)
+static rt_uint8_t cache_buf2[SDIO_BUFF_SIZE];
+#endif
+
+/**
+ * @brief This function get order from sdio.
+ * @param data
+ * @retval sdio order
+ */
+static int get_order(rt_uint32_t data)
+{
+ int order = 0;
+
+ switch (data)
+ {
+ case 1:
+ order = 0;
+ break;
+
+ case 2:
+ order = 1;
+ break;
+
+ case 4:
+ order = 2;
+ break;
+
+ case 8:
+ order = 3;
+ break;
+
+ case 16:
+ order = 4;
+ break;
+
+ case 32:
+ order = 5;
+ break;
+
+ case 64:
+ order = 6;
+ break;
+
+ case 128:
+ order = 7;
+ break;
+
+ case 256:
+ order = 8;
+ break;
+
+ case 512:
+ order = 9;
+ break;
+
+ case 1024:
+ order = 10;
+ break;
+
+ case 2048:
+ order = 11;
+ break;
+
+ case 4096:
+ order = 12;
+ break;
+
+ case 8192:
+ order = 13;
+ break;
+
+ case 16384:
+ order = 14;
+ break;
+
+ default :
+ order = 0;
+ break;
+ }
+
+ return order;
+}
+
+/**
+ * @brief This function wait sdio cmd completed.
+ * @param sdio rthw_sdio
+ * @retval None
+ */
+static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
+{
+ rt_uint32_t status;
+ struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
+ struct rt_mmcsd_data *data = cmd->data;
+ SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
+
+ if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+ rt_tick_from_millisecond(5000), &status) != RT_EOK)
+ {
+ LOG_E("wait cmd completed timeout");
+ cmd->err = -RT_ETIMEOUT;
+ return;
+ }
+
+ if (sdio->pkg == RT_NULL)
+ {
+ return;
+ }
+ /* Get Card Specific Data */
+ cmd->resp[0] = hsd->RESP1;
+ if (resp_type(cmd) == RESP_R2)
+ {
+ cmd->resp[1] = hsd->RESP2;
+ cmd->resp[2] = hsd->RESP3;
+ cmd->resp[3] = hsd->RESP4;
+ }
+ /* Check for error conditions */
+ if (status & SDIO_ERRORS)
+ {
+ if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
+ {
+ cmd->err = RT_EOK;
+ }
+ else
+ {
+ cmd->err = -RT_ERROR;
+ }
+ }
+ else
+ {
+ cmd->err = RT_EOK;
+ }
+
+ if (status & SDMMC_IT_CTIMEOUT)
+ {
+ cmd->err = -RT_ETIMEOUT;
+ }
+ if (status & SDMMC_IT_DCRCFAIL)
+ {
+ data->err = -RT_ERROR;
+ }
+
+ if (status & SDMMC_IT_DTIMEOUT)
+ {
+ data->err = -RT_ETIMEOUT;
+ }
+
+ if (cmd->err == RT_EOK)
+ {
+ LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+ }
+ else
+ {
+ LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
+ status,
+ status & SDMMC_STA_CCRCFAIL ? "CCRCFAIL " : "",
+ status & SDMMC_STA_DCRCFAIL ? "DCRCFAIL " : "",
+ status & SDMMC_STA_CTIMEOUT ? "CTIMEOUT " : "",
+ status & SDMMC_STA_DTIMEOUT ? "DTIMEOUT " : "",
+ status & SDMMC_STA_TXUNDERR ? "TXUNDERR " : "",
+ status & SDMMC_STA_RXOVERR ? "RXOVERR " : "",
+ status == 0 ? "NULL" : "",
+ cmd->cmd_code,
+ cmd->arg,
+ data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
+ data ? data->blks * data->blksize : 0,
+ data ? data->blksize : 0
+ );
+ }
+}
+
+/**
+ * @brief This function send command.
+ * @param sdio rthw_sdio
+ * @param pkg sdio package
+ * @retval None
+ */
+static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
+{
+ struct rt_mmcsd_cmd *cmd = pkg->cmd;
+ struct rt_mmcsd_data *data = cmd->data;
+ SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
+ rt_uint32_t reg_cmd;
+
+ rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL);
+ /* save pkg */
+ sdio->pkg = pkg;
+
+ LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
+ cmd->cmd_code,
+ cmd->arg,
+ resp_type(cmd) == RESP_NONE ? "NONE" : "",
+ resp_type(cmd) == RESP_R1 ? "R1" : "",
+ resp_type(cmd) == RESP_R1B ? "R1B" : "",
+ resp_type(cmd) == RESP_R2 ? "R2" : "",
+ resp_type(cmd) == RESP_R3 ? "R3" : "",
+ resp_type(cmd) == RESP_R4 ? "R4" : "",
+ resp_type(cmd) == RESP_R5 ? "R5" : "",
+ resp_type(cmd) == RESP_R6 ? "R6" : "",
+ resp_type(cmd) == RESP_R7 ? "R7" : "",
+ data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
+ data ? data->blks * data->blksize : 0,
+ data ? data->blksize : 0
+ );
+
+ /* open irq */
+ __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDIO_MASKR_ALL);
+ reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
+
+ /* data pre configuration */
+ if (data != RT_NULL)
+ {
+ if (data->flags & DATA_DIR_WRITE)
+ {
+ SCB_CleanDCache_by_Addr((uint32_t*)sdio->cache_buf, data->blks * data->blksize);
+ }
+ else
+ {
+ SCB_InvalidateDCache_by_Addr((uint32_t*)sdio->cache_buf, data->blks * data->blksize + 32);
+ }
+
+ reg_cmd |= SDMMC_CMD_CMDTRANS;
+ __HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
+ hsd->DTIMER = HW_SDIO_DATATIMEOUT;
+ hsd->DLEN = data->blks * data->blksize;
+ hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0) | \
+ (data->flags & DATA_STREAM ? SDMMC_DCTRL_DTMODE_0 : 0);
+ hsd->IDMABASER = (rt_uint32_t)sdio->cache_buf;
+ hsd->IDMACTRL = SDMMC_IDMA_IDMAEN;
+ }
+ /* config cmd reg */
+ if (resp_type(cmd) == RESP_NONE)
+ reg_cmd |= SDMMC_RESPONSE_NO;
+ else if (resp_type(cmd) == RESP_R2)
+ reg_cmd |= SDMMC_RESPONSE_LONG;
+ else
+ reg_cmd |= SDMMC_RESPONSE_SHORT;
+
+ hsd->ARG = cmd->arg;
+ hsd->CMD = reg_cmd;
+ /* wait completed */
+ rthw_sdio_wait_completed(sdio);
+
+ /* Waiting for data to be sent to completion */
+ if (data != RT_NULL)
+ {
+ volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
+
+ while (count && (hsd->STA & SDMMC_STA_DPSMACT))
+ {
+ count--;
+ }
+
+ if ((count == 0) || (hsd->STA & SDIO_ERRORS))
+ {
+ cmd->err = -RT_ERROR;
+ }
+ }
+
+ /* data post configuration */
+ if (data != RT_NULL)
+ {
+ if (data->flags & DATA_DIR_READ)
+ {
+ SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)sdio->cache_buf & ~(32U - 1U)), data->blks * data->blksize + 32U);
+ rt_memcpy(data->buf, sdio->cache_buf, data->blks * data->blksize);
+ }
+ }
+}
+
+/**
+ * @brief This function send sdio request.
+ * @param sdio rthw_sdio
+ * @param req request
+ * @retval None
+ */
+static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+ struct sdio_pkg pkg;
+ struct rthw_sdio *sdio = host->private_data;
+ struct rt_mmcsd_data *data;
+
+ RTHW_SDIO_LOCK(sdio);
+
+ if (req->cmd != RT_NULL)
+ {
+ rt_memset(&pkg, 0, sizeof(pkg));
+ data = req->cmd->data;
+ pkg.cmd = req->cmd;
+
+ if (data != RT_NULL)
+ {
+ rt_uint32_t size = data->blks * data->blksize;
+
+ RT_ASSERT(size <= SDIO_BUFF_SIZE);
+
+ if (data->flags & DATA_DIR_WRITE)
+ {
+ rt_memcpy(sdio->cache_buf, data->buf, size);
+ }
+ }
+
+ rthw_sdio_send_command(sdio, &pkg);
+ }
+
+ if (req->stop != RT_NULL)
+ {
+ rt_memset(&pkg, 0, sizeof(pkg));
+ pkg.cmd = req->stop;
+ rthw_sdio_send_command(sdio, &pkg);
+ }
+
+ RTHW_SDIO_UNLOCK(sdio);
+
+ mmcsd_req_complete(sdio->host);
+}
+
+/**
+ * @brief This function config sdio.
+ * @param host rt_mmcsd_host
+ * @param io_cfg rt_mmcsd_io_cfg
+ * @retval None
+ */
+static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+ rt_uint32_t clk = io_cfg->clock;
+ struct rthw_sdio *sdio = host->private_data;
+ SD_HandleTypeDef *hsd = &sdio->sdio_des.hw_sdio;
+ SDMMC_InitTypeDef Init = {0};
+ rt_uint32_t sdmmc_clk = sdio->sdio_des.clk_get();
+
+ if (sdmmc_clk < SD_INIT_FREQ)
+ {
+ LOG_E("The clock rate is too low! rata:%d", sdmmc_clk);
+ return;
+ }
+
+ if (clk > host->freq_max)
+ clk = host->freq_max;
+
+ if (clk > sdmmc_clk)
+ {
+ LOG_W("Setting rate is greater than clock source rate.");
+ clk = sdmmc_clk;
+ }
+
+ LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
+ clk / 1000,
+ io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
+ io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
+ io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
+ io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
+ io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
+ io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
+ );
+
+ if (sdmmc_clk != 0U)
+ {
+ hsd->Init.ClockDiv = sdmmc_clk / (2U * clk);
+ /* Configure the SDMMC peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
+ {
+ Init.BusWide = SDMMC_BUS_WIDE_4B;
+ }
+ else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
+ {
+ Init.BusWide = SDMMC_BUS_WIDE_8B;
+ }
+ else
+ {
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
+ }
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ //CARD_ULTRA_HIGH_SPEED :UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01
+ else if (MMCSD_TIMING_UHS_SDR50 <= io_cfg->timing && io_cfg->timing <= MMCSD_TIMING_UHS_DDR50)
+ {
+ /* UltraHigh speed SD card,user Clock div */
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ //CARD_HIGH_SPEED: High Speed Card <25Mo/s , Spec version 2.00
+ else if (io_cfg->timing == MMCSD_TIMING_SD_HS)
+ {
+ /* High speed SD card, Max Frequency = 50Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+ //CARD_NORMAL_SPEED: Normal Speed Card <12.5Mo/s , Spec Version 1.01
+ else if (io_cfg->timing == MMCSD_TIMING_LEGACY)
+ {
+ /* No High speed SD card, Max Frequency = 25Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+ (void)SDMMC_Init(hsd->Instance, Init);
+ }
+ switch ((io_cfg->power_mode)&0X03)
+ {
+ case MMCSD_POWER_OFF:
+ /* Set Power State to OFF */
+ (void)SDMMC_PowerState_OFF(hsd->Instance);
+ break;
+ case MMCSD_POWER_UP:
+ /* In F4 series chips, 0X01 is reserved bit and has no practical effect.
+ For F7 series chips, 0X01 is power-on after power-off,The SDMMC disables the function and the card clock stops.
+ For H7 series chips, 0X03 is the power-on function.
+ */
+ case MMCSD_POWER_ON:
+ /* Set Power State to ON */
+ (void)SDMMC_PowerState_ON(hsd->Instance);
+ break;
+ default:
+ LOG_W("unknown power mode %d", io_cfg->power_mode);
+ break;
+ }
+}
+
+/**
+ * @brief This function update sdio interrupt.
+ * @param host rt_mmcsd_host
+ * @param enable
+ * @retval None
+ */
+void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
+{
+ struct rthw_sdio *sdio = host->private_data;
+
+ if (enable)
+ {
+ LOG_D("enable sdio irq");
+ __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
+ }
+ else
+ {
+ LOG_D("disable sdio irq");
+ __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
+ }
+}
+
+/**
+ * @brief This function detect sdcard.
+ * @param host rt_mmcsd_host
+ * @retval 0x01
+ */
+static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
+{
+ LOG_D("try to detect device");
+ return 0x01;
+}
+
+/**
+ * @brief This function interrupt process function.
+ * @param host rt_mmcsd_host
+ * @retval None
+ */
+void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
+{
+ struct rthw_sdio *sdio = host->private_data;
+ rt_uint32_t intstatus = sdio->sdio_des.hw_sdio.Instance->STA;
+
+ /* clear irq flag*/
+ __HAL_SD_CLEAR_FLAG(&sdio->sdio_des.hw_sdio, intstatus);
+ rt_event_send(&sdio->event, intstatus);
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+ rthw_sdio_request,
+ rthw_sdio_iocfg,
+ rthw_sd_detect,
+ rthw_sdio_irq_update,
+};
+
+/**
+ * @brief This function create mmcsd host.
+ * @param sdio_des stm32_sdio_des
+ * @retval rt_mmcsd_host
+ */
+struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
+{
+ struct rt_mmcsd_host *host;
+ struct rthw_sdio *sdio = RT_NULL;
+
+ if (sdio_des == RT_NULL)
+ {
+ LOG_E("L:%d F:%s",(sdio_des == RT_NULL ? "sdio_des is NULL" : ""));
+ return RT_NULL;
+ }
+
+ sdio = rt_malloc(sizeof(struct rthw_sdio));
+
+ if (sdio == RT_NULL)
+ {
+ LOG_E("L:%d F:%s malloc rthw_sdio fail");
+ return RT_NULL;
+ }
+
+ rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+
+ host = mmcsd_alloc_host();
+
+ if (host == RT_NULL)
+ {
+ LOG_E("L:%d F:%s mmcsd alloc host fail");
+ rt_free(sdio);
+ return RT_NULL;
+ }
+
+ rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
+#ifdef BSP_USING_SDIO1
+ if(sdio_des->hw_sdio.Instance == SDMMC1)
+ {
+ sdio->cache_buf = cache_buf1;
+ rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO);
+ rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_PRIO);
+ }
+#endif /* BSP_USING_SDIO1 */
+#ifdef BSP_USING_SDIO2
+ if(sdio_des->hw_sdio.Instance == SDMMC2)
+ {
+ sdio->cache_buf = cache_buf2;
+ rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
+ rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_PRIO);
+ }
+#endif /* BSP_USING_SDIO2 */
+
+ /* set host default attributes */
+ host->ops = &ops;
+ host->freq_min = 400 * 1000;
+ host->freq_max = SDIO_MAX_FREQ;
+ host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
+
+#ifndef SDIO_USING_1_BIT
+ host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
+#else
+ host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
+#endif
+ host->max_seg_size = SDIO_BUFF_SIZE;
+ host->max_dma_segs = 1;
+ host->max_blk_size = 512;
+ host->max_blk_count = 512;
+
+ /* link up host and sdio */
+ sdio->host = host;
+ host->private_data = sdio;
+
+ rthw_sdio_irq_update(host, 1);
+
+ /* ready to change */
+ mmcsd_change(host);
+
+ return host;
+}
+
+/**
+ * @brief This function get stm32 sdio clock.
+ * @param hw_sdio: stm32_sdio
+ * @retval PCLK2Freq
+ */
+static rt_uint32_t stm32_sdio_clock_get(void)
+{
+ return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12);
+}
+
+void SDMMC1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ /* Process All SDIO Interrupt Sources */
+ rthw_sdio_irq_process(host1);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void SDMMC2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ /* Process All SDIO Interrupt Sources */
+ rthw_sdio_irq_process(host2);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+int rt_hw_sdio_init(void)
+{
+#ifdef BSP_USING_SDIO1
+ struct stm32_sdio_des sdio_des1 = {0};
+ sdio_des1.hw_sdio.Instance = SDMMC1;
+
+ HAL_SD_MspInit(&sdio_des1.hw_sdio);
+ HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
+ HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+
+ sdio_des1.clk_get = stm32_sdio_clock_get;
+
+ host1 = sdio_host_create(&sdio_des1);
+
+ if (host1 == RT_NULL)
+ {
+ LOG_E("host1 create fail");
+ return -RT_ERROR;
+ }
+#endif /* BSP_USING_SDIO1 */
+
+#ifdef BSP_USING_SDIO2
+ struct stm32_sdio_des sdio_des2 = {0};
+ sdio_des2.hw_sdio.Instance = SDMMC2;
+
+ HAL_SD_MspInit(&sdio_des2.hw_sdio);
+ HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0);
+ HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
+
+ sdio_des2.clk_get = stm32_sdio_clock_get;
+
+ host2 = sdio_host_create(&sdio_des2);
+
+ if (host2 == RT_NULL)
+ {
+ LOG_E("host2 create fail");
+ return -RT_ERROR;
+ }
+#endif /* BSP_USING_SDIO2 */
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_sdio_init);
+
+void stm32_mmcsd_change(void)
+{
+#ifdef BSP_USING_SDIO1
+ mmcsd_change(host1);
+#endif /* BSP_USING_SDIO2 */
+#ifdef BSP_USING_SDIO2
+ mmcsd_change(host2);
+#endif /* BSP_USING_SDIO2 */
+}
+
+#endif /* RT_USING_SDIO */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c
new file mode 100644
index 00000000000..b5e8473a9f1
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-08 balanceTWK first version
+ */
+
+#include
+#include "drv_soft_i2c.h"
+#include "drv_config.h"
+#include
+#include
+
+#ifdef RT_USING_I2C
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.i2c"
+#include
+
+#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
+#error "Please define at least one BSP_USING_I2Cx"
+#endif
+
+static const struct stm32_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_I2C1
+ I2C1_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C2
+ I2C2_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C3
+ I2C3_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C4
+ I2C4_BUS_CONFIG,
+#endif
+};
+
+static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param Stm32 i2c dirver class.
+ */
+static void stm32_i2c_gpio_init(struct stm32_i2c *i2c)
+{
+ struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)i2c->ops.data;
+
+ rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+ rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+ rt_pin_write(cfg->scl, PIN_HIGH);
+ rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param Stm32 config class.
+ * @param The sda pin state.
+ */
+static void stm32_set_sda(void *data, rt_int32_t state)
+{
+ struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
+ if (state)
+ {
+ rt_pin_write(cfg->sda, PIN_HIGH);
+ }
+ else
+ {
+ rt_pin_write(cfg->sda, PIN_LOW);
+ }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param Stm32 config class.
+ * @param The scl pin state.
+ */
+static void stm32_set_scl(void *data, rt_int32_t state)
+{
+ struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
+ if (state)
+ {
+ rt_pin_write(cfg->scl, PIN_HIGH);
+ }
+ else
+ {
+ rt_pin_write(cfg->scl, PIN_LOW);
+ }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t stm32_get_sda(void *data)
+{
+ struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
+ return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t stm32_get_scl(void *data)
+{
+ struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
+ return rt_pin_read(cfg->scl);
+}
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void stm32_udelay(rt_uint32_t us)
+{
+ rt_uint32_t ticks;
+ rt_uint32_t told, tnow, tcnt = 0;
+ rt_uint32_t reload = SysTick->LOAD;
+
+ ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+ told = SysTick->VAL;
+ while (1)
+ {
+ tnow = SysTick->VAL;
+ if (tnow != told)
+ {
+ if (tnow < told)
+ {
+ tcnt += told - tnow;
+ }
+ else
+ {
+ tcnt += reload - tnow + told;
+ }
+ told = tnow;
+ if (tcnt >= ticks)
+ {
+ break;
+ }
+ }
+ }
+}
+
+static const struct rt_i2c_bit_ops stm32_bit_ops_default =
+{
+ .data = RT_NULL,
+ .set_sda = stm32_set_sda,
+ .set_scl = stm32_set_scl,
+ .get_sda = stm32_get_sda,
+ .get_scl = stm32_get_scl,
+ .udelay = stm32_udelay,
+ .delay_us = 1,
+ .timeout = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param stm32 config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t stm32_i2c_bus_unlock(const struct stm32_soft_i2c_config *cfg)
+{
+ rt_int32_t i = 0;
+
+ if (PIN_LOW == rt_pin_read(cfg->sda))
+ {
+ while (i++ < 9)
+ {
+ rt_pin_write(cfg->scl, PIN_HIGH);
+ stm32_udelay(100);
+ rt_pin_write(cfg->scl, PIN_LOW);
+ stm32_udelay(100);
+ }
+ }
+ if (PIN_LOW == rt_pin_read(cfg->sda))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+ rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct stm32_i2c);
+ rt_err_t result;
+
+ for (int i = 0; i < obj_num; i++)
+ {
+ i2c_obj[i].ops = stm32_bit_ops_default;
+ i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
+ i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+ stm32_i2c_gpio_init(&i2c_obj[i]);
+ result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+ RT_ASSERT(result == RT_EOK);
+ stm32_i2c_bus_unlock(&soft_i2c_config[i]);
+
+ LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+ soft_i2c_config[i].bus_name,
+ soft_i2c_config[i].scl,
+ soft_i2c_config[i].sda);
+ }
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_spi.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_spi.c
new file mode 100644
index 00000000000..4df7aba5c09
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_spi.c
@@ -0,0 +1,914 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-5 SummerGift first version
+ * 2018-12-11 greedyhao Porting for stm32f7xx
+ * 2019-01-03 zylx modify DMA initialization and spixfer function
+ * 2020-01-15 whj4674672 Porting for stm32h7xx
+ */
+
+#include "board.h"
+#include
+#include
+
+#ifdef RT_USING_SPI
+
+#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
+
+#include "drv_spi.h"
+#include "drv_config.h"
+#include
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.spi"
+#include
+
+enum
+{
+#ifdef BSP_USING_SPI1
+ SPI1_INDEX,
+#endif
+#ifdef BSP_USING_SPI2
+ SPI2_INDEX,
+#endif
+#ifdef BSP_USING_SPI3
+ SPI3_INDEX,
+#endif
+#ifdef BSP_USING_SPI4
+ SPI4_INDEX,
+#endif
+#ifdef BSP_USING_SPI5
+ SPI5_INDEX,
+#endif
+#ifdef BSP_USING_SPI6
+ SPI6_INDEX,
+#endif
+};
+
+static struct stm32_spi_config spi_config[] =
+{
+#ifdef BSP_USING_SPI1
+ SPI1_BUS_CONFIG,
+#endif
+
+#ifdef BSP_USING_SPI2
+ SPI2_BUS_CONFIG,
+#endif
+
+#ifdef BSP_USING_SPI3
+ SPI3_BUS_CONFIG,
+#endif
+
+#ifdef BSP_USING_SPI4
+ SPI4_BUS_CONFIG,
+#endif
+
+#ifdef BSP_USING_SPI5
+ SPI5_BUS_CONFIG,
+#endif
+
+#ifdef BSP_USING_SPI6
+ SPI6_BUS_CONFIG,
+#endif
+};
+
+static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
+
+static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
+{
+ RT_ASSERT(spi_drv != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
+
+ if (cfg->mode & RT_SPI_SLAVE)
+ {
+ spi_handle->Init.Mode = SPI_MODE_SLAVE;
+ }
+ else
+ {
+ spi_handle->Init.Mode = SPI_MODE_MASTER;
+ }
+
+ if (cfg->mode & RT_SPI_3WIRE)
+ {
+ spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
+ }
+ else
+ {
+ spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
+ }
+
+ if (cfg->data_width == 8)
+ {
+ spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
+ spi_handle->TxXferSize = 8;
+ spi_handle->RxXferSize = 8;
+ }
+ else if (cfg->data_width == 16)
+ {
+ spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
+ }
+ else
+ {
+ return RT_EIO;
+ }
+
+ if (cfg->mode & RT_SPI_CPHA)
+ {
+ spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+ }
+ else
+ {
+ spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+ }
+
+ if (cfg->mode & RT_SPI_CPOL)
+ {
+ spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+ }
+ else
+ {
+ spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+ }
+
+ if (cfg->mode & RT_SPI_NO_CS)
+ {
+ spi_handle->Init.NSS = SPI_NSS_SOFT;
+ }
+ else
+ {
+ spi_handle->Init.NSS = SPI_NSS_SOFT;
+ }
+
+ uint32_t SPI_APB_CLOCK;
+
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
+ SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();
+#elif defined(SOC_SERIES_STM32H7RS)
+ SPI_APB_CLOCK = HAL_RCC_GetSysClockFreq();
+#else
+ SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
+#endif
+
+ if (cfg->max_hz >= SPI_APB_CLOCK / 2)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
+ }
+ else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
+ {
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
+ }
+ else
+ {
+ /* min prescaler 256 */
+ spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+ }
+
+ LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
+ HAL_RCC_GetSysClockFreq(),
+ SPI_APB_CLOCK,
+ cfg->max_hz,
+ spi_handle->Init.BaudRatePrescaler);
+
+ if (cfg->mode & RT_SPI_MSB)
+ {
+ spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
+ }
+ else
+ {
+ spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
+ }
+
+ spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
+ spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ spi_handle->State = HAL_SPI_STATE_RESET;
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
+ spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+#elif defined(SOC_SERIES_STM32H7RS)
+ spi_handle->Init.Mode = SPI_MODE_MASTER;
+ spi_handle->Init.NSS = SPI_NSS_SOFT;
+ spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
+ spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+ spi_handle->Init.CRCPolynomial = 7;
+ spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+ spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+ spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+ spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
+ spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
+ spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
+ spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
+ spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
+#endif
+
+ if (HAL_SPI_Init(spi_handle) != HAL_OK)
+ {
+ return RT_EIO;
+ }
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
+ || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
+ SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
+#endif
+
+ /* DMA configuration */
+ if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
+ {
+ HAL_DMA_Init(&spi_drv->dma.handle_rx);
+
+ __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
+
+ /* NVIC configuration for DMA transfer complete interrupt */
+ HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
+ HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
+ }
+
+ if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
+ {
+ HAL_DMA_Init(&spi_drv->dma.handle_tx);
+
+ __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
+
+ /* NVIC configuration for DMA transfer complete interrupt */
+ HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
+ HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
+ }
+
+ __HAL_SPI_ENABLE(spi_handle);
+
+ LOG_D("%s init done", spi_drv->config->bus_name);
+ return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+ HAL_StatusTypeDef state;
+ rt_size_t message_length, already_send_length;
+ rt_uint16_t send_length;
+ rt_uint8_t *recv_buf;
+ const rt_uint8_t *send_buf;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(device->bus != RT_NULL);
+ RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+ RT_ASSERT(message != RT_NULL);
+
+ struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
+ SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
+ struct stm32_hw_spi_cs *cs = device->parent.user_data;
+
+ if (message->cs_take)
+ {
+ HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
+ }
+
+ LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
+ LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
+ spi_drv->config->bus_name,
+ (uint32_t)message->send_buf,
+ (uint32_t)message->recv_buf, message->length);
+
+ message_length = message->length;
+ recv_buf = message->recv_buf;
+ send_buf = message->send_buf;
+ while (message_length)
+ {
+ /* the HAL library use uint16 to save the data length */
+ if (message_length > 65535)
+ {
+ send_length = 65535;
+ message_length = message_length - 65535;
+ }
+ else
+ {
+ send_length = message_length;
+ message_length = 0;
+ }
+
+ /* calculate the start address */
+ already_send_length = message->length - send_length - message_length;
+ send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
+ recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
+
+ /* start once data exchange in DMA mode */
+ if (message->send_buf && message->recv_buf)
+ {
+ if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
+ {
+ state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length);
+ }
+ else
+ {
+ state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000);
+ }
+ }
+ else if (message->send_buf)
+ {
+ if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
+ {
+ state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length);
+ }
+ else
+ {
+ state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
+ }
+ }
+ else
+ {
+ memset((uint8_t *)recv_buf, 0xff, send_length);
+ if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
+ {
+ state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length);
+ }
+ else
+ {
+ state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
+ }
+ }
+
+ if (state != HAL_OK)
+ {
+ LOG_I("spi transfer error : %d", state);
+ message->length = 0;
+ spi_handle->State = HAL_SPI_STATE_READY;
+ }
+ else
+ {
+ LOG_D("%s transfer done", spi_drv->config->bus_name);
+ }
+
+ /* For simplicity reasons, this example is just waiting till the end of the
+ transfer, but application may perform other tasks while transfer operation
+ is ongoing. */
+ while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
+ }
+
+ if (message->cs_release)
+ {
+ HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
+ }
+
+ return message->length;
+}
+
+static rt_err_t spi_configure(struct rt_spi_device *device,
+ struct rt_spi_configuration *configuration)
+{
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
+
+ struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
+ spi_drv->cfg = configuration;
+
+ return stm32_spi_init(spi_drv, configuration);
+}
+
+static const struct rt_spi_ops stm_spi_ops =
+{
+ .configure = spi_configure,
+ .xfer = spixfer,
+};
+
+static int rt_hw_spi_bus_init(void)
+{
+ rt_err_t result;
+ for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
+ {
+ spi_bus_obj[i].config = &spi_config[i];
+ spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
+ spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
+
+ if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
+ {
+ /* Configure the DMA handler for Transmission process */
+ spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
+//#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+// spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
+//#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+// spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
+//#endif
+// spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+// spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+// spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
+// spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+// spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+// spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
+// spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
+//#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+// spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+// spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+// spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
+// spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
+//#endif
+
+ {
+ rt_uint32_t tmpreg = 0x00U;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+ SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
+#endif
+ UNUSED(tmpreg); /* To avoid compiler warnings */
+ }
+ }
+
+ if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
+ {
+ /* Configure the DMA handler for Transmission process */
+ spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
+//#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+// spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
+//#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+// spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
+//#endif
+// spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+// spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+// spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
+// spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+// spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+// spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
+// spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
+//#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+// spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+// spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+// spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
+// spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
+//#endif
+
+ {
+ rt_uint32_t tmpreg = 0x00U;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+ SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
+#endif
+ UNUSED(tmpreg); /* To avoid compiler warnings */
+ }
+ }
+
+ result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
+ RT_ASSERT(result == RT_EOK);
+
+ LOG_D("%s bus init done", spi_config[i].bus_name);
+ }
+
+ return result;
+}
+
+/**
+ * Attach the spi device to SPI bus, this function must be used after initialization.
+ */
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
+{
+ RT_ASSERT(bus_name != RT_NULL);
+ RT_ASSERT(device_name != RT_NULL);
+
+ rt_err_t result;
+ struct rt_spi_device *spi_device;
+ struct stm32_hw_spi_cs *cs_pin;
+
+ /* initialize the cs pin && select the slave*/
+ GPIO_InitTypeDef GPIO_Initure;
+ GPIO_Initure.Pin = cs_gpio_pin;
+ GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_Initure.Pull = GPIO_PULLUP;
+ GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
+ HAL_GPIO_WritePin(cs_gpiox, cs_gpio_pin, GPIO_PIN_SET);
+
+ /* attach the device to spi bus*/
+ spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+ RT_ASSERT(spi_device != RT_NULL);
+ cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
+ RT_ASSERT(cs_pin != RT_NULL);
+ cs_pin->GPIOx = cs_gpiox;
+ cs_pin->GPIO_Pin = cs_gpio_pin;
+ result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+ if (result != RT_EOK)
+ {
+ LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
+ }
+
+ RT_ASSERT(result == RT_EOK);
+
+ LOG_D("%s attach to %s done", device_name, bus_name);
+
+ return result;
+}
+
+#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
+void SPI1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI1_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI1_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
+
+#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
+void SPI2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI2_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI2_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
+
+#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
+void SPI3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI3_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI3_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
+
+#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
+void SPI4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI4_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI4_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
+
+#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
+void SPI5_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI5_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI5_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
+
+#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
+/**
+ * @brief This function handles DMA Rx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI6_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
+/**
+ * @brief This function handles DMA Tx interrupt request.
+ * @param None
+ * @retval None
+ */
+void SPI6_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
+
+static void stm32_get_dma_info(void)
+{
+#ifdef BSP_SPI1_RX_USING_DMA
+ spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
+ spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
+#endif
+#ifdef BSP_SPI1_TX_USING_DMA
+ spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
+ spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
+#endif
+
+#ifdef BSP_SPI2_RX_USING_DMA
+ spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
+ spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
+#endif
+#ifdef BSP_SPI2_TX_USING_DMA
+ spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
+ spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
+#endif
+
+#ifdef BSP_SPI3_RX_USING_DMA
+ spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
+ spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
+#endif
+#ifdef BSP_SPI3_TX_USING_DMA
+ spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
+ spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
+#endif
+
+#ifdef BSP_SPI4_RX_USING_DMA
+ spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
+ spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
+#endif
+#ifdef BSP_SPI4_TX_USING_DMA
+ spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
+ spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
+#endif
+
+#ifdef BSP_SPI5_RX_USING_DMA
+ spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
+ spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
+#endif
+#ifdef BSP_SPI5_TX_USING_DMA
+ spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
+ spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
+#endif
+
+#ifdef BSP_SPI6_RX_USING_DMA
+ spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
+ static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
+ spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
+#endif
+#ifdef BSP_SPI6_TX_USING_DMA
+ spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
+ static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
+ spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
+#endif
+}
+
+#if defined(SOC_SERIES_STM32F0)
+void SPI1_DMA_RX_TX_IRQHandler(void)
+{
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
+ SPI1_DMA_TX_IRQHandler();
+#endif
+
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
+ SPI1_DMA_RX_IRQHandler();
+#endif
+}
+
+void SPI2_DMA_RX_TX_IRQHandler(void)
+{
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
+ SPI2_DMA_TX_IRQHandler();
+#endif
+
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
+ SPI2_DMA_RX_IRQHandler();
+#endif
+}
+#endif /* SOC_SERIES_STM32F0 */
+
+int rt_hw_spi_init(void)
+{
+ stm32_get_dma_info();
+ return rt_hw_spi_bus_init();
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
+#endif /* RT_USING_SPI */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_spi_ili9488.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_spi_ili9488.c
new file mode 100644
index 00000000000..7cd926eb913
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_spi_ili9488.c
@@ -0,0 +1,1167 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-08-10 zylx first version
+ * 2022-02-01 Rudy Lo add lcd_fill_array function
+ */
+
+#include
+
+#ifdef BSP_USING_SPI_LCD_ILI9488
+#include
+#include "drv_spi.h"
+#include "drv_spi_ili9488.h"
+#include
+#include "drv_lcd_font.h"
+#include
+#include
+
+#if defined(PKG_USING_GUIENGINE)
+#include
+#endif
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.spi_lcd"
+#include
+
+#define LCD_DC_PIN GET_PIN(C, 7)
+
+#define LCD_DEVICE(dev) (struct drv_lcd_device*)(dev)
+
+#define LCD_CLEAR_SEND_NUMBER (LCD_H * LCD_W *3)
+
+static rt_uint32_t BACK_COLOR = WHITE, FORE_COLOR = BLACK;
+static struct rt_spi_device *spi_dev_lcd;
+
+static int rt_hw_lcd_config(void)
+{
+ spi_dev_lcd = (struct rt_spi_device *)rt_device_find("spi20");
+
+ /* config spi */
+ {
+ struct rt_spi_configuration cfg;
+ cfg.data_width = 8;
+ cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
+ cfg.max_hz = 50 * 1000 * 1000;
+
+ rt_spi_configure(spi_dev_lcd, &cfg);
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t lcd_write_cmd(const rt_uint8_t cmd)
+{
+ rt_size_t len;
+
+ rt_pin_write(LCD_DC_PIN, PIN_LOW);
+
+ len = rt_spi_send(spi_dev_lcd, &cmd, 1);
+
+ if (len != 1)
+ {
+ LOG_I("lcd_write_cmd error. %d", len);
+ return -RT_ERROR;
+ }
+ else
+ {
+ return RT_EOK;
+ }
+}
+
+static rt_err_t lcd_write_data(const rt_uint8_t data)
+{
+ rt_size_t len;
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+
+ len = rt_spi_send(spi_dev_lcd, &data, 1);
+
+ if (len != 1)
+ {
+ LOG_I("lcd_write_data error. %d", len);
+ return -RT_ERROR;
+ }
+ else
+ {
+ return RT_EOK;
+ }
+}
+
+static rt_err_t lcd_write_half_word(const rt_uint16_t da)
+{
+ rt_size_t len;
+ char data[2] = {0};
+
+ data[0] = da >> 8;
+ data[1] = da;
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ len = rt_spi_send(spi_dev_lcd, data, 2);
+ if (len != 2)
+ {
+ LOG_I("lcd_write_half_word error. %d", len);
+ return -RT_ERROR;
+ }
+ else
+ {
+ return RT_EOK;
+ }
+}
+
+static rt_err_t lcd_write_three_bytes(const rt_uint32_t da)
+{
+ rt_size_t len;
+ char data[3] = {0};
+
+ data[0] = da >> 16;
+ data[1] = da >> 8;
+ data[2] = da;
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ len = rt_spi_send(spi_dev_lcd, data, 3);
+ if (len != 3)
+ {
+ LOG_I("lcd_write_half_word error. %d", len);
+ return -RT_ERROR;
+ }
+ else
+ {
+ return RT_EOK;
+ }
+}
+
+static void lcd_gpio_init(void)
+{
+ rt_hw_lcd_config();
+
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ rt_pin_mode(LCD_DC_PIN, PIN_MODE_OUTPUT);
+ rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT);
+ rt_pin_mode(LCD_RES_PIN, PIN_MODE_OUTPUT);
+ rt_pin_write(LCD_BL_PIN, PIN_LOW);
+}
+
+int rt_hw_spi_lcd_init(void)
+{
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+ rt_hw_spi_device_attach("spi2", "spi20", GPIOI, GPIO_PIN_0);
+ lcd_gpio_init();
+
+ rt_pin_write(LCD_RES_PIN, PIN_HIGH);
+ rt_thread_mdelay(10);
+ rt_pin_write(LCD_RES_PIN, PIN_LOW);
+ rt_thread_mdelay(50);
+ rt_pin_write(LCD_RES_PIN, PIN_HIGH);
+ rt_thread_mdelay(200);
+
+ //************* Start Initial Sequence **********//
+ lcd_write_cmd(0xE0);
+ lcd_write_data(0x00);
+ lcd_write_data(0x07);
+ lcd_write_data(0x0f);
+ lcd_write_data(0x0D);
+ lcd_write_data(0x1B);
+ lcd_write_data(0x0A);
+ lcd_write_data(0x3c);
+ lcd_write_data(0x78);
+ lcd_write_data(0x4A);
+ lcd_write_data(0x07);
+ lcd_write_data(0x0E);
+ lcd_write_data(0x09);
+ lcd_write_data(0x1B);
+ lcd_write_data(0x1e);
+ lcd_write_data(0x0f);
+
+ lcd_write_cmd(0xE1);
+ lcd_write_data(0x00);
+ lcd_write_data(0x22);
+ lcd_write_data(0x24);
+ lcd_write_data(0x06);
+ lcd_write_data(0x12);
+ lcd_write_data(0x07);
+ lcd_write_data(0x36);
+ lcd_write_data(0x47);
+ lcd_write_data(0x47);
+ lcd_write_data(0x06);
+ lcd_write_data(0x0a);
+ lcd_write_data(0x07);
+ lcd_write_data(0x30);
+ lcd_write_data(0x37);
+ lcd_write_data(0x0f);
+
+ lcd_write_cmd(0xC0);
+ lcd_write_data(0x10);
+ lcd_write_data(0x10);
+
+ lcd_write_cmd(0xC1);
+ lcd_write_data(0x41);
+
+ lcd_write_cmd(0xC5);
+ lcd_write_data(0x00);
+ lcd_write_data(0x22);
+ lcd_write_data(0x80);
+
+ lcd_write_cmd(0x36);
+#ifndef LCD_HOR_SCREEN
+ lcd_write_data(0x48);
+#else
+ lcd_write_data(0x28);
+#endif
+
+ lcd_write_cmd(0x3A); //Interface Mode Control
+ lcd_write_data(0x66);
+
+ lcd_write_cmd(0XB0); //Interface Mode Control
+ lcd_write_data(0x00);
+ lcd_write_cmd(0xB1); //Frame rate 70HZ
+ lcd_write_data(0xB0);
+ lcd_write_data(0x11);
+ lcd_write_cmd(0xB4);
+ lcd_write_data(0x02);
+ lcd_write_cmd(0xB6); //RGB/MCU Interface Control
+ lcd_write_data(0x02);
+ lcd_write_data(0x02);
+
+ lcd_write_cmd(0xB7);
+ lcd_write_data(0xC6);
+
+ lcd_write_cmd(0xE9);
+ lcd_write_data(0x00);
+
+ lcd_write_cmd(0XF7);
+ lcd_write_data(0xA9);
+ lcd_write_data(0x51);
+ lcd_write_data(0x2C);
+ lcd_write_data(0x82);
+
+ lcd_fill(0, 0, LCD_WIDTH, LCD_HEIGHT, LCD_FULL_COLOR);
+
+ lcd_write_cmd(0x11);
+ rt_thread_mdelay(120);
+ lcd_write_cmd(0x29);
+
+ rt_thread_mdelay(50); //delay screen update to prevent screen appears white when the default color is black
+
+ return RT_EOK;
+}
+
+/**
+ * Set background color and foreground color
+ *
+ * @param back background color
+ * @param fore fore color
+ *
+ * @return void
+ */
+void lcd_set_color(rt_uint32_t back, rt_uint32_t fore)
+{
+ BACK_COLOR = back;
+ FORE_COLOR = fore;
+}
+
+void lcd_display_on(void)
+{
+ rt_pin_write(LCD_BL_PIN, PIN_HIGH);
+}
+
+void lcd_display_off(void)
+{
+ rt_pin_write(LCD_BL_PIN, PIN_LOW);
+}
+
+/* lcd enter the minimum power consumption mode and backlight off. */
+void lcd_enter_sleep(void)
+{
+ lcd_display_off();
+ rt_thread_mdelay(5);
+ lcd_write_cmd(0x28);
+ rt_thread_mdelay(10);
+ lcd_write_cmd(0x10);
+ rt_thread_mdelay(120);
+}
+/* lcd turn off sleep mode and backlight on. */
+void lcd_exit_sleep(void)
+{
+ lcd_display_on();
+ rt_thread_mdelay(5);
+ lcd_write_cmd(0x11);
+ rt_thread_mdelay(120);
+ lcd_write_cmd(0x29);
+}
+
+/**
+ * Set drawing area
+ *
+ * @param x1 start of x position
+ * @param y1 start of y position
+ * @param x2 end of x position
+ * @param y2 end of y position
+ *
+ * @return void
+ */
+void lcd_address_set(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+ lcd_write_cmd(0x2a);
+ lcd_write_data(x1 >> 8);
+ lcd_write_data(x1);
+ lcd_write_data(x2 >> 8);
+ lcd_write_data(x2);
+
+ lcd_write_cmd(0x2b);
+ lcd_write_data(y1 >> 8);
+ lcd_write_data(y1);
+ lcd_write_data(y2 >> 8);
+ lcd_write_data(y2);
+
+ lcd_write_cmd(0x2C);
+}
+
+/**
+ * clear the lcd.
+ *
+ * @param color Fill color
+ *
+ * @return void
+ */
+void lcd_clear(rt_uint32_t color)
+{
+ rt_uint32_t i, j;
+ rt_uint8_t data[3] = {0};
+ rt_uint8_t *buf = RT_NULL;
+
+ data[0] = color >> 16;
+ data[1] = color >> 8;
+ data[2] = color;
+ lcd_address_set(0, 0, LCD_WIDTH - 1, LCD_HEIGHT - 1);
+
+ buf = rt_malloc(LCD_BUF_SIZE);
+ if (buf)
+ {
+ /* color is 16 bit */
+ for (j = 0; j < LCD_BUF_SIZE / 3; j++)
+ {
+ buf[j * 3] = data[0];
+ buf[j * 3 + 1] = data[1];
+ buf[j * 3 + 2] = data[2];
+ }
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, buf, LCD_BUF_SIZE);
+ rt_free(buf);
+ }
+ else
+ {
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ for (i = 0; i < LCD_WIDTH; i++)
+ {
+ for (j = 0; j < LCD_HEIGHT; j++)
+ {
+ rt_spi_send(spi_dev_lcd, data, 3);
+ }
+ }
+ }
+}
+
+/**
+ * display a point on the lcd using the given colour.
+ *
+ * @param x x position
+ * @param y y position
+ * @param color color of point
+ *
+ * @return void
+ */
+void lcd_draw_point_color(rt_uint16_t x, rt_uint16_t y, rt_uint32_t color)
+{
+ lcd_address_set(x, y, x, y);
+ lcd_write_three_bytes(color);
+}
+
+/**
+ * display a point on the lcd.
+ *
+ * @param x x position
+ * @param y y position
+ *
+ * @return void
+ */
+void lcd_draw_point(rt_uint16_t x, rt_uint16_t y)
+{
+ lcd_draw_point_color(x, y, FORE_COLOR);
+}
+
+/**
+ * full color on the lcd.
+ *
+ * @param x_start start of x position
+ * @param y_start start of y position
+ * @param x_end end of x position
+ * @param y_end end of y position
+ * @param color Fill color
+ *
+ * @return void
+ */
+void lcd_fill(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, rt_uint32_t color)
+{
+ rt_uint32_t i = 0, j = 0;
+ rt_uint32_t size = 0, size_remain = 0;
+ rt_uint8_t *fill_buf = RT_NULL;
+
+ size = (x_end - x_start) * (y_end - y_start) * 3;
+
+ if (size > LCD_CLEAR_SEND_NUMBER)
+ {
+ /* the number of remaining to be filled */
+ size_remain = size - LCD_CLEAR_SEND_NUMBER;
+ size = LCD_CLEAR_SEND_NUMBER;
+ }
+
+ lcd_address_set(x_start, y_start, x_end, y_end);
+
+ fill_buf = (rt_uint8_t *)rt_malloc(LCD_CLEAR_SEND_NUMBER);
+ if (fill_buf)
+ {
+ /* fast fill */
+ while (1)
+ {
+ for (i = 0; i < size / 3; i++)
+ {
+ fill_buf[3 * i] = color >> 16;
+ fill_buf[3 * i + 1] = color >> 8;
+ fill_buf[3 * i + 2] = color;
+ }
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, fill_buf, size);
+
+ /* Fill completed */
+ if (size_remain == 0)
+ break;
+
+ /* calculate the number of fill next time */
+ if (size_remain > LCD_CLEAR_SEND_NUMBER)
+ {
+ size_remain = size_remain - LCD_CLEAR_SEND_NUMBER;
+ }
+ else
+ {
+ size = size_remain;
+ size_remain = 0;
+ }
+
+ }
+ rt_free(fill_buf);
+ }
+ else
+ {
+ for (i = y_start; i <= y_end; i++)
+ {
+ for (j = x_start; j <= x_end; j++)lcd_write_three_bytes(color);
+ }
+ }
+}
+
+/**
+ * full color array on the lcd.
+ *
+ * @param x_start start of x position
+ * @param y_start start of y position
+ * @param x_end end of x position
+ * @param y_end end of y position
+ * @param pcolor Fill color array's pointer
+ *
+ * @return void
+ */
+void lcd_fill_array(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, void *pcolor)
+{
+ rt_uint32_t size = 0;
+ rt_uint8_t *array = RT_NULL;
+
+ size = (x_end - x_start + 1) * (y_end - y_start + 1) * 3 /* 24bit */;
+ array = (rt_uint8_t *)rt_malloc(size);
+
+ if (!array) {
+ LOG_E("not enough memory");
+ return ;
+ }
+
+ rt_uint32_t *color_p = (rt_uint32_t *)pcolor;
+
+ for (rt_uint16_t i = 0; i < size / 3; i++)
+ {
+ array[3 * i] = *color_p >> 16;
+ array[3 * i + 1] = *color_p >> 8;
+ array[3 * i + 2] = *color_p;
+ color_p++;
+ }
+
+ lcd_address_set(x_start, y_start, x_end, y_end);
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, array, size);
+
+ rt_free(array);
+}
+
+/**
+ * display a line on the lcd.
+ *
+ * @param x1 x1 position
+ * @param y1 y1 position
+ * @param x2 x2 position
+ * @param y2 y2 position
+ *
+ * @return void
+ */
+void lcd_draw_line(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+ rt_uint16_t t;
+ rt_uint32_t i = 0;
+ int xerr = 0, yerr = 0, delta_x, delta_y, distance;
+ int incx, incy, row, col;
+
+ if (y1 == y2)
+ {
+ /* fast draw transverse line */
+ lcd_address_set(x1, y1, x2, y2);
+
+ rt_uint8_t line_buf[960] = {0};
+
+ for (i = 0; i < x2 - x1; i++)
+ {
+ line_buf[3 * i] = FORE_COLOR >> 16;
+ line_buf[3 * i + 1] = FORE_COLOR >> 8;
+ line_buf[3 * i + 2] = FORE_COLOR;
+ }
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, line_buf, (x2 - x1) * 3);
+
+ return ;
+ }
+
+ delta_x = x2 - x1;
+ delta_y = y2 - y1;
+ row = x1;
+ col = y1;
+ if (delta_x > 0)incx = 1;
+ else if (delta_x == 0)incx = 0;
+ else
+ {
+ incx = -1;
+ delta_x = -delta_x;
+ }
+ if (delta_y > 0)incy = 1;
+ else if (delta_y == 0)incy = 0;
+ else
+ {
+ incy = -1;
+ delta_y = -delta_y;
+ }
+ if (delta_x > delta_y)distance = delta_x;
+ else distance = delta_y;
+ for (t = 0; t <= distance + 1; t++)
+ {
+ lcd_draw_point(row, col);
+ xerr += delta_x ;
+ yerr += delta_y ;
+ if (xerr > distance)
+ {
+ xerr -= distance;
+ row += incx;
+ }
+ if (yerr > distance)
+ {
+ yerr -= distance;
+ col += incy;
+ }
+ }
+}
+
+/**
+ * display a rectangle on the lcd.
+ *
+ * @param x1 x1 position
+ * @param y1 y1 position
+ * @param x2 x2 position
+ * @param y2 y2 position
+ *
+ * @return void
+ */
+void lcd_draw_rectangle(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+ lcd_draw_line(x1, y1, x2, y1);
+ lcd_draw_line(x1, y1, x1, y2);
+ lcd_draw_line(x1, y2, x2, y2);
+ lcd_draw_line(x2, y1, x2, y2);
+}
+
+/**
+ * display a circle on the lcd.
+ *
+ * @param x x position of Center
+ * @param y y position of Center
+ * @param r radius
+ *
+ * @return void
+ */
+void lcd_draw_circle(rt_uint16_t x0, rt_uint16_t y0, rt_uint8_t r)
+{
+ int a, b;
+ int di;
+ a = 0;
+ b = r;
+ di = 3 - (r << 1);
+ while (a <= b)
+ {
+ lcd_draw_point(x0 - b, y0 - a);
+ lcd_draw_point(x0 + b, y0 - a);
+ lcd_draw_point(x0 - a, y0 + b);
+ lcd_draw_point(x0 - b, y0 - a);
+ lcd_draw_point(x0 - a, y0 - b);
+ lcd_draw_point(x0 + b, y0 + a);
+ lcd_draw_point(x0 + a, y0 - b);
+ lcd_draw_point(x0 + a, y0 + b);
+ lcd_draw_point(x0 - b, y0 + a);
+ a++;
+ //Bresenham
+ if (di < 0)di += 4 * a + 6;
+ else
+ {
+ di += 10 + 4 * (a - b);
+ b--;
+ }
+ lcd_draw_point(x0 + a, y0 + b);
+ }
+}
+
+static void lcd_show_char(rt_uint16_t x, rt_uint16_t y, rt_uint8_t data, rt_uint32_t size)
+{
+ rt_uint8_t temp;
+ rt_uint8_t num = 0;;
+ rt_uint8_t pos, t;
+ rt_uint32_t colortemp = FORE_COLOR;
+ rt_uint8_t *font_buf = RT_NULL;
+
+ if (x > LCD_WIDTH - size / 2 || y > LCD_HEIGHT - size)return;
+
+ data = data - ' ';
+#ifdef ASC2_1608
+ if (size == 16)
+ {
+ lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);//(x,y,x+8-1,y+16-1)
+
+ font_buf = (rt_uint8_t *)rt_malloc(size * size / 2 * 3);
+ if (!font_buf)
+ {
+ /* fast show char */
+ for (pos = 0; pos < size * (size / 2) / 8; pos++)
+ {
+ temp = asc2_1608[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+ for (t = 0; t < 8; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ lcd_write_three_bytes(colortemp);
+ temp <<= 1;
+ }
+ }
+ }
+ else
+ {
+ for (pos = 0; pos < size * (size / 2) / 8; pos++)
+ {
+ temp = asc2_1608[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+ for (t = 0; t < 8; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ font_buf[3 * (8 * pos + t)] = colortemp >> 16;
+ font_buf[3 * (8 * pos + t) + 1] = colortemp >> 8;
+ font_buf[3 * (8 * pos + t) + 2] = colortemp;
+ temp <<= 1;
+ }
+ }
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, font_buf, size * size / 2 * 3);
+ rt_free(font_buf);
+ }
+ }
+ else
+#endif
+
+#ifdef ASC2_2412
+ if (size == 24)
+ {
+ lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);
+
+ font_buf = (rt_uint8_t *)rt_malloc(size * size / 2 * 3);
+ if (!font_buf)
+ {
+ /* fast show char */
+ for (pos = 0; pos < (size * 16) / 8; pos++)
+ {
+ temp = asc2_2412[(rt_uint16_t)data * (size * 16) / 8 + pos];
+ if (pos % 2 == 0)
+ {
+ num = 8;
+ }
+ else
+ {
+ num = 4;
+ }
+
+ for (t = 0; t < num; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ lcd_write_three_bytes(colortemp);
+ temp <<= 1;
+ }
+ }
+ }
+ else
+ {
+ for (pos = 0; pos < (size * 16) / 8; pos++)
+ {
+ temp = asc2_2412[(rt_uint16_t)data * (size * 16) / 8 + pos];
+ if (pos % 2 == 0)
+ {
+ num = 8;
+ }
+ else
+ {
+ num = 4;
+ }
+
+ for (t = 0; t < num; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ if (num == 8)
+ {
+ font_buf[3 * (12 * (pos / 2) + t)] = colortemp >> 16;
+ font_buf[3 * (12 * (pos / 2) + t) + 1] = colortemp >> 8;
+ font_buf[3 * (12 * (pos / 2) + t) + 2] = colortemp;
+ }
+ else
+ {
+ font_buf[3 * (8 + 12 * (pos / 2) + t)] = colortemp >> 16;
+ font_buf[3 * (8 + 12 * (pos / 2) + t) + 1] = colortemp >> 8;
+ font_buf[3 * (8 + 12 * (pos / 2) + t) + 2] = colortemp;
+ }
+ temp <<= 1;
+ }
+ }
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, font_buf, size * size / 2 * 3);
+ rt_free(font_buf);
+ }
+ }
+ else
+#endif
+
+#ifdef ASC2_3216
+ if (size == 32)
+ {
+ lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);
+
+ font_buf = (rt_uint8_t *)rt_malloc(size * size / 2 * 3);
+ if (!font_buf)
+ {
+ /* fast show char */
+ for (pos = 0; pos < size * (size / 2) / 8; pos++)
+ {
+ temp = asc2_3216[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+ for (t = 0; t < 8; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ lcd_write_three_bytes(colortemp);
+ temp <<= 1;
+ }
+ }
+ }
+ else
+ {
+ for (pos = 0; pos < size * (size / 2) / 8; pos++)
+ {
+ temp = asc2_3216[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+ for (t = 0; t < 8; t++)
+ {
+ if (temp & 0x80)colortemp = FORE_COLOR;
+ else colortemp = BACK_COLOR;
+ font_buf[3 * (8 * pos + t)] = colortemp >> 16;
+ font_buf[3 * (8 * pos + t) + 1] = colortemp >> 8;
+ font_buf[3 * (8 * pos + t) + 2] = colortemp;
+ temp <<= 1;
+ }
+ }
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, font_buf, size * size / 2 * 3);
+ rt_free(font_buf);
+ }
+ }
+ else
+#endif
+ {
+ LOG_E("There is no any define ASC2_1208 && ASC2_2412 && ASC2_2416 && ASC2_3216 !");
+ }
+}
+
+/**
+ * display the number on the lcd.
+ *
+ * @param x x position
+ * @param y y position
+ * @param num number
+ * @param len length of number
+ * @param size size of font
+ *
+ * @return void
+ */
+void lcd_show_num(rt_uint16_t x, rt_uint16_t y, rt_uint32_t num, rt_uint8_t len, rt_uint32_t size)
+{
+ lcd_show_string(x, y, size, "%d", num);
+}
+
+/**
+ * display the string on the lcd.
+ *
+ * @param x x position
+ * @param y y position
+ * @param size size of font
+ * @param p the string to be display
+ *
+ * @return 0: display success
+ * -1: size of font is not support
+ */
+rt_err_t lcd_show_string(rt_uint16_t x, rt_uint16_t y, rt_uint32_t size, const char *fmt, ...)
+{
+#define LCD_STRING_BUF_LEN 128
+
+ va_list args;
+ rt_uint8_t buf[LCD_STRING_BUF_LEN] = {0};
+ rt_uint8_t *p = RT_NULL;
+
+ if (size != 16 && size != 24 && size != 32)
+ {
+ LOG_E("font size(%d) is not support!", size);
+ return -RT_ERROR;
+ }
+
+ va_start(args, fmt);
+ rt_vsnprintf((char *)buf, 100, (const char *)fmt, args);
+ va_end(args);
+
+ p = buf;
+ while (*p != '\0')
+ {
+ if (x > LCD_WIDTH - size / 2)
+ {
+ x = 0;
+ y += size;
+ }
+ if (y > LCD_HEIGHT - size)
+ {
+ y = x = 0;
+ lcd_clear(RED);
+ }
+ lcd_show_char(x, y, *p, size);
+ x += size / 2;
+ p++;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * display the image on the lcd.
+ *
+ * @param x x position
+ * @param y y position
+ * @param length length of image
+ * @param wide wide of image
+ * @param p image
+ *
+ * @return 0: display success
+ * -1: the image is too large
+ */
+rt_err_t lcd_show_image(rt_uint16_t x, rt_uint16_t y, rt_uint16_t length, rt_uint16_t wide, const rt_uint8_t *p)
+{
+ RT_ASSERT(p);
+
+ if (x + length > LCD_WIDTH || y + wide > LCD_HEIGHT)
+ {
+ return -RT_ERROR;
+ }
+
+ lcd_address_set(x, y, x + length - 1, y + wide - 1);
+
+ rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+ rt_spi_send(spi_dev_lcd, p, length * wide * 3);
+
+ return RT_EOK;
+}
+
+struct drv_lcd_device
+{
+ struct rt_device parent;
+
+ struct rt_device_graphic_info lcd_info;
+
+ struct rt_semaphore lcd_lock;
+
+ /* 0:front_buf is being used 1: back_buf is being used*/
+ rt_uint8_t cur_buf;
+ rt_uint8_t *front_buf;
+ rt_uint8_t *back_buf;
+};
+
+struct drv_lcd_device _lcd;
+
+static rt_err_t drv_lcd_init(struct rt_device *device)
+{
+ struct drv_lcd_device *lcd = LCD_DEVICE(device);
+ /* nothing, right now */
+ lcd = lcd;
+ return RT_EOK;
+}
+
+static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args)
+{
+ struct drv_lcd_device *lcd = LCD_DEVICE(device);
+ struct rt_device_rect_info *rect_info = RT_NULL;
+ uint32_t data_start_addr = 0;
+ uint32_t i = 0;
+
+ switch (cmd)
+ {
+ case RTGRAPHIC_CTRL_RECT_UPDATE:
+ {
+ /* update */
+ rect_info = (struct rt_device_rect_info *)args;
+ if(rect_info != NULL)
+ {
+ data_start_addr = rect_info->y * LCD_BYTES_PER_PIXEL * LCD_WIDTH + rect_info->x * LCD_BYTES_PER_PIXEL;
+ for(i = 0; i < rect_info->height; i++)
+ {
+ memcpy(&_lcd.front_buf[i * LCD_BYTES_PER_PIXEL * rect_info->width], &_lcd.lcd_info.framebuffer[data_start_addr + i * LCD_BYTES_PER_PIXEL * LCD_WIDTH], rect_info->width * LCD_BYTES_PER_PIXEL);
+ }
+ lcd_show_image(rect_info->x, rect_info->y, rect_info->width, rect_info->height, _lcd.front_buf);
+ }
+ else
+ {
+ memcpy(_lcd.front_buf, _lcd.lcd_info.framebuffer, LCD_BUF_SIZE);
+ lcd_show_image(0, 0, LCD_WIDTH, LCD_HEIGHT, _lcd.front_buf);
+ }
+ }
+ break;
+
+ case RTGRAPHIC_CTRL_GET_INFO:
+ {
+ struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args;
+
+ RT_ASSERT(info != RT_NULL);
+ info->pixel_format = lcd->lcd_info.pixel_format;
+ info->bits_per_pixel = lcd->lcd_info.bits_per_pixel;
+ info->width = lcd->lcd_info.width;
+ info->height = lcd->lcd_info.height;
+ info->framebuffer = lcd->lcd_info.framebuffer;
+ }
+ break;
+ }
+
+ return RT_EOK;
+}
+
+#if defined(LCD_BACKLIGHT_USING_GPIO)
+void turn_on_lcd_backlight(void)
+{
+ rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT);
+ rt_pin_write(LCD_BL_PIN, PIN_HIGH);
+}
+#else
+void turn_on_lcd_backlight(void)
+{
+
+}
+#endif
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops lcd_ops =
+{
+ drv_lcd_init,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ drv_lcd_control
+};
+#endif
+
+int drv_lcd_ili9488_hw_init(void)
+{
+ rt_err_t result = RT_EOK;
+ struct rt_device *device = &_lcd.parent;
+
+ /* memset _lcd to zero */
+ memset(&_lcd, 0x00, sizeof(_lcd));
+
+ /* init lcd_lock semaphore */
+ result = rt_sem_init(&_lcd.lcd_lock, "lcd_lock", 0, RT_IPC_FLAG_FIFO);
+ if (result != RT_EOK)
+ {
+ LOG_E("init semaphore failed!\n");
+ result = -RT_ENOMEM;
+ goto __exit;
+ }
+
+ /* config LCD dev info */
+ _lcd.lcd_info.height = LCD_HEIGHT;
+ _lcd.lcd_info.width = LCD_WIDTH;
+ _lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
+ _lcd.lcd_info.pixel_format = LCD_PIXEL_FORMAT;
+
+ /* malloc memory for double Buffering */
+ _lcd.lcd_info.framebuffer = rt_malloc(LCD_BUF_SIZE);
+ _lcd.front_buf = rt_malloc(LCD_BUF_SIZE);
+ if (_lcd.lcd_info.framebuffer == RT_NULL || _lcd.front_buf == RT_NULL)
+ {
+ LOG_E("init frame buffer failed!\n");
+ result = -RT_ENOMEM;
+ goto __exit;
+ }
+
+ /* memset buff to 0xFF */
+ memset(_lcd.lcd_info.framebuffer, 0xFF, LCD_BUF_SIZE);
+ memset(_lcd.front_buf, 0xFF, LCD_BUF_SIZE);
+
+ device->type = RT_Device_Class_Graphic;
+#ifdef RT_USING_DEVICE_OPS
+ device->ops = &lcd_ops;
+#else
+ device->init = drv_lcd_init;
+ device->control = drv_lcd_control;
+#endif
+
+ /* register lcd device */
+ rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR);
+
+ /* init spi lcd */
+ if (rt_hw_spi_lcd_init() != RT_EOK)
+ {
+ result = -RT_ERROR;
+ goto __exit;
+ }
+ else
+ {
+ turn_on_lcd_backlight();
+ }
+
+#if defined(PKG_USING_GUIENGINE)
+ rtgui_graphic_set_device(device);
+#endif
+
+__exit:
+ if (result != RT_EOK)
+ {
+ rt_sem_detach(&_lcd.lcd_lock);
+
+ if (_lcd.lcd_info.framebuffer)
+ {
+ rt_free(_lcd.lcd_info.framebuffer);
+ }
+
+ if (_lcd.back_buf)
+ {
+ rt_free(_lcd.back_buf);
+ }
+
+ if (_lcd.front_buf)
+ {
+ rt_free(_lcd.front_buf);
+ }
+ }
+ return result;
+}
+INIT_COMPONENT_EXPORT(drv_lcd_ili9488_hw_init);
+
+#ifdef DRV_DEBUG
+#ifdef FINSH_USING_MSH
+int ili9488_test()
+{
+ struct drv_lcd_device *lcd;
+ lcd = (struct drv_lcd_device *)rt_device_find("lcd");
+ struct rt_device_rect_info rect_info = {0, 0, LCD_WIDTH, LCD_HEIGHT};
+ uint32_t i = 0;
+
+ lcd_clear(WHITE);
+
+ lcd_show_image(0, 0, 240, 69, image_rttlogo);
+
+ lcd_set_color(WHITE, BLACK);
+
+ lcd_show_string(10, 69, 16, "Hello, RT-Thread!");
+ lcd_show_string(10, 69+16, 24, "RT-Thread");
+ lcd_show_string(10, 69+16+24, 32, "RT-Thread");
+
+ lcd_draw_line(0, 69+16+24+32, LCD_H, 69+16+24+32);
+
+ lcd_draw_point(160, 310);
+ for (int i = 0; i < 150; i += 4)
+ {
+ lcd_draw_circle(160, 310, i);
+ }
+
+ rt_thread_mdelay(2000);
+
+ while (1)
+ {
+ i += 10;
+ if(i >= 120)
+ {
+ i = 0;
+ }
+
+ rect_info.x = i;
+ rect_info.y = i;
+ rect_info.width =LCD_WIDTH - 2 * i;
+ rect_info.height =LCD_HEIGHT - 2 * i;
+
+ /* red */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0xFF;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0x00;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info);
+ rt_thread_mdelay(1000);
+ /* green */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0xFF;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0x00;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info);
+ rt_thread_mdelay(1000);
+ /* blue */
+ for (int i = 0; i < LCD_BUF_SIZE / 3; i++)
+ {
+ lcd->lcd_info.framebuffer[3 * i] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 1] = 0x00;
+ lcd->lcd_info.framebuffer[3 * i + 2] = 0xFF;
+ }
+ lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info);
+ rt_thread_mdelay(1000);
+ }
+}
+MSH_CMD_EXPORT(ili9488_test, test ili9488 driver);
+#endif /* FINSH_USING_MSH */
+#endif /* DRV_DEBUG */
+#endif /* BSP_USING_SPI_LCD_ILI9488 */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c
new file mode 100644
index 00000000000..cc9ad0448b4
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c
@@ -0,0 +1,1294 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-10-30 SummerGift first version
+ * 2020-03-16 SummerGift add device close feature
+ * 2020-03-20 SummerGift fix bug caused by ORE
+ * 2020-05-02 whj4674672 support stm32h7 uart dma
+ * 2020-09-09 forest-rain support stm32wl uart
+ * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
+ */
+
+#include "board.h"
+#include "drv_usart.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_SERIAL
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.usart"
+#include
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
+ !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
+ !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
+#endif
+
+/* Number of while blocking timeouts for the stm32_putc */
+#define TX_BLOCK_TIMEOUT 0x0FFFFFFF
+
+enum
+{
+#ifdef BSP_USING_UART1
+ UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+ UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+ UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+ UART4_INDEX,
+#endif
+#ifdef BSP_USING_UART5
+ UART5_INDEX,
+#endif
+#ifdef BSP_USING_UART6
+ UART6_INDEX,
+#endif
+#ifdef BSP_USING_UART7
+ UART7_INDEX,
+#endif
+#ifdef BSP_USING_UART8
+ UART8_INDEX,
+#endif
+#ifdef BSP_USING_LPUART1
+ LPUART1_INDEX,
+#endif
+};
+
+static struct stm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+ UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+ UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+ UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+ UART4_CONFIG,
+#endif
+#ifdef BSP_USING_UART5
+ UART5_CONFIG,
+#endif
+#ifdef BSP_USING_UART6
+ UART6_CONFIG,
+#endif
+#ifdef BSP_USING_UART7
+ UART7_CONFIG,
+#endif
+#ifdef BSP_USING_UART8
+ UART8_CONFIG,
+#endif
+#ifdef BSP_USING_LPUART1
+ LPUART1_CONFIG,
+#endif
+};
+
+static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
+{
+ rt_uint32_t mask = 0x00FFU;
+ if (word_length == UART_WORDLENGTH_8B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x00FFU ;
+ }
+ else
+ {
+ mask = 0x007FU ;
+ }
+ }
+#ifdef UART_WORDLENGTH_9B
+ else if (word_length == UART_WORDLENGTH_9B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x01FFU ;
+ }
+ else
+ {
+ mask = 0x00FFU ;
+ }
+ }
+#endif
+#ifdef UART_WORDLENGTH_7B
+ else if (word_length == UART_WORDLENGTH_7B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x007FU ;
+ }
+ else
+ {
+ mask = 0x003FU ;
+ }
+ }
+ else
+ {
+ mask = 0x0000U;
+ }
+#endif
+ return mask;
+}
+
+static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+ uart->handle.Instance = uart->config->Instance;
+ uart->handle.Init.BaudRate = cfg->baud_rate;
+ uart->handle.Init.Mode = UART_MODE_TX_RX;
+#ifdef USART_CR1_OVER8
+ uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16;
+#else
+ uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
+#endif /* USART_CR1_OVER8 */
+
+ switch (cfg->flowcontrol)
+ {
+ case RT_SERIAL_FLOWCONTROL_NONE:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ break;
+ case RT_SERIAL_FLOWCONTROL_CTSRTS:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
+ break;
+ default:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ break;
+ }
+
+ switch (cfg->data_bits)
+ {
+ case DATA_BITS_8:
+ if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
+ uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
+ else
+ uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+ break;
+ case DATA_BITS_9:
+ uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
+ break;
+ default:
+ uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+ break;
+ }
+
+ switch (cfg->stop_bits)
+ {
+ case STOP_BITS_1:
+ uart->handle.Init.StopBits = UART_STOPBITS_1;
+ break;
+ case STOP_BITS_2:
+ uart->handle.Init.StopBits = UART_STOPBITS_2;
+ break;
+ default:
+ uart->handle.Init.StopBits = UART_STOPBITS_1;
+ break;
+ }
+
+ switch (cfg->parity)
+ {
+ case PARITY_NONE:
+ uart->handle.Init.Parity = UART_PARITY_NONE;
+ break;
+ case PARITY_ODD:
+ uart->handle.Init.Parity = UART_PARITY_ODD;
+ break;
+ case PARITY_EVEN:
+ uart->handle.Init.Parity = UART_PARITY_EVEN;
+ break;
+ default:
+ uart->handle.Init.Parity = UART_PARITY_NONE;
+ break;
+ }
+
+#ifdef RT_SERIAL_USING_DMA
+ if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
+ uart->dma_rx.remaining_cnt = cfg->bufsz;
+ }
+#endif
+
+ if (HAL_UART_Init(&uart->handle) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+ uart->DR_mask = stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity);
+ uart->tx_block_timeout = TX_BLOCK_TIMEOUT;
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct stm32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+ rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ switch (cmd)
+ {
+ /* disable interrupt */
+ case RT_DEVICE_CTRL_CLR_INT:
+ {
+ /* disable uart irq */
+ NVIC_DisableIRQ(uart->config->irq_type);
+ rt_uint32_t direction = (rt_uint32_t)arg;
+ if(direction == RT_DEVICE_FLAG_INT_RX)
+ {
+ /* disable interrupt */
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
+ }
+
+#ifdef RT_SERIAL_USING_DMA
+ /* disable DMA */
+ if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
+ {
+ HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
+ if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+ }
+ else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
+ {
+ HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
+ if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+ }
+#endif
+ break;
+ }
+
+ /* enable interrupt */
+ case RT_DEVICE_CTRL_SET_INT:
+ {
+ /* enable uart irq */
+ HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
+ HAL_NVIC_EnableIRQ(uart->config->irq_type);
+ rt_uint32_t direction = (rt_uint32_t)arg;
+ if(direction == RT_DEVICE_FLAG_INT_RX)
+ {
+ /* enable interrupt */
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
+ }
+ break;
+ }
+
+#ifdef RT_SERIAL_USING_DMA
+ case RT_DEVICE_CTRL_CONFIG:
+ {
+ stm32_dma_config(serial, ctrl_arg);
+ break;
+ }
+#endif
+
+ case RT_DEVICE_CTRL_CLOSE:
+ {
+ if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
+ {
+ RT_ASSERT(0)
+ }
+ break;
+ }
+
+ case UART_CTRL_SET_BLOCK_TIMEOUT:
+ {
+ rt_uint32_t block_timeout = (rt_uint32_t)arg;
+ if(block_timeout > 0)
+ {
+ uart->tx_block_timeout = block_timeout;
+ }
+ else
+ {
+ return -RT_ERROR;
+ }
+ break;
+ }
+
+ default:
+ break;
+ }
+ return RT_EOK;
+}
+
+static int stm32_putc(struct rt_serial_device *serial, char c)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+ rt_uint32_t block_timeout = uart->tx_block_timeout;
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
+ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
+ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \
+ || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
+ uart->handle.Instance->TDR = c;
+#else
+ uart->handle.Instance->DR = c;
+#endif
+ while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET && --block_timeout);
+ return (block_timeout != 0) ? 1 : -1;
+}
+
+static int stm32_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ ch = -1;
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
+ {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
+ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
+ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
+ || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
+ ch = uart->handle.Instance->RDR & uart->DR_mask;
+#else
+ ch = uart->handle.Instance->DR & uart->DR_mask;
+#endif
+ }
+ return ch;
+}
+
+static rt_ssize_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ if (size == 0)
+ {
+ return 0;
+ }
+
+ if (RT_SERIAL_DMA_TX == direction)
+ {
+ if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
+ {
+ return size;
+ }
+ else
+ {
+ return 0;
+ }
+ }
+ return 0;
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
+{
+ struct stm32_uart *uart;
+ rt_base_t level;
+ rt_size_t recv_len, counter;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ level = rt_hw_interrupt_disable();
+ recv_len = 0;
+ counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
+
+ switch (isr_flag)
+ {
+ case UART_RX_DMA_IT_IDLE_FLAG:
+ if (counter <= uart->dma_rx.remaining_cnt)
+ recv_len = uart->dma_rx.remaining_cnt - counter;
+ else
+ recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
+ break;
+
+ case UART_RX_DMA_IT_HT_FLAG:
+ if (counter < uart->dma_rx.remaining_cnt)
+ recv_len = uart->dma_rx.remaining_cnt - counter;
+ break;
+
+ case UART_RX_DMA_IT_TC_FLAG:
+ if(counter >= uart->dma_rx.remaining_cnt)
+ recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter;
+
+ default:
+ break;
+ }
+
+ if (recv_len)
+ {
+ uart->dma_rx.remaining_cnt = counter;
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+ }
+ rt_hw_interrupt_enable(level);
+
+}
+
+#endif
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+ struct stm32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ /* UART in mode Receiver -------------------------------------------------*/
+ if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
+ (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
+ {
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+ }
+ else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
+ (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
+ {
+ if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
+ {
+ HAL_UART_IRQHandler(&(uart->handle));
+ }
+ else
+ {
+ /* Transmission complete interrupt disable ( CR1 Register) */
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+ }
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+ }
+#ifdef RT_SERIAL_USING_DMA
+ else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
+ && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
+ {
+ dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
+ __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
+ }
+#endif
+ else
+ {
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
+ {
+ __HAL_UART_CLEAR_OREFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
+ {
+ __HAL_UART_CLEAR_NEFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
+ {
+ __HAL_UART_CLEAR_FEFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
+ {
+ __HAL_UART_CLEAR_PEFLAG(&uart->handle);
+ }
+#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
+ && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
+ && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
+ && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS)
+#ifdef SOC_SERIES_STM32F3
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
+ }
+#else
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
+ }
+#endif
+#endif
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
+ }
+ }
+}
+
+#if defined(BSP_USING_UART1)
+void USART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART1_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
+void UART1_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
+void UART1_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void USART2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART2_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
+void UART2_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
+void UART2_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void USART3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART3_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
+void UART3_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
+void UART3_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
+#endif /* BSP_USING_UART3*/
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART4_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
+void UART4_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
+void UART4_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
+#endif /* BSP_USING_UART4*/
+
+#if defined(BSP_USING_UART5)
+void UART5_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART5_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
+void UART5_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
+void UART5_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
+#endif /* BSP_USING_UART5*/
+
+#if defined(BSP_USING_UART6)
+void USART6_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART6_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
+void UART6_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
+void UART6_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
+#endif /* BSP_USING_UART6*/
+
+#if defined(BSP_USING_UART7)
+void UART7_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART7_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
+void UART7_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
+void UART7_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
+#endif /* BSP_USING_UART7*/
+
+#if defined(BSP_USING_UART8)
+void UART8_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART8_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
+void UART8_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
+void UART8_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
+#endif /* BSP_USING_UART8*/
+
+#if defined(BSP_USING_LPUART1)
+void LPUART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[LPUART1_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
+void LPUART1_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
+#endif /* BSP_USING_LPUART1*/
+
+#if defined(SOC_SERIES_STM32G0)
+#if defined(BSP_USING_UART2)
+#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
+void USART2_LPUART2_IRQHandler(void)
+{
+ USART2_IRQHandler();
+}
+#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
+#endif /* defined(BSP_USING_UART2) */
+#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
+ || defined(BSP_USING_LPUART1)
+#if defined(STM32G070xx)
+void USART3_4_IRQHandler(void)
+#elif defined(STM32G071xx) || defined(STM32G081xx)
+void USART3_4_LPUART1_IRQHandler(void)
+#elif defined(STM32G0B0xx)
+void USART3_4_5_6_IRQHandler(void)
+#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
+void USART3_4_5_6_LPUART1_IRQHandler(void)
+#endif /* defined(STM32G070xx) */
+{
+#if defined(BSP_USING_UART3)
+ USART3_IRQHandler();
+#endif
+#if defined(BSP_USING_UART4)
+ UART4_IRQHandler();
+#endif
+#if defined(BSP_USING_UART5)
+ UART5_IRQHandler();
+#endif
+#if defined(BSP_USING_UART6)
+ USART6_IRQHandler();
+#endif
+#if defined(BSP_USING_LPUART1)
+ LPUART1_IRQHandler();
+#endif
+}
+#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
+#if defined(RT_SERIAL_USING_DMA)
+void UART_DMA_RX_TX_IRQHandler(void)
+{
+#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
+ UART1_DMA_TX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
+ UART1_DMA_RX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
+ UART2_DMA_TX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
+ UART2_DMA_RX_IRQHandler();
+#endif
+}
+#endif /* defined(RT_SERIAL_USING_DMA) */
+#endif /* defined(SOC_SERIES_STM32G0) */
+
+static void stm32_uart_get_dma_config(void)
+{
+#ifdef BSP_USING_UART1
+ uart_obj[UART1_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART1_RX_USING_DMA
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
+ uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
+#endif
+#ifdef BSP_UART1_TX_USING_DMA
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
+ uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART2
+ uart_obj[UART2_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART2_RX_USING_DMA
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
+ uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
+#endif
+#ifdef BSP_UART2_TX_USING_DMA
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
+ uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART3
+ uart_obj[UART3_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART3_RX_USING_DMA
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
+ uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
+#endif
+#ifdef BSP_UART3_TX_USING_DMA
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
+ uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART4
+ uart_obj[UART4_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART4_RX_USING_DMA
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
+ uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
+#endif
+#ifdef BSP_UART4_TX_USING_DMA
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
+ uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART5
+ uart_obj[UART5_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART5_RX_USING_DMA
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
+ uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
+#endif
+#ifdef BSP_UART5_TX_USING_DMA
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
+ uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART6
+ uart_obj[UART6_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART6_RX_USING_DMA
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
+ uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
+#endif
+#ifdef BSP_UART6_TX_USING_DMA
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
+ uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART7
+ uart_obj[UART7_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART7_RX_USING_DMA
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
+ uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
+#endif
+#ifdef BSP_UART7_TX_USING_DMA
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
+ uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART8
+ uart_obj[UART8_INDEX].uart_dma_flag = 0;
+#ifdef BSP_UART8_RX_USING_DMA
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
+ uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
+#endif
+#ifdef BSP_UART8_TX_USING_DMA
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
+ uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_LPUART1
+ uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
+#ifdef BSP_LPUART1_RX_USING_DMA
+ uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
+ uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
+#endif
+#endif
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
+{
+ struct rt_serial_rx_fifo *rx_fifo;
+ DMA_HandleTypeDef *DMA_Handle;
+ struct dma_config *dma_config;
+ struct stm32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ DMA_Handle = &uart->dma_rx.handle;
+ dma_config = uart->config->dma_rx;
+ }
+ else /* RT_DEVICE_FLAG_DMA_TX == flag */
+ {
+ DMA_Handle = &uart->dma_tx.handle;
+ dma_config = uart->config->dma_tx;
+ }
+ LOG_D("%s dma config start", uart->config->name);
+
+ {
+ rt_uint32_t tmpreg = 0x00U;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
+ || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
+ || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
+#elif defined(SOC_SERIES_STM32MP1)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
+#endif
+
+#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
+ /* enable DMAMUX clock for L4+ and G4 */
+ __HAL_RCC_DMAMUX1_CLK_ENABLE();
+#elif defined(SOC_SERIES_STM32MP1)
+ __HAL_RCC_DMAMUX_CLK_ENABLE();
+#endif
+
+ UNUSED(tmpreg); /* To avoid compiler warnings */
+ }
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
+ }
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ {
+ __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
+ }
+
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
+ DMA_Handle->Instance = dma_config->Instance;
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ DMA_Handle->Instance = dma_config->Instance;
+ DMA_Handle->Init.Channel = dma_config->channel;
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
+ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+ DMA_Handle->Instance = dma_config->Instance;
+ DMA_Handle->Init.Request = dma_config->request;
+#endif
+ DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
+ DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
+ DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ DMA_Handle->Init.Mode = DMA_CIRCULAR;
+ }
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ {
+ DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ DMA_Handle->Init.Mode = DMA_NORMAL;
+ }
+
+ DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+ DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+#endif
+ if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ /* enable interrupt */
+ if (flag == RT_DEVICE_FLAG_DMA_RX)
+ {
+ rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+ /* Start DMA transfer */
+ if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
+ {
+ /* Transfer error in reception process */
+ RT_ASSERT(0);
+ }
+ CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
+ }
+
+ /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
+ HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
+ HAL_NVIC_EnableIRQ(dma_config->dma_irq);
+
+ HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
+ HAL_NVIC_EnableIRQ(uart->config->irq_type);
+
+ LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
+ LOG_D("%s dma config done", uart->config->name);
+}
+
+/**
+ * @brief UART error callbacks
+ * @param huart: UART handle
+ * @note This example shows a simple way to report transfer error, and you can
+ * add your own implementation.
+ * @retval None
+ */
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ RT_ASSERT(huart != NULL);
+ struct stm32_uart *uart = (struct stm32_uart *)huart;
+ LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
+ UNUSED(uart);
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param huart: UART handle
+ * @note This example shows a simple way to report end of DMA Rx transfer, and
+ * you can add your own implementation.
+ * @retval None
+ */
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
+}
+
+/**
+ * @brief Rx Half transfer completed callback
+ * @param huart: UART handle
+ * @note This example shows a simple way to report end of DMA Rx Half transfer,
+ * and you can add your own implementation.
+ * @retval None
+ */
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
+}
+
+static void _dma_tx_complete(struct rt_serial_device *serial)
+{
+ struct stm32_uart *uart;
+ rt_size_t trans_total_index;
+ rt_base_t level;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ level = rt_hw_interrupt_disable();
+ trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
+ rt_hw_interrupt_enable(level);
+
+ if (trans_total_index == 0)
+ {
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+ }
+}
+
+/**
+ * @brief HAL_UART_TxCpltCallback
+ * @param huart: UART handle
+ * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
+ * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
+ * @retval None
+ */
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ _dma_tx_complete(&uart->serial);
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops stm32_uart_ops =
+{
+ .configure = stm32_configure,
+ .control = stm32_control,
+ .putc = stm32_putc,
+ .getc = stm32_getc,
+ .dma_transmit = stm32_dma_transmit
+};
+
+int rt_hw_usart_init(void)
+{
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+ rt_err_t result = 0;
+
+ stm32_uart_get_dma_config();
+
+ for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct stm32_uart); i++)
+ {
+ /* init UART object */
+ uart_obj[i].config = &uart_config[i];
+ uart_obj[i].serial.ops = &stm32_uart_ops;
+ uart_obj[i].serial.config = config;
+
+ /* register UART device */
+ result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+ RT_DEVICE_FLAG_RDWR
+ | RT_DEVICE_FLAG_INT_RX
+ | RT_DEVICE_FLAG_INT_TX
+ | uart_obj[i].uart_dma_flag
+ , NULL);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return result;
+}
+
+#endif /* RT_USING_SERIAL */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c
new file mode 100644
index 00000000000..0eed8aebc3d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c
@@ -0,0 +1,1363 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-06-01 KyleChan first version
+ */
+
+#include "board.h"
+#include "drv_usart_v2.h"
+
+#ifdef RT_USING_SERIAL_V2
+
+//#define DRV_DEBUG
+#define DBG_TAG "drv.usart"
+#ifdef DRV_DEBUG
+#define DBG_LVL DBG_LOG
+#else
+#define DBG_LVL DBG_INFO
+#endif /* DRV_DEBUG */
+#include
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
+ !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
+ !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
+ #error "Please define at least one BSP_USING_UARTx"
+ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART1
+ UART1_INDEX,
+#endif
+
+#ifdef BSP_USING_UART2
+ UART2_INDEX,
+#endif
+
+#ifdef BSP_USING_UART3
+ UART3_INDEX,
+#endif
+
+#ifdef BSP_USING_UART4
+ UART4_INDEX,
+#endif
+
+#ifdef BSP_USING_UART5
+ UART5_INDEX,
+#endif
+
+#ifdef BSP_USING_UART6
+ UART6_INDEX,
+#endif
+
+#ifdef BSP_USING_UART7
+ UART7_INDEX,
+#endif
+
+#ifdef BSP_USING_UART8
+ UART8_INDEX,
+#endif
+
+#ifdef BSP_USING_LPUART1
+ LPUART1_INDEX,
+#endif
+};
+
+static struct stm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+ UART1_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART2
+ UART2_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART3
+ UART3_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART4
+ UART4_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART5
+ UART5_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART6
+ UART6_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART7
+ UART7_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART8
+ UART8_CONFIG,
+#endif
+
+#ifdef BSP_USING_LPUART1
+ LPUART1_CONFIG,
+#endif
+};
+
+
+static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+ uart->handle.Instance = uart->config->Instance;
+ uart->handle.Init.BaudRate = cfg->baud_rate;
+ uart->handle.Init.Mode = UART_MODE_TX_RX;
+#ifdef USART_CR1_OVER8
+ uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16;
+#else
+ uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
+#endif /* USART_CR1_OVER8 */
+
+ switch (cfg->data_bits)
+ {
+ case DATA_BITS_8:
+ if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
+ uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
+ else
+ uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+ break;
+ case DATA_BITS_9:
+ uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
+ break;
+ default:
+ uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+ break;
+ }
+
+ switch (cfg->stop_bits)
+ {
+ case STOP_BITS_1:
+ uart->handle.Init.StopBits = UART_STOPBITS_1;
+ break;
+ case STOP_BITS_2:
+ uart->handle.Init.StopBits = UART_STOPBITS_2;
+ break;
+ default:
+ uart->handle.Init.StopBits = UART_STOPBITS_1;
+ break;
+ }
+
+ switch (cfg->parity)
+ {
+ case PARITY_NONE:
+ uart->handle.Init.Parity = UART_PARITY_NONE;
+ break;
+ case PARITY_ODD:
+ uart->handle.Init.Parity = UART_PARITY_ODD;
+ break;
+ case PARITY_EVEN:
+ uart->handle.Init.Parity = UART_PARITY_EVEN;
+ break;
+ default:
+ uart->handle.Init.Parity = UART_PARITY_NONE;
+ break;
+ }
+
+ switch (cfg->flowcontrol)
+ {
+ case RT_SERIAL_FLOWCONTROL_NONE:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ break;
+ case RT_SERIAL_FLOWCONTROL_CTSRTS:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
+ break;
+ default:
+ uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ break;
+ }
+
+#ifdef RT_SERIAL_USING_DMA
+ uart->dma_rx.remaining_cnt = serial->config.rx_bufsz;
+#endif
+
+ if (HAL_UART_Init(&uart->handle) != HAL_OK)
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct stm32_uart *uart;
+
+ rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
+ {
+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
+ ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
+ else
+ ctrl_arg = RT_DEVICE_FLAG_INT_RX;
+ }
+ else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
+ {
+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+ ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
+ else
+ ctrl_arg = RT_DEVICE_FLAG_INT_TX;
+ }
+
+ switch (cmd)
+ {
+ /* disable interrupt */
+ case RT_DEVICE_CTRL_CLR_INT:
+
+ NVIC_DisableIRQ(uart->config->irq_type);
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
+ else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
+#ifdef RT_SERIAL_USING_DMA
+ else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
+ {
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
+
+ HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
+ if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+ }
+ else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
+ {
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
+
+ HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
+ if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+ }
+#endif
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT:
+
+ HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
+ HAL_NVIC_EnableIRQ(uart->config->irq_type);
+
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
+ else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE);
+ break;
+
+ case RT_DEVICE_CTRL_CONFIG:
+ if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
+ {
+
+#ifdef RT_SERIAL_USING_DMA
+ stm32_dma_config(serial, ctrl_arg);
+#endif
+ }
+ else
+ stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
+ break;
+
+ case RT_DEVICE_CHECK_OPTMODE:
+ {
+ if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
+ return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
+ else
+ return RT_SERIAL_TX_BLOCKING_BUFFER;
+ }
+ case RT_DEVICE_CTRL_CLOSE:
+ if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
+ {
+ RT_ASSERT(0)
+ }
+ break;
+
+ }
+ return RT_EOK;
+}
+
+static int stm32_putc(struct rt_serial_device *serial, char c)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+ UART_SET_TDR(&uart->handle, c);
+ while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
+
+ return 1;
+}
+
+rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
+{
+ rt_uint32_t mask = 0;
+ if (word_length == UART_WORDLENGTH_8B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x00FFU ;
+ }
+ else
+ {
+ mask = 0x007FU ;
+ }
+ }
+#ifdef UART_WORDLENGTH_9B
+ else if (word_length == UART_WORDLENGTH_9B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x01FFU ;
+ }
+ else
+ {
+ mask = 0x00FFU ;
+ }
+ }
+#endif
+#ifdef UART_WORDLENGTH_7B
+ else if (word_length == UART_WORDLENGTH_7B)
+ {
+ if (parity == UART_PARITY_NONE)
+ {
+ mask = 0x007FU ;
+ }
+ else
+ {
+ mask = 0x003FU ;
+ }
+ }
+ else
+ {
+ mask = 0x0000U;
+ }
+#endif
+ return mask;
+}
+
+static int stm32_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct stm32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ ch = -1;
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
+ ch = UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity));
+ return ch;
+}
+
+static rt_ssize_t stm32_transmit(struct rt_serial_device *serial,
+ rt_uint8_t *buf,
+ rt_size_t size,
+ rt_uint32_t tx_flag)
+{
+ struct stm32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ HAL_UART_Transmit_DMA(&uart->handle, buf, size);
+ return size;
+ }
+
+ stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
+
+ return size;
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
+{
+ struct stm32_uart *uart;
+ rt_size_t recv_len, counter;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ recv_len = 0;
+ counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
+
+ if (counter <= uart->dma_rx.remaining_cnt)
+ recv_len = uart->dma_rx.remaining_cnt - counter;
+ else
+ recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter;
+ if (recv_len)
+ {
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+ SCB_InvalidateDCache_by_Addr((uint32_t *)rx_fifo->buffer, serial->config.rx_bufsz);
+#endif
+ uart->dma_rx.remaining_cnt = counter;
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+ }
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+ struct stm32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+ /* If the Read data register is not empty and the RXNE interrupt is enabled (RDR) */
+ if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
+ (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
+ {
+ struct rt_serial_rx_fifo *rx_fifo;
+ rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+ RT_ASSERT(rx_fifo != RT_NULL);
+
+ rt_ringbuffer_putchar(&(rx_fifo->rb), UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity)));
+
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+ }
+ /* If the Transmit data register is empty and the TXE interrupt enable is enabled (TDR) */
+ else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) &&
+ (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE)) != RESET)
+ {
+ struct rt_serial_tx_fifo *tx_fifo;
+ tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx;
+ RT_ASSERT(tx_fifo != RT_NULL);
+
+ rt_uint8_t put_char = 0;
+ if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char))
+ {
+ UART_SET_TDR(&uart->handle, put_char);
+ }
+ else
+ {
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TC);
+ }
+ }
+ else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
+ (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
+ {
+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ /* The HAL_UART_TxCpltCallback will be triggered */
+ HAL_UART_IRQHandler(&(uart->handle));
+ }
+ else
+ {
+ /* Transmission complete interrupt disable ( CR1 Register) */
+ __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+ }
+ /* Clear Transmission complete interrupt flag ( ISR Register ) */
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+ }
+
+#ifdef RT_SERIAL_USING_DMA
+ else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
+ && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
+ {
+ dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
+ __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
+ }
+#endif
+ else
+ {
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
+ {
+ LOG_E("(%s) serial device Overrun error!", serial->parent.parent.name);
+ __HAL_UART_CLEAR_OREFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
+ {
+ __HAL_UART_CLEAR_NEFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
+ {
+ __HAL_UART_CLEAR_FEFLAG(&uart->handle);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
+ {
+ __HAL_UART_CLEAR_PEFLAG(&uart->handle);
+ }
+#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
+ && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32H7RS) \
+ && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
+ }
+#endif
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+ }
+ if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
+ {
+ UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
+ }
+ }
+}
+
+#if defined(BSP_USING_UART1)
+void USART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART1_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
+void UART1_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
+void UART1_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void USART2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART2_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
+void UART2_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
+void UART2_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void USART3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART3_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
+void UART3_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
+void UART3_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
+#endif /* BSP_USING_UART3*/
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART4_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
+void UART4_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
+
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
+void UART4_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
+#endif /* BSP_USING_UART4*/
+
+#if defined(BSP_USING_UART5)
+void UART5_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART5_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
+void UART5_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
+void UART5_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
+#endif /* BSP_USING_UART5*/
+
+#if defined(BSP_USING_UART6)
+void USART6_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART6_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
+void UART6_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
+void UART6_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
+#endif /* BSP_USING_UART6*/
+
+#if defined(BSP_USING_UART7)
+void UART7_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART7_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
+void UART7_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
+void UART7_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
+#endif /* BSP_USING_UART7*/
+
+#if defined(BSP_USING_UART8)
+void UART8_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART8_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
+void UART8_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
+void UART8_DMA_TX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
+#endif /* BSP_USING_UART8*/
+
+#if defined(BSP_USING_LPUART1)
+void LPUART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[LPUART1_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
+void LPUART1_DMA_RX_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
+#endif /* BSP_USING_LPUART1*/
+
+#if defined(SOC_SERIES_STM32G0)
+#if defined(BSP_USING_UART2)
+#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
+void USART2_LPUART2_IRQHandler(void)
+{
+ USART2_IRQHandler();
+}
+#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */
+#endif /* defined(BSP_USING_UART2) */
+#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \
+ || defined(BSP_USING_LPUART1)
+#if defined(STM32G070xx)
+void USART3_4_IRQHandler(void)
+#elif defined(STM32G071xx) || defined(STM32G081xx)
+void USART3_4_LPUART1_IRQHandler(void)
+#elif defined(STM32G0B0xx)
+void USART3_4_5_6_IRQHandler(void)
+#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
+void USART3_4_5_6_LPUART1_IRQHandler(void)
+#endif /* defined(STM32G070xx) */
+{
+#if defined(BSP_USING_UART3)
+ USART3_IRQHandler();
+#endif
+#if defined(BSP_USING_UART4)
+ UART4_IRQHandler();
+#endif
+#if defined(BSP_USING_UART5)
+ UART5_IRQHandler();
+#endif
+#if defined(BSP_USING_UART6)
+ USART6_IRQHandler();
+#endif
+#if defined(BSP_USING_LPUART1)
+ LPUART1_IRQHandler();
+#endif
+}
+#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */
+#if defined(RT_SERIAL_USING_DMA)
+void UART_DMA_RX_TX_IRQHandler(void)
+{
+#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA)
+ UART1_DMA_TX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA)
+ UART1_DMA_RX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA)
+ UART2_DMA_TX_IRQHandler();
+#endif
+#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA)
+ UART2_DMA_RX_IRQHandler();
+#endif
+}
+#endif /* defined(RT_SERIAL_USING_DMA) */
+#endif /* defined(SOC_SERIES_STM32G0) */
+
+static void stm32_uart_get_config(void)
+{
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#ifdef BSP_USING_UART1
+ uart_obj[UART1_INDEX].serial.config = config;
+ uart_obj[UART1_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
+ uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
+
+#ifdef BSP_UART1_RX_USING_DMA
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
+ uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
+#endif
+
+#ifdef BSP_UART1_TX_USING_DMA
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
+ uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART2
+ uart_obj[UART2_INDEX].serial.config = config;
+ uart_obj[UART2_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
+ uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
+
+#ifdef BSP_UART2_RX_USING_DMA
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
+ uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
+#endif
+
+#ifdef BSP_UART2_TX_USING_DMA
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
+ uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART3
+ uart_obj[UART3_INDEX].serial.config = config;
+ uart_obj[UART3_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
+ uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
+
+#ifdef BSP_UART3_RX_USING_DMA
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
+ uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
+#endif
+
+#ifdef BSP_UART3_TX_USING_DMA
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
+ uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART4
+ uart_obj[UART4_INDEX].serial.config = config;
+ uart_obj[UART4_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
+ uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
+
+#ifdef BSP_UART4_RX_USING_DMA
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
+ uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
+#endif
+
+#ifdef BSP_UART4_TX_USING_DMA
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
+ uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART5
+ uart_obj[UART5_INDEX].serial.config = config;
+ uart_obj[UART5_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
+ uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
+
+#ifdef BSP_UART5_RX_USING_DMA
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
+ uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
+#endif
+
+#ifdef BSP_UART5_TX_USING_DMA
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
+ uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART6
+ uart_obj[UART6_INDEX].serial.config = config;
+ uart_obj[UART6_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
+ uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
+
+#ifdef BSP_UART6_RX_USING_DMA
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
+ uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
+#endif
+
+#ifdef BSP_UART6_TX_USING_DMA
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
+ uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART7
+ uart_obj[UART7_INDEX].serial.config = config;
+ uart_obj[UART7_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
+ uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
+
+#ifdef BSP_UART7_RX_USING_DMA
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
+ uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
+#endif
+
+#ifdef BSP_UART7_TX_USING_DMA
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
+ uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_UART8
+ uart_obj[UART8_INDEX].serial.config = config;
+ uart_obj[UART8_INDEX].uart_dma_flag = 0;
+
+ uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
+ uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
+
+#ifdef BSP_UART8_RX_USING_DMA
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
+ uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
+#endif
+
+#ifdef BSP_UART8_TX_USING_DMA
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+ static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
+ uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
+#endif
+#endif
+
+#ifdef BSP_USING_LPUART1
+ uart_obj[LPUART1_INDEX].serial.config = config;
+ uart_obj[LPUART1_INDEX].uart_dma_flag = 0;
+
+ uart_obj[LPUART1_INDEX].serial.config.rx_bufsz = BSP_LPUART1_RX_BUFSIZE;
+ uart_obj[LPUART1_INDEX].serial.config.tx_bufsz = BSP_LPUART1_TX_BUFSIZE;
+
+#ifdef BSP_LPUART1_RX_USING_DMA
+ uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+ static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
+ uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
+#endif
+#endif
+}
+
+#ifdef RT_SERIAL_USING_DMA
+static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
+{
+ struct rt_serial_rx_fifo *rx_fifo;
+ DMA_HandleTypeDef *DMA_Handle;
+ struct dma_config *dma_config;
+ struct stm32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
+ uart = rt_container_of(serial, struct stm32_uart, serial);
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ DMA_Handle = &uart->dma_rx.handle;
+ dma_config = uart->config->dma_rx;
+ }
+ else /* RT_DEVICE_FLAG_DMA_TX == flag */
+ {
+ DMA_Handle = &uart->dma_tx.handle;
+ dma_config = uart->config->dma_tx;
+ }
+ LOG_D("%s dma config start", uart->config->name);
+
+ {
+ rt_uint32_t tmpreg = 0x00U;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
+ || defined(SOC_SERIES_STM32L0)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
+ || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32WB)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
+#elif defined(SOC_SERIES_STM32MP1)
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
+ SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
+ tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
+#endif
+
+#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB))
+ /* enable DMAMUX clock for L4+ and G4 */
+ __HAL_RCC_DMAMUX1_CLK_ENABLE();
+#elif defined(SOC_SERIES_STM32MP1)
+ __HAL_RCC_DMAMUX_CLK_ENABLE();
+#endif
+
+ UNUSED(tmpreg); /* To avoid compiler warnings */
+ }
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
+ }
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ {
+ __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
+ }
+
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
+ DMA_Handle->Instance = dma_config->Instance;
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+ DMA_Handle->Instance = dma_config->Instance;
+ DMA_Handle->Init.Channel = dma_config->channel;
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
+ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+ DMA_Handle->Instance = dma_config->Instance;
+ DMA_Handle->Init.Request = dma_config->request;
+#elif !defined(SOC_SERIES_STM32H7RS)
+ DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
+ DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
+ DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ DMA_Handle->Init.Mode = DMA_CIRCULAR;
+ }
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ {
+ DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ DMA_Handle->Init.Mode = DMA_NORMAL;
+ }
+
+ DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
+#endif
+
+#if defined(SOC_SERIES_STM32H7RS)
+ DMA_Handle->Instance = dma_config->Instance;
+ DMA_Handle->Init.Request = dma_config->request;
+ DMA_Handle->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
+
+ DMA_Handle->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
+ DMA_Handle->Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
+ DMA_Handle->Init.Priority = DMA_LOW_PRIORITY_LOW_WEIGHT;
+ DMA_Handle->Init.SrcBurstLength = 1;
+ DMA_Handle->Init.DestBurstLength = 1;
+ DMA_Handle->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
+ DMA_Handle->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
+ {
+ DMA_Handle->Init.SrcInc = DMA_SINC_FIXED;
+ DMA_Handle->Init.DestInc = DMA_DINC_INCREMENTED;
+ DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
+ DMA_Handle->Init.Mode = DMA_NORMAL;
+ }
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ {
+ DMA_Handle->Init.SrcInc = DMA_SINC_INCREMENTED;
+ DMA_Handle->Init.DestInc = DMA_DINC_FIXED;
+ DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
+ }
+#endif /* SOC_SERIES_STM32F1 */
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+ DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+#endif
+ if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
+ {
+ RT_ASSERT(0);
+ }
+
+ /* enable interrupt */
+ if (flag == RT_DEVICE_FLAG_DMA_RX)
+ {
+ rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+ RT_ASSERT(rx_fifo != RT_NULL);
+ /* Start DMA transfer */
+ if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.rx_bufsz) != HAL_OK)
+ {
+ /* Transfer error in reception process */
+ RT_ASSERT(0);
+ }
+ CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
+ __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
+ }
+
+ /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
+ HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
+ HAL_NVIC_EnableIRQ(dma_config->dma_irq);
+
+ HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
+ HAL_NVIC_EnableIRQ(uart->config->irq_type);
+
+ LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
+ LOG_D("%s dma config done", uart->config->name);
+}
+
+/**
+ * @brief UART error callbacks
+ * @param huart: UART handle
+ * @note This example shows a simple way to report transfer error, and you can
+ * add your own implementation.
+ * @retval None
+ */
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ RT_ASSERT(huart != NULL);
+ struct stm32_uart *uart = (struct stm32_uart *)huart;
+ LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
+ UNUSED(uart);
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param huart: UART handle
+ * @note This example shows a simple way to report end of DMA Rx transfer, and
+ * you can add your own implementation.
+ * @retval None
+ */
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
+}
+
+/**
+ * @brief Rx Half transfer completed callback
+ * @param huart: UART handle
+ * @note This example shows a simple way to report end of DMA Rx Half transfer,
+ * and you can add your own implementation.
+ * @retval None
+ */
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
+}
+
+/**
+ * @brief HAL_UART_TxCpltCallback
+ * @param huart: UART handle
+ * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
+ * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
+ * @retval None
+ */
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ struct stm32_uart *uart;
+ struct rt_serial_device *serial;
+ rt_size_t trans_total_index;
+ rt_base_t level;
+
+ RT_ASSERT(huart != NULL);
+ uart = (struct stm32_uart *)huart;
+ serial = &uart->serial;
+ RT_ASSERT(serial != RT_NULL);
+
+ level = rt_hw_interrupt_disable();
+ trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
+ rt_hw_interrupt_enable(level);
+
+ if (trans_total_index) return;
+
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops stm32_uart_ops =
+{
+ .configure = stm32_configure,
+ .control = stm32_control,
+ .putc = stm32_putc,
+ .getc = stm32_getc,
+ .transmit = stm32_transmit
+};
+
+int rt_hw_usart_init(void)
+{
+ rt_err_t result = 0;
+ rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
+
+ stm32_uart_get_config();
+ for (int i = 0; i < obj_num; i++)
+ {
+ /* init UART object */
+ uart_obj[i].config = &uart_config[i];
+ uart_obj[i].serial.ops = &stm32_uart_ops;
+ /* register UART device */
+ result = rt_hw_serial_register(&uart_obj[i].serial,
+ uart_obj[i].config->name,
+ RT_DEVICE_FLAG_RDWR,
+ NULL);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return result;
+}
+
+#endif /* RT_USING_SERIAL_V2 */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usbd.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usbd.c
new file mode 100644
index 00000000000..7d980ec7237
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usbd.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-04-10 ZYH first version
+ * 2019-10-27 flybreak Compatible with the HS
+ */
+
+#include
+#include "board.h"
+
+#ifdef BSP_USING_USBD
+
+#include
+#include
+#include
+
+static PCD_HandleTypeDef _stm_pcd;
+static struct udcd _stm_udc;
+static struct ep_id _ep_pool[] =
+{
+ {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED },
+ {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
+ {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
+ {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
+ {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
+ {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
+#if !defined(SOC_SERIES_STM32F1)
+ {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
+#endif
+ {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED },
+};
+
+void USBD_IRQ_HANDLER(void)
+{
+ rt_interrupt_enter();
+ HAL_PCD_IRQHandler(&_stm_pcd);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd)
+{
+ /* open ep0 OUT and IN */
+ HAL_PCD_EP_Open(pcd, 0x00, 0x40, EP_TYPE_CTRL);
+ HAL_PCD_EP_Open(pcd, 0x80, 0x40, EP_TYPE_CTRL);
+ rt_usbd_reset_handler(&_stm_udc);
+}
+
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest *)hpcd->Setup);
+}
+
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ if (epnum == 0)
+ {
+ rt_usbd_ep0_in_handler(&_stm_udc);
+ }
+ else
+ {
+ rt_usbd_ep_in_handler(&_stm_udc, 0x80 | epnum, hpcd->IN_ep[epnum].xfer_count);
+ }
+}
+
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ rt_usbd_connect_handler(&_stm_udc);
+}
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ rt_usbd_sof_handler(&_stm_udc);
+}
+
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ rt_usbd_disconnect_handler(&_stm_udc);
+}
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ if (epnum != 0)
+ {
+ rt_usbd_ep_out_handler(&_stm_udc, epnum, hpcd->OUT_ep[epnum].xfer_count);
+ }
+ else
+ {
+ rt_usbd_ep0_out_handler(&_stm_udc, hpcd->OUT_ep[0].xfer_count);
+ }
+}
+
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+{
+ if (state == 1)
+ {
+#if defined(SOC_SERIES_STM32F1)
+ rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT);
+ rt_pin_write(BSP_USB_CONNECT_PIN, BSP_USB_PULL_UP_STATUS);
+#endif
+ }
+ else
+ {
+#if defined(SOC_SERIES_STM32F1)
+ rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT);
+ rt_pin_write(BSP_USB_CONNECT_PIN, !BSP_USB_PULL_UP_STATUS);
+#endif
+ }
+}
+
+static rt_err_t _ep_set_stall(rt_uint8_t address)
+{
+ HAL_PCD_EP_SetStall(&_stm_pcd, address);
+ return RT_EOK;
+}
+
+static rt_err_t _ep_clear_stall(rt_uint8_t address)
+{
+ HAL_PCD_EP_ClrStall(&_stm_pcd, address);
+ return RT_EOK;
+}
+
+static rt_err_t _set_address(rt_uint8_t address)
+{
+ HAL_PCD_SetAddress(&_stm_pcd, address);
+ return RT_EOK;
+}
+
+static rt_err_t _set_config(rt_uint8_t address)
+{
+ return RT_EOK;
+}
+
+static rt_err_t _ep_enable(uep_t ep)
+{
+ RT_ASSERT(ep != RT_NULL);
+ RT_ASSERT(ep->ep_desc != RT_NULL);
+ HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress,
+ ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
+ return RT_EOK;
+}
+
+static rt_err_t _ep_disable(uep_t ep)
+{
+ RT_ASSERT(ep != RT_NULL);
+ RT_ASSERT(ep->ep_desc != RT_NULL);
+ HAL_PCD_EP_Close(&_stm_pcd, ep->ep_desc->bEndpointAddress);
+ return RT_EOK;
+}
+
+static rt_size_t _ep_read(rt_uint8_t address, void *buffer)
+{
+ rt_size_t size = 0;
+ RT_ASSERT(buffer != RT_NULL);
+ return size;
+}
+
+static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+ HAL_PCD_EP_Receive(&_stm_pcd, address, buffer, size);
+ return size;
+}
+
+static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+ HAL_PCD_EP_Transmit(&_stm_pcd, address, buffer, size);
+ return size;
+}
+
+static rt_err_t _ep0_send_status(void)
+{
+ HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0);
+ return RT_EOK;
+}
+
+static rt_err_t _suspend(void)
+{
+ return RT_EOK;
+}
+
+static rt_err_t _wakeup(void)
+{
+ return RT_EOK;
+}
+
+static rt_err_t _init(rt_device_t device)
+{
+ PCD_HandleTypeDef *pcd;
+ /* Set LL Driver parameters */
+ pcd = (PCD_HandleTypeDef *)device->user_data;
+ pcd->Instance = USBD_INSTANCE;
+ memset(&pcd->Init, 0, sizeof pcd->Init);
+ pcd->Init.dev_endpoints = 8;
+ pcd->Init.speed = USBD_PCD_SPEED;
+ pcd->Init.ep0_mps = DEP0CTL_MPS_64;
+#if !defined(SOC_SERIES_STM32F1)
+ pcd->Init.phy_itface = USBD_PCD_PHY_MODULE;
+#endif
+ /* Initialize LL Driver */
+ HAL_PCD_Init(pcd);
+ /* USB interrupt Init */
+ HAL_NVIC_SetPriority(USBD_IRQ_TYPE, 2, 0);
+ HAL_NVIC_EnableIRQ(USBD_IRQ_TYPE);
+#if !defined(SOC_SERIES_STM32F1)
+ HAL_PCDEx_SetRxFiFo(pcd, 0x80);
+ HAL_PCDEx_SetTxFiFo(pcd, 0, 0x40);
+ HAL_PCDEx_SetTxFiFo(pcd, 1, 0x40);
+ HAL_PCDEx_SetTxFiFo(pcd, 2, 0x40);
+ HAL_PCDEx_SetTxFiFo(pcd, 3, 0x40);
+#else
+ HAL_PCDEx_PMAConfig(pcd, 0x00, PCD_SNG_BUF, 0x18);
+ HAL_PCDEx_PMAConfig(pcd, 0x80, PCD_SNG_BUF, 0x58);
+ HAL_PCDEx_PMAConfig(pcd, 0x81, PCD_SNG_BUF, 0x98);
+ HAL_PCDEx_PMAConfig(pcd, 0x01, PCD_SNG_BUF, 0x118);
+ HAL_PCDEx_PMAConfig(pcd, 0x82, PCD_SNG_BUF, 0xD8);
+ HAL_PCDEx_PMAConfig(pcd, 0x02, PCD_SNG_BUF, 0x158);
+ HAL_PCDEx_PMAConfig(pcd, 0x83, PCD_SNG_BUF, 0x198);
+#endif
+ HAL_PCD_Start(pcd);
+ return RT_EOK;
+}
+
+const static struct udcd_ops _udc_ops =
+{
+ _set_address,
+ _set_config,
+ _ep_set_stall,
+ _ep_clear_stall,
+ _ep_enable,
+ _ep_disable,
+ _ep_read_prepare,
+ _ep_read,
+ _ep_write,
+ _ep0_send_status,
+ _suspend,
+ _wakeup,
+};
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops _ops =
+{
+ _init,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+ RT_NULL,
+};
+#endif
+
+int stm_usbd_register(void)
+{
+ rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
+ _stm_udc.parent.type = RT_Device_Class_USBDevice;
+#ifdef RT_USING_DEVICE_OPS
+ _stm_udc.parent.ops = &_ops;
+#else
+ _stm_udc.parent.init = _init;
+#endif
+ _stm_udc.parent.user_data = &_stm_pcd;
+ _stm_udc.ops = &_udc_ops;
+ /* Register endpoint infomation */
+ _stm_udc.ep_pool = _ep_pool;
+ _stm_udc.ep0.id = &_ep_pool[0];
+#ifdef BSP_USBD_SPEED_HS
+ _stm_udc.device_is_hs = RT_TRUE;
+#endif
+ rt_device_register((rt_device_t)&_stm_udc, "usbd", 0);
+ rt_usb_device_init();
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(stm_usbd_register);
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usbh.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usbh.c
new file mode 100644
index 00000000000..80295b3aa82
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usbh.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-10-30 ZYH the first version
+ * 2019-12-19 tyustli port to stm32 series
+ */
+#include "drv_usbh.h"
+#include "board.h"
+#include
+#include
+
+#ifdef BSP_USING_USBH
+
+static HCD_HandleTypeDef stm32_hhcd_fs;
+static struct rt_completion urb_completion;
+static volatile rt_bool_t connect_status = RT_FALSE;
+
+void OTG_FS_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ HAL_HCD_IRQHandler(&stm32_hhcd_fs);
+ rt_interrupt_leave();
+}
+
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ uhcd_t hcd = (uhcd_t)hhcd->pData;
+ if (!connect_status)
+ {
+ connect_status = RT_TRUE;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n"));
+ rt_usbh_root_hub_connect_handler(hcd, OTG_FS_PORT, RT_FALSE);
+ }
+}
+
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+ uhcd_t hcd = (uhcd_t)hhcd->pData;
+ if (connect_status)
+ {
+ connect_status = RT_FALSE;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n"));
+ rt_usbh_root_hub_disconnect_handler(hcd, OTG_FS_PORT);
+ }
+}
+
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+ rt_completion_done(&urb_completion);
+}
+
+static rt_err_t drv_reset_port(rt_uint8_t port)
+{
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("reset port\n"));
+ HAL_HCD_ResetPort(&stm32_hhcd_fs);
+ return RT_EOK;
+}
+
+static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
+{
+ int timeout = timeouts;
+
+ while (1)
+ {
+ if (!connect_status)
+ {
+ return -1;
+ }
+ rt_completion_init(&urb_completion);
+ HAL_HCD_HC_SubmitRequest(&stm32_hhcd_fs,
+ pipe->pipe_index,
+ (pipe->ep.bEndpointAddress & 0x80) >> 7,
+ pipe->ep.bmAttributes,
+ token,
+ buffer,
+ nbytes,
+ 0);
+ rt_completion_wait(&urb_completion, timeout);
+ rt_thread_mdelay(1);
+ if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_NAK)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("nak\n"));
+ if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
+ {
+ rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
+ }
+ HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index);
+ HAL_HCD_HC_Init(&stm32_hhcd_fs,
+ pipe->pipe_index,
+ pipe->ep.bEndpointAddress,
+ pipe->inst->address,
+ USB_OTG_SPEED_FULL,
+ pipe->ep.bmAttributes,
+ pipe->ep.wMaxPacketSize);
+ continue;
+ }
+ else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_STALL)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("stall\n"));
+ pipe->status = UPIPE_STATUS_STALL;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ return -1;
+ }
+ else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == URB_ERROR)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error\n"));
+ pipe->status = UPIPE_STATUS_ERROR;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ return -1;
+ }
+ else if(URB_DONE == HAL_HCD_HC_GetURBState(&stm32_hhcd_fs, pipe->pipe_index))
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("ok\n"));
+ pipe->status = UPIPE_STATUS_OK;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ size_t size = HAL_HCD_HC_GetXferCount(&stm32_hhcd_fs, pipe->pipe_index);
+ if (pipe->ep.bEndpointAddress & 0x80)
+ {
+ return size;
+ }
+ else if (pipe->ep.bEndpointAddress & 0x00)
+ {
+ return size;
+ }
+ return nbytes;
+ }
+
+ continue;
+ }
+}
+
+static rt_uint16_t pipe_index = 0;
+static rt_uint8_t drv_get_free_pipe_index(void)
+{
+ rt_uint8_t idx;
+ for (idx = 1; idx < 16; idx++)
+ {
+ if (!(pipe_index & (0x01 << idx)))
+ {
+ pipe_index |= (0x01 << idx);
+ return idx;
+ }
+ }
+ return 0xff;
+}
+
+static void drv_free_pipe_index(rt_uint8_t index)
+{
+ pipe_index &= ~(0x01 << index);
+}
+
+static rt_err_t drv_open_pipe(upipe_t pipe)
+{
+ pipe->pipe_index = drv_get_free_pipe_index();
+ HAL_HCD_HC_Init(&stm32_hhcd_fs,
+ pipe->pipe_index,
+ pipe->ep.bEndpointAddress,
+ pipe->inst->address,
+ USB_OTG_SPEED_FULL,
+ pipe->ep.bmAttributes,
+ pipe->ep.wMaxPacketSize);
+ /* Set DATA0 PID token*/
+ if (stm32_hhcd_fs.hc[pipe->pipe_index].ep_is_in)
+ {
+ stm32_hhcd_fs.hc[pipe->pipe_index].toggle_in = 0;
+ }
+ else
+ {
+ stm32_hhcd_fs.hc[pipe->pipe_index].toggle_out = 0;
+ }
+ return RT_EOK;
+}
+
+static rt_err_t drv_close_pipe(upipe_t pipe)
+{
+ HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index);
+ drv_free_pipe_index(pipe->pipe_index);
+ return RT_EOK;
+}
+
+static struct uhcd_ops _uhcd_ops =
+{
+ drv_reset_port,
+ drv_pipe_xfer,
+ drv_open_pipe,
+ drv_close_pipe,
+};
+
+static rt_err_t stm32_hcd_init(rt_device_t device)
+{
+ HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)device->user_data;
+ hhcd->Instance = USB_OTG_FS;
+ hhcd->Init.Host_channels = 8;
+ hhcd->Init.speed = HCD_SPEED_FULL;
+ hhcd->Init.dma_enable = DISABLE;
+ hhcd->Init.phy_itface = HCD_PHY_EMBEDDED;
+ hhcd->Init.Sof_enable = DISABLE;
+ RT_ASSERT(HAL_HCD_Init(hhcd) == HAL_OK);
+ HAL_HCD_Start(hhcd);
+#ifdef USBH_USING_CONTROLLABLE_POWER
+ rt_pin_mode(USBH_POWER_PIN, PIN_MODE_OUTPUT);
+ rt_pin_write(USBH_POWER_PIN, PIN_LOW);
+#endif
+ return RT_EOK;
+}
+
+int stm_usbh_register(void)
+{
+ rt_err_t res = -RT_ERROR;
+
+ uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd));
+ if (uhcd == RT_NULL)
+ {
+ rt_kprintf("uhcd malloc failed\r\n");
+ return -RT_ERROR;
+ }
+
+ rt_memset((void *)uhcd, 0, sizeof(struct uhcd));
+
+ uhcd->parent.type = RT_Device_Class_USBHost;
+ uhcd->parent.init = stm32_hcd_init;
+ uhcd->parent.user_data = &stm32_hhcd_fs;
+
+ uhcd->ops = &_uhcd_ops;
+ uhcd->num_ports = OTG_FS_PORT;
+ stm32_hhcd_fs.pData = uhcd;
+
+ res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE);
+ if (res != RT_EOK)
+ {
+ rt_kprintf("register usb host failed res = %d\r\n", res);
+ return -RT_ERROR;
+ }
+
+ rt_usb_host_init();
+
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(stm_usbh_register);
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_wdt.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_wdt.c
new file mode 100644
index 00000000000..9485472adf1
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_wdt.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-07 balanceTWK first version
+ */
+
+#include
+#include
+#include
+
+#ifdef RT_USING_WDT
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.wdt"
+#include
+
+struct stm32_wdt_obj
+{
+ IWDG_HandleTypeDef hiwdg;
+ rt_uint16_t is_start;
+};
+static struct stm32_wdt_obj stm32_wdt;
+static struct rt_watchdog_ops ops;
+static rt_watchdog_t watchdog;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+ return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+ switch (cmd)
+ {
+ /* feed the watchdog */
+ case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+ if(HAL_IWDG_Refresh(&stm32_wdt.hiwdg) != HAL_OK)
+ {
+ LOG_E("watch dog keepalive fail.");
+ }
+ break;
+ /* set watchdog timeout */
+ case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+#if defined(LSI_VALUE)
+ if(LSI_VALUE)
+ {
+ stm32_wdt.hiwdg.Init.Reload = (*((rt_uint32_t*)arg)) * LSI_VALUE / 256 ;
+ }
+ else
+ {
+ LOG_E("Please define the value of LSI_VALUE!");
+ }
+ if(stm32_wdt.hiwdg.Init.Reload > 0xFFF)
+ {
+ LOG_E("wdg set timeout parameter too large, please less than %ds",0xFFF * 256 / LSI_VALUE);
+ return -RT_EINVAL;
+ }
+#else
+ #error "Please define the value of LSI_VALUE!"
+#endif
+ if(stm32_wdt.is_start)
+ {
+ if (HAL_IWDG_Init(&stm32_wdt.hiwdg) != HAL_OK)
+ {
+ LOG_E("wdg set timeout failed.");
+ return -RT_ERROR;
+ }
+ }
+ break;
+ case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+#if defined(LSI_VALUE)
+ if(LSI_VALUE)
+ {
+ (*((rt_uint32_t*)arg)) = stm32_wdt.hiwdg.Init.Reload * 256 / LSI_VALUE;
+ }
+ else
+ {
+ LOG_E("Please define the value of LSI_VALUE!");
+ }
+#else
+ #error "Please define the value of LSI_VALUE!"
+#endif
+ break;
+ case RT_DEVICE_CTRL_WDT_START:
+ if (HAL_IWDG_Init(&stm32_wdt.hiwdg) != HAL_OK)
+ {
+ LOG_E("wdt start failed.");
+ return -RT_ERROR;
+ }
+ stm32_wdt.is_start = 1;
+ break;
+ default:
+ LOG_W("This command is not supported.");
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+
+int rt_wdt_init(void)
+{
+#if defined(SOC_SERIES_STM32H7)
+ stm32_wdt.hiwdg.Instance = IWDG1;
+#else
+ stm32_wdt.hiwdg.Instance = IWDG;
+#endif
+ stm32_wdt.hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
+
+ stm32_wdt.hiwdg.Init.Reload = 0x00000FFF;
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) \
+ || defined(SOC_SERIES_STM32H7)
+ stm32_wdt.hiwdg.Init.Window = 0x00000FFF;
+#endif
+ stm32_wdt.is_start = 0;
+
+ ops.init = &wdt_init;
+ ops.control = &wdt_control;
+ watchdog.ops = &ops;
+ /* register watchdog device */
+ if (rt_hw_watchdog_register(&watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+ {
+ LOG_E("wdt device register failed.");
+ return -RT_ERROR;
+ }
+ LOG_D("wdt device register success.");
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_wdt_init);
+
+#endif /* RT_USING_WDT */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_wlan.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_wlan.c
new file mode 100644
index 00000000000..94e05bc204d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_wlan.c
@@ -0,0 +1,259 @@
+/*
+ * File : drv_wlan.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-08-30 ZeroFree the first version
+ */
+
+#include
+#include
+
+#ifdef RT_USING_WIFI
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "WLAN"
+#define DBG_COLOR
+#define DBG_LEVEL DBG_LOG
+#include
+
+#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=02:0A:F7:fe:86:1c"
+#define WIFI_IMAGE_PARTITION_NAME "wifi_image"
+#define WIFI_INIT_THREAD_STACK_SIZE (1024 * 4)
+#define WIFI_INIT_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX/2)
+#define WIFI_INIT_WAIT_TIME (rt_tick_from_millisecond(1000))
+
+extern int wifi_hw_init(void);
+static rt_bool_t init_flag = 0;
+static const struct fal_partition *partition = RT_NULL;
+
+ALIGN(64)
+static const char wifi_nvram_image[] =
+ // # The following parameter values are just placeholders, need to be updated.
+ "manfid=0x2d0" "\x00"
+ "prodid=0x0726" "\x00"
+ "vendid=0x14e4" "\x00"
+ "devid=0x43e2" "\x00"
+ "boardtype=0x0726" "\x00"
+ "boardrev=0x1101" "\x00"
+ "boardnum=22" "\x00"
+ "xtalfreq=26000" "\x00"
+ "sromrev=11" "\x00"
+ "boardflags=0x00404201" "\x00"
+ "boardflags3=0x08000000" "\x00"
+ NVRAM_GENERATED_MAC_ADDRESS "\x00"
+ "nocrc=1" "\x00"
+ "ag0=255" "\x00"
+ "aa2g=1" "\x00"
+ "ccode=ALL"
+ "\x00"
+ //#Antenna diversity
+ "swdiv_en=1" "\x00"
+ "swdiv_gpio=2" "\x00"
+
+ "pa0itssit=0x20" "\x00"
+ "extpagain2g=0" "\x00"
+ //#PA parameters for 2.4GHz, measured at CHIP OUTPUT
+ "pa2ga0=-215,5267,-656" "\x00"
+ "AvVmid_c0=0x0,0xc8" "\x00"
+ "cckpwroffset0=5" "\x00"
+ //# PPR params
+ "maxp2ga0=80" "\x00"
+ "txpwrbckof=6" "\x00"
+ "cckbw202gpo=0x6666" "\x00"
+ "legofdmbw202gpo=0xaaaaaaaa" "\x00"
+ "mcsbw202gpo=0xbbbbbbbb" "\x00"
+ "propbw202gpo=0xdd" "\x00"
+ //# OFDM IIR :
+ "ofdmdigfilttype=18" "\x00"
+ "ofdmdigfilttypebe=18" "\x00"
+ //# PAPD mode:
+ "papdmode=1" "\x00"
+ "papdvalidtest=1" "\x00"
+ "pacalidx2g=32" "\x00"
+ "papdepsoffset=-36" "\x00"
+ "papdendidx=61" "\x00"
+ //# LTECX flags
+ // "ltecxmux=1" "\x00"
+ //"ltecxpadnum=0x02030401" "\x00"
+ // "ltecxfnsel=0x3003" "\x00"
+ // "ltecxgcigpio=0x3012" "\x00"
+ //#il0macaddr=00:90:4c:c5:12:38
+ "wl0id=0x431b" "\x00"
+ "deadman_to=0xffffffff" "\x00"
+ //# muxenab: 0x1 for UART enable, 0x2 for GPIOs, 0x8 for JTAG, 0x10 for HW OOB
+ "muxenab=0x11" "\x00"
+ //# CLDO PWM voltage settings - 0x4 - 1.1 volt
+ //#cldo_pwm=0x4 "\x00"
+ //#VCO freq 326.4MHz
+ "spurconfig=0x3" "\x00"
+ "\x00\x00";
+
+int wiced_platform_resource_size(int resource)
+{
+ int size = 0;
+
+ /* Download firmware */
+ if (resource == 0)
+ {
+ size = rt_ota_get_raw_fw_size(partition);
+ }
+ else if (resource == 1)
+ {
+ size = sizeof(wifi_nvram_image);
+ }
+
+ return size;
+}
+
+int wiced_platform_resource_read(int resource, uint32_t offset, void* buffer, uint32_t buffer_size)
+{
+ if (resource == 0)
+ {
+ /* read RF firmware from partition */
+ fal_partition_read(partition, offset, buffer, buffer_size);
+ }
+ else if (resource == 1)
+ {
+ memcpy(buffer, &wifi_nvram_image[offset], buffer_size);
+ }
+
+ return buffer_size;
+}
+
+/**
+ * wait milliseconds for wifi low level initialize complete
+ *
+ * time_ms: timeout in milliseconds
+ */
+int rt_hw_wlan_wait_init_done(rt_uint32_t time_ms)
+{
+ rt_uint32_t time_cnt = 0;
+
+ /* wait wifi low level initialize complete */
+ while (time_cnt <= (time_ms / 100))
+ {
+ time_cnt++;
+ rt_thread_mdelay(100);
+ if (init_flag == 1)
+ {
+ break;
+ }
+ }
+
+ if (time_cnt > (time_ms / 100))
+ {
+ return -RT_ETIMEOUT;
+ }
+
+ return RT_EOK;
+}
+
+
+static void wifi_init_thread_entry(void *parameter)
+{
+ /* initialize fal */
+ fal_init();
+ partition = fal_partition_find(WIFI_IMAGE_PARTITION_NAME);
+
+ if (partition == RT_NULL)
+ {
+ LOG_E("%s partition is not exist, please check your configuration!", WIFI_IMAGE_PARTITION_NAME);
+ return;
+ }
+
+ { /* upgrade the wifi_image */
+ int result = 0;
+ /* verify OTA download partition */
+ if (rt_ota_init() >= 0 && rt_ota_part_fw_verify(fal_partition_find(RT_OTA_DL_PART_NAME)) >= 0)
+ {
+ /* do upgrade when check upgrade OK */
+ if (rt_ota_check_upgrade() && (result = rt_ota_upgrade()) < 0)
+ {
+ log_e("OTA upgrade failed!");
+ //TODO upgrade to safe image?
+ }
+ /* when upgrade success, erase download partition firmware.
+ * The purpose is to prevent other programs from using.
+ */
+ if (result >= 0)
+ {
+ fal_partition_erase(fal_partition_find(RT_OTA_DL_PART_NAME), 0, 4096);
+ }
+
+ }
+ }
+
+ if (rt_ota_part_fw_verify(partition) >= 0)
+ {
+ /* initialize low level wifi(ap6212) library */
+ wifi_hw_init();
+
+ /* waiting for sdio bus stability */
+ rt_thread_delay(WIFI_INIT_WAIT_TIME);
+
+ /* set wifi work mode */
+ rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+ /* NEED TODO !!! */
+ /* rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); */
+
+ init_flag = 1;
+ }
+ else
+ {
+ LOG_E("Wi-Fi image was NOT found on %s partition!", WIFI_IMAGE_PARTITION_NAME);
+ }
+}
+
+int rt_hw_wlan_init(void)
+{
+ if (init_flag == 1)
+ {
+ return RT_EOK;
+ }
+
+ rt_thread_t tid = RT_NULL;
+
+ tid = rt_thread_create("wifi_init", wifi_init_thread_entry, RT_NULL, WIFI_INIT_THREAD_STACK_SIZE, WIFI_INIT_THREAD_PRIORITY, 20);
+ if (tid)
+ {
+ rt_thread_startup(tid);
+ }
+ else
+ {
+ LOG_E("Create wifi initialization thread fail!");
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+INIT_APP_EXPORT(rt_hw_wlan_init);
+//MSH_CMD_EXPORT(rt_hw_wlan_init,rt_hw_wlan_init)
+
+static int ap6212_init(void)
+{
+#define AP6212_WL_REG_ON GET_PIN(C, 13)
+
+ /* enable the WLAN REG pin */
+ rt_pin_mode(AP6212_WL_REG_ON, PIN_MODE_OUTPUT);
+ rt_pin_write(AP6212_WL_REG_ON, PIN_HIGH);
+
+ return 0;
+}
+INIT_PREV_EXPORT(ap6212_init);
+
+#endif /* RT_USING_WIFI */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_xspi_norflash.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_xspi_norflash.c
new file mode 100644
index 00000000000..c32fb7e6157
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_xspi_norflash.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-10-11 stackyuan the first version
+ */
+
+#include
+#include
+#include
+static int rt_norflash_init(void)
+{
+// extern rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name);
+// extern int fal_init(void);
+
+// rt_hw_spi_device_attach("spi1", "spi10", GPIOA, GPIO_PIN_4);
+
+ /* initialize SPI Flash device */
+// rt_sfud_flash_probe("norflash0", "spi10");
+
+ fal_init();
+
+ return 0;
+}
+#ifndef FIRMWARE_EXEC_USING_QEMU
+INIT_ENV_EXPORT(rt_norflash_init);
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h b/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h
new file mode 100644
index 00000000000..e70e7ad171d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h
@@ -0,0 +1,53 @@
+/*
+ * File : fal_cfg.h
+ * This file is part of FAL (Flash Abstraction Layer) package
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-05-17 armink the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include
+#include
+
+#define NOR_FLASH_DEV_NAME "norflash0"
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE \
+{ \
+ &nor_flash0, \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+#define FAL_PART_TABLE \
+{ \
+ {FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME, 0, 512*1024, 0}, \
+ {FAL_PART_MAGIC_WORD, "bt_image", NOR_FLASH_DEV_NAME, 512*1024, 512*1024, 0}, \
+ {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 1024*1024, 2*1024*1024, 0}, \
+ {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 3*1024*1024, 1*1024*1024, 0}, \
+ {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c b/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c
new file mode 100644
index 00000000000..08644405175
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-13 balanceTWK add sdcard port file
+ * 2019-06-11 WillianChan Add SD card hot plug detection
+ */
+
+#include
+
+#ifdef BSP_USING_FS
+#if DFS_FILESYSTEMS_MAX < 4
+#error "Please define DFS_FILESYSTEMS_MAX more than 4"
+#endif
+#if DFS_FILESYSTEM_TYPES_MAX < 4
+#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4"
+#endif
+
+#ifdef BSP_USING_SPI_FLASH_FS
+#include "fal.h"
+#endif
+
+#include
+#include "dfs_romfs.h"
+#include "drv_sdmmc.h"
+
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include
+
+static const struct romfs_dirent _romfs_root[] = {
+ {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
+ {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}};
+
+const struct romfs_dirent romfs_root = {
+ ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])};
+
+#ifdef BSP_USING_SDCARD_FS
+
+/* SD Card hot plug detection pin */
+#define SD_CHECK_PIN GET_PIN(F, 2)
+
+static void _sdcard_mount(void)
+{
+ rt_device_t device;
+
+ device = rt_device_find("sd0");
+ if (device == NULL)
+ {
+ mmcsd_wait_cd_changed(0);
+ stm32_mmcsd_change();
+ mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+ device = rt_device_find("sd0");
+ }
+ if (device != RT_NULL)
+ {
+ if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK)
+ {
+ LOG_I("sd card mount to '/sdcard'");
+ }
+ else
+ {
+ LOG_W("sd card mount to '/sdcard' failed!");
+ }
+ }
+}
+
+static void _sdcard_unmount(void)
+{
+ rt_thread_mdelay(200);
+ dfs_unmount("/sdcard");
+ LOG_I("Unmount \"/sdcard\"");
+
+ mmcsd_wait_cd_changed(0);
+ stm32_mmcsd_change();
+ mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+}
+
+static void sd_mount(void *parameter)
+{
+ rt_uint8_t re_sd_check_pin = 1;
+ rt_thread_mdelay(200);
+ if (rt_pin_read(SD_CHECK_PIN))
+ {
+ _sdcard_mount();
+ }
+ while (1)
+ {
+ rt_thread_mdelay(200);
+ if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
+ {
+ _sdcard_mount();
+ }
+
+ if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0)
+ {
+ _sdcard_unmount();
+ }
+ }
+}
+
+#endif /* BSP_USING_SDCARD_FS */
+
+int mount_init(void)
+{
+ if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0)
+ {
+ LOG_E("rom mount to '/' failed!");
+ }
+#ifdef BSP_USING_SPI_FLASH_FS
+ struct rt_device *flash_dev = RT_NULL;
+
+#ifndef RT_USING_WIFI
+ fal_init();
+#endif
+
+ flash_dev = fal_mtd_nor_device_create("filesystem");
+
+ if (flash_dev)
+ {
+ //mount filesystem
+ if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0)
+ {
+ LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name);
+ dfs_mkfs("lfs", flash_dev->parent.name);
+ if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0)
+ {
+ LOG_I("mount to '/flash' success!");
+ }
+ }
+ else
+ {
+ LOG_I("mount to '/flash' success!");
+ }
+ }
+ else
+ {
+ LOG_E("Can't create block device filesystem or bt_image partition.");
+ }
+
+#endif
+
+#ifdef BSP_USING_SDCARD_FS
+ rt_thread_t tid;
+
+ rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
+
+ tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+ 2048, RT_THREAD_PRIORITY_MAX - 2, 20);
+ if (tid != RT_NULL)
+ {
+ rt_thread_startup(tid);
+ }
+ else
+ {
+ LOG_E("create sd_mount thread err!");
+ }
+#endif
+ return RT_EOK;
+}
+INIT_APP_EXPORT(mount_init);
+
+#endif /* BSP_USING_FS */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/adc_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/adc_config.h
new file mode 100644
index 00000000000..f3e1dc1e9a2
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/adc_config.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-06 zylx first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG \
+ { \
+ .Instance = ADC1, \
+ .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
+ .Init.Resolution = ADC_RESOLUTION_16B, \
+ .Init.ScanConvMode = ADC_SCAN_DISABLE, \
+ .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
+ .Init.LowPowerAutoWait = DISABLE, \
+ .Init.ContinuousConvMode = DISABLE, \
+ .Init.NbrOfConversion = 1, \
+ .Init.DiscontinuousConvMode = DISABLE, \
+ .Init.NbrOfDiscConversion = 1, \
+ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \
+ .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+ .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
+ .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
+ .Init.OversamplingMode = DISABLE, \
+ }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG \
+ { \
+ .Instance = ADC2, \
+ .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2, \
+ .Init.Resolution = ADC_RESOLUTION_12B, \
+ .Init.ScanConvMode = ADC_SCAN_DISABLE, \
+ .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
+ .Init.LowPowerAutoWait = DISABLE, \
+ .Init.ContinuousConvMode = DISABLE, \
+ .Init.NbrOfConversion = 1, \
+ .Init.DiscontinuousConvMode = DISABLE, \
+ .Init.NbrOfDiscConversion = 1, \
+ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \
+ .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+ .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
+ .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
+ .Init.OversamplingMode = DISABLE, \
+ }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG \
+ { \
+ .Instance = ADC3, \
+ .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2, \
+ .Init.Resolution = ADC_RESOLUTION_12B, \
+ .Init.ScanConvMode = ADC_SCAN_DISABLE, \
+ .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
+ .Init.LowPowerAutoWait = DISABLE, \
+ .Init.ContinuousConvMode = DISABLE, \
+ .Init.NbrOfConversion = 1, \
+ .Init.DiscontinuousConvMode = DISABLE, \
+ .Init.NbrOfDiscConversion = 1, \
+ .Init.ExternalTrigConv = ADC_SOFTWARE_START, \
+ .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+ .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
+ .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
+ .Init.OversamplingMode = DISABLE, \
+ }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h
new file mode 100644
index 00000000000..69095851e9b
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-01-02 zylx first version
+ * 2019-01-08 SummerGift clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* GPDMA1_Channel2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler GPDMA1_Channel2_IRQHandler
+#define UART1_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
+#define UART1_RX_DMA_INSTANCE GPDMA1_Channel2
+#define UART1_RX_DMA_REQUEST GPDMA1_REQUEST_USART1_RX
+#define UART1_RX_DMA_IRQ GPDMA1_Channel2_IRQn
+#endif
+
+/* GPDMA1_Channel */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler GPDMA1_Channel3_IRQHandler
+#define UART1_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
+#define UART1_TX_DMA_INSTANCE GPDMA1_Channel3
+#define UART1_TX_DMA_REQUEST GPDMA1_REQUEST_USART1_TX
+#define UART1_TX_DMA_IRQ GPDMA1_Channel3_IRQn
+#endif
+
+/* GPDMA1_Channel0 */
+#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_DMA_TX_IRQHandler GPDMA1_Channel0_IRQHandler
+#define UART7_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
+#define UART7_TX_DMA_INSTANCE GPDMA1_Channel0
+#define UART7_TX_DMA_REQUEST GPDMA1_REQUEST_UART7_TX
+// #define UART7_TX_DMA_CHANNEL GPDMA1_Channel0
+#define UART7_TX_DMA_IRQ GPDMA1_Channel0_IRQn
+#endif
+
+/* GPDMA1_Channel1 */
+#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler GPDMA1_Channel1_IRQHandler
+#define UART7_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN
+#define UART7_RX_DMA_INSTANCE GPDMA1_Channel1
+#define UART7_RX_DMA_REQUEST GPDMA1_REQUEST_UART7_RX
+// #define UART7_RX_DMA_CHANNEL GPDMA1_Channel11
+#define UART7_RX_DMA_IRQ GPDMA1_Channel1_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE DMA2_Stream2
+#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
+#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE DMA2_Stream7
+#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
+#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/pwm_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/pwm_config.h
new file mode 100644
index 00000000000..4d9f2818e45
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/pwm_config.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-13 zylx first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG \
+ { \
+ .tim_handle.Instance = TIM2, \
+ .name = "pwm2", \
+ .channel = 0 \
+ }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG \
+ { \
+ .tim_handle.Instance = TIM3, \
+ .name = "pwm3", \
+ .channel = 0 \
+ }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG \
+ { \
+ .tim_handle.Instance = TIM4, \
+ .name = "pwm4", \
+ .channel = 0 \
+ }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG \
+ { \
+ .tim_handle.Instance = TIM5, \
+ .name = "pwm5", \
+ .channel = 0 \
+ }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/qspi_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/qspi_config.h
new file mode 100644
index 00000000000..6affde03fd8
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/qspi_config.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-22 zylx first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG \
+ { \
+ .Instance = QUADSPI, \
+ .Init.FifoThreshold = 4, \
+ .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+ .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
+ }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG \
+ { \
+ .Instance = QSPI_DMA_INSTANCE, \
+ .Init.Channel = QSPI_DMA_CHANNEL, \
+ .Init.Direction = DMA_PERIPH_TO_MEMORY, \
+ .Init.PeriphInc = DMA_PINC_DISABLE, \
+ .Init.MemInc = DMA_MINC_ENABLE, \
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
+ .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
+ .Init.Mode = DMA_NORMAL, \
+ .Init.Priority = DMA_PRIORITY_LOW \
+ }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn QUADSPI_IRQn
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h
new file mode 100644
index 00000000000..3ddfb26a516
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-13 BalanceTWK first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include
+#include "stm32h7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG \
+ { \
+ .Instance = SDMMC1, \
+ .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
+ .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
+ .dma_rx.Instance = DMA2_Stream3, \
+ .dma_rx.channel = DMA_CHANNEL_4, \
+ .dma_rx.dma_irq = DMA2_Stream3_IRQn, \
+ .dma_tx.Instance = DMA2_Stream6, \
+ .dma_tx.channel = DMA_CHANNEL_4, \
+ .dma_tx.dma_irq = DMA2_Stream6_IRQn, \
+ }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/spi_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/spi_config.h
new file mode 100644
index 00000000000..b984ffa0f77
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/spi_config.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 SummerGift first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG \
+ { \
+ .Instance = SPI1, \
+ .bus_name = "spi1", \
+ }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI1_TX_DMA_RCC, \
+ .Instance = SPI1_TX_DMA_INSTANCE, \
+ .channel = SPI1_TX_DMA_CHANNEL, \
+ .dma_irq = SPI1_TX_DMA_IRQ, \
+ }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI1_RX_DMA_RCC, \
+ .Instance = SPI1_RX_DMA_INSTANCE, \
+ .channel = SPI1_RX_DMA_CHANNEL, \
+ .dma_irq = SPI1_RX_DMA_IRQ, \
+ }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG \
+ { \
+ .Instance = SPI2, \
+ .bus_name = "spi2", \
+ }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI2_TX_DMA_RCC, \
+ .Instance = SPI2_TX_DMA_INSTANCE, \
+ .channel = SPI2_TX_DMA_CHANNEL, \
+ .dma_irq = SPI2_TX_DMA_IRQ, \
+ }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI2_RX_DMA_RCC, \
+ .Instance = SPI2_RX_DMA_INSTANCE, \
+ .channel = SPI2_RX_DMA_CHANNEL, \
+ .dma_irq = SPI2_RX_DMA_IRQ, \
+ }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG \
+ { \
+ .Instance = SPI3, \
+ .bus_name = "spi3", \
+ }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI3_TX_DMA_RCC, \
+ .Instance = SPI3_TX_DMA_INSTANCE, \
+ .channel = SPI3_TX_DMA_CHANNEL, \
+ .dma_irq = SPI3_TX_DMA_IRQ, \
+ }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI3_RX_DMA_RCC, \
+ .Instance = SPI3_RX_DMA_INSTANCE, \
+ .channel = SPI3_RX_DMA_CHANNEL, \
+ .dma_irq = SPI3_RX_DMA_IRQ, \
+ }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG \
+ { \
+ .Instance = SPI4, \
+ .bus_name = "spi4", \
+ }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI4_TX_DMA_RCC, \
+ .Instance = SPI4_TX_DMA_INSTANCE, \
+ .channel = SPI4_TX_DMA_CHANNEL, \
+ .dma_irq = SPI4_TX_DMA_IRQ, \
+ }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI4_RX_DMA_RCC, \
+ .Instance = SPI4_RX_DMA_INSTANCE, \
+ .channel = SPI4_RX_DMA_CHANNEL, \
+ .dma_irq = SPI4_RX_DMA_IRQ, \
+ }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG \
+ { \
+ .Instance = SPI5, \
+ .bus_name = "spi5", \
+ }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI5_TX_DMA_RCC, \
+ .Instance = SPI5_TX_DMA_INSTANCE, \
+ .channel = SPI5_TX_DMA_CHANNEL, \
+ .dma_irq = SPI5_TX_DMA_IRQ, \
+ }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG \
+ { \
+ .dma_rcc = SPI5_RX_DMA_RCC, \
+ .Instance = SPI5_RX_DMA_INSTANCE, \
+ .channel = SPI5_RX_DMA_CHANNEL, \
+ .dma_irq = SPI5_RX_DMA_IRQ, \
+ }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h
new file mode 100644
index 00000000000..da318d0dde0
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-11 zylx first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG \
+ { \
+ .maxfreq = 1000000, \
+ .minfreq = 3000, \
+ .maxcnt = 0xFFFF, \
+ .cntmode = HWTIMER_CNTMODE_UP, \
+ }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG \
+ { \
+ .tim_handle.Instance = TIM13, \
+ .tim_irqn = TIM8_UP_TIM13_IRQn, \
+ .name = "timer13", \
+ }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG \
+ { \
+ .tim_handle.Instance = TIM14, \
+ .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \
+ .name = "timer14", \
+ }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h
new file mode 100644
index 00000000000..f48cab32d18
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-10-30 SummerGift first version
+ * 2019-01-03 zylx modify dma support
+ * 2020-12-08 wanghaijing Adaptive stm32h7 uart dma
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG \
+ { \
+ .name = "uart1", \
+ .Instance = USART1, \
+ .irq_type = USART1_IRQn, \
+ }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG \
+ { \
+ .Instance = UART1_RX_DMA_INSTANCE, \
+ .request = UART1_RX_DMA_REQUEST, \
+ .dma_rcc = UART1_RX_DMA_RCC, \
+ .dma_irq = UART1_RX_DMA_IRQ, \
+ }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG \
+ { \
+ .Instance = UART1_TX_DMA_INSTANCE, \
+ .request = UART1_TX_DMA_REQUEST, \
+ .dma_rcc = UART1_TX_DMA_RCC, \
+ .dma_irq = UART1_TX_DMA_IRQ, \
+ }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG \
+ { \
+ .name = "uart2", \
+ .Instance = USART2, \
+ .irq_type = USART2_IRQn, \
+ }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG \
+ { \
+ .Instance = UART2_RX_DMA_INSTANCE, \
+ .request = UART2_RX_DMA_REQUEST, \
+ .dma_rcc = UART2_RX_DMA_RCC, \
+ .dma_irq = UART2_RX_DMA_IRQ, \
+ }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG \
+ { \
+ .Instance = UART2_TX_DMA_INSTANCE, \
+ .request = UART2_TX_DMA_REQUEST, \
+ .dma_rcc = UART2_TX_DMA_RCC, \
+ .dma_irq = UART2_TX_DMA_IRQ, \
+ }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG \
+ { \
+ .name = "uart3", \
+ .Instance = USART3, \
+ .irq_type = USART3_IRQn, \
+ .tx_pin_name = BSP_UART3_TX_PIN, \
+ .rx_pin_name = BSP_UART3_RX_PIN, \
+ }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG \
+ { \
+ .Instance = UART3_RX_DMA_INSTANCE, \
+ .request = UART3_RX_DMA_REQUEST, \
+ .dma_rcc = UART3_RX_DMA_RCC, \
+ .dma_irq = UART3_RX_DMA_IRQ, \
+ }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG \
+ { \
+ .Instance = UART3_TX_DMA_INSTANCE, \
+ .request = UART3_TX_DMA_REQUEST, \
+ .dma_rcc = UART3_TX_DMA_RCC, \
+ .dma_irq = UART3_TX_DMA_IRQ, \
+ }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG \
+ { \
+ .name = "uart4", \
+ .Instance = UART4, \
+ .irq_type = UART4_IRQn, \
+ }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG \
+ { \
+ .Instance = UART4_RX_DMA_INSTANCE, \
+ .request = UART4_RX_DMA_REQUEST, \
+ .dma_rcc = UART4_RX_DMA_RCC, \
+ .dma_irq = UART4_RX_DMA_IRQ, \
+ }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG \
+ { \
+ .Instance = UART4_TX_DMA_INSTANCE, \
+ .request = UART4_TX_DMA_REQUEST, \
+ .dma_rcc = UART4_TX_DMA_RCC, \
+ .dma_irq = UART4_TX_DMA_IRQ, \
+ }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG \
+ { \
+ .name = "uart5", \
+ .Instance = UART5, \
+ .irq_type = UART5_IRQn, \
+ .tx_pin_name = BSP_UART5_TX_PIN, \
+ .rx_pin_name = BSP_UART5_RX_PIN, \
+ }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG \
+ { \
+ .Instance = UART5_RX_DMA_INSTANCE, \
+ .request = UART5_RX_DMA_REQUEST, \
+ .dma_rcc = UART5_RX_DMA_RCC, \
+ .dma_irq = UART5_RX_DMA_IRQ, \
+ }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG \
+ { \
+ .Instance = UART5_TX_DMA_INSTANCE, \
+ .request = UART5_TX_DMA_REQUEST, \
+ .dma_rcc = UART5_TX_DMA_RCC, \
+ .dma_irq = UART5_TX_DMA_IRQ, \
+ }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG \
+ { \
+ .name = "uart6", \
+ .Instance = USART6, \
+ .irq_type = USART6_IRQn, \
+ .tx_pin_name = BSP_UART6_TX_PIN, \
+ .rx_pin_name = BSP_UART6_RX_PIN, \
+ }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG \
+ { \
+ .Instance = UART6_RX_DMA_INSTANCE, \
+ .request = UART6_RX_DMA_REQUEST, \
+ .dma_rcc = UART6_RX_DMA_RCC, \
+ .dma_irq = UART6_RX_DMA_IRQ, \
+ }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG \
+ { \
+ .Instance = UART6_TX_DMA_INSTANCE, \
+ .request = UART6_TX_DMA_REQUEST, \
+ .dma_rcc = UART6_TX_DMA_RCC, \
+ .dma_irq = UART6_TX_DMA_IRQ, \
+ }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG \
+ { \
+ .name = "uart7", \
+ .Instance = UART7, \
+ .irq_type = UART7_IRQn, \
+ }
+#endif /* UART7_CONFIG */
+
+#if defined(BSP_UART7_RX_USING_DMA)
+#ifndef UART7_DMA_RX_CONFIG
+#define UART7_DMA_RX_CONFIG \
+ { \
+ .Instance = UART7_RX_DMA_INSTANCE, \
+ .request = UART7_RX_DMA_REQUEST, \
+ .dma_rcc = UART7_RX_DMA_RCC, \
+ .dma_irq = UART7_RX_DMA_IRQ, \
+ }
+#endif /* UART7_DMA_RX_CONFIG */
+#endif /* BSP_UART7_RX_USING_DMA */
+
+#if defined(BSP_UART7_TX_USING_DMA)
+#ifndef UART7_DMA_TX_CONFIG
+#define UART7_DMA_TX_CONFIG \
+ { \
+ .Instance = UART7_TX_DMA_INSTANCE, \
+ .request = UART7_TX_DMA_REQUEST, \
+ .dma_rcc = UART7_TX_DMA_RCC, \
+ .dma_irq = UART7_TX_DMA_IRQ, \
+ }
+#endif /* UART7_DMA_TX_CONFIG */
+#endif /* BSP_UART7_TX_USING_DMA */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG \
+ { \
+ .name = "uart8", \
+ .Instance = UART8, \
+ .irq_type = UART8_IRQn, \
+ .tx_pin_name = BSP_UART8_TX_PIN, \
+ .rx_pin_name = BSP_UART8_RX_PIN, \
+ }
+#endif /* UART8_CONFIG */
+
+#if defined(BSP_UART8_RX_USING_DMA)
+#ifndef UART8_DMA_RX_CONFIG
+#define UART8_DMA_RX_CONFIG \
+ { \
+ .Instance = UART8_RX_DMA_INSTANCE, \
+ .request = UART8_RX_DMA_REQUEST, \
+ .dma_rcc = UART8_RX_DMA_RCC, \
+ .dma_irq = UART8_RX_DMA_IRQ, \
+ }
+#endif /* UART8_DMA_RX_CONFIG */
+#endif /* BSP_UART8_RX_USING_DMA */
+
+#if defined(BSP_UART8_TX_USING_DMA)
+#ifndef UART8_DMA_TX_CONFIG
+#define UART8_DMA_TX_CONFIG \
+ { \
+ .Instance = UART8_TX_DMA_INSTANCE, \
+ .request = UART8_TX_DMA_REQUEST, \
+ .dma_rcc = UART8_TX_DMA_RCC, \
+ .dma_irq = UART8_TX_DMA_IRQ, \
+ }
+#endif /* UART8_DMA_TX_CONFIG */
+#endif /* BSP_UART8_TX_USING_DMA */
+#endif /* BSP_USING_UART8 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/usbd_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/usbd_config.h
new file mode 100644
index 00000000000..13727dd914b
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/usbd_config.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-04-10 ZYH first version
+ * 2019-10-27 flybreak Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE OTG_HS_IRQn
+#define USBD_IRQ_HANDLER OTG_HS_IRQHandler
+#define USBD_INSTANCE USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE OTG_FS_IRQn
+#define USBD_IRQ_HANDLER OTG_FS_IRQHandler
+#define USBD_INSTANCE USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED PCD_SPEED_HIGH
+#elif BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE PCD_PHY_ULPI
+#elif BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE PCD_PHY_EMBEDDED
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h
new file mode 100644
index 00000000000..a9276b16ab9
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-7 SummerGift first version
+ */
+
+#ifndef __DRV_COMMON_H__
+
+#define __DRV_COMMON_H__
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+void _Error_Handler(void);
+
+#ifndef Error_Handler
+#define Error_Handler(msg) _Error_Handler(msg)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#define __STM32_PORT(port) GPIO##port##_BASE
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+#define STM32_FLASH_START_ADRESS ROM_START
+#define STM32_FLASH_SIZE ROM_SIZE
+#define STM32_FLASH_END_ADDRESS ROM_END
+
+#define STM32_SRAM1_SIZE RAM_SIZE
+#define STM32_SRAM1_START RAM_START
+#define STM32_SRAM1_END RAM_END
+
+#define STM32_PSRAM_SIZE ((uint32_t)32*1024*1024)
+#define STM32_PSRAM_START ((uint32_t)0x90000000)
+#define STM32_PSRAM_END ((uint32_t)(STM32_PSRAM_START + STM32_PSRAM_SIZE))
+
+#define PSRAM_HEAP_BEGIN STM32_PSRAM_START
+#define PSRAM_HEAP_SIZE STM32_PSRAM_SIZE
+#define PSRAM_HEAP_END STM32_PSRAM_END
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__ARMCC_VERSION)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+
+#define HEAP_END STM32_SRAM1_END
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h
new file mode 100644
index 00000000000..23085d85bf2
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-10-30 SummerGift first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_STM32F0)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/tim_config.h"
+#include "config/pwm_config.h"
+#include "config/adc_config.h"
+#elif defined(SOC_SERIES_STM32F1)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/usbd_config.h"
+#include "config/pulse_encoder_config.h"
+#elif defined(SOC_SERIES_STM32F2)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#elif defined(SOC_SERIES_STM32F4)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/qspi_config.h"
+#include "config/usbd_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/pulse_encoder_config.h"
+#elif defined(SOC_SERIES_STM32F7)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/qspi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#elif defined(SOC_SERIES_STM32L0)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#elif defined(SOC_SERIES_STM32L1)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/usbd_config.h"
+#elif defined(SOC_SERIES_STM32L4)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/qspi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/usbd_config.h"
+#elif defined(SOC_SERIES_STM32G0)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/pwm_config.h"
+#elif defined(SOC_SERIES_STM32G4)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/qspi_config.h"
+#include "config/usbd_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/pulse_encoder_config.h"
+#elif defined(SOC_SERIES_STM32H7)
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/qspi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/sdio_config.h"
+#include "config/pwm_config.h"
+#include "config/usbd_config.h"
+#elif defined(SOC_SERIES_STM32H7RS)
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dcmi.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dcmi.h
new file mode 100644
index 00000000000..3ef25c7c095
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dcmi.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-27 thread-liu the first version
+ */
+
+#ifndef __DRV_DCMI_H__
+#define __DRV_DCMI_H__
+
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct rt_dcmi_device
+{
+ struct rt_device parent;
+};
+
+extern DMA_HandleTypeDef hdma_dcmi;
+extern void rt_hw_dcmi_dma_config(rt_uint32_t dst_addr1, rt_uint32_t dst_addr2, rt_uint32_t len);
+extern void DCMI_Start(void);
+extern void DCMI_Stop(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h
new file mode 100644
index 00000000000..59a9aedeb7a
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-10 SummerGift first version
+ * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
+ */
+
+#ifndef __DRV_DMA_H_
+#define __DRV_DMA_H_
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\
+ || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \
+ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
+ || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
+#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
+ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
+#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
+
+struct dma_config {
+ DMA_INSTANCE_TYPE *Instance;
+ uint32_t request;
+ rt_uint32_t dma_rcc;
+ IRQn_Type dma_irq;
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3)
+ rt_uint32_t channel;
+#endif
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
+ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5)
+ rt_uint32_t request;
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_DMA_H_ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h
new file mode 100644
index 00000000000..2252aa6ef98
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-25 zylx first version
+ * 2020-07-18 wanghaijing add SPECIAL_MODES_REG
+ */
+
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#include
+#include
+#include
+#include
+
+#define ETH_RX_BUFFER_SIZE (1536)
+#define BSP_ETH_PHY_ADDR (0x00)
+//#define BSP_ETH_USING_DEBUG
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG 0x00U
+#define PHY_RESET_MASK (1<<15)
+#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG 0x01U
+#define PHY_LINKED_STATUS_MASK (1<<2)
+#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG 0x02U
+
+/* The PHY ID two register */
+#define PHY_ID2_REG 0x03U
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG 0x04U
+
+/* The PHY SPECIAL MODES REGISTER */
+#define PHY_SPECIAL_MODES_REG 0x12U
+
+
+//#define PHY_Status_REG 0x1FU
+//#define PHY_FULL_DUPLEX_MASK (1<<4)
+#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
+#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
+#define PHY_Status_LINK_UP(sr) ((sr) & PHY_LINK_STATUS_MASK)
+
+#ifdef PHY_USING_LAN8720A
+/* The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG 0x1DU
+/* The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG 0x1EU
+#define PHY_LINK_DOWN_MASK (1<<4)
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
+
+/* The PHY status register. */
+#define PHY_Status_REG 0x1FU
+#define PHY_10M_MASK (1<<2)
+#define PHY_100M_MASK (1<<3)
+#define PHY_FULL_DUPLEX_MASK (1<<4)
+#endif /* PHY_USING_LAN8720A */
+
+#ifdef PHY_USING_DM9161CEP
+#define PHY_Status_REG 0x11U
+#define PHY_10M_MASK ((1<<12) || (1<<13))
+#define PHY_100M_MASK ((1<<14) || (1<<15))
+#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
+/* The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG 0x15U
+/* The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG 0x15U
+#define PHY_LINK_CHANGE_FLAG (1<<2)
+#define PHY_LINK_CHANGE_MASK (1<<9)
+#define PHY_INT_MASK 0
+
+#endif /* PHY_USING_DM9161CEP */
+
+#ifdef PHY_USING_DP83848C
+#define PHY_Status_REG 0x10U
+#define PHY_10M_MASK (1<<1)
+#define PHY_FULL_DUPLEX_MASK (1<<2)
+#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
+#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
+#define PHY_INTERRUPT_FLAG_REG 0x12U
+#define PHY_LINK_CHANGE_FLAG (1<<13)
+#define PHY_INTERRUPT_CTRL_REG 0x11U
+#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
+#define PHY_INTERRUPT_MASK_REG 0x12U
+#define PHY_INT_MASK (1<<5)
+#endif /* PHY_USING_DP83848C */
+
+#ifdef PHY_USING_YT8512C
+/* The PHY status register. */
+#define PHY_Status_REG 0x11U
+/* 10M这个对应的函数实际上是没有被使用的，所以下面的10M的掩码可以先随便设 */
+/* 下面定义几个的都是特殊状态寄存器的内容 */
+#define PHY_10M_MASK (1<<14)
+#define PHY_100M_MASK (1<<14)
+#define PHY_FULL_DUPLEX_MASK (1<<13)
+#define PHY_LINK_STATUS_MASK (1<<10)
+/* 中断掩码寄存器. */
+//#define PHY_INTERRUPT_MASK_REG 0x12U
+//#define PHY_LINK_CHANGE_FLAG (1<<2)
+//#define PHY_LINK_CHANGE_MASK (1<<9)
+//#define PHY_INT_MASK 0
+
+#endif /* PHY_USING_LAN8720A */
+
+#endif /* __DRV_ETH_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h
new file mode 100644
index 00000000000..52c5a80778a
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-02-24 heyuan the first version
+ * 2020-08-17 malongwei Fix something
+ */
+
+#ifndef __DRV_FDCAN_H__
+#define __DRV_FDCAN_H__
+
+#include
+#include
+
+#ifdef RT_USING_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FDCAN_FRAMEFORMAT_CLASSIC (0)
+#define BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS (1)
+#define BSP_FDCAN_FRAMEFORMAT_FD_BRS (2)
+
+enum _BSP_FDCAN_DATA_BAUD{
+ BSP_FDCAN_BAUD_DATA_2M=(2*1000*1000),
+ BSP_FDCAN_BAUD_DATA_2M5=(2500*1000),
+ BSP_FDCAN_BAUD_DATA_4M=(4*1000*1000),
+ BSP_FDCAN_BAUD_DATA_5M=(5*1000*1000)
+};
+
+#define BSP_CAN_CMD_SET_BRS_BAUD (0x30)
+
+typedef struct
+{
+ const char *name;
+ FDCAN_HandleTypeDef fdcanHandle;
+ FDCAN_RxHeaderTypeDef RxHeader;
+ FDCAN_TxHeaderTypeDef TxHeader;
+ uint8_t u8RxDataBuffer[8];
+ uint8_t u8TxDataBuufer[8];
+
+#ifdef RT_CAN_USING_HDR
+ FDCAN_FilterTypeDef FilterConfig; /*FDCAN filter*/
+ uint8_t std_filter_num;
+ uint8_t ext_filter_num;
+#endif
+
+ struct rt_can_device device; /* inherit from can device */
+} _stm32_fdcan_t;
+
+/* h7r，前面范围时仲裁/经典CAN范围，后面时数据段范围 */
+typedef struct
+{
+ uint32_t u32NBaudrate; /* <1M, ? */
+ uint16_t u16Nbrp; /* 1-512, 1-32 */
+ uint8_t u8Nsjw; /* 1-128, 1-16 */
+ uint8_t u8Ntseg1; /* 1-256, 1-32 */
+ uint8_t u8Ntseg2; /* 1-128, 1-16 */
+} _stm32_fdcan_NTconfig_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_CAN */
+#endif /* __DRV_FDCAN_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_flash.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_flash.h
new file mode 100644
index 00000000000..df26482c7e8
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_flash.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-5 SummerGift first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include
+#include "rtdevice.h"
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int stm32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_FLASH_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gc0328c.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gc0328c.h
new file mode 100644
index 00000000000..ffa0cd70571
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gc0328c.h
@@ -0,0 +1,521 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-27 thread-liu first version
+ */
+
+#ifndef __DRV_GC0328C_H__
+#define __DRV_GC0328C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+#define GC0328C_ID 0X9d
+
+const rt_uint8_t gc0328c_init_talbe[][2] = {
+ {0xFE,0x80},
+ {0xFE,0x80},
+ {0xFC,0x16},
+ {0xFC,0x16},
+ {0xFC,0x16},
+ {0xFC,0x16},
+ {0xF1,0x00},
+ {0xF2,0x00},
+ {0xFE,0x00},
+ {0x4F,0x00},
+ {0x03,0x00},
+ {0x04,0xC0},
+ {0x42,0x00},
+ {0x77,0x5A},
+ {0x78,0x40},
+ {0x79,0x56},
+ {0xFE,0x00},
+ {0x0D,0x01},
+ {0x0E,0xE8},
+ {0x0F,0x02},
+ {0x10,0x88},
+ {0x09,0x00},
+ {0x0A,0x00},
+ {0x0B,0x00},
+ {0x0C,0x00},
+ {0x16,0x00},
+ {0x17,0x14},
+ {0x18,0x0E},
+ {0x19,0x06},
+ {0x1B,0x48},
+ {0x1F,0xC8},
+ {0x20,0x01},
+ {0x21,0x78},
+ {0x22,0xB0},
+ {0x23,0x04},
+ {0x24,0x16},
+ {0x26,0x00},
+ {0x50,0x01},
+ {0x70,0x45},
+ {0x05,0x00},
+ {0x06,0xDE},
+ {0x07,0x00},
+ {0x08,0xA7},
+ {0xFE,0x01},
+ {0x29,0x00},
+ {0x2A,0x83},
+ {0x2B,0x02},
+ {0x2C,0x8F},
+ {0x2D,0x02},
+ {0x2E,0x8F},
+ {0x2F,0x02},
+ {0x30,0x8F},
+ {0x31,0x02},
+ {0x32,0x8F},
+ {0xFE,0x00},
+ {0xFE,0x01},
+ {0x50,0x00},
+ {0x4F,0x00},
+ {0x4C,0x01},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4D,0x30},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x40},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x50},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x60},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x70},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4F,0x01},
+ {0x50,0x88},
+ {0xFE,0x00},
+ {0xFE,0x00},
+ {0x27,0xB7},
+ {0x28,0x7F},
+ {0x29,0x20},
+ {0x33,0x20},
+ {0x34,0x20},
+ {0x35,0x20},
+ {0x36,0x20},
+ {0x32,0x08},
+ {0x3B,0x00},
+ {0x3C,0x00},
+ {0x3D,0x00},
+ {0x3E,0x00},
+ {0x47,0x00},
+ {0x48,0x00},
+ {0x40,0x7F},
+ {0x41,0x26},
+ {0x42,0xFB},
+ {0x44,0x26}, //02=yuv=22 26=rgb565
+ {0x45,0x00},
+ {0x46,0x03}, //HSYNC and VSYNC polarity
+ {0x49,0x23}, //first_second_switch
+ {0x4F,0x01},
+ {0x4B,0x01},
+ {0x50,0x01},
+ {0x7E,0x0A},
+ {0x7F,0x03},
+ {0x81,0x15},
+ {0x82,0x90},
+ {0x83,0x02},
+ {0x84,0xE5},
+ {0x90,0x2C},
+ {0x92,0x02},
+ {0x94,0x02},
+ {0x95,0x35},
+ {0xD1,0x24},
+ {0xD2,0x24},
+ {0xD3,0x40},
+ {0xDD,0xD3},
+ {0xDE,0x38},
+ {0xE4,0x88},
+ {0xE5,0x40},
+ {0xD7,0x0E},
+ {0xFE,0x00},
+ {0xBF,0x0E},
+ {0xC0,0x1C},
+ {0xC1,0x34},
+ {0xC2,0x48},
+ {0xC3,0x5A},
+ {0xC4,0x6E},
+ {0xC5,0x80},
+ {0xC6,0x9C},
+ {0xC7,0xB4},
+ {0xC8,0xC7},
+ {0xC9,0xD7},
+ {0xCA,0xE3},
+ {0xCB,0xED},
+ {0xCC,0xF2},
+ {0xCD,0xF8},
+ {0xCE,0xFD},
+ {0xCF,0xFF},
+ {0xFE,0x00},
+ {0x63,0x00},
+ {0x64,0x05},
+ {0x65,0x0B},
+ {0x66,0x19},
+ {0x67,0x2E},
+ {0x68,0x40},
+ {0x69,0x54},
+ {0x6A,0x66},
+ {0x6B,0x86},
+ {0x6C,0xA7},
+ {0x6D,0xC6},
+ {0x6E,0xE4},
+ {0x6F,0xFF},
+ {0xFE,0x01},
+ {0x18,0x02},
+ {0xFE,0x00},
+ {0x97,0x30},
+ {0x98,0x00},
+ {0x9B,0x60},
+ {0x9C,0x60},
+ {0xA4,0x50},
+ {0xA8,0x80},
+ {0xAA,0x40},
+ {0xA2,0x23},
+ {0xAD,0x28},
+ {0xFE,0x01},
+ {0x9C,0x00},
+ {0x9E,0xC0},
+ {0x9F,0x40},
+ {0xFE,0x01},
+ {0x08,0xA0},
+ {0x09,0xE8},
+ {0x10,0x08},
+ {0x11,0x21},
+ {0x12,0x11},
+ {0x13,0x45},
+ {0x15,0xFC},
+ {0x18,0x02},
+ {0x21,0xF0},
+ {0x22,0x60},
+ {0x23,0x30},
+ {0x25,0x00},
+ {0x24,0x14},
+ {0x3D,0x80},
+ {0x3E,0x40},
+ {0xFE,0x01},
+ {0x51,0x88},
+ {0x52,0x12},
+ {0x53,0x80},
+ {0x54,0x60},
+ {0x55,0x01},
+ {0x56,0x02},
+ {0x58,0x00},
+ {0x5B,0x02},
+ {0x5E,0xA4},
+ {0x5F,0x8A},
+ {0x61,0xDC},
+ {0x62,0xDC},
+ {0x70,0xFC},
+ {0x71,0x10},
+ {0x72,0x10},
+ {0x73,0x20},
+ {0x74,0x20},
+ {0x75,0x01},
+ {0x76,0x00},
+ {0x77,0x40},
+ {0x78,0x70},
+ {0x79,0x00},
+ {0x7B,0x00},
+ {0x7C,0x71},
+ {0x7D,0x00},
+ {0x80,0x70},
+ {0x81,0x58},
+ {0x82,0x98},
+ {0x83,0x60},
+ {0x84,0x58},
+ {0x85,0x50},
+ {0xFE,0x00},
+ {0xFE,0x01},
+ {0xC0,0x10},
+ {0xC1,0x0C},
+ {0xC2,0x0A},
+ {0xC6,0x0E},
+ {0xC7,0x0B},
+ {0xC8,0x0A},
+ {0xBA,0x26},
+ {0xBB,0x1C},
+ {0xBC,0x1D},
+ {0xB4,0x23},
+ {0xB5,0x1C},
+ {0xB6,0x1A},
+ {0xC3,0x00},
+ {0xC4,0x00},
+ {0xC5,0x00},
+ {0xC9,0x00},
+ {0xCA,0x00},
+ {0xCB,0x00},
+ {0xBD,0x00},
+ {0xBE,0x00},
+ {0xBF,0x00},
+ {0xB7,0x07},
+ {0xB8,0x05},
+ {0xB9,0x05},
+ {0xA8,0x07},
+ {0xA9,0x06},
+ {0xAA,0x00},
+ {0xAB,0x04},
+ {0xAC,0x00},
+ {0xAD,0x02},
+ {0xAE,0x0D},
+ {0xAF,0x05},
+ {0xB0,0x00},
+ {0xB1,0x07},
+ {0xB2,0x03},
+ {0xB3,0x00},
+ {0xA4,0x00},
+ {0xA5,0x00},
+ {0xA6,0x00},
+ {0xA7,0x00},
+ {0xA1,0x3C},
+ {0xA2,0x50},
+ {0xFE,0x00},
+ {0xB1,0x12},
+ {0xB2,0xF5},
+ {0xB3,0xFE},
+ {0xB4,0xE0},
+ {0xB5,0x15},
+ {0xB6,0xC8},
+ {0xFE,0x01},
+ {0x50,0x00},
+ {0xFE,0x01},
+ {0x4F,0x00},
+ {0x4C,0x01},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4F,0x00},
+ {0x4D,0x34},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x02},
+ {0x4E,0x02},
+ {0x4D,0x44},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x53},
+ {0x4E,0x08},
+ {0x4E,0x08},
+ {0x4E,0x04},
+ {0x4E,0x04},
+ {0x4D,0x65},
+ {0x4E,0x04},
+ {0x4D,0x73},
+ {0x4E,0x20},
+ {0x4D,0x83},
+ {0x4E,0x20},
+ {0x4F,0x01},
+ {0x50,0x88},
+ {0xFE,0x00},
+ {0xF1,0x07},
+ {0xF2,0x01},
+};
+
+const rt_uint8_t gc0328c_5pfs_talbe[][2] =
+{
+ // all AEC_EXP_LEVEL_X set to 0xa3c = 2620
+ {0xFE,0x01}, // page p1
+
+ {0x2B,0x0a}, // AEC_EXP_LEVEL_0 [11:8]
+ {0x2C,0x3c}, // AEC_EXP_LEVEL_0 [7:0]
+
+ {0x2D,0x0a}, // AEC_EXP_LEVEL_1
+ {0x2E,0x3c},
+
+ {0x2F,0x0a}, // AEC_EXP_LEVEL_2
+ {0x30,0x3c},
+
+ {0x31,0x0a}, // AEC_EXP_LEVEL_3
+ {0x32,0x3c},
+
+ //{0x33,0x2a}, // AEC_EXP_MIN
+ //{0x34,0x3c},
+};
+
+const rt_uint8_t gc0328c_10pfs_talbe[][2] =
+{
+ // all AEC_EXP_LEVEL_X set to 0x51e = 1310
+ {0xFE,0x01}, // page p1
+
+ {0x2B,0x05}, // AEC_EXP_LEVEL_0 [11:8]
+ {0x2C,0x1e}, // AEC_EXP_LEVEL_0 [7:0]
+
+ {0x2D,0x05}, // AEC_EXP_LEVEL_1
+ {0x2E,0x1e},
+
+ {0x2F,0x05}, // AEC_EXP_LEVEL_2
+ {0x30,0x1e},
+
+ {0x31,0x05}, // AEC_EXP_LEVEL_3
+ {0x32,0x1e},
+
+ //{0x33,0x25}, // // AEC_EXP_MIN
+ //{0x34,0x1e},
+};
+
+const rt_uint8_t gc0328c_20pfs_talbe[][2] =
+{
+ // all AEC_EXP_LEVEL_X set to 0x28f = 655
+ {0xFE,0x01}, // page p1
+
+ {0x2B,0x02}, // AEC_EXP_LEVEL_0 [11:8]
+ {0x2C,0x8f}, // AEC_EXP_LEVEL_0 [7:0]
+
+ {0x2D,0x02}, // AEC_EXP_LEVEL_1
+ {0x2E,0x8f},
+
+ {0x2F,0x02}, // AEC_EXP_LEVEL_2
+ {0x30,0x8f},
+
+ {0x31,0x02}, // AEC_EXP_LEVEL_3
+ {0x32,0x8f},
+
+ //{0x33,0x22}, // // AEC_EXP_MIN
+ //{0x34,0x8f},
+};
+
+#define GC_QVGA_USE_SUBSAMPLE 1 // the angle of view is not changed when use QVGA
+const rt_uint8_t gc0328c_QVGA_320_240_talbe[][2] =
+{
+#if (GC_QVGA_USE_SUBSAMPLE == 0) // crop window mode
+ {0xFE,0x00},
+ {0x50,0x01},
+ {0x51,0x00},
+ {0x52,0x78},
+ {0x53,0x00},
+ {0x54,0xa0},
+
+ {0x55,0x00},
+ {0x56,0xf0},
+ {0x57,0x01},
+ {0x58,0x40},
+#else
+ // subsample mode
+ {0xFE,0x00},
+ {0x59,0x22},
+
+ {0xFE,0x00},
+ {0x50,0x01},
+ {0x51,0x00},
+ {0x52,0x00},
+ {0x53,0x00},
+ {0x54,0x00},
+#endif
+
+ {0x55,0x00},
+ {0x56,0xf0},
+ {0x57,0x01},
+ {0x58,0x40},
+};
+
+const rt_uint8_t gc0328c_VGA_640_480_talbe[][2] =
+{
+#if (GC_QVGA_USE_SUBSAMPLE == 1)
+ {0xFE,0x00},
+ {0x59,0x11},
+#endif
+
+ {0xFE,0x00},
+ {0x50,0x01},
+ {0x51,0x00},
+ {0x52,0x00},
+ {0x53,0x00},
+ {0x54,0x00},
+
+ {0x55,0x01},
+ {0x56,0xe0},
+ {0x57,0x02},
+ {0x58,0x80},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h
new file mode 100644
index 00000000000..fa3c7a01f81
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-06 balanceTWK first version
+ * 2020-06-16 thread-liu add stm32mp1
+ * 2020-09-01 thread-liu add GPIOZ
+ * 2020-09-18 geniusgogo optimization design pin-index algorithm
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __STM32_PORT(port) GPIO##port##_BASE
+
+#if defined(SOC_SERIES_STM32MP1)
+#define GET_PIN(PORTx,PIN) (GPIO##PORTx == GPIOZ) ? (176 + PIN) : ((rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN))
+#else
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+#endif
+
+struct pin_irq_map
+{
+ rt_uint16_t pinbit;
+ IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lcd_font.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lcd_font.h
new file mode 100644
index 00000000000..a326936b7b9
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lcd_font.h
@@ -0,0 +1,795 @@
+#ifndef __DRV_LCD_FONT_H__
+#define __DRV_LCD_FONT_H__
+#include
+/* DejaVu Sans Mono */
+/*
+ (0) !(1) "(2) #(3) $(4) %(5) &(6) '(7)
+ ((8) )(9) *(10) +(11) ,(12) -(13) .(14) /(15)
+ 0(16) 1(17) 2(18) 3(19) 4(20) 5(21) 6(22) 7(23)
+ 8(24) 9(25) :(26) ;(27) <(28) =(29) >(30) ?(31)
+ @(32) A(33) B(34) C(35) D(36) E(37) F(38) G(39)
+ H(40) I(41) J(42) K(43) L(44) M(45) N(46) O(47)
+ P(48) Q(49) R(50) S(51) T(52) U(53) V(54) W(55)
+ X(56) Y(57) Z(58) [(59) \(60) ](61) ^(62) _(63)
+ `(64) a(65) b(66) c(67) d(68) e(69) f(70) g(71)
+ h(72) i(73) j(74) k(75) l(76) m(77) n(78) o(79)
+ p(80) q(81) r(82) s(83) t(84) u(85) v(86) w(87)
+ x(88) y(89) z(90) {(91) |(92) }(93)
+*/
+
+#define ASC2_1608
+#define ASC2_2412
+#define ASC2_3216
+
+#if !defined(ASC2_1608) && !defined(ASC2_2412) && !defined(ASC2_2416) && !defined(ASC2_3216)
+#error "There is no any define ASC2_1608 && ASC2_2412 && ASC2_2416 && ASC2_3216 !"
+#endif
+
+#ifdef ASC2_1608
+const uint8_t asc2_1608[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x10,0x10,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x28,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x12,0x12,0x16,0x7F,0x24,0x24,0xFE,0x28,0x48,0x48,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x08,0x08,0x3E,0x49,0x48,0x68,0x3E,0x0B,0x09,0x49,0x3E,0x08,0x08,0x00,/*"$",4*/
+0x00,0x00,0x00,0x60,0x90,0x90,0x62,0x0C,0x30,0x46,0x09,0x09,0x06,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x1C,0x20,0x20,0x30,0x30,0x49,0x45,0x45,0x62,0x3D,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x0C,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x00,0x00,/*"(",8*/
+0x00,0x00,0x30,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x30,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x08,0x49,0x3E,0x1C,0x6B,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x10,0xFE,0x10,0x10,0x10,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x20,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x02,0x04,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x00,/*"/",15*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x49,0x41,0x41,0x41,0x22,0x1C,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x18,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x3E,0x43,0x01,0x01,0x02,0x06,0x0C,0x10,0x20,0x7F,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x3E,0x41,0x01,0x03,0x1C,0x03,0x01,0x01,0x43,0x3E,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x06,0x0A,0x1A,0x12,0x22,0x42,0x7F,0x02,0x02,0x02,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x7E,0x40,0x40,0x7C,0x42,0x01,0x01,0x01,0x42,0x3C,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x1E,0x31,0x60,0x40,0x5E,0x63,0x41,0x41,0x23,0x1E,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x7F,0x03,0x02,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x3E,0x41,0x41,0x41,0x3E,0x63,0x41,0x41,0x63,0x3E,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x3C,0x62,0x41,0x41,0x63,0x3D,0x01,0x03,0x46,0x3C,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x10,0x20,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x01,0x0E,0x38,0x40,0x38,0x0E,0x01,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x40,0x38,0x0E,0x01,0x0E,0x38,0x40,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x38,0x44,0x04,0x0C,0x18,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x1E,0x33,0x21,0x47,0x49,0x49,0x49,0x49,0x47,0x20,0x30,0x0E,0x00,/*"@",32*/
+0x00,0x00,0x00,0x08,0x14,0x14,0x14,0x14,0x22,0x3E,0x22,0x41,0x41,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x7E,0x41,0x41,0x41,0x7E,0x43,0x41,0x41,0x43,0x7E,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x1E,0x21,0x40,0x40,0x40,0x40,0x40,0x40,0x21,0x1E,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x7C,0x42,0x41,0x41,0x41,0x41,0x41,0x41,0x42,0x7C,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x7F,0x40,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x7F,0x40,0x40,0x40,0x40,0x40,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x1E,0x21,0x40,0x40,0x40,0x43,0x41,0x41,0x21,0x1E,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x41,0x41,0x41,0x41,0x7F,0x41,0x41,0x41,0x41,0x41,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x7C,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x1C,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x44,0x38,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x42,0x44,0x48,0x50,0x70,0x78,0x48,0x44,0x46,0x42,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x63,0x63,0x55,0x55,0x55,0x49,0x41,0x41,0x41,0x41,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x61,0x61,0x51,0x51,0x49,0x49,0x45,0x45,0x43,0x43,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1C,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x7E,0x43,0x41,0x41,0x43,0x7E,0x40,0x40,0x40,0x40,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1E,0x06,0x02,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x7E,0x43,0x41,0x41,0x43,0x7C,0x42,0x41,0x41,0x40,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x1E,0x61,0x40,0x40,0x30,0x0E,0x01,0x01,0x43,0x3E,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x63,0x3E,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x41,0x41,0x22,0x22,0x22,0x14,0x14,0x14,0x14,0x08,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x81,0x81,0x81,0x5A,0x5A,0x5A,0x66,0x66,0x66,0x66,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x41,0x22,0x14,0x14,0x08,0x14,0x14,0x22,0x22,0x41,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x82,0x44,0x44,0x28,0x38,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x7F,0x03,0x02,0x04,0x08,0x08,0x10,0x20,0x60,0x7F,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x1C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x1C,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x40,0x20,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x04,0x02,0x00,/*"\",60*/
+0x00,0x00,0x38,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x38,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x10,0x28,0x44,0xC6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,/*"_",63*/
+0x00,0x30,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x1C,0x22,0x02,0x3E,0x42,0x42,0x46,0x3A,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x40,0x40,0x40,0x7C,0x64,0x42,0x42,0x42,0x42,0x64,0x5C,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x1C,0x22,0x40,0x40,0x40,0x40,0x22,0x1C,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x02,0x02,0x02,0x3E,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x26,0x42,0x7E,0x40,0x40,0x22,0x1C,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x0C,0x10,0x10,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x3A,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x02,0x22,0x1C,/*"g",71*/
+0x00,0x00,0x40,0x40,0x40,0x5C,0x62,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x10,0x10,0x00,0x70,0x10,0x10,0x10,0x10,0x10,0x10,0x7C,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x08,0x08,0x00,0x38,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x70,/*"j",74*/
+0x00,0x00,0x40,0x40,0x40,0x44,0x48,0x50,0x70,0x48,0x48,0x44,0x42,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x70,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x0E,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x7E,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x5C,0x62,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x66,0x42,0x42,0x42,0x42,0x66,0x3C,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x5C,0x64,0x42,0x42,0x42,0x42,0x64,0x7C,0x40,0x40,0x40,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x3A,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x02,0x02,0x02,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x32,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x40,0x70,0x0E,0x02,0x42,0x3C,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x10,0x10,0x7E,0x10,0x10,0x10,0x10,0x10,0x10,0x0E,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x46,0x3A,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x42,0x24,0x24,0x24,0x18,0x18,0x18,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x81,0x81,0x5A,0x5A,0x5A,0x5A,0x24,0x24,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x24,0x18,0x18,0x18,0x24,0x24,0x42,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x22,0x24,0x24,0x14,0x18,0x18,0x08,0x08,0x10,0x30,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x7E,0x02,0x04,0x08,0x10,0x20,0x40,0x7E,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x0C,0x10,0x10,0x10,0x10,0x10,0x60,0x10,0x10,0x10,0x10,0x10,0x0C,0x00,/*"{",91*/
+0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,/*"|",92*/
+0x00,0x00,0x60,0x10,0x10,0x10,0x10,0x10,0x0C,0x10,0x10,0x10,0x10,0x10,0x60,0x00,/*"}",93*/
+};
+#endif
+
+#ifdef ASC2_2412
+const uint8_t asc2_2412[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x19,0x80,0x19,0x80,
+0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x60,0x04,0x40,0x0C,0xC0,0x0C,0xC0,
+0x7F,0xF0,0x7F,0xF0,0x08,0x80,0x19,0x80,0x19,0x80,0xFF,0xE0,0xFF,0xE0,0x33,0x00,
+0x33,0x00,0x22,0x00,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x02,0x00,0x0F,0x80,0x1F,0xC0,0x3A,0x40,
+0x32,0x00,0x32,0x00,0x3A,0x00,0x1F,0x00,0x07,0xC0,0x02,0xE0,0x02,0x60,0x02,0x60,
+0x22,0xE0,0x3F,0xC0,0x1F,0x80,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,/*"$",4*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x48,0x00,0xCC,0x00,0xCC,0x00,
+0xCC,0x00,0x48,0x40,0x79,0xC0,0x0E,0x00,0x73,0xC0,0x02,0x40,0x06,0x60,0x06,0x60,
+0x06,0x60,0x02,0x40,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0x80,0x18,0x00,0x18,0x00,
+0x18,0x00,0x0C,0x00,0x1E,0x00,0x36,0x30,0x63,0x30,0x63,0xB0,0x61,0xA0,0x60,0xE0,
+0x30,0xC0,0x3F,0x60,0x0E,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x02,0x00,0x02,0x00,0x06,0x00,0x06,0x00,
+0x04,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x04,0x00,0x06,0x00,0x06,0x00,0x02,0x00,0x02,0x00,0x01,0x00,0x00,0x00,0x00,0x00,/*"(",8*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
+0x02,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x02,0x00,0x06,0x00,0x06,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x00,0x44,0x40,0x35,0x80,
+0x0E,0x00,0x0E,0x00,0x35,0x80,0x44,0x40,0x04,0x00,0x04,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x7F,0xE0,0x7F,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x1F,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0xC0,0x00,0xC0,0x01,0x80,
+0x01,0x80,0x03,0x00,0x03,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,
+0x18,0x00,0x18,0x00,0x30,0x00,0x30,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"/",15*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,0x00,0x3F,0x80,0x31,0x80,0x71,0xC0,
+0x60,0xC0,0x60,0xC0,0x66,0xC0,0x66,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x71,0xC0,
+0x31,0x80,0x3F,0x80,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x1F,0x00,0x1B,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x1F,0xE0,0x1F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x7F,0x80,0x41,0xC0,0x00,0xC0,
+0x00,0xC0,0x00,0xC0,0x01,0xC0,0x01,0x80,0x03,0x00,0x06,0x00,0x0C,0x00,0x18,0x00,
+0x30,0x00,0x7F,0xC0,0x7F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x7F,0x80,0x41,0xC0,0x00,0xC0,
+0x00,0xC0,0x01,0xC0,0x0F,0x80,0x0F,0x80,0x01,0x80,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x41,0xC0,0x7F,0x80,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x07,0x80,0x05,0x80,
+0x0D,0x80,0x09,0x80,0x19,0x80,0x31,0x80,0x31,0x80,0x61,0x80,0x7F,0xE0,0x7F,0xE0,
+0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x80,0x3F,0x80,0x30,0x00,0x30,0x00,
+0x30,0x00,0x3F,0x00,0x3F,0x80,0x21,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x41,0x80,0x7F,0x80,0x3E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x1F,0x80,0x38,0x80,0x30,0x00,
+0x70,0x00,0x60,0x00,0x6F,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xC0,0x7F,0xC0,0x01,0x80,0x01,0x80,
+0x01,0x80,0x03,0x00,0x03,0x00,0x03,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x3F,0x80,0x71,0xC0,0x60,0xC0,
+0x60,0xC0,0x31,0x80,0x1F,0x00,0x3F,0x80,0x31,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x3F,0x80,0x71,0x80,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x71,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x00,0xC0,0x01,0x80,
+0x23,0x80,0x3F,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,
+0x01,0xE0,0x07,0x80,0x1E,0x00,0x70,0x00,0x70,0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,
+0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,
+0x78,0x00,0x1E,0x00,0x07,0x80,0x00,0xE0,0x00,0xE0,0x07,0x80,0x1E,0x00,0x78,0x00,
+0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0xC0,0x10,0x60,0x00,0x60,
+0x00,0xE0,0x01,0xC0,0x03,0x80,0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x18,0xC0,0x30,0x60,
+0x30,0x60,0x23,0xE0,0x62,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,
+0x62,0x60,0x33,0xE0,0x30,0x00,0x18,0x00,0x1C,0x00,0x07,0x80,0x00,0x00,0x00,0x00,/*"@",32*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x0F,0x00,0x0F,0x00,
+0x0F,0x00,0x1F,0x80,0x19,0x80,0x19,0x80,0x19,0x80,0x3F,0xC0,0x3F,0xC0,0x30,0xC0,
+0x30,0xC0,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x7F,0x80,0x61,0xC0,0x60,0xC0,
+0x60,0xC0,0x61,0xC0,0x7F,0x80,0x7F,0x80,0x60,0xC0,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0xE0,0x7F,0xC0,0x7F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x1F,0xE0,0x38,0x20,0x30,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x30,0x00,
+0x38,0x20,0x1F,0xE0,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x7F,0x80,0x61,0xC0,0x60,0xC0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0xC0,
+0x61,0xC0,0x7F,0x80,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x7F,0xC0,0x7F,0xC0,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0xC0,0x38,0x40,0x30,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x61,0xE0,0x61,0xE0,0x60,0x60,0x60,0x60,0x30,0x60,
+0x38,0x60,0x1F,0xE0,0x0F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x7F,0xE0,0x7F,0xE0,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xC0,0x3F,0xC0,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x3F,0xC0,0x3F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x1F,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x43,0x80,0x7F,0x00,0x3E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0xC0,0x61,0x80,0x63,0x00,
+0x66,0x00,0x6C,0x00,0x7C,0x00,0x7E,0x00,0x76,0x00,0x63,0x00,0x63,0x80,0x61,0x80,
+0x60,0xC0,0x60,0xE0,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x70,0xE0,0x70,0xE0,0x79,0xE0,
+0x69,0x60,0x69,0x60,0x6F,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x60,0x70,0x60,0x78,0x60,0x78,0x60,
+0x6C,0x60,0x6C,0x60,0x64,0x60,0x66,0x60,0x62,0x60,0x63,0x60,0x63,0x60,0x61,0xE0,
+0x61,0xE0,0x60,0xE0,0x60,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x3F,0xC0,0x30,0xC0,0x70,0xE0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x70,0xE0,
+0x30,0xC0,0x3F,0xC0,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x80,0x7F,0xC0,0x60,0xE0,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0xE0,0x7F,0xC0,0x7F,0x80,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x3F,0xC0,0x30,0xC0,0x70,0xE0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x70,0xE0,
+0x30,0xC0,0x1F,0x80,0x0F,0x00,0x01,0x80,0x00,0xC0,0x00,0x80,0x00,0x00,0x00,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x7F,0xC0,0x60,0xE0,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0xC0,0x7F,0xC0,0x7F,0x80,0x61,0xC0,0x60,0xC0,0x60,0x60,
+0x60,0x60,0x60,0x30,0x60,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x3F,0xC0,0x70,0x40,0x60,0x00,
+0x60,0x00,0x70,0x00,0x3E,0x00,0x1F,0x80,0x01,0xC0,0x00,0x60,0x00,0x60,0x00,0x60,
+0x40,0xE0,0x7F,0xC0,0x3F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0xFF,0xF0,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x70,0xE0,0x3F,0xC0,0x1F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x30,0xC0,0x30,0xC0,
+0x30,0xC0,0x30,0xC0,0x19,0x80,0x19,0x80,0x19,0x80,0x1F,0x80,0x0F,0x00,0x0F,0x00,
+0x0F,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x30,0xC0,0x30,0xC0,0x30,0x60,0x60,
+0x66,0x60,0x66,0x60,0x6F,0x60,0x6F,0x60,0x69,0x60,0x69,0x60,0x39,0xC0,0x39,0xC0,
+0x39,0xC0,0x30,0xC0,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x30,0xC0,0x39,0xC0,0x19,0x80,
+0x0F,0x00,0x0F,0x00,0x06,0x00,0x06,0x00,0x0F,0x00,0x0F,0x00,0x1B,0x80,0x19,0x80,
+0x31,0xC0,0x30,0xC0,0x60,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x70,0x60,0x60,0x30,0xC0,0x30,0xC0,
+0x19,0x80,0x1F,0x80,0x0F,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0xC0,0x01,0xC0,
+0x01,0x80,0x03,0x00,0x07,0x00,0x06,0x00,0x0E,0x00,0x0C,0x00,0x18,0x00,0x38,0x00,
+0x30,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x07,0x80,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x07,0x80,0x07,0x80,0x00,0x00,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x30,0x00,0x30,0x00,0x18,0x00,
+0x18,0x00,0x0C,0x00,0x0C,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x03,0x00,0x03,0x00,
+0x01,0x80,0x01,0x80,0x00,0xC0,0x00,0xC0,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,/*"\",60*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x0F,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x0F,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0F,0x80,0x0D,0x80,0x18,0xC0,
+0x30,0x60,0x60,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0xFF,0xF0,/*"_",63*/
+0x00,0x00,0x00,0x00,0x18,0x00,0x0C,0x00,0x06,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x3F,0x80,0x21,0xC0,0x00,0xC0,0x1F,0xC0,0x3F,0xC0,0x70,0xC0,0x60,0xC0,
+0x61,0xC0,0x7F,0xC0,0x1C,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x6F,0x00,0x7F,0x80,0x71,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0x80,0x7F,0x80,0x6F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0F,0x00,0x3F,0x80,0x30,0x80,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x30,0x80,0x3F,0x80,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0F,0x00,0x3F,0x80,0x31,0xC0,0x60,0xC0,0x7F,0xC0,0x7F,0xC0,0x60,0x00,0x60,0x00,
+0x30,0x40,0x3F,0xC0,0x0F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xE0,0x03,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x3F,0xE0,0x3F,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x21,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,/*"g",71*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x67,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x3E,0x00,0x3E,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x1F,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x3E,0x00,0x3C,0x00,0x00,0x00,/*"j",74*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x61,0xC0,0x63,0x80,0x67,0x00,0x6E,0x00,0x7C,0x00,0x7C,0x00,0x76,0x00,0x67,0x00,
+0x63,0x00,0x61,0x80,0x61,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x00,0xFC,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0E,0x00,0x07,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x6D,0xC0,0x7F,0xE0,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,
+0x66,0x60,0x66,0x60,0x66,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x67,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x3F,0x80,0x31,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0x80,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x6F,0x00,0x7F,0x80,0x71,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0x80,0x7F,0x80,0x6F,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0x00,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0C,0xE0,0x0D,0xF0,0x0F,0x10,0x0E,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x80,0x3F,0xC0,0x60,0x40,0x60,0x00,0x7F,0x00,0x1F,0x80,0x01,0xC0,0x00,0xC0,
+0x41,0xC0,0x7F,0x80,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x7F,0xC0,0x7F,0xC0,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0F,0xC0,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0xC0,0x3F,0xC0,0x1C,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x71,0xC0,0x31,0x80,0x31,0x80,0x3B,0x80,0x1B,0x00,0x1B,0x00,0x1B,0x00,
+0x0E,0x00,0x0E,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xC0,0x30,0xC0,0x30,0x60,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x3F,0xC0,0x39,0xC0,
+0x39,0xC0,0x39,0xC0,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x71,0xC0,0x31,0x80,0x1B,0x00,0x1F,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1F,0x00,
+0x1B,0x00,0x31,0x80,0x71,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x31,0x80,0x31,0x80,0x31,0x80,0x1B,0x00,0x1B,0x00,0x1F,0x00,0x0E,0x00,
+0x0E,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x38,0x00,0x38,0x00,0x00,0x00,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x7F,0xC0,0x7F,0xC0,0x03,0x80,0x03,0x00,0x07,0x00,0x0E,0x00,0x1C,0x00,0x18,0x00,
+0x30,0x00,0x7F,0xC0,0x7F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x07,0xC0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x3C,0x00,0x3C,0x00,0x0E,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x07,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,/*"{",91*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,/*"|",92*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x3E,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x03,0xC0,0x03,0xC0,0x07,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x3E,0x00,0x3C,0x00,0x00,0x00,0x00,0x00,/*"}",93*/
+};
+#endif
+
+#ifdef ASC2_3216
+const uint8_t asc2_3216[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x06,0x30,
+0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x8C,0x03,0x8C,0x03,0x0C,
+0x03,0x18,0x03,0x18,0x03,0x18,0x7F,0xFF,0x7F,0xFF,0x06,0x30,0x06,0x30,0x0E,0x30,
+0x0C,0x70,0x0C,0x60,0xFF,0xFE,0xFF,0xFE,0x18,0x60,0x18,0xC0,0x18,0xC0,0x18,0xC0,
+0x30,0xC0,0x31,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,
+0x03,0xF0,0x0F,0xFC,0x0E,0x8C,0x1C,0x80,0x1C,0x80,0x1C,0x80,0x1C,0x80,0x0E,0x80,
+0x0F,0xE0,0x03,0xF8,0x00,0xFC,0x00,0x9E,0x00,0x8E,0x00,0x8E,0x00,0x8E,0x10,0x9C,
+0x1F,0xF8,0x07,0xF0,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00,0x00,0x00,/*"$",4*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x7E,0x00,
+0xE7,0x00,0xC3,0x00,0xC3,0x00,0xC3,0x00,0xE7,0x00,0x7E,0x1C,0x3C,0x78,0x01,0xC0,
+0x07,0x00,0x3C,0x78,0x70,0xFC,0x01,0xCE,0x01,0x86,0x01,0x86,0x01,0x86,0x01,0xCE,
+0x00,0xFC,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x0F,0xE0,
+0x1E,0x20,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F,0x00,0x1F,0x00,
+0x3F,0x83,0x33,0xC3,0x71,0xE3,0x70,0xE3,0x70,0xF6,0x70,0x7E,0x78,0x3C,0x3C,0x3E,
+0x1F,0xEE,0x07,0xCF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x60,0x00,0x60,
+0x00,0xE0,0x00,0xC0,0x01,0xC0,0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x01,0x80,0x01,0xC0,
+0x01,0xC0,0x00,0xC0,0x00,0xE0,0x00,0x60,0x00,0x60,0x00,0x30,0x00,0x00,0x00,0x00,/*"(",8*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x03,0x00,0x03,0x00,
+0x03,0x80,0x01,0x80,0x01,0xC0,0x01,0xC0,0x00,0xC0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x00,0x03,0x00,0x06,0x00,0x00,0x00,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,
+0x21,0x84,0x39,0x9C,0x0F,0xF0,0x03,0xC0,0x03,0xC0,0x0F,0xF0,0x39,0x9C,0x21,0x84,
+0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x7F,0xFE,0x7F,0xFE,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x80,0x03,0x00,0x00,0x00,0x00,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x07,0xF0,0x07,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x38,
+0x00,0x38,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0xE0,0x00,0xE0,0x01,0xC0,0x01,0xC0,
+0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x07,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"/",15*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x39,0xCE,0x39,0xCE,
+0x39,0xCE,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xE0,
+0x0C,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x0F,0xFE,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x3F,0xF8,
+0x38,0x3C,0x20,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1E,0x00,0x3C,
+0x00,0x7C,0x00,0xF8,0x00,0xF0,0x01,0xE0,0x03,0xC0,0x07,0x00,0x0E,0x00,0x1C,0x00,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xF8,
+0x18,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x3C,0x07,0xF0,0x07,0xF0,
+0x00,0x3C,0x00,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1E,0x30,0x3C,
+0x3F,0xF8,0x0F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0xF0,
+0x01,0xF0,0x01,0xF0,0x03,0x70,0x07,0x70,0x06,0x70,0x0C,0x70,0x0C,0x70,0x18,0x70,
+0x38,0x70,0x30,0x70,0x60,0x70,0x7F,0xFE,0x7F,0xFE,0x00,0x70,0x00,0x70,0x00,0x70,
+0x00,0x70,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xE0,0x1F,0xF8,0x10,0x3C,0x00,0x1C,
+0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x20,0x3C,
+0x3F,0xF8,0x1F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x04,0x1E,0x00,0x1C,0x00,0x1C,0x00,0x38,0x00,0x39,0xF0,0x3B,0xF8,0x3E,0x3C,
+0x3C,0x1E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x18,0x0E,0x1C,0x1C,0x0E,0x3C,
+0x0F,0xF8,0x03,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,
+0x00,0x1E,0x00,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x70,0x00,0x70,
+0x00,0xF0,0x00,0xE0,0x00,0xE0,0x01,0xE0,0x01,0xC0,0x01,0xC0,0x03,0x80,0x03,0x80,
+0x03,0x80,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xFC,
+0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x07,0xF0,0x0F,0xF8,
+0x1E,0x3C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3C,0x1E,0x1E,0x3C,
+0x0F,0xF8,0x07,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x0F,0xF8,
+0x1E,0x38,0x3C,0x1C,0x38,0x0C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3C,0x1E,
+0x1E,0x3E,0x0F,0xEE,0x07,0xCE,0x00,0x0E,0x00,0x1C,0x00,0x1C,0x00,0x3C,0x10,0x78,
+0x1F,0xF0,0x0F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x00,0x07,0x00,0x07,0x00,0x06,0x00,0x00,0x00,0x00,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x1E,0x00,0x7E,0x01,0xF8,0x0F,0xC0,0x3F,0x00,
+0x78,0x00,0x78,0x00,0x3F,0x00,0x0F,0xC0,0x01,0xF8,0x00,0x7E,0x00,0x1E,0x00,0x02,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x7F,0xFE,
+0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x40,0x00,0x78,0x00,0x7E,0x00,0x1F,0x80,0x03,0xF0,0x00,0xFC,
+0x00,0x1E,0x00,0x1E,0x00,0xFC,0x03,0xF0,0x1F,0x80,0x7E,0x00,0x78,0x00,0x40,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x1C,0x38,0x10,0x1C,0x00,0x1C,0x00,0x3C,0x00,0x3C,0x00,0x78,0x00,0xF0,0x01,0xE0,
+0x03,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,
+0x07,0xFC,0x0E,0x0E,0x1C,0x06,0x18,0x03,0x30,0x03,0x30,0x7B,0x61,0xFF,0x61,0x87,
+0x63,0x03,0x63,0x03,0x63,0x03,0x63,0x03,0x63,0x03,0x61,0x87,0x71,0xFF,0x30,0x7B,
+0x30,0x00,0x18,0x00,0x1C,0x00,0x0F,0x04,0x03,0xFC,0x00,0xFC,0x00,0x00,0x00,0x00,/*"@",32*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x03,0xE0,
+0x03,0xE0,0x03,0xE0,0x03,0xE0,0x07,0x70,0x07,0x70,0x07,0x70,0x0F,0x78,0x0E,0x38,
+0x0E,0x38,0x0E,0x38,0x1F,0xFC,0x1F,0xFC,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x78,0x0F,0x70,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xE0,0x3F,0xF8,
+0x38,0x38,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x38,0x3F,0xF0,0x3F,0xF0,
+0x38,0x3C,0x38,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x3C,
+0x3F,0xF8,0x3F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x0C,0x1E,0x04,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,
+0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x04,0x0F,0x0C,
+0x07,0xFC,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xC0,0x3F,0xF0,
+0x38,0x78,0x38,0x1C,0x38,0x1C,0x38,0x0C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0C,0x38,0x1C,0x38,0x1C,0x38,0x78,
+0x3F,0xF0,0x3F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x1F,0xFE,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x1F,0xFE,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x0C,0x1E,0x04,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x7E,
+0x38,0x7E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x0F,0x1E,
+0x07,0xFE,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3F,0xFE,0x3F,0xFE,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x1F,0xFC,0x1F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x07,0xF8,
+0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,
+0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x20,0x38,0x30,0x70,
+0x3F,0xF0,0x0F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x07,0x38,0x0E,
+0x38,0x1C,0x38,0x38,0x38,0x70,0x38,0xE0,0x39,0xC0,0x3B,0x80,0x3F,0x80,0x3F,0xC0,
+0x3F,0xC0,0x3D,0xE0,0x38,0xF0,0x38,0x70,0x38,0x78,0x38,0x3C,0x38,0x1C,0x38,0x1E,
+0x38,0x0F,0x38,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x1E,0x78,0x1E,
+0x7C,0x3E,0x7C,0x3E,0x7C,0x3E,0x76,0x6E,0x76,0x6E,0x76,0x6E,0x72,0x4E,0x73,0xCE,
+0x73,0xCE,0x71,0x8E,0x71,0x8E,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x70,0x0E,
+0x70,0x0E,0x70,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x0E,0x3C,0x0E,
+0x3E,0x0E,0x3E,0x0E,0x3E,0x0E,0x3B,0x0E,0x3B,0x0E,0x3B,0x8E,0x39,0x8E,0x39,0x8E,
+0x38,0xCE,0x38,0xCE,0x38,0xEE,0x38,0x6E,0x38,0x6E,0x38,0x3E,0x38,0x3E,0x38,0x3E,
+0x38,0x1E,0x38,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xF0,0x1F,0xFC,
+0x1C,0x1E,0x1C,0x0F,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x0F,0x1C,0x1E,
+0x1F,0xFC,0x1F,0xF0,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x70,0x00,0x38,0x00,0x1C,0x00,0x10,0x00,0x00,0x00,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xE0,0x3F,0xF0,
+0x38,0x78,0x38,0x3C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x38,
+0x3F,0xF0,0x3F,0xE0,0x38,0xF0,0x38,0x78,0x38,0x38,0x38,0x3C,0x38,0x1C,0x38,0x1E,
+0x38,0x0E,0x38,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x0F,0xFC,
+0x1E,0x0C,0x3C,0x04,0x38,0x00,0x38,0x00,0x38,0x00,0x3E,0x00,0x1F,0xC0,0x0F,0xF8,
+0x03,0xFC,0x00,0x3C,0x00,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x20,0x1E,0x38,0x3C,
+0x3F,0xF8,0x0F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFF,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x1C,0x38,0x1C,
+0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,
+0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x1C,0x38,
+0x0F,0xF0,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x07,0x78,0x0F,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1E,0x3C,0x0E,0x38,
+0x0E,0x38,0x0E,0x38,0x07,0x70,0x07,0x70,0x07,0x70,0x03,0xE0,0x03,0xE0,0x03,0xE0,
+0x03,0xE0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xE0,0x07,
+0xE0,0x07,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x73,0xCE,0x73,0xCE,0x73,0xCE,0x73,0xCE,
+0x3B,0xDC,0x3E,0x7C,0x3E,0x7C,0x3E,0x7C,0x3E,0x7C,0x3C,0x3C,0x3C,0x3C,0x1C,0x38,
+0x1C,0x38,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x07,0x3C,0x0F,
+0x1C,0x0E,0x1E,0x1E,0x0F,0x3C,0x07,0x38,0x07,0xF0,0x03,0xF0,0x01,0xE0,0x01,0xE0,
+0x01,0xE0,0x03,0xF0,0x07,0xF0,0x07,0x78,0x0F,0x3C,0x0E,0x1C,0x1E,0x1E,0x3C,0x0E,
+0x38,0x07,0x78,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x0F,0x38,0x0E,
+0x3C,0x1E,0x1C,0x1C,0x1E,0x3C,0x0E,0x38,0x07,0x70,0x07,0xF0,0x03,0xE0,0x03,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,
+0x00,0x1E,0x00,0x1C,0x00,0x3C,0x00,0x78,0x00,0x70,0x00,0xF0,0x00,0xE0,0x01,0xE0,
+0x03,0xC0,0x03,0x80,0x07,0x80,0x07,0x00,0x0F,0x00,0x1E,0x00,0x1C,0x00,0x3C,0x00,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x03,0xF0,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0xF0,0x03,0xF0,0x00,0x00,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0x38,0x00,
+0x38,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x07,0x00,0x07,0x00,
+0x03,0x80,0x03,0x80,0x03,0x80,0x01,0xC0,0x01,0xC0,0x00,0xE0,0x00,0xE0,0x00,0x70,
+0x00,0x70,0x00,0x70,0x00,0x38,0x00,0x38,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,/*"\",60*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x07,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x07,0xE0,0x07,0xE0,0x00,0x00,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x03,0xC0,
+0x07,0xE0,0x0E,0x70,0x0C,0x30,0x18,0x18,0x38,0x1C,0x70,0x0E,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,/*"_",63*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x07,0x00,0x03,0x00,0x01,0x80,
+0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xFC,0x18,0x1C,0x00,0x0E,0x00,0x0E,
+0x07,0xFE,0x0F,0xFE,0x1C,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x1E,0x3C,0x3E,
+0x1F,0xEE,0x07,0xCE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0xF8,0x1F,0xFC,0x1F,0x1E,0x1E,0x0E,0x1C,0x07,
+0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1E,0x0E,0x1F,0x1E,
+0x1F,0xFC,0x1C,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF0,0x07,0xF8,0x0F,0x0C,0x0E,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F,0x0C,
+0x07,0xF8,0x01,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x00,0x0E,
+0x00,0x0E,0x00,0x0E,0x00,0x0E,0x07,0xCE,0x0F,0xFE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xFE,0x07,0xCE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,0x1E,0x3C,0x1C,0x1C,0x3C,0x0E,
+0x38,0x0E,0x38,0x0E,0x3F,0xFE,0x3F,0xFE,0x38,0x00,0x38,0x00,0x1C,0x04,0x1E,0x0C,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0xFE,0x01,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x1F,0xFE,0x1F,0xFE,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xCE,0x0F,0xEE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xEE,0x07,0xCE,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x08,0x3C,0x0F,0xF8,0x07,0xE0,/*"g",71*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0xF0,0x1D,0xF8,0x1E,0x3C,0x1E,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xC0,0x1F,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x0F,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x01,0xC0,0x1F,0xC0,0x1F,0x00,/*"j",74*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x0F,0x1C,0x1E,0x1C,0x3C,0x1C,0x78,0x1C,0xF0,
+0x1D,0xE0,0x1F,0xC0,0x1F,0xE0,0x1F,0xE0,0x1E,0xF0,0x1C,0x78,0x1C,0x3C,0x1C,0x1C,
+0x1C,0x1E,0x1C,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x80,0x7F,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x01,0xC0,
+0x01,0xFC,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x1C,0x7F,0xBE,0x71,0xE7,0x71,0xC7,0x71,0xC7,
+0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,
+0x71,0xC7,0x71,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0xF0,0x1D,0xF8,0x1E,0x3C,0x1E,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,0x1E,0x3C,0x1C,0x1C,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1E,0x3C,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0xF8,0x1F,0xFC,0x1F,0x1E,0x1E,0x0E,0x1C,0x07,
+0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1E,0x0E,0x1F,0x1E,
+0x1F,0xFC,0x1C,0xF8,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xCE,0x0F,0xFE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xFE,0x07,0xCE,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x3C,0x07,0x7E,0x07,0xC2,0x07,0x80,0x07,0x80,
+0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,
+0x07,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x0F,0xF8,0x1E,0x08,0x1C,0x00,0x1C,0x00,
+0x1F,0x00,0x0F,0xF0,0x07,0xF8,0x00,0xFC,0x00,0x3C,0x00,0x1C,0x00,0x1C,0x10,0x3C,
+0x1F,0xF8,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x3F,0xFE,0x3F,0xFE,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0xC0,
+0x01,0xFE,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x3C,0x1E,0x3C,
+0x0F,0xDC,0x07,0x9C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x0E,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x1C,0x38,
+0x1C,0x38,0x1E,0x78,0x0E,0x70,0x0E,0x70,0x0F,0xF0,0x07,0xE0,0x07,0xE0,0x07,0xE0,
+0x03,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xE0,0x07,0x70,0x0E,0x70,0x0E,0x71,0x8E,
+0x71,0x8E,0x7B,0xDE,0x3B,0xDC,0x3A,0x5C,0x3A,0x5C,0x3E,0x7C,0x1E,0x78,0x1C,0x38,
+0x1C,0x38,0x1C,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x1E,0x78,0x0E,0x70,0x0F,0xF0,0x07,0xE0,
+0x03,0xC0,0x03,0xC0,0x01,0x80,0x03,0xC0,0x07,0xE0,0x0F,0xF0,0x0E,0x70,0x1E,0x78,
+0x3C,0x3C,0x78,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x0E,0x38,0x1C,0x38,0x1C,0x3C,0x3C,0x1C,0x38,
+0x1C,0x38,0x1E,0x78,0x0E,0x70,0x0E,0x70,0x07,0xE0,0x07,0xE0,0x07,0xE0,0x03,0xC0,
+0x03,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x0F,0x00,0x3E,0x00,0x3C,0x00,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,0x00,0x3C,0x00,0x78,0x00,0x70,
+0x00,0xF0,0x01,0xE0,0x01,0xC0,0x03,0xC0,0x07,0x80,0x07,0x00,0x0F,0x00,0x1E,0x00,
+0x1F,0xFC,0x1F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x00,0xFC,0x01,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x03,0x80,0x1F,0x00,0x1F,0x00,0x03,0x80,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xE0,0x00,0xFC,0x00,0x7C,0x00,0x00,/*"{",91*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,/*"|",92*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x1F,0x80,0x03,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x00,0xE0,0x00,0x7C,0x00,0x7C,0x00,0xE0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x03,0xC0,0x1F,0x80,0x1F,0x00,0x00,0x00,/*"}",93*/
+};
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h
new file mode 100644
index 00000000000..7d888bfc5ce
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-15 SummerGift first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG "drv"
+#else
+#define DBG_TAG LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL DBG_LOG
+#else
+#define DBG_LVL DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lptim.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lptim.h
new file mode 100644
index 00000000000..ff25049462c
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_lptim.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-05-06 Zero-Free first version
+ */
+
+#ifndef __DRV_PMTIMER_H__
+#define __DRV_PMTIMER_H__
+
+#include
+
+rt_uint32_t stm32h7_lptim_get_countfreq(void);
+rt_uint32_t stm32h7_lptim_get_tick_max(void);
+rt_uint32_t stm32h7_lptim_get_current_tick(void);
+
+rt_err_t stm32h7_lptim_start(rt_uint32_t load);
+void stm32h7_lptim_stop(void);
+
+#endif /* __DRV_PMTIMER_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_ov2640.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_ov2640.h
new file mode 100644
index 00000000000..46a067b78e7
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_ov2640.h
@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-07-27 thread-liu first version
+ */
+
+#ifndef __DRV_OV2640_H__
+#define __DRV_OV2640_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+#define OV2640_MID 0X7FA2
+#define OV2640_PID 0X2642
+
+
+//当选择DSP地址(0XFF=0X00)时,OV2640的DSP寄存器地址映射表
+#define OV2640_DSP_R_BYPASS 0x05
+#define OV2640_DSP_Qs 0x44
+#define OV2640_DSP_CTRL 0x50
+#define OV2640_DSP_HSIZE1 0x51
+#define OV2640_DSP_VSIZE1 0x52
+#define OV2640_DSP_XOFFL 0x53
+#define OV2640_DSP_YOFFL 0x54
+#define OV2640_DSP_VHYX 0x55
+#define OV2640_DSP_DPRP 0x56
+#define OV2640_DSP_TEST 0x57
+#define OV2640_DSP_ZMOW 0x5A
+#define OV2640_DSP_ZMOH 0x5B
+#define OV2640_DSP_ZMHH 0x5C
+#define OV2640_DSP_BPADDR 0x7C
+#define OV2640_DSP_BPDATA 0x7D
+#define OV2640_DSP_CTRL2 0x86
+#define OV2640_DSP_CTRL3 0x87
+#define OV2640_DSP_SIZEL 0x8C
+#define OV2640_DSP_HSIZE2 0xC0
+#define OV2640_DSP_VSIZE2 0xC1
+#define OV2640_DSP_CTRL0 0xC2
+#define OV2640_DSP_CTRL1 0xC3
+#define OV2640_DSP_R_DVP_SP 0xD3
+#define OV2640_DSP_IMAGE_MODE 0xDA
+#define OV2640_DSP_RESET 0xE0
+#define OV2640_DSP_MS_SP 0xF0
+#define OV2640_DSP_SS_ID 0x7F
+#define OV2640_DSP_SS_CTRL 0xF8
+#define OV2640_DSP_MC_BIST 0xF9
+#define OV2640_DSP_MC_AL 0xFA
+#define OV2640_DSP_MC_AH 0xFB
+#define OV2640_DSP_MC_D 0xFC
+#define OV2640_DSP_P_STATUS 0xFE
+#define OV2640_DSP_RA_DLMT 0xFF
+
+//当选择传感器地址(0XFF=0X01)时,OV2640的DSP寄存器地址映射表
+#define OV2640_SENSOR_GAIN 0x00
+#define OV2640_SENSOR_COM1 0x03
+#define OV2640_SENSOR_REG04 0x04
+#define OV2640_SENSOR_REG08 0x08
+#define OV2640_SENSOR_COM2 0x09
+#define OV2640_SENSOR_PIDH 0x0A
+#define OV2640_SENSOR_PIDL 0x0B
+#define OV2640_SENSOR_COM3 0x0C
+#define OV2640_SENSOR_COM4 0x0D
+#define OV2640_SENSOR_AEC 0x10
+#define OV2640_SENSOR_CLKRC 0x11
+#define OV2640_SENSOR_COM7 0x12
+#define OV2640_SENSOR_COM8 0x13
+#define OV2640_SENSOR_COM9 0x14
+#define OV2640_SENSOR_COM10 0x15
+#define OV2640_SENSOR_HREFST 0x17
+#define OV2640_SENSOR_HREFEND 0x18
+#define OV2640_SENSOR_VSTART 0x19
+#define OV2640_SENSOR_VEND 0x1A
+#define OV2640_SENSOR_MIDH 0x1C
+#define OV2640_SENSOR_MIDL 0x1D
+#define OV2640_SENSOR_AEW 0x24
+#define OV2640_SENSOR_AEB 0x25
+#define OV2640_SENSOR_W 0x26
+#define OV2640_SENSOR_REG2A 0x2A
+#define OV2640_SENSOR_FRARL 0x2B
+#define OV2640_SENSOR_ADDVSL 0x2D
+#define OV2640_SENSOR_ADDVHS 0x2E
+#define OV2640_SENSOR_YAVG 0x2F
+#define OV2640_SENSOR_REG32 0x32
+#define OV2640_SENSOR_ARCOM2 0x34
+#define OV2640_SENSOR_REG45 0x45
+#define OV2640_SENSOR_FLL 0x46
+#define OV2640_SENSOR_FLH 0x47
+#define OV2640_SENSOR_COM19 0x48
+#define OV2640_SENSOR_ZOOMS 0x49
+#define OV2640_SENSOR_COM22 0x4B
+#define OV2640_SENSOR_COM25 0x4E
+#define OV2640_SENSOR_BD50 0x4F
+#define OV2640_SENSOR_BD60 0x50
+#define OV2640_SENSOR_REG5D 0x5D
+#define OV2640_SENSOR_REG5E 0x5E
+#define OV2640_SENSOR_REG5F 0x5F
+#define OV2640_SENSOR_REG60 0x60
+#define OV2640_SENSOR_HISTO_LOW 0x61
+#define OV2640_SENSOR_HISTO_HIGH 0x62
+
+/* Automatic exposure setting parameters table, support 5 levels */
+const rt_uint8_t OV2640_AUTOEXPOSURE_LEVEL[5][8]=
+{
+ {
+ 0xFF,0x01,
+ 0x24,0x20,
+ 0x25,0x18,
+ 0x26,0x60,
+ },
+ {
+ 0xFF,0x01,
+ 0x24,0x34,
+ 0x25,0x1c,
+ 0x26,0x00,
+ },
+ {
+ 0xFF,0x01,
+ 0x24,0x3e,
+ 0x25,0x38,
+ 0x26,0x81,
+ },
+ {
+ 0xFF,0x01,
+ 0x24,0x48,
+ 0x25,0x40,
+ 0x26,0x81,
+ },
+ {
+ 0xFF,0x01,
+ 0x24,0x58,
+ 0x25,0x50,
+ 0x26,0x92,
+ },
+};
+
+const rt_uint8_t ov2640_sxga_init_reg_tbl[][2]=
+{
+ {0xff, 0x00},
+ {0x2c, 0xff},
+ {0x2e, 0xdf},
+ {0xff, 0x01},
+ {0x3c, 0x32},
+ {0x11, 0x00},
+ {0x09, 0x02},
+ {0x04, 0xD8},
+ {0x13, 0xe5},
+ {0x14, 0x48},
+ {0x2c, 0x0c},
+ {0x33, 0x78},
+ {0x3a, 0x33},
+ {0x3b, 0xfB},
+ {0x3e, 0x00},
+ {0x43, 0x11},
+ {0x16, 0x10},
+ {0x39, 0x92},
+ {0x35, 0xda},
+ {0x22, 0x1a},
+ {0x37, 0xc3},
+ {0x23, 0x00},
+ {0x34, 0xc0},
+ {0x36, 0x1a},
+ {0x06, 0x88},
+ {0x07, 0xc0},
+ {0x0d, 0x87},
+ {0x0e, 0x41},
+ {0x4c, 0x00},
+ {0x48, 0x00},
+ {0x5B, 0x00},
+ {0x42, 0x03},
+ {0x4a, 0x81},
+ {0x21, 0x99},
+ {0x24, 0x40},
+ {0x25, 0x38},
+ {0x26, 0x82},
+ {0x5c, 0x00},
+ {0x63, 0x00},
+ {0x46, 0x00},
+ {0x0c, 0x3c},
+ {0x61, 0x70},
+ {0x62, 0x80},
+ {0x7c, 0x05},
+ {0x20, 0x80},
+ {0x28, 0x30},
+ {0x6c, 0x00},
+ {0x6d, 0x80},
+ {0x6e, 0x00},
+ {0x70, 0x02},
+ {0x71, 0x94},
+ {0x73, 0xc1},
+ {0x3d, 0x34},
+ {0x5a, 0x57},
+ {0x12, 0x00},
+ {0x17, 0x11},
+ {0x18, 0x75},
+ {0x19, 0x01},
+ {0x1a, 0x97},
+ {0x32, 0x36},
+ {0x03, 0x0f},
+ {0x37, 0x40},
+ {0x4f, 0xca},
+ {0x50, 0xa8},
+ {0x5a, 0x23},
+ {0x6d, 0x00},
+ {0x6d, 0x38},
+ {0xff, 0x00},
+ {0xe5, 0x7f},
+ {0xf9, 0xc0},
+ {0x41, 0x24},
+ {0xe0, 0x14},
+ {0x76, 0xff},
+ {0x33, 0xa0},
+ {0x42, 0x20},
+ {0x43, 0x18},
+ {0x4c, 0x00},
+ {0x87, 0xd5},
+ {0x88, 0x3f},
+ {0xd7, 0x03},
+ {0xd9, 0x10},
+ {0xd3, 0x82},
+ {0xc8, 0x08},
+ {0xc9, 0x80},
+ {0x7c, 0x00},
+ {0x7d, 0x00},
+ {0x7c, 0x03},
+ {0x7d, 0x48},
+ {0x7d, 0x48},
+ {0x7c, 0x08},
+ {0x7d, 0x20},
+ {0x7d, 0x10},
+ {0x7d, 0x0e},
+ {0x90, 0x00},
+ {0x91, 0x0e},
+ {0x91, 0x1a},
+ {0x91, 0x31},
+ {0x91, 0x5a},
+ {0x91, 0x69},
+ {0x91, 0x75},
+ {0x91, 0x7e},
+ {0x91, 0x88},
+ {0x91, 0x8f},
+ {0x91, 0x96},
+ {0x91, 0xa3},
+ {0x91, 0xaf},
+ {0x91, 0xc4},
+ {0x91, 0xd7},
+ {0x91, 0xe8},
+ {0x91, 0x20},
+ {0x92, 0x00},
+ {0x93, 0x06},
+ {0x93, 0xe3},
+ {0x93, 0x05},
+ {0x93, 0x05},
+ {0x93, 0x00},
+ {0x93, 0x04},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x96, 0x00},
+ {0x97, 0x08},
+ {0x97, 0x19},
+ {0x97, 0x02},
+ {0x97, 0x0c},
+ {0x97, 0x24},
+ {0x97, 0x30},
+ {0x97, 0x28},
+ {0x97, 0x26},
+ {0x97, 0x02},
+ {0x97, 0x98},
+ {0x97, 0x80},
+ {0x97, 0x00},
+ {0x97, 0x00},
+ {0xc3, 0xef},
+ {0xa4, 0x00},
+ {0xa8, 0x00},
+ {0xc5, 0x11},
+ {0xc6, 0x51},
+ {0xbf, 0x80},
+ {0xc7, 0x10},
+ {0xb6, 0x66},
+ {0xb8, 0xA5},
+ {0xb7, 0x64},
+ {0xb9, 0x7C},
+ {0xb3, 0xaf},
+ {0xb4, 0x97},
+ {0xb5, 0xFF},
+ {0xb0, 0xC5},
+ {0xb1, 0x94},
+ {0xb2, 0x0f},
+ {0xc4, 0x5c},
+ {0xc0, 0xc8},
+ {0xc1, 0x96},
+ {0x8c, 0x00},
+ {0x86, 0x3d},
+ {0x50, 0x00},
+ {0x51, 0x90},
+ {0x52, 0x2c},
+ {0x53, 0x00},
+ {0x54, 0x00},
+ {0x55, 0x88},
+ {0x5a, 0x90},
+ {0x5b, 0x2C},
+ {0x5c, 0x05},
+ {0xd3, 0x02},
+ {0xc3, 0xed},
+ {0x7f, 0x00},
+ {0xda, 0x09},
+ {0xe5, 0x1f},
+ {0xe1, 0x67},
+ {0xe0, 0x00},
+ {0xdd, 0x7f},
+ {0x05, 0x00},
+};
+
+/* SVGA 800*600 */
+const rt_uint8_t ov2640_svga_init_reg_tbl[][2]=
+{
+ {0xff, 0x00},
+ {0x2c, 0xff},
+ {0x2e, 0xdf},
+ {0xff, 0x01},
+ {0x3c, 0x32},
+ {0x11, 0x00},
+ {0x09, 0x02},
+ {0x04, 0xD8},
+ {0x13, 0xe5},
+ {0x14, 0x48},
+ {0x2c, 0x0c},
+ {0x33, 0x78},
+ {0x3a, 0x33},
+ {0x3b, 0xfB},
+ {0x3e, 0x00},
+ {0x43, 0x11},
+ {0x16, 0x10},
+ {0x39, 0x92},
+ {0x35, 0xda},
+ {0x22, 0x1a},
+ {0x37, 0xc3},
+ {0x23, 0x00},
+ {0x34, 0xc0},
+ {0x36, 0x1a},
+ {0x06, 0x88},
+ {0x07, 0xc0},
+ {0x0d, 0x87},
+ {0x0e, 0x41},
+ {0x4c, 0x00},
+ {0x48, 0x00},
+ {0x5B, 0x00},
+ {0x42, 0x03},
+ {0x4a, 0x81},
+ {0x21, 0x99},
+ {0x24, 0x40},
+ {0x25, 0x38},
+ {0x26, 0x82},
+ {0x5c, 0x00},
+ {0x63, 0x00},
+ {0x46, 0x22},
+ {0x0c, 0x3c},
+ {0x61, 0x70},
+ {0x62, 0x80},
+ {0x7c, 0x05},
+ {0x20, 0x80},
+ {0x28, 0x30},
+ {0x6c, 0x00},
+ {0x6d, 0x80},
+ {0x6e, 0x00},
+ {0x70, 0x02},
+ {0x71, 0x94},
+ {0x73, 0xc1},
+ {0x3d, 0x34},
+ {0x5a, 0x57},
+ {0x12, 0x40},
+ {0x17, 0x11},
+ {0x18, 0x43},
+ {0x19, 0x00},
+ {0x1a, 0x4b},
+ {0x32, 0x09},
+ {0x37, 0xc0},
+ {0x4f, 0xca},
+ {0x50, 0xa8},
+ {0x5a, 0x23},
+ {0x6d, 0x00},
+ {0x3d, 0x38},
+ {0xff, 0x00},
+ {0xe5, 0x7f},
+ {0xf9, 0xc0},
+ {0x41, 0x24},
+ {0xe0, 0x14},
+ {0x76, 0xff},
+ {0x33, 0xa0},
+ {0x42, 0x20},
+ {0x43, 0x18},
+ {0x4c, 0x00},
+ {0x87, 0xd5},
+ {0x88, 0x3f},
+ {0xd7, 0x03},
+ {0xd9, 0x10},
+ {0xd3, 0x82},
+ {0xc8, 0x08},
+ {0xc9, 0x80},
+ {0x7c, 0x00},
+ {0x7d, 0x00},
+ {0x7c, 0x03},
+ {0x7d, 0x48},
+ {0x7d, 0x48},
+ {0x7c, 0x08},
+ {0x7d, 0x20},
+ {0x7d, 0x10},
+ {0x7d, 0x0e},
+ {0x90, 0x00},
+ {0x91, 0x0e},
+ {0x91, 0x1a},
+ {0x91, 0x31},
+ {0x91, 0x5a},
+ {0x91, 0x69},
+ {0x91, 0x75},
+ {0x91, 0x7e},
+ {0x91, 0x88},
+ {0x91, 0x8f},
+ {0x91, 0x96},
+ {0x91, 0xa3},
+ {0x91, 0xaf},
+ {0x91, 0xc4},
+ {0x91, 0xd7},
+ {0x91, 0xe8},
+ {0x91, 0x20},
+ {0x92, 0x00},
+ {0x93, 0x06},
+ {0x93, 0xe3},
+ {0x93, 0x05},
+ {0x93, 0x05},
+ {0x93, 0x00},
+ {0x93, 0x04},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x93, 0x00},
+ {0x96, 0x00},
+ {0x97, 0x08},
+ {0x97, 0x19},
+ {0x97, 0x02},
+ {0x97, 0x0c},
+ {0x97, 0x24},
+ {0x97, 0x30},
+ {0x97, 0x28},
+ {0x97, 0x26},
+ {0x97, 0x02},
+ {0x97, 0x98},
+ {0x97, 0x80},
+ {0x97, 0x00},
+ {0x97, 0x00},
+ {0xc3, 0xed},
+ {0xa4, 0x00},
+ {0xa8, 0x00},
+ {0xc5, 0x11},
+ {0xc6, 0x51},
+ {0xbf, 0x80},
+ {0xc7, 0x10},
+ {0xb6, 0x66},
+ {0xb8, 0xA5},
+ {0xb7, 0x64},
+ {0xb9, 0x7C},
+ {0xb3, 0xaf},
+ {0xb4, 0x97},
+ {0xb5, 0xFF},
+ {0xb0, 0xC5},
+ {0xb1, 0x94},
+ {0xb2, 0x0f},
+ {0xc4, 0x5c},
+ {0xc0, 0x64},
+ {0xc1, 0x4B},
+ {0x8c, 0x00},
+ {0x86, 0x3D},
+ {0x50, 0x00},
+ {0x51, 0xC8},
+ {0x52, 0x96},
+ {0x53, 0x00},
+ {0x54, 0x00},
+ {0x55, 0x00},
+ {0x5a, 0xC8},
+ {0x5b, 0x96},
+ {0x5c, 0x00},
+ {0xd3, 0x02},
+ {0xc3, 0xed},
+ {0x7f, 0x00},
+ {0xda, 0x09},
+ {0xe5, 0x1f},
+ {0xe1, 0x67},
+ {0xe0, 0x00},
+ {0xdd, 0x7f},
+ {0x05, 0x00},
+};
+
+const rt_uint8_t ov2640_jpeg_reg_tbl[][2]=
+{
+ {0xff, 0x01},
+ {0xe0, 0x14},
+ {0xe1, 0x77},
+ {0xe5, 0x1f},
+ {0xd7, 0x03},
+ {0xda, 0x10},
+ {0xe0, 0x00},
+};
+
+const rt_uint8_t ov2640_rgb565_reg_tbl[][2]=
+{
+ {0xFF, 0x00},
+ {0xDA, 0x09},
+ {0xD7, 0x03},
+ {0xDF, 0x02},
+ {0x33, 0xa0},
+ {0x3C, 0x00},
+ {0xe1, 0x67},
+
+ {0xff, 0x01},
+ {0xe0, 0x00},
+ {0xe1, 0x00},
+ {0xe5, 0x00},
+ {0xd7, 0x00},
+ {0xda, 0x00},
+ {0xe0, 0x00},
+};
+const rt_uint8_t ov2640_yuv422_reg_tbl[][2] =
+{
+ {0xFF, 0x00},
+ {0xDA, 0x10},
+ {0xD7, 0x03},
+ {0xDF, 0x00},
+ {0x33, 0x80},
+ {0x3C, 0x40},
+ {0xe1, 0x77},
+ {0x00, 0x00},
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_qspi.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_qspi.h
new file mode 100644
index 00000000000..699221cdc9c
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_qspi.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-27 zylx first version
+ */
+
+#ifndef __DRV_QSPI_H_
+#define __DRV_QSPI_H_
+#include
+
+rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h
new file mode 100644
index 00000000000..4ad86b6bfa2
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-10-30 Evlers first version
+ */
+
+#ifndef __DRV_SDMMC_H__
+#define __DRV_SDMMC_H__
+
+#include
+#include "rtdevice.h"
+#include
+#include
+#include
+#include
+#include
+
+#define SDIO_BUFF_SIZE 16384
+#define SDIO_ALIGN_LEN 32
+
+#define SDIO1_BASE_ADDRESS (SDMMC1_BASE)
+#define SDIO2_BASE_ADDRESS (SDMMC2_BASE)
+
+#ifndef SDIO_CLOCK_FREQ
+#define SDIO_CLOCK_FREQ (200U * 1000 * 1000)
+#endif
+
+#ifndef SDIO_BUFF_SIZE
+#define SDIO_BUFF_SIZE (4096)
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+#define SDIO_ALIGN_LEN (32)
+#endif
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ (50 * 1000 * 1000)
+#endif
+
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ 50000000U /* Normal speed phase : 50 MHz max */
+#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
+
+#define SDIO_ERRORS \
+ (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
+ SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
+ SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
+ SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
+
+#define SDIO_MASKR_ALL \
+ (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
+ SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
+ SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
+
+#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU)
+
+typedef rt_uint32_t (*sdio_clk_get)(void);
+
+struct stm32_sdio_des
+{
+ SD_HandleTypeDef hw_sdio;
+ sdio_clk_get clk_get;
+};
+
+extern void stm32_mmcsd_change(void);
+
+#endif /* __DRV_SDMMC_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h
new file mode 100644
index 00000000000..5cca0920215
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-08 balanceTWK first version
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include
+#include
+#include
+
+#ifdef RT_USING_I2C
+
+/* stm32 config class */
+struct stm32_soft_i2c_config
+{
+ rt_uint8_t scl;
+ rt_uint8_t sda;
+ const char *bus_name;
+};
+/* stm32 i2c dirver class */
+struct stm32_i2c
+{
+ struct rt_i2c_bit_ops ops;
+ struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG \
+ { \
+ .scl = BSP_I2C1_SCL_PIN, \
+ .sda = BSP_I2C1_SDA_PIN, \
+ .bus_name = "i2c1", \
+ }
+#endif
+
+#ifdef BSP_USING_I2C2
+#define I2C2_BUS_CONFIG \
+ { \
+ .scl = BSP_I2C2_SCL_PIN, \
+ .sda = BSP_I2C2_SDA_PIN, \
+ .bus_name = "i2c2", \
+ }
+#endif
+
+#ifdef BSP_USING_I2C3
+#define I2C3_BUS_CONFIG \
+ { \
+ .scl = BSP_I2C3_SCL_PIN, \
+ .sda = BSP_I2C3_SDA_PIN, \
+ .bus_name = "i2c3", \
+ }
+#endif
+
+#ifdef BSP_USING_I2C4
+#define I2C4_BUS_CONFIG \
+ { \
+ .scl = BSP_I2C4_SCL_PIN, \
+ .sda = BSP_I2C4_SDA_PIN, \
+ .bus_name = "i2c4", \
+ }
+#endif
+int rt_hw_i2c_init(void);
+
+#endif
+
+#endif /* RT_USING_I2C */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi.h
new file mode 100644
index 00000000000..5d9ad6a6aba
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-11-5 SummerGift first version
+ */
+
+#ifndef __DRV_SPI_H_
+#define __DRV_SPI_H_
+
+#include
+#include "rtdevice.h"
+#include
+#include
+#include "drv_dma.h"
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
+
+struct stm32_hw_spi_cs
+{
+ GPIO_TypeDef* GPIOx;
+ uint16_t GPIO_Pin;
+};
+
+struct stm32_spi_config
+{
+ SPI_TypeDef *Instance;
+ char *bus_name;
+ struct dma_config *dma_rx, *dma_tx;
+};
+
+struct stm32_spi_device
+{
+ rt_uint32_t pin;
+ char *bus_name;
+ char *device_name;
+};
+
+#define SPI_USING_RX_DMA_FLAG (1<<0)
+#define SPI_USING_TX_DMA_FLAG (1<<1)
+
+/* stm32 spi dirver class */
+struct stm32_spi
+{
+ SPI_HandleTypeDef handle;
+ struct stm32_spi_config *config;
+ struct rt_spi_configuration *cfg;
+
+ struct
+ {
+ DMA_HandleTypeDef handle_rx;
+ DMA_HandleTypeDef handle_tx;
+ } dma;
+
+ rt_uint8_t spi_dma_flag;
+ struct rt_spi_bus spi_bus;
+};
+
+#endif /*__DRV_SPI_H_ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi_ili9488.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi_ili9488.h
new file mode 100644
index 00000000000..7f01561489c
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_spi_ili9488.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-08-14 flybreak the first version
+ * 2018-09-18 balanceTWK add sleep mode function
+ * 2022-02-01 Rudy Lo add lcd_fill_array function
+ */
+
+#ifndef __DRV_LCD_SPI_H__
+#define __DRV_LCD_SPI_H__
+
+#include
+
+#define LCD_W 480
+#define LCD_H 320
+
+//POINT_COLOR
+#define WHITE 0xFFFFFF
+#define BLACK 0x000000
+#define BLUE 0x0000FF
+//#define BRED 0XF81F
+//#define GRED 0XFFE0
+//#define GBLUE 0X07FF
+#define RED 0xFF0000
+//#define MAGENTA 0xF81F
+#define GREEN 0x00FF00
+//#define CYAN 0x7FFF
+//#define YELLOW 0xFFE0
+//#define BROWN 0XBC40
+//#define BRRED 0XFC07
+//#define GRAY 0X8430
+//#define GRAY175 0XAD75
+//#define GRAY151 0X94B2
+//#define GRAY187 0XBDD7
+//#define GRAY240 0XF79E
+
+int rt_hw_spi_lcd_init(void);
+
+void lcd_clear(rt_uint32_t color);
+void lcd_address_set(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_set_color(rt_uint32_t back, rt_uint32_t fore);
+
+void lcd_draw_point(rt_uint16_t x, rt_uint16_t y);
+void lcd_draw_point_color(rt_uint16_t x, rt_uint16_t y, rt_uint32_t color);
+void lcd_draw_circle(rt_uint16_t x0, rt_uint16_t y0, rt_uint8_t r);
+void lcd_draw_line(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_draw_rectangle(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_fill(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, rt_uint32_t color);
+void lcd_fill_array(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, void *pcolor);
+
+void lcd_show_num(rt_uint16_t x, rt_uint16_t y, rt_uint32_t num, rt_uint8_t len, rt_uint32_t size);
+rt_err_t lcd_show_string(rt_uint16_t x, rt_uint16_t y, rt_uint32_t size, const char *fmt, ...);
+rt_err_t lcd_show_image(rt_uint16_t x, rt_uint16_t y, rt_uint16_t length, rt_uint16_t wide, const rt_uint8_t *p);
+
+void lcd_enter_sleep(void);
+void lcd_exit_sleep(void);
+void lcd_display_on(void);
+void lcd_display_off(void);
+
+#endif /* __DRV_LCD_SPI_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_touch.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_touch.h
new file mode 100644
index 00000000000..84b9d5fd498
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_touch.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-06-20 Rbb666 Add GT9147 Touch Device
+ */
+
+#ifndef __DRV_TOUCH_H__
+#define __DRV_TOUCH_H__
+
+#include "rtthread.h"
+#include "rtdevice.h"
+
+#ifdef BSP_USING_TOUCH
+# define TOUCH_DBG_LEVEL DBG_LOG
+
+# define TOUCH_EVENT_UP (0x01)
+# define TOUCH_EVENT_DOWN (0x02)
+# define TOUCH_EVENT_MOVE (0x03)
+# define TOUCH_EVENT_NONE (0x80)
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h
new file mode 100644
index 00000000000..a9d42f3680a
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-10-30 SummerGift first version
+ * 2019-03-05 whj4674672 add stm32h7
+ * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include
+#include "rtdevice.h"
+#include
+#include
+#include "drv_dma.h"
+
+int rt_hw_usart_init(void);
+
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
+ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
+#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
+#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
+
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \
+ || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
+ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \
+ || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS)
+#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
+#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
+ || defined(SOC_SERIES_STM32MP1)
+#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
+#endif
+
+#define UART_RX_DMA_IT_IDLE_FLAG 0x00
+#define UART_RX_DMA_IT_HT_FLAG 0x01
+#define UART_RX_DMA_IT_TC_FLAG 0x02
+
+#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20
+
+/* stm32 config class */
+struct stm32_uart_config
+{
+ const char *name;
+ USART_TypeDef *Instance;
+ IRQn_Type irq_type;
+ struct dma_config *dma_rx;
+ struct dma_config *dma_tx;
+};
+
+/* stm32 uart dirver class */
+struct stm32_uart
+{
+ UART_HandleTypeDef handle;
+ struct stm32_uart_config *config;
+ rt_uint32_t DR_mask;
+ rt_uint32_t tx_block_timeout;
+
+#ifdef RT_SERIAL_USING_DMA
+ struct
+ {
+ DMA_HandleTypeDef handle;
+ rt_size_t remaining_cnt;
+ } dma_rx;
+ struct
+ {
+ DMA_HandleTypeDef handle;
+ } dma_tx;
+#endif
+ rt_uint16_t uart_dma_flag;
+ struct rt_serial_device serial;
+};
+
+#endif /* __DRV_USART_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h
new file mode 100644
index 00000000000..46b81596c9f
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-06-01 KyleChan first version
+ */
+
+#ifndef __DRV_USART_V2_H__
+#define __DRV_USART_V2_H__
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int rt_hw_usart_init(void);
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
+ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
+ || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32G4)
+#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TDR = (__DATA__))
+#define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->RDR & MASK)
+
+#else
+#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->DR = (__DATA__))
+#define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->DR & MASK)
+#endif
+
+
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \
+ || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
+ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
+#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
+#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
+ || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32MP1)
+#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
+#endif
+
+#define UART_RX_DMA_IT_IDLE_FLAG 0x00
+#define UART_RX_DMA_IT_HT_FLAG 0x01
+#define UART_RX_DMA_IT_TC_FLAG 0x02
+
+
+/* stm32 config class */
+struct stm32_uart_config
+{
+ const char *name;
+ USART_TypeDef *Instance;
+ IRQn_Type irq_type;
+
+#ifdef RT_SERIAL_USING_DMA
+ struct dma_config *dma_rx;
+ struct dma_config *dma_tx;
+#endif
+};
+
+/* stm32 uart dirver class */
+struct stm32_uart
+{
+ UART_HandleTypeDef handle;
+ struct stm32_uart_config *config;
+
+#ifdef RT_SERIAL_USING_DMA
+ struct
+ {
+ DMA_HandleTypeDef handle;
+ rt_size_t remaining_cnt;
+ } dma_rx;
+ struct
+ {
+ DMA_HandleTypeDef handle;
+ } dma_tx;
+#endif
+ rt_uint16_t uart_dma_flag;
+ struct rt_serial_device serial;
+};
+
+#endif /* __DRV_USART_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usbh.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usbh.h
new file mode 100644
index 00000000000..b2d2d1b4053
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usbh.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-12-12 ZYH the first version
+ * 2019-12-19 tyustli port to stm32 series
+ */
+#ifndef __DRV_USBH_H__
+#define __DRV_USBH_H__
+#include
+
+#define OTG_FS_PORT 1
+
+int stm_usbh_register(void);
+
+#endif
+
+/************* end of file ************/
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_port.h b/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_port.h
new file mode 100644
index 00000000000..6d958cd1205
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_port.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-01-08 zylx first version
+ */
+
+#ifndef __LCD_PORT_H__
+#define __LCD_PORT_H__
+
+#include
+#include
+#include
+
+struct drv_lcd_device
+{
+ struct rt_device parent;
+ struct rt_device_graphic_info lcd_info;
+
+ struct rt_semaphore lcd_lock;
+
+ /* 0:front_buf is being used 1: back_buf is being used*/
+ rt_uint8_t cur_buf;
+ rt_uint8_t *front_buf;
+ rt_uint8_t *back_buf;
+};
+
+#if defined(BSP_USING_OLED_454_MIPI)
+ /* RT-Thread AMOLED 1.44 inch screen, 454 * 454 bridged by SSD2828 RGB to mipi IC */
+ #define LCD_WIDTH 454
+ #define LCD_HEIGHT 454
+ #define LCD_BITS_PER_PIXEL 16
+ #define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+ #define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 //RTGRAPHIC_PIXEL_FORMAT_RGB888
+
+ #define LCD_HSYNC_WIDTH 20
+ #define LCD_VSYNC_HEIGHT 4
+ #define LCD_HBP 40
+ #define LCD_VBP 12
+ #define LCD_HFP 20
+ #define LCD_VFP 20
+
+ #define LCD_BACKLIGHT_USING_GPIO
+ #define LCD_BL_GPIO_NUM GET_PIN(G, 15)
+
+#elif defined(BSP_USING_LCD_360_REDUCED)
+ /* RT-Thread produced or atk 4.3 inch screen, 360 * 360 reduced on 800 * 480 */
+ #define LCD_WIDTH 360//800//480//800
+ #define LCD_HEIGHT 360//480//800//480
+ #define LCD_BITS_PER_PIXEL 16//24
+ #define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+ #define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 //RTGRAPHIC_PIXEL_FORMAT_RGB888
+
+ #define LCD_HSYNC_WIDTH 1
+ #define LCD_VSYNC_HEIGHT 1
+ #define LCD_HBP 6//88
+ #define LCD_VBP 6//32
+ #define LCD_HFP 480//40+440
+ #define LCD_VFP 133//13+120
+
+ #define LCD_BACKLIGHT_USING_GPIO
+ #define LCD_BL_GPIO_NUM GET_PIN(G, 15)
+
+#elif defined(BSP_USING_LCD_454_REDUCED)
+ /* RT-Thread produced or atk 4.3 inch screen, 454 * 454 reduced on 800 * 480 */
+ #define LCD_WIDTH 454
+ #define LCD_HEIGHT 454
+ #define LCD_BITS_PER_PIXEL 16
+ #define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+ #define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 //RTGRAPHIC_PIXEL_FORMAT_RGB888
+
+ #define LCD_HSYNC_WIDTH 1
+ #define LCD_VSYNC_HEIGHT 1
+ #define LCD_HBP 6
+ #define LCD_VBP 6
+ #define LCD_HFP (480 - 94)
+ #define LCD_VFP (133 - 26)
+
+ #define LCD_BACKLIGHT_USING_GPIO
+ #define LCD_BL_GPIO_NUM GET_PIN(G, 15)
+
+#else
+ //BSP_USING_LCD_800_RGB
+ /* RT-Thread produced or atk 4.3 inch screen, 800 * 480 , PixClock 33Mhz */
+ #define LCD_WIDTH 800 //480
+ #define LCD_HEIGHT 480 //272
+ #define LCD_BITS_PER_PIXEL 16
+ #define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+ #define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
+
+ // applied to ATK-4384 LCD screen
+ #define LCD_HSYNC_WIDTH 48
+ #define LCD_VSYNC_HEIGHT 3
+ #define LCD_HBP 88
+ #define LCD_VBP 32
+ #define LCD_HFP 40
+ #define LCD_VFP 13
+
+ #define LCD_BACKLIGHT_USING_GPIO
+ #define LCD_BL_GPIO_NUM GET_PIN(G, 15) //LCD Backlight set PG15 High to Enable.
+
+#endif
+
+#endif /* __LCD_PORT_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_spi_port.h b/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_spi_port.h
new file mode 100644
index 00000000000..d5925bd0e5c
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/lcd_spi_port.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-08-10 zylx first version
+ */
+
+#ifndef __LCD_PORT_H__
+#define __LCD_PORT_H__
+
+/* rt-thread 3.5 inch screen, 320 * 480 */
+#define LCD_HOR_SCREEN
+#define LCD_FULL_COLOR BLACK
+
+#ifndef LCD_FULL_COLOR
+#define LCD_FULL_COLOR WHITE
+#endif
+
+#ifndef LCD_HOR_SCREEN
+#define LCD_WIDTH 320
+#define LCD_HEIGHT 480
+#else
+#define LCD_WIDTH 480
+#define LCD_HEIGHT 320
+#endif
+#define LCD_BITS_PER_PIXEL 24
+#define LCD_BYTES_PER_PIXEL (LCD_BITS_PER_PIXEL / 8)
+#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BYTES_PER_PIXEL)
+#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB888
+
+#define LCD_BACKLIGHT_USING_GPIO
+#define LCD_BL_PIN GET_PIN(C, 6)
+#define LCD_RES_PIN GET_PIN(A, 3)
+/* rt-thread 3.5 inch screen, 320 * 480 */
+
+#endif /* __LCD_PORT_H__ */
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h b/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h
new file mode 100644
index 00000000000..cefc1742e7d
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-01-24 yuanjie The first version for STM32H7RSxx
+ */
+
+#ifndef __PSRAM_PORT_H__
+#define __PSRAM_PORT_H__
+
+/* parameters for psram peripheral */
+#define PSRAM_BANK_ADDR ((uint32_t)0x70000000)
+/* data width: 8, 16, 32 */
+#define PSRAM_DATA_WIDTH 32
+#define PSRAM_SIZE ((uint32_t)0x2000000) // 256Mbits, 32MB
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h b/bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h
new file mode 100644
index 00000000000..752703417d4
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h
@@ -0,0 +1,2072 @@
+const unsigned char image_rttlogo[] = { /* 0X10,0X10,0X00,0XF0,0X00,0X45,0X01,0X1B, */
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XDF,0XFF,0XBF,0X7F,
+0XBE,0XFF,0XBE,0XFF,0XB6,0XFF,0XA6,0XBF,0XA6,0XBF,0XB6,0XDF,0XBE,0XDF,0XBE,0XFF,
+0XBF,0X1F,0XCF,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XFF,0XB6,0XDF,0X85,0XBF,
+0X4C,0X9E,0X23,0X9B,0X02,0X98,0X02,0X37,0X01,0X96,0X01,0X36,0X01,0X36,0X00,0XF4,
+0X00,0XD4,0X00,0XD5,0X00,0XD5,0X00,0XD5,0X00,0XD4,0X00,0XD4,0X00,0XD4,0X00,0XD4,
+0X00,0XF4,0X01,0X15,0X01,0X36,0X01,0X76,0X01,0XD7,0X02,0X78,0X13,0X3A,0X3C,0X1C,
+0X64,0XFE,0X9E,0X7F,0XDF,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XF7,0XFF,0X96,0X5F,0X4C,0X7D,0X0A,0XDA,0X01,0XB7,0X01,0X36,0X00,0XB4,0X00,0XF4,
+0X01,0X35,0X01,0X76,0X01,0XD7,0X02,0X18,0X02,0X79,0X02,0X78,0X02,0X98,0X02,0X98,
+0X02,0XB8,0X02,0XB8,0X02,0X98,0X02,0X99,0X02,0XB9,0X02,0X98,0X02,0XB8,0X02,0XB8,
+0X02,0XB9,0X02,0X78,0X02,0X79,0X02,0X78,0X02,0X37,0X02,0X17,0X01,0X96,0X01,0X56,
+0X00,0XF5,0X00,0XD4,0X00,0XF5,0X01,0X76,0X02,0X99,0X3C,0X1C,0X8D,0XFF,0XDF,0XDF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XCF,0X5F,0X5C,0X9E,0X01,0XF7,
+0X00,0XB4,0X00,0XF4,0X00,0XF5,0X01,0XB7,0X02,0X58,0X02,0X98,0X02,0XB9,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X78,0X01,0XD7,0X01,0X35,0X00,0XF5,0X00,0X94,
+0X01,0X56,0X4C,0X7D,0XCF,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X8D,0XBF,0X1B,0X3A,0X01,0X96,0X00,0XD4,0X00,0XF4,0X02,0X17,
+0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X79,0X02,0X78,0X02,0X79,0X02,0X79,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X79,0X02,0X98,0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X78,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0XB8,
+0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X78,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0XB9,
+0X02,0X59,0X01,0X15,0X00,0XB4,0X01,0X96,0X2B,0X7B,0X9E,0X3F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X85,0X3F,
+0X00,0XF5,0X01,0X76,0X00,0XB4,0X01,0X76,0X02,0X59,0X02,0XB9,0X02,0XB9,0X02,0X99,
+0X02,0X78,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,
+0X02,0X98,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X98,0X02,0X98,
+0X02,0X98,0X02,0X99,0X02,0XB8,0X02,0X58,0X01,0X56,0X00,0X94,0X01,0X55,0X1B,0X3A,
+0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XE7,0XFF,
+0X00,0X53,0X01,0XD7,0X02,0XD9,0X02,0XB9,0X02,0X38,0X01,0X15,0X00,0XF5,0X02,0X98,
+0X02,0XB9,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X79,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X79,0X02,0X99,0X02,0X79,0X02,0X98,0X02,0X98,0X02,0XB9,0X02,0X78,0X01,0X97,
+0X00,0XB4,0X01,0X15,0X1B,0X1A,0XAE,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XD7,0XBF,0X00,0X94,0X01,0X97,0X00,0X94,0X01,0X96,0X6D,0X5F,0XAE,0X9F,0X01,0X76,
+0X02,0X79,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X98,
+0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,
+0X02,0XB9,0X02,0XB9,0X01,0X76,0X00,0X94,0X01,0XB6,0X6C,0XBE,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X2B,0XDB,0X01,0XD7,0XA6,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X75,0X3E,
+0X00,0XD4,0X02,0XD9,0X02,0X7A,0X02,0X79,0X02,0X98,0X02,0X79,0X02,0X98,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X79,
+0X02,0X99,0X02,0X98,0X02,0X99,0X02,0XB9,0X02,0X37,0X00,0XD5,0X01,0X15,0X33,0XBB,
+0XBE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X6D,0X3E,0X01,0X35,0X01,0XB6,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X17,0X01,0XD7,0X02,0X99,0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,0X02,0X98,0X02,0X98,0X02,0X78,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,
+0X02,0X99,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0XD9,0X02,0X98,0X01,0X36,
+0X00,0X74,0X02,0X58,0XA6,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XC6,0XFF,0X00,0X11,
+0X00,0XF4,0X02,0X38,0X00,0X74,0XAE,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XFF,
+0X53,0XDB,0X7D,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X9E,0X7F,0X00,0X93,0X02,0XD9,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0XB8,
+0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X78,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X98,
+0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,
+0X02,0X78,0X02,0X78,0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X79,0X02,0X99,0X02,0XB8,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X79,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X79,
+0X02,0XB9,0X01,0XB6,0X00,0X94,0X02,0X17,0XB6,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X99,
+0X01,0X76,0X02,0XD9,0X01,0X96,0X0B,0X1A,0XFF,0XFF,0XDF,0XBF,0X23,0X3A,0X00,0X94,
+0X00,0X54,0X00,0X93,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X01,0X96,0X02,0X17,0X02,0X98,0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X79,
+0X02,0X98,0X02,0X98,0X02,0X79,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,
+0X02,0X38,0X02,0X17,0X01,0XD7,0X01,0XB7,0X01,0X97,0X01,0X97,0X01,0X97,0X01,0X97,
+0X01,0XB7,0X01,0X97,0X01,0X97,0X01,0XB7,0X01,0XD7,0X01,0XF8,0X02,0X38,0X02,0X38,
+0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X78,0X02,0X99,
+0X02,0X99,0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X78,
+0X02,0X79,0X02,0X99,0X02,0XB9,0X01,0XD7,0X00,0X33,0X43,0XFC,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XE7,0XFF,
+0X00,0X54,0X02,0XD9,0X02,0X78,0X00,0X11,0XCE,0XFF,0X7D,0X7F,0X00,0X11,0X02,0XD9,
+0X02,0XF9,0X00,0XF5,0X4C,0X9D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X96,0X5F,0X00,0XF4,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X79,0X02,0X79,
+0X01,0XD7,0X01,0X96,0X01,0X35,0X00,0XF4,0X00,0XF4,0X00,0XF5,0X01,0X55,0X01,0XD7,
+0X01,0XF7,0X02,0X37,0X02,0XD9,0X0B,0X3A,0X1B,0X7B,0X1B,0X7B,0X1B,0X9B,0X1B,0X7B,
+0X13,0X9B,0X1B,0X9B,0X1B,0X9B,0X0B,0X5A,0X02,0XF9,0X02,0X78,0X02,0X17,0X01,0XB7,
+0X01,0X35,0X00,0XF5,0X00,0XD5,0X00,0XF5,0X01,0X35,0X01,0X96,0X01,0XF7,0X02,0X58,
+0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,
+0X02,0X99,0X02,0X98,0X02,0X99,0X02,0XB9,0X02,0XB9,0X00,0XF5,0X01,0X36,0X85,0X7F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X13,0X3A,0X00,0X11,0X01,0XB7,0X43,0XBB,0XFF,0XFF,0XFF,0XFF,0X01,0XB6,0X01,0XF8,
+0X02,0XB9,0X02,0X99,0X00,0X74,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X01,0XD6,0X02,0X18,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X38,0X01,0XB6,0X01,0X15,0X00,0XF5,0X01,0X15,0X01,0X96,
+0X02,0X98,0X1B,0XBC,0X54,0XDE,0X85,0XDF,0XB6,0XFF,0XDF,0XDF,0XF7,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XFF,0XBF,0X1F,0X8D,0XFF,0X5C,0XDE,0X1B,0XBB,0X02,0XB9,0X01,0X96,
+0X00,0XF5,0X00,0XF4,0X01,0X15,0X01,0X97,0X02,0X38,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0XD9,0X02,0X38,0X00,0XB4,
+0X01,0X76,0X95,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X9E,0X3F,0X09,0XB6,0XFF,0XFF,
+0XFF,0XFF,0X84,0XBD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X9E,0X3F,0X00,0X12,
+0X01,0XD8,0X00,0XF5,0X00,0X32,0X8D,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XAE,0X9F,0X2B,0XBB,0X02,0X78,0X02,0X78,0X02,0XB9,0X02,0X79,0X01,0XD7,0X01,0X56,
+0X00,0XB5,0X01,0X15,0X01,0XD6,0X13,0X7B,0X65,0X1F,0XAE,0X9F,0XEF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XEF,0XFF,0XA6,0XBF,0X5C,0XDE,0X0B,0X1A,0X01,0XD7,0X00,0XD4,0X00,0XF4,0X01,0X96,
+0X02,0X38,0X02,0X99,0X02,0XB9,0X02,0X98,0X02,0X79,0X02,0X98,0X02,0X99,0X02,0XB9,
+0X02,0X17,0X00,0X74,0X02,0X98,0XE7,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X4C,0X3C,0X01,0X56,0X00,0X95,0X00,0X53,0X02,0XD9,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X9D,0XFF,0X5C,0X7D,0XFF,0XFF,0X3C,0X1C,
+0X01,0X96,0X8D,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XDF,0X9F,0X33,0X3A,0X01,0XB7,
+0X00,0XB4,0X01,0XB7,0X02,0X78,0X01,0XB6,0X00,0XD5,0X01,0X15,0X02,0X77,0X34,0X1C,
+0X8D,0XDF,0XE7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XD7,0X9F,0X6D,0X7F,0X13,0X5A,
+0X01,0XD7,0X00,0XB4,0X01,0X14,0X01,0XF7,0X02,0X99,0X02,0XB9,0X02,0X79,0X02,0X99,
+0X02,0X99,0X02,0XD9,0X01,0X76,0X00,0X94,0X64,0X9D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X3B,0XBC,0X00,0X53,0X02,0XF9,0X02,0XD9,0X00,0X53,
+0XF7,0XFF,0XFF,0XFF,0X44,0X1C,0X01,0XD6,0X00,0X95,0X00,0X10,0XBF,0X7F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0X11,0X02,0X38,
+0X01,0X96,0X00,0XF4,0X01,0X75,0X1B,0X9B,0X85,0XDF,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XCF,0X7F,0X64,0XDE,0X02,0X78,0X00,0XF5,0X00,0XF5,0X01,0XF7,0X02,0X98,
+0X02,0XB9,0X02,0X99,0X02,0XB9,0X02,0X79,0X00,0XB3,0X01,0XF7,0XE7,0XDF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X38,0X02,0XD8,0X01,0XB7,
+0X02,0X18,0XFF,0XFF,0X0B,0X1A,0X00,0XB4,0X02,0XD9,0X02,0X38,0X00,0XB4,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X2B,0XFC,0X00,0X11,
+0X1B,0X7A,0X9E,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XEF,0XFF,0X64,0XFE,0X02,0X58,0X00,0XB4,
+0X01,0X36,0X02,0X79,0X02,0XD9,0X02,0X98,0X02,0XD9,0X01,0X96,0X00,0X94,0X75,0X5F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X7D,0XBF,0X00,0X12,0X01,0X35,0X00,0X74,
+0X0A,0X78,0XFF,0XFF,0XFF,0XFF,0X00,0XB4,0X02,0X99,0X02,0XF9,0X00,0XF4,0X12,0XFA,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XCF,0X9F,
+0X3C,0X1C,0X00,0XF4,0X00,0XF5,0X02,0X38,0X02,0XB9,0X02,0XD9,0X02,0X78,0X00,0XF4,
+0X01,0X96,0X6C,0X7D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0XB6,0X4C,0X5C,0XD7,0X7F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X0B,0X3A,0X00,0XF4,0X01,0X15,0X00,0XF5,0X01,0X15,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X5C,0X9D,0X01,0XB6,0X00,0XB4,0X01,0XD6,0X02,0XBA,0X02,0XB9,
+0X02,0X18,0X00,0X33,0X1A,0XD9,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XDF,0XBF,0X00,0X93,0X4C,0X9D,0XDF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X95,0XDF,0X02,0X58,0X00,0X94,0X01,0X96,
+0X02,0XB9,0X02,0XFA,0X00,0XF5,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XAE,0X9F,0X02,0XB8,
+0X00,0XB4,0X00,0XF5,0X02,0X79,0X01,0XD7,0X00,0XB4,0XBE,0X7F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XE7,0XDF,0X85,0X9F,0X01,0X95,0X01,0X36,0X02,0X38,0X00,0X74,0X6D,0X1E,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X12,0XD9,0X00,0XB4,0X01,0X76,0X00,0X53,0X95,0XDF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XC6,0XFF,0X02,0X78,0X00,0X93,0X00,0X13,
+0X75,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X95,0XBF,0X01,0X36,
+0X00,0X10,0X1B,0X1A,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X3B,0XFC,0X00,0X10,0X01,0X56,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XB6,0XFF,0X00,0X10,0X00,0XF4,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0XF7,0X01,0X56,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0X5C,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XC7,0X3F,0X54,0X3D,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XA6,0X3F,0X8D,0XDF,0X96,0X3F,0X9E,0X1F,0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,
+0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,
+0X96,0X3F,0X96,0X3F,0X96,0X3F,0XA6,0X7F,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X85,0X3F,0X96,0X5F,
+0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,
+0X96,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,
+0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,
+0X85,0X9F,0XCF,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X96,0X3F,0X8D,0XFF,0X96,0X3F,0X96,0X3F,
+0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,0X96,0X3F,
+0X96,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,
+0X96,0X3F,0X96,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X3F,0X96,0X3F,0X85,0X5F,0XDF,0XBF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XD7,0XBF,0X85,0X7F,0X96,0X3F,0X96,0X3F,0X96,0X3F,
+0X85,0X7F,0XCF,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XEF,0XBF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X85,0X3F,0X96,0X3F,0X9E,0X3F,0X96,0X5F,0X7D,0X3F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X00,0XD3,0X00,0X53,0X00,0XF5,0X00,0XF4,0X01,0X15,0X00,0XF4,0X00,0XF5,0X00,0XF5,
+0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF5,0X00,0XF4,0X00,0XF4,
+0X00,0XF4,0X00,0XF4,0X00,0XD5,0X00,0XF4,0X01,0X14,0X01,0XD7,0X3B,0XFC,0XEF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X8E,0X3F,0X00,0X10,0X00,0XF4,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,
+0X00,0XF4,0X00,0XF4,0X00,0XF5,0X01,0X14,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF4,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,
+0X00,0X12,0X02,0X99,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0XD4,0X00,0X53,0X00,0XF4,0X00,0XF4,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF4,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF4,
+0X00,0XF5,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF5,0X00,0XF4,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF4,0X00,0XF5,0X00,0XF5,0X00,0X11,0X33,0XDB,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X2B,0XBC,0X00,0X11,0X00,0XF5,0X00,0XF4,0X00,0XF6,
+0X00,0X11,0X1B,0XBB,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XC7,0X3F,0X00,0X11,0X00,0XF5,0X00,0XF5,0X01,0X15,0X00,0X10,0X75,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X78,0X02,0X38,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0XB8,0X02,0XB8,
+0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0XB9,0X02,0XB9,0X02,0X99,
+0X02,0XB9,0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X79,0X02,0X38,0X00,0XF4,0X00,0X54,
+0X85,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XAE,0XDF,0X01,0X15,0X02,0X99,
+0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X9A,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X76,0X34,0X1C,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X38,0X02,0X18,0X02,0X79,0X02,0XB9,
+0X02,0XB9,0X02,0X98,0X02,0X98,0X02,0XB9,0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X9A,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0XB9,
+0X02,0X99,0X02,0X98,0X02,0XB8,0X02,0XB9,0X02,0X99,0X02,0XB9,0X01,0X35,0X64,0XFE,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0XB9,0X02,0X99,0X02,0XB9,
+0X01,0X36,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XF5,0X9E,0X1F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X77,0X02,0X17,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X79,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0XB9,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X78,0X02,0X99,0X02,0XB8,0X02,0XB8,0X02,0X79,
+0X00,0X12,0X9E,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XAF,0X1F,0X00,0XF4,0X02,0XB9,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,
+0X02,0X99,0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X79,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X76,0X33,0XDB,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X38,0X02,0X18,0X02,0X98,0X02,0XB9,
+0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0XB9,0X02,0X99,0X02,0X98,
+0X02,0X98,0X02,0X99,0X02,0X78,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0X36,0X5C,0XFE,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0XFD,0X01,0X36,0X02,0X98,0X02,0X99,0X02,0X99,
+0X01,0X36,0X44,0XFD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X14,0X02,0X98,0X02,0X79,0X02,0X9A,0X00,0XB5,0X96,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X38,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0XD9,0X02,0X18,0X00,0XF5,
+0X00,0XF4,0X00,0XF4,0X00,0XF5,0X00,0XF4,0X00,0XF5,0X00,0XF4,0X00,0XF4,0X01,0X15,
+0X01,0X76,0X02,0X58,0X02,0XB9,0X02,0X99,0X02,0X79,0X02,0X78,0X02,0X99,0X02,0XB9,
+0X02,0X17,0X01,0X15,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X8E,0X3F,0X00,0X10,0X00,0XF5,
+0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF4,0X00,0XF5,0X00,0XF5,0X00,0XF4,0X00,0XF4,
+0X01,0X97,0X02,0XD8,0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X99,0X01,0X36,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,
+0X00,0X12,0X02,0XB9,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0XB4,0X00,0X53,0X00,0XF5,0X00,0XF5,
+0X00,0XF4,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF4,0X00,0XF4,0X01,0XD7,0X02,0XDA,
+0X02,0X98,0X02,0X78,0X02,0X98,0X02,0X99,0X02,0X99,0X01,0X36,0X00,0XF3,0X00,0XD4,
+0X00,0XF5,0X00,0XF5,0X00,0XF4,0X00,0XF5,0X00,0XF4,0X01,0X15,0X00,0X11,0X33,0XDC,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFF,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0XB9,
+0X01,0X35,0X4C,0XFD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X79,0X02,0X99,0X02,0X98,0X00,0XB4,0X9E,0X5F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X78,0X01,0XF7,0X02,0X99,0X02,0X78,0X02,0XB9,0X01,0XD7,0X13,0X7B,0XB6,0XDF,
+0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0XBF,0X8D,0XDF,
+0X2B,0XDC,0X01,0X55,0X01,0XB6,0X02,0XD9,0X02,0X99,0X02,0X79,0X02,0X79,0X02,0X98,
+0X02,0XD9,0X00,0X74,0X75,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X95,0X7F,0XA6,0X7F,
+0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X5F,0XA6,0X7F,0XAE,0XDF,
+0X54,0X9E,0X01,0XD7,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X58,0X02,0X78,0X8D,0XDF,
+0XAE,0XBF,0XA6,0X7F,0XA6,0X5F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,0XA6,0X7F,
+0X95,0XBF,0XD7,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XA6,0X5F,0X9E,0X1F,0XA6,0X7F,0X9E,0X7F,
+0XA6,0X5F,0XA6,0X5F,0XA6,0X5F,0XA6,0X7F,0XA6,0X7F,0XB6,0XBF,0X4C,0X5C,0X01,0XD7,
+0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X79,0X02,0X57,0X85,0X9F,0XAE,0X9F,0XA6,0X7F,
+0XA6,0X7F,0XA6,0X7F,0X9E,0X7F,0XA6,0X5F,0XA6,0X5F,0X9E,0X7F,0X95,0XBF,0XE7,0XDF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X35,0X02,0X99,0X02,0XB9,0X02,0X98,
+0X01,0X36,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X00,0XF5,0X02,0X98,0X02,0X98,0X02,0X98,0X00,0XD4,0X96,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X57,0X02,0X17,0X02,0X99,0X02,0X98,0X02,0X99,0X00,0XB4,0X6D,0X7F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X02,0X37,0X01,0X96,0X02,0XB9,0X02,0X98,0X02,0X78,0X02,0X99,
+0X02,0X99,0X01,0X96,0X0B,0X3A,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X00,0XF5,0X02,0X79,0X02,0X99,0X02,0X99,0X01,0XF7,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XD7,0X7F,0X00,0X94,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X17,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XDE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X98,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0X15,0X54,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X36,0X02,0X78,0X02,0X99,0X02,0X78,0X02,0X99,
+0X02,0X99,0X02,0X38,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0XBF,0X01,0X15,0X02,0X98,0X02,0X99,0X02,0X99,0X01,0XF7,0X02,0X79,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XBE,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X38,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X79,0X02,0X99,
+0X01,0X36,0X55,0X3E,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XF7,0XFF,0X00,0XF4,0X02,0X79,0X02,0X78,0X02,0XB9,0X00,0XD5,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X38,0X02,0X79,0X02,0X79,0X02,0XB9,0X00,0XF5,0X54,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X23,0XDB,0X01,0X56,0X02,0X78,0X02,0X98,0X02,0X99,
+0X02,0X99,0X02,0X38,0X01,0XB7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X76,0X44,0X9D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XC7,0X1F,0X01,0X35,0X02,0X99,0X02,0X78,0X02,0XB9,0X00,0XB4,0X9E,0X5F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X78,0X01,0XF7,0X02,0X98,0X02,0X98,0X02,0X99,0X01,0X15,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XBD,0X00,0XF5,0X02,0X99,0X02,0X98,0X02,0X79,
+0X02,0X98,0X02,0X58,0X01,0XD6,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X79,0X02,0X79,0X02,0X58,0X02,0X78,0X02,0X58,0X02,0X78,0X02,0X58,
+0X02,0X78,0X02,0X58,0X02,0X37,0X02,0XD9,0X44,0X5D,0XC6,0XDF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X35,0X02,0X38,0X02,0X58,
+0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X78,0X02,0X57,0X02,0X58,0X02,0X78,0X02,0X37,
+0X02,0X78,0X54,0X7D,0XD7,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XEF,0XFF,0X6D,0X3E,
+0X13,0X9B,0X02,0X78,0X02,0X38,0X02,0X58,0X02,0X78,0X02,0X57,0X02,0X78,0X02,0X58,
+0X02,0X58,0X02,0X58,0X02,0X78,0X00,0XB3,0XBF,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0X75,0X02,0X17,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X78,
+0X02,0X78,0X02,0X77,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X17,0X02,0XD9,0X54,0XDE,
+0XE7,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XBE,0XDF,0X4C,0X7D,
+0X02,0XF9,0X02,0X38,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X57,0X02,0X58,0X02,0X58,
+0X02,0X78,0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X01,0XF8,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0X35,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X44,0X7C,0X01,0X35,0X02,0X99,0X02,0X99,0X02,0XB8,
+0X02,0X99,0X02,0X38,0X01,0XB7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0XB9,0X02,0X59,0X01,0XF8,0X02,0X18,0X02,0X17,0X01,0XF7,0X02,0X17,0X02,0X17,
+0X02,0X17,0X02,0X18,0X02,0X38,0X01,0XB7,0X01,0X15,0X00,0X73,0X12,0X99,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0XD4,0X01,0XF7,0X02,0X18,
+0X02,0X17,0X02,0X17,0X02,0X18,0X01,0XF8,0X02,0X17,0X02,0X17,0X02,0X17,0X02,0X18,
+0X01,0XD7,0X01,0X14,0X00,0X33,0X44,0X1D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X1A,0XFA,0X00,0XD4,0X00,0XD5,
+0X01,0X76,0X02,0X18,0X02,0X17,0X02,0X17,0X01,0XF8,0X01,0XF7,0X02,0X17,0X02,0X18,
+0X02,0X17,0X02,0X17,0X02,0X17,0X00,0X53,0XAE,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0X15,0X01,0XD7,0X02,0X18,0X02,0X17,0X02,0X17,0X02,0X17,0X01,0XF8,0X02,0X18,
+0X02,0X17,0X02,0X18,0X02,0X18,0X01,0XF7,0X01,0XF8,0X02,0X17,0X01,0XD7,0X00,0XF5,
+0X00,0X94,0X12,0XB8,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X9D,0XFF,0X01,0XB7,0X00,0XB4,0X01,0X14,
+0X01,0XB7,0X02,0X17,0X02,0X37,0X02,0X17,0X02,0X18,0X01,0XF7,0X02,0X17,0X02,0X17,
+0X01,0XF8,0X02,0X38,0X02,0XB9,0X02,0X98,0X02,0X79,0X02,0XB9,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X01,0XF7,0X02,0X99,0X02,0XB8,0X02,0XB9,0X01,0X15,0X5D,0X1F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0XB9,0X01,0XB7,0X02,0X99,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB9,0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0XB9,0X02,0X98,0X02,0X99,0X02,0XB8,0X02,0XD9,0X00,0XB4,0X02,0X58,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X79,0X02,0X99,0X02,0X99,0X02,0XB8,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X00,0X11,0X7D,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XCF,0XBF,0X00,0X53,0X01,0X35,0X02,0X99,0X02,0XB9,
+0X02,0XB8,0X02,0X79,0X02,0XB8,0X02,0XB8,0X02,0X79,0X02,0X99,0X02,0X98,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XF5,0XBF,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0X96,0X02,0X58,0X02,0X99,0X02,0X99,0X02,0XB8,0X02,0X98,0X02,0X79,0X02,0X99,
+0X02,0X99,0X02,0X98,0X02,0X78,0X02,0X98,0X02,0X98,0X02,0XB9,0X02,0X99,0X02,0XB9,
+0X02,0X99,0X01,0X56,0X00,0X13,0XDF,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X3B,0XBB,0X00,0X32,0X01,0XD7,0X02,0XB9,0X02,0X99,
+0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X99,
+0X02,0X99,0X02,0XB9,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0XB8,0X02,0X99,0X02,0X99,0X00,0XF5,0X5D,0X1E,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XBE,0XFF,0X01,0X15,0X02,0X98,0X02,0X99,0X02,0X98,0X02,0XB8,
+0X02,0X78,0X01,0XD6,0X02,0XB9,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0XDA,0X02,0X18,0X01,0X16,0X01,0X15,0X01,0X15,0X01,0X35,0X01,0X36,0X01,0X15,
+0X01,0X15,0X01,0X76,0X02,0X58,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0XDA,0X00,0X73,
+0X8D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X98,
+0X02,0X99,0X02,0XD9,0X02,0X37,0X00,0XF5,0X01,0X15,0X01,0X16,0X02,0X17,0X02,0XB9,
+0X02,0X98,0X02,0X99,0X02,0X99,0X01,0XF7,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0XD5,0X01,0X97,0X02,0XD9,0X02,0X99,0X02,0XD9,
+0X02,0X38,0X01,0X36,0X00,0XF5,0X01,0X14,0X01,0X15,0X00,0XF5,0X01,0X15,0X00,0XF5,
+0X00,0XF4,0X00,0XF5,0X00,0XF5,0X00,0X11,0X9E,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X00,0X12,0X00,0XB4,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X01,0X15,0X00,0XF5,0X00,0XF5,
+0X01,0X15,0X00,0XD5,0X01,0X15,0X00,0XF5,0X01,0X15,0X01,0XD7,0X02,0XDA,0X02,0X99,
+0X02,0XB8,0X02,0XD9,0X01,0X96,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X33,0XDC,0X00,0X74,0X02,0XB9,0X02,0X98,0X02,0X79,0X02,0X99,
+0X02,0XB9,0X02,0X17,0X01,0X55,0X01,0X36,0X01,0X15,0X01,0X15,0X01,0X16,0X01,0X15,
+0X00,0XF4,0X01,0XB7,0X02,0XD9,0X02,0X98,0X02,0X99,0X02,0XB9,0X00,0XD4,0X96,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X79,0X02,0X98,0X02,0X99,0X01,0X15,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X9E,0X1F,0X01,0X56,0X02,0X38,0X02,0XB9,0X02,0X99,0X02,0X79,0X02,0X98,
+0X02,0XD9,0X00,0XF5,0X44,0X5D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XA6,0XBF,0X9E,0X7F,
+0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,0XA6,0XBF,
+0X8E,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X38,0X03,0X39,0X75,0X7F,0X6D,0X3F,0X6D,0X1F,0X6D,0X3E,0X65,0X1E,0X6D,0X3E,
+0X65,0X5F,0X34,0X1C,0X01,0X96,0X01,0XD7,0X02,0XD9,0X02,0X98,0X02,0XB8,0X01,0XF7,
+0X01,0XB6,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X55,0X02,0X79,0X02,0X99,
+0X02,0X98,0X02,0X17,0X13,0X7A,0X7D,0X9F,0X75,0X7F,0X65,0X1F,0X02,0X58,0X01,0X96,
+0X02,0XD9,0X02,0X98,0X02,0X99,0X02,0XB9,0X00,0XB4,0XBF,0X1F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X02,0X37,0X01,0X36,0X02,0XDA,0X02,0X99,0X02,0XD9,0X01,0X76,
+0X01,0XD7,0X64,0XDF,0X85,0XFF,0X96,0X7F,0XAE,0XFF,0XA6,0XFF,0XA6,0XDF,0XAE,0XDF,
+0XA6,0XDF,0XAE,0XDF,0XA6,0XFF,0X95,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XA6,0X3F,0XA6,0XBF,0XA6,0XDF,0XAE,0XDF,0XA6,0XDF,0XA6,0XDF,0XA6,0XDF,0XA6,0XDF,
+0XA6,0XDF,0XAE,0XDF,0XAE,0XDF,0XA6,0X9F,0X75,0X9F,0X02,0X99,0X01,0X56,0X02,0XB9,
+0X02,0X79,0X02,0X99,0X02,0XD9,0X00,0X53,0X85,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X9E,0X5F,0X00,0X13,0X02,0X99,0X02,0X98,0X02,0X79,0X02,0XD9,0X02,0X58,
+0X00,0XF5,0X02,0X78,0X3C,0X7D,0X65,0X3E,0X6D,0X3F,0X6D,0X3F,0X6D,0X3E,0X6D,0X3F,
+0X75,0X9F,0X3C,0X3D,0X02,0X18,0X02,0X99,0X02,0X78,0X02,0X99,0X00,0XB5,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X38,0X02,0X17,0X02,0X99,0X02,0X78,0X02,0X98,0X02,0X58,0X02,0XD9,0X13,0X7A,
+0X0B,0X3A,0X0B,0X3A,0X0B,0X3A,0X0B,0X3A,0X0B,0X3A,0X0B,0X3A,0X0B,0X1A,0X0B,0X1A,
+0X02,0X17,0X00,0XF5,0X02,0X38,0X02,0XDA,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X79,
+0X02,0X79,0X00,0X54,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0X94,0X00,0X74,
+0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,0X00,0XF5,
+0X00,0X11,0XC7,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X15,0X5D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0XF7,0X01,0XD7,0X02,0XB9,0X02,0X78,0X02,0XD9,
+0X00,0X94,0X9E,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X98,0X00,0XB5,0X95,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X0A,0XD9,
+0X01,0XD7,0X02,0X99,0X02,0XB9,0X02,0XB9,0X00,0XD4,0X9E,0X1F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X4C,0X7D,0X00,0X93,0X02,0XDA,0X02,0X79,0X02,0XB9,0X01,0X95,0X0A,0XFA,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X2B,0X9B,0X01,0X96,
+0X02,0X98,0X02,0XB9,0X02,0X98,0X01,0X97,0X03,0X19,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X01,0X96,0X01,0XF8,0X02,0XBA,0X02,0X99,0X02,0X99,0X02,0X38,0X01,0X15,
+0X95,0XDF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X00,0XF5,0X02,0X99,0X02,0X98,0X02,0X99,0X00,0XB5,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X18,0X02,0X99,0X02,0X98,0X02,0X79,0X02,0XDA,0X02,0X38,0X01,0X96,
+0X01,0XB7,0X01,0XB7,0X01,0XB7,0X01,0XB7,0X01,0XB7,0X01,0XB7,0X01,0X97,0X01,0XB7,
+0X02,0X38,0X02,0X99,0X02,0XB9,0X02,0X78,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0XB9,
+0X00,0X53,0X44,0X5D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X37,0X02,0X38,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X15,0XDF,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X55,0X4C,0XFD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XBF,0X5F,0X00,0XF6,0X02,0X78,0X02,0X98,0X02,0XB9,
+0X00,0XB4,0X6C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X00,0XF4,0X7D,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XCF,0XBF,
+0X00,0XF5,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XF4,0XA6,0X3F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X01,0X36,0X02,0X38,0X02,0X98,0X02,0X99,0X02,0X79,0X00,0XF5,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,
+0X02,0X38,0X02,0X79,0X02,0X78,0X02,0X38,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XB6,0XDF,0X00,0X93,0X02,0XB9,0X02,0X98,0X02,0X99,0X02,0XB9,0X00,0XB4,0XAE,0X5F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XE7,0XFF,0X00,0XF5,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X79,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XB8,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X79,0X02,0X78,0X02,0XB9,0X02,0X99,0X01,0XD7,0X00,0X33,
+0X33,0X5A,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0XF5,0X00,0XD5,
+0X01,0X56,0X01,0X56,0X01,0X56,0X01,0X56,0X01,0X56,0X01,0X56,0X01,0X56,0X01,0X56,
+0X00,0X12,0XCF,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X76,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XE7,0XFF,
+0X00,0X33,0X01,0XD7,0X01,0XF7,0X02,0X17,0X00,0X13,0X95,0XDF,0XFF,0XFF,0XFF,0XFF,
+0XCF,0X5F,0X00,0XD5,0X02,0XB8,0X02,0X99,0X02,0X99,0X01,0X97,0X02,0XD9,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X79,
+0X01,0XF7,0X02,0X79,0X02,0X79,0X02,0X58,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X3C,0X3D,0X01,0X16,0X02,0XB9,0X02,0X98,0X02,0X99,0X01,0X76,0X13,0X5A,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0XD9,0X02,0X37,0X01,0X55,
+0X01,0X76,0X01,0X76,0X01,0X76,0X01,0X95,0X01,0X35,0X01,0XB7,0X02,0XB9,0X02,0X99,
+0X02,0X79,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0XB9,0X01,0XB6,0X01,0XF7,0X95,0XDF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X43,0XFB,0X2B,0XBB,
+0X34,0X1C,0X34,0X1C,0X34,0X1C,0X34,0X1C,0X34,0X1C,0X34,0X1C,0X34,0X1C,0X34,0X1C,
+0X22,0XF9,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0XB8,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XEF,0XFF,
+0X01,0X76,0X02,0X98,0X02,0XB9,0X02,0X99,0X01,0X15,0XAE,0X7F,0XFF,0XFF,0XFF,0XFF,
+0X85,0XDF,0X00,0XF4,0X02,0XB8,0X02,0X79,0X02,0X99,0X01,0XB7,0X23,0X9B,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X77,
+0X02,0X18,0X02,0X99,0X02,0X99,0X02,0X58,0X01,0X76,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0XD9,0X01,0XD7,0X02,0X99,0X02,0X99,0X02,0XB8,0X00,0XB4,0XBE,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X79,0X02,0X99,0X02,0X98,0X02,0X38,0X02,0XFA,0X3C,0X5C,
+0X2B,0XFC,0X23,0XFC,0X2C,0X1C,0X2B,0XFB,0X3C,0X5D,0X03,0X1A,0X02,0X17,0X02,0XB9,
+0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X99,0X01,0X56,0X8D,0XDF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0X99,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X54,0XBE,0X01,0X16,0X02,0X99,0X02,0X78,0X02,0X99,0X02,0XB8,0X02,0X78,0X01,0XB7,
+0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X96,
+0X01,0XB6,0X01,0X97,0X01,0X96,0X00,0X12,0XAE,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XCF,0X1F,0X3B,0XFC,0X02,0X58,0X01,0X96,0X01,0X77,0X01,0X96,0X01,0X76,
+0X01,0X97,0X01,0X96,0X01,0X96,0X01,0X96,0X01,0X97,0X01,0XB6,0X01,0XB7,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X58,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X38,0X02,0X18,0X02,0X98,0X02,0X99,0X02,0X78,0X01,0X76,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X78,0X02,0X17,0X02,0X79,0X02,0X98,0X02,0X99,0X00,0XF5,0X65,0X1E,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X35,0X01,0XF8,
+0X02,0X99,0X02,0XB8,0X02,0X78,0X02,0X99,0X00,0XF4,0X75,0X9F,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0X99,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X54,0X7D,0X01,0X35,0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X38,
+0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,0X02,0X58,
+0X02,0X58,0X02,0X78,0X02,0X59,0X00,0X94,0XB7,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X44,0X1C,0X00,0X33,0X01,0X35,0X01,0XF8,0X02,0X59,0X02,0X58,0X02,0X58,0X02,0X58,
+0X02,0X59,0X02,0X58,0X02,0X58,0X02,0X78,0X02,0X59,0X02,0X58,0X02,0X58,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X58,0X01,0X97,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0XD7,0X02,0X38,0X02,0X98,0X02,0X99,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X01,0XF7,0X02,0X99,0X02,0X99,0X02,0XB8,0X00,0XF4,0X5D,0X3E,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X8D,0XDF,0X00,0X94,
+0X02,0XB9,0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X79,0X00,0XF5,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X85,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X54,0X5D,0X01,0X35,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X78,
+0X02,0X78,0X02,0X78,0X02,0X78,0X02,0X78,0X02,0X78,0X02,0X78,0X02,0X79,0X02,0X78,
+0X02,0X79,0X02,0X78,0X02,0X78,0X00,0XD4,0XB7,0X1F,0XFF,0XFF,0XFF,0XFF,0X9E,0X7F,
+0X00,0X13,0X02,0X58,0X02,0XD9,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X78,0X02,0X79,
+0X02,0X79,0X02,0X78,0X02,0X79,0X02,0X99,0X02,0X79,0X02,0X79,0X02,0X78,0X02,0X98,
+0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X58,0X01,0X76,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0XD7,0X02,0X38,0X02,0X98,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0X15,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0XD8,
+0X01,0X56,0X02,0XB9,0X02,0X99,0X02,0X99,0X02,0XB9,0X01,0X56,0X0A,0XD9,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X99,0X01,0X15,0X85,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X4C,0XDE,0X01,0X16,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0XD9,0X02,0X58,0X01,0X36,
+0X01,0X56,0X01,0X36,0X01,0X36,0X01,0X56,0X01,0X36,0X01,0X36,0X01,0X36,0X01,0X56,
+0X01,0X35,0X01,0X56,0X01,0X75,0X00,0X10,0XA6,0X7F,0XFF,0XFF,0XFF,0XFF,0X01,0X56,
+0X01,0XF8,0X02,0XB8,0X02,0X79,0X02,0XB8,0X02,0X98,0X01,0X35,0X00,0XF5,0X01,0X55,
+0X01,0X36,0X01,0X35,0X01,0X35,0X01,0X55,0X01,0X36,0X01,0X56,0X01,0X76,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X78,0X01,0X76,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X37,0X02,0X18,0X02,0X98,0X02,0X99,0X02,0X78,0X01,0X76,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X57,0X02,0X17,0X02,0X79,0X02,0X99,0X02,0X99,0X01,0X35,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XFF,
+0X00,0X94,0X02,0XB9,0X02,0X98,0X02,0X78,0X02,0X98,0X02,0XD9,0X00,0X13,0XA6,0X9F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0XB9,0X00,0XF4,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X8D,0XDF,0X00,0XF4,0X02,0X99,0X02,0X79,0X02,0X99,0X01,0XD7,0X1B,0X9B,0XFF,0XFF,
+0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,
+0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XE7,0XDF,0XFF,0XFF,0XFF,0XFF,0XAE,0XBF,0X00,0X74,
+0X02,0XB9,0X02,0X98,0X02,0X79,0X02,0X98,0X01,0XB7,0X65,0X3F,0XDF,0XFF,0XFF,0XFF,
+0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XF7,0XFF,0XFF,0XFF,0XDF,0XBF,0X02,0X78,
+0X02,0X38,0X02,0X99,0X02,0X79,0X02,0X58,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0XD9,0X01,0XD7,0X02,0X99,0X02,0X79,0X02,0X98,0X00,0XB4,0XC7,0X5F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X18,0X02,0X98,0X02,0X79,0X02,0XB9,0X00,0XF5,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X23,0X9B,0X01,0X35,0X02,0XB9,0X02,0X99,0X02,0X78,0X02,0XB8,0X01,0XD7,0X01,0XD7,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XF8,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB8,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X99,
+0X02,0X98,0X01,0X15,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XD7,0XBF,0X00,0XD4,0X02,0X99,0X02,0X99,0X02,0X98,0X01,0X96,0X0B,0X5B,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X15,
+0X02,0X98,0X02,0X99,0X02,0X99,0X01,0X36,0X44,0X5D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X57,
+0X01,0XF7,0X02,0X79,0X02,0X99,0X02,0X58,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X3C,0X3C,0X01,0X56,0X02,0X99,0X02,0X98,0X02,0X99,0X01,0X56,0X23,0XBB,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XDF,0XDF,0X01,0X15,0X02,0X99,0X02,0X99,0X02,0X99,0X00,0XD4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X01,0XF7,0X02,0XB8,0X02,0X98,0X02,0X98,0X01,0X15,0X5D,0X1F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X00,0X93,0X02,0XB8,0X02,0X99,0X02,0X78,0X02,0XB9,0X02,0XD9,0X00,0X73,
+0X9E,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X17,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X38,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0XFE,0X01,0X35,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X36,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XF4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X79,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X99,0X02,0X78,0X02,0X78,0X01,0X36,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0X9D,0X01,0X35,
+0X02,0X99,0X02,0X98,0X02,0X99,0X00,0X94,0XB6,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X77,
+0X02,0X18,0X02,0X98,0X02,0X99,0X02,0X58,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X96,0X1F,0X00,0X94,0X02,0XD9,0X02,0X99,0X02,0X79,0X02,0XB9,0X00,0X94,0XE7,0XDF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XD7,0XFF,0X01,0X15,0X02,0X78,0X02,0X79,0X02,0X98,0X00,0XF4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X38,0X02,0X99,0X02,0X78,0X02,0X99,0X01,0X15,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X02,0XB9,0X01,0X76,0X02,0X98,0X02,0X99,0X02,0X78,0X02,0X99,0X01,0XB7,
+0X02,0X78,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X00,0XF5,0X02,0X99,0X02,0X78,0X02,0X78,0X02,0X18,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF4,
+0X02,0XB8,0X02,0X99,0X02,0X99,0X02,0X17,0X02,0X17,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XDE,0X01,0X36,0X02,0X98,0X02,0X98,0X02,0XB9,
+0X01,0X55,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X97,0X02,0X58,0X02,0X99,0X02,0XB9,
+0X00,0XD4,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X79,0X02,0X99,
+0X02,0X99,0X00,0XF5,0X7D,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X0A,0XD9,0X01,0X15,0X02,0XD8,0X02,0X78,0X02,0X99,0X01,0X34,0X6D,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0XDE,0X01,0X15,
+0X02,0X99,0X02,0X99,0X02,0X99,0X01,0X35,0X44,0X7D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X58,
+0X01,0XF7,0X02,0X98,0X02,0X99,0X02,0X59,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X00,0XD4,0X02,0X79,0X02,0X99,0X02,0X99,0X02,0X99,0X01,0XD7,0X01,0XF7,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X00,0XF4,0X02,0X78,0X02,0X99,0X02,0X99,0X00,0XD5,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X17,0X02,0X78,0X02,0X98,0X02,0X99,0X00,0XF4,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XEF,0XFF,0X00,0X94,0X02,0XB8,0X02,0X99,0X02,0X79,0X02,0X99,0X02,0XB8,
+0X00,0X93,0XAE,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X01,0X15,0X02,0X78,0X02,0X99,0X02,0X99,0X01,0XF7,0X02,0X79,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XBE,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X35,0X02,0XB9,0X02,0X79,0X02,0X99,
+0X01,0X56,0X4C,0XDD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X79,0X02,0XB9,
+0X00,0XF5,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0XB8,
+0X02,0X99,0X01,0X15,0X85,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X00,0XF5,0X02,0X38,0X02,0XB9,0X02,0X99,0X02,0X98,0X01,0X36,
+0X4C,0X7D,0XDF,0X9F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X8E,0X1F,0X00,0XD4,
+0X02,0XBA,0X02,0X99,0X02,0X98,0X02,0X79,0X01,0X97,0X8D,0XDF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0X78,
+0X02,0X18,0X02,0X99,0X02,0X78,0X02,0X59,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X1B,0X7A,0X01,0X15,0X02,0XD9,0X02,0X99,0X02,0X99,0X02,0XD9,0X01,0XD7,
+0X01,0X56,0X5C,0XDE,0XCF,0X7F,0XEF,0XFF,0XE7,0XDF,0XE7,0XDF,0XE7,0XDF,0XE7,0XFF,
+0XEF,0XFF,0X85,0XBF,0X01,0XB7,0X02,0XB9,0X02,0X98,0X02,0XB8,0X00,0XB5,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X02,0X18,0X02,0X99,0X02,0X99,0X02,0XB9,0X01,0X16,0X5C,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X0B,0X3B,0X01,0X56,0X02,0XB8,0X02,0X79,0X02,0X98,0X02,0X99,
+0X01,0XD7,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XD7,0X9F,0X01,0X15,0X02,0XB8,0X02,0X79,0X02,0X99,0X01,0XF7,0X02,0X98,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X98,0X02,0X99,0X02,0XB8,0X02,0X37,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X5C,0XFE,0X01,0X36,0X02,0X99,0X02,0X79,0X02,0X99,
+0X01,0X35,0X4C,0XFE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X97,0X02,0X59,0X02,0X79,0X02,0XB8,
+0X00,0XF4,0X6D,0X1E,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X78,0X02,0X79,
+0X02,0X99,0X00,0XF5,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X9E,0X7F,0X00,0X12,0X02,0XB9,0X02,0X99,0X02,0XB9,0X02,0X99,
+0X01,0X55,0X00,0XD5,0X01,0XB7,0X02,0X37,0X02,0X17,0X02,0X17,0X02,0X18,0X02,0X17,
+0X02,0X37,0X02,0X37,0X02,0X37,0X00,0X73,0XB6,0XDF,0XFF,0XFF,0XFF,0XFF,0X00,0XD4,
+0X02,0X78,0X02,0X99,0X02,0X79,0X02,0XB9,0X02,0X98,0X01,0X15,0X01,0X97,0X02,0X58,
+0X02,0X37,0X01,0XF7,0X02,0X17,0X02,0X17,0X02,0X17,0X02,0X58,0X02,0X38,0X02,0X99,
+0X02,0X99,0X02,0X99,0X02,0XB8,0X02,0X58,0X01,0X76,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0X00,0X53,0X01,0XD7,0X02,0XB9,0X02,0XB8,0X02,0X99,0X02,0XB9,
+0X02,0X58,0X01,0X15,0X00,0XF4,0X01,0X14,0X01,0X15,0X00,0XF5,0X01,0X15,0X01,0X15,
+0X01,0X15,0X01,0X96,0X02,0XDA,0X02,0X78,0X02,0X99,0X02,0XB9,0X00,0XD4,0X96,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X58,0X01,0XF7,0X02,0X78,0X02,0X98,0X02,0X99,0X00,0XF5,0X5C,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XD7,0X7F,0X00,0X54,0X02,0XB9,0X02,0X98,0X02,0X99,0X02,0X98,
+0X02,0XB8,0X00,0X94,0XB6,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XDF,0X9F,0X00,0XF5,0X02,0X99,0X02,0X98,0X02,0X98,0X01,0XF7,0X02,0X98,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0X00,0XF5,
+0X02,0X99,0X02,0X79,0X02,0X99,0X02,0X37,0X01,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0XFE,0X01,0X36,0X02,0XB8,0X02,0X99,0X02,0X99,
+0X01,0X36,0X44,0XFD,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X78,0X02,0X98,0X02,0XB8,
+0X00,0XD5,0X6D,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X56,0X02,0X79,0X02,0X99,
+0X02,0XB8,0X01,0X15,0X85,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X2B,0X7A,0X00,0X33,0X02,0X58,0X02,0XD9,0X02,0X79,
+0X02,0X99,0X02,0X99,0X02,0X38,0X02,0X38,0X02,0X38,0X02,0X38,0X02,0X38,0X02,0X38,
+0X02,0X18,0X02,0X38,0X02,0X38,0X00,0X93,0XAE,0XFF,0XFF,0XFF,0XFF,0XFF,0X0B,0X19,
+0X00,0XB4,0X02,0XD9,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X58,0X02,0X38,
+0X02,0X38,0X02,0X38,0X02,0X18,0X02,0X38,0X02,0X38,0X02,0X17,0X02,0X38,0X02,0X99,
+0X02,0X98,0X02,0X79,0X02,0X78,0X02,0X78,0X01,0X96,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XCF,0X1F,0X00,0X93,0X01,0X76,0X02,0XB9,0X02,0XB9,0X02,0X98,
+0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X79,0X02,0X79,0X02,0X99,0X02,0X79,0X02,0X99,
+0X02,0X99,0X02,0XB9,0X02,0X79,0X02,0X98,0X02,0X99,0X02,0XBA,0X00,0XB4,0X9E,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X02,0X38,0X02,0X17,0X02,0X99,0X02,0X99,0X02,0XB8,0X00,0XF5,0X54,0XFE,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X02,0XD9,0X01,0X56,0X02,0XB9,0X02,0X99,0X02,0X99,
+0X02,0X99,0X01,0XB7,0X02,0X58,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XD7,0X9F,0X00,0XF5,0X02,0XB9,0X02,0X79,0X02,0X99,0X02,0X18,0X02,0X78,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XBE,0XDF,0X00,0XF4,
+0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X38,0X01,0XD7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X54,0XDE,0X01,0X35,0X02,0X99,0X02,0X99,0X02,0X99,
+0X01,0X35,0X4C,0XDE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X96,0X02,0X58,0X02,0X78,0X02,0X99,
+0X00,0XF4,0X6D,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0X36,0X02,0X79,0X02,0X79,
+0X02,0XB9,0X00,0XF5,0X7D,0X7F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X74,0XDE,0X00,0XD5,0X00,0XD4,0X01,0XD7,
+0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X98,0X02,0X98,0X02,0X99,
+0X02,0X99,0X02,0X98,0X02,0X98,0X00,0XF5,0XB7,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X01,0X96,0X00,0X93,0X01,0XD7,0X02,0X78,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X99,
+0X02,0X98,0X02,0X79,0X02,0X99,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X99,0X02,0X99,
+0X02,0X98,0X02,0X99,0X02,0X98,0X02,0X59,0X01,0X76,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X01,0XF7,0X00,0X93,0X01,0X56,0X02,0X38,
+0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X78,0X02,0XB9,0X02,0X78,
+0X02,0X98,0X02,0X98,0X02,0X99,0X02,0X99,0X02,0X78,0X02,0X99,0X00,0XB5,0X96,0X3F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X00,0XF4,0X00,0X93,0X01,0X15,0X00,0XF5,0X01,0X35,0X00,0X11,0X33,0XFC,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XE7,0XFF,0X00,0X12,0X00,0XF5,0X01,0X35,0X01,0X15,
+0X01,0X15,0X01,0X35,0X00,0X10,0X64,0XDE,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XC7,0X1F,0X00,0X11,0X01,0X15,0X01,0X15,0X01,0X35,0X00,0X54,0X01,0X15,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X9E,0X1F,0X00,0X11,
+0X01,0X16,0X01,0X14,0X01,0X15,0X00,0X94,0X00,0X92,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X33,0XFB,0X00,0X11,0X01,0X36,0X01,0X14,0X01,0X15,
+0X00,0X12,0X1B,0XDC,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0X11,0X00,0XF4,0X01,0X15,0X01,0X35,
+0X00,0X11,0X4C,0X3B,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X00,0X12,0X00,0XF5,0X01,0X15,
+0X01,0X36,0X00,0X11,0X64,0X9D,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0X64,0X9E,0X02,0X78,
+0X01,0X76,0X01,0X15,0X01,0X35,0X01,0X15,0X00,0XF5,0X01,0X34,0X01,0X35,0X00,0XF5,
+0X01,0X34,0X01,0X35,0X00,0XF5,0X00,0X11,0XA6,0X5F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0X6C,0X7D,0X02,0X57,0X01,0X36,0X00,0XF5,0X00,0XF5,0X01,0X15,0X01,0X35,
+0X01,0X15,0X00,0XF5,0X01,0X35,0X01,0X15,0X01,0X15,0X01,0X15,0X01,0X15,0X01,0X35,
+0X01,0X15,0X01,0X15,0X01,0X35,0X00,0XF5,0X00,0X12,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0X5F,0X1B,0X5A,0X01,0XD7,
+0X01,0X34,0X01,0X16,0X00,0XF5,0X01,0X15,0X01,0X15,0X01,0X35,0X01,0X14,0X01,0X15,
+0X01,0X15,0X01,0X15,0X01,0X35,0X00,0XF5,0X01,0X15,0X01,0X35,0X00,0X11,0X7D,0X7F,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XC7,0X5F,0XBF,0X1F,0XC7,0X7F,0XC7,0X7F,0XC7,0X7F,0XAE,0XBF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XCF,0XBF,0XB7,0X1F,0XC7,0X7F,0XC7,0X7F,
+0XC7,0X5F,0XC7,0X7F,0XB6,0XDF,0XBF,0X3F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XB6,0XBF,0XC7,0X7F,0XC7,0X5F,0XC7,0X7F,0XBF,0X1F,0XC7,0X7F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XAE,0X9F,
+0XC7,0X7F,0XC7,0X7F,0XC7,0X7F,0XBF,0X3F,0XBF,0X1F,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XF7,0XFF,0XAE,0XDF,0XC7,0X7F,0XC7,0X5F,0XC7,0X7F,
+0XAE,0XDF,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XDF,0XBF,0X7F,0XC7,0X7F,0XBF,0X7F,
+0XAE,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XB6,0XFF,0XC7,0X5F,0XC7,0X7F,
+0XC7,0X7F,0XAE,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XEF,0XFF,0XD7,0X9F,0XBF,0X5F,0XC7,0X5F,0XC7,0X5F,0XC7,0X5F,0XBF,0X7F,
+0XC7,0X5F,0XC7,0X5F,0XC7,0X7F,0XAE,0XBF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XD7,0X9F,0XC7,0X5F,0XC7,0X7F,0XC7,0X5F,
+0XC7,0X7F,0XBF,0X7F,0XC7,0X5F,0XC7,0X7F,0XC7,0X5F,0XC7,0X5F,0XC7,0X7F,0XC7,0X7F,
+0XC7,0X5F,0XC7,0X7F,0XC7,0X7F,0XBF,0X5F,0XB6,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XF7,0XFF,0XDF,0X9F,0XC7,0X7F,0XC7,0X7F,0XC7,0X5F,0XC7,0X5F,0XC7,0X7F,0XC7,0X5F,
+0XC7,0X5F,0XC7,0X7F,0XC7,0X7F,0XC7,0X7F,0XC7,0X5F,0XC7,0X7F,0XAE,0X9F,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+};
diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/sdram_port.h b/bsp/stm32/stm32h7r7-atk/board/port/include/sdram_port.h
new file mode 100644
index 00000000000..9ebe1c0679b
--- /dev/null
+++ b/bsp/stm32/stm32h7r7-atk/board/port/include/sdram_port.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2018-12-04 zylx The first version for STM32F4xx
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+/* Bank1 or Bank2 */
+#define SDRAM_TARGET_BANK 1
+/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
+#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
+/* data width: 8, 16, 32 */
+#define SDRAM_DATA_WIDTH 16
+/* column bit numbers: 8, 9, 10, 11 */
+#define SDRAM_COLUMN_BITS 9
+/* row bit numbers: 11, 12, 13 */
+#define SDRAM_ROW_BITS 13
+/* cas latency clock number: 1, 2, 3 */
+#define SDRAM_CAS_LATENCY 2
+/* read pipe delay: 0, 1, 2 */
+#define SDRAM_RPIPE_DELAY 0
+/* clock divid: 2, 3 */
+#define SDCLOCK_PERIOD 2
+/* refresh rate counter */
+#define SDRAM_REFRESH_COUNT ((uint32_t)0x02A5)
+#define SDRAM_SIZE ((uint32_t)0x2000000)
+
+/* Timing configuration for W9825G6KH-6 */
+/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
+/* TMRD: 2 Clock cycles */
+#define LOADTOACTIVEDELAY 2
+/* TXSR: 8x10ns */
+#define EXITSELFREFRESHDELAY 8
+/* TRAS: 5x10ns */
+#define SELFREFRESHTIME 6
+/* TRC: 7x10ns */
+#define ROWCYCLEDELAY 6
+/* TWR: 2 Clock cycles */
+#define WRITERECOVERYTIME 2
+/* TRP: 2x10ns */
+#define RPDELAY 2
+/* TRCD: 2x10ns */
+#define RCDDELAY 2
+
+/* memory mode register */
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
+#endif
diff --git a/bsp/stm32/stm32h7r7-atk/board/stldr/ATK-DNH7R7_XSPI_MULTIPLE.FLM b/bsp/stm32/stm32h7r7-atk/board/stldr/ATK-DNH7R7_XSPI_MULTIPLE.FLM
new file mode 100644
index 0000000000000000000000000000000000000000..9d462bf6af234f91fa5f13b62bc10796cd0bc82f
GIT binary patch
literal 352336
zcmd443w%`7wLiYkV;)JyWD*cUh&Yo3n2;z5SOvA^%uE;_T9SZQv9)?81UP}j1W=2X
zpPU42gZ2U1_F8)HE%x!hwzo<~qy?2`0@V7Tb_OyPtJTq3f#Ih;nM~plRDR!e&P*~v
zZ2P;v|Lwi{A!k3=UTf{O*Is+?wfAhEe|>=CIF|X3XC9V`DPOX%NAVB;S*~C%MtOzI
zX%xNel=k_r_N@QKl41EyG4N87S(w)OL7rCsLH+QPjlUZ{w@z8E3Pt_BgZ1C)9c=#=
zbIsSCj!aBhE~QwF(l8ni3#Y++4YTIDSuML;bKzrW7jaS$@zS9(>*r
z9$ZrU^8qejI2~d2iLS3OO~Ch?>n#ude1PZ02OqQv2njs@pb%%3j|^~JWh6J@Ep7^Q
zhd9r52|GVSULVMdSa$LrpAi#xiV&x6M+kh1Kn#TOL0kuxN
zdZv82TqRe_A4HFyV7(bi2{)oh&7z3=7pCn8KgQ`yR#j)BA2^a=bTbWp0@Zb^Az`TF7*KAM?>1)&K^e~
zQ|jUXn@%MIC9GGQbZSzbcI(-O{dwATXKi)=?i)JBTwISvH36T?gaL=3TpY*`h=DvU
zcy?omtH{$%eK04~?8?>t^`kuPPahbqR=5IY{f;S;y)0rmZE=SOnBzy6>_R`Vsk3!!
z^$uS=`uP0u5%KhV{>JW*@0F9Mt`nwbA-aPHISrkIP=6CiyXkb=Q3_c>SUSrJOJ14Mx&$=nMB^vFsBF_PbM+pPB
zwfwE(+|z<}7BIO|x3)gv^F+TnzXaHLZMmnt)_c0|?EabW65zz~-zm+H9O(W<_g>%R
zs4&YOdFu;T>q5iNd?it_);_y?{wqj{e}?&*pv*;x&Qi
zW=x6jGisu|(mr@w8TX!Z#=iHwB{lDHxj%UKs*=eBOZmaOvr7&Q9ue4k&a3ymC*``3
z%PQZ9GWUGsU#O<1WY>FK3CfpH`Of!PZdn|-RtwZh`7hsNB?kxlcpmV8y#VZIQ;X$i
z_~gF#d@~4(n)moz;J#QFX82Vw!Tc0PcZNb@`(-w}ou9tfbaIT&MnSNIH)+IMd*C)@_Qg2JivZ5oy=eY1N
zaMI58$@7!f6dshr$zn(rFEdTlO{!RLrhQO{Rz0LSh$?OpsDWN^IqMeb9Jq!&L+22c
zRENq_*@bnILUDsXB2vUjy4Y}^FE^5NTI6zcku6kmweB;{5W)>T2N-B3J(Q_W?U?n&
zK(4m&4AMDEfG}t(odms9-0P^z)mqO;lXv;f9P2r-B7;q8uX2c+sDMcpr7DjylR*SWr9in
zkEXjnC4DS@+2yn88BOSxk_1TGw(|<$u83zLGVmG!h<%6;uW6)zd|~6
z!FI3k)(@ZCV8Y(%clzxHZ>8iFX}D?{Z`Qz#)Xy2g4}54asdlH-bs4OQPS(Kxjq+@4
z`Nj-=GM~Z1fRjnr)TPR_?!7Z0p0RxVnr@eVCe7DG%YR4}iF`|me}?~vZg*`zvup4*
zjOsmSwhWdfB=&{U9g-b6&`HL4gEn$Z3b7f*y{w9l$^mNEY*VbDHl0&ZJ3b{L<(HyW
zF5g~3?c1kvbNY~8-0KP4pgWwHNgdFnLy{&ki&kJEt$H!^NdYUC51j0gOt{%}<|==S
zAFlKG=4uEek8sq7;p8rkflq|1bFZUJO4i)UCsf`AyAApI^;&_$afTmk(DS7o;D#Vf
z@=JQY(+P?lZj@fiB~&h5nlC621MKPFuqDL*eOy=O0K
z%m+3Wk0L?id*od0VqFY)6lSyb=V}Eyo1Eu)|Cm5}5C2fwkYi36s~?!#+eCD7>2IMw
ztlJAa7KC+%zpOW`i^liU$`$%M4H@IyeFhw6e%X>?M(;LH#M6eR(X2G@?Q-IqVF6+|4wB$mNOO#KDaV!ZuuGOCSy6a!u@kNF
zKHUY)Owy7mwE5*!!y7s@PA>MWKau?C-(Bw6`|=^vrnQ_v6Y6rvIRh
zGXqck`{B*{Yw*A)4*8_-H8D&6na1xU&SvmiGF;I}S`
zOQM{?S1N%<1b68v-%Kzp`Ai6tS-TftIjHsbCp8^g>vPh{w`rc|3RB2
zg7Us`ia({!9w)1|<-jn*ed78H?LGrSmvAyh&?!cc58B>}o=A_6QGC6cbHr-Mrq6v|
zx`&g73ou{vkd4v#x^CFRw`&E^<2)aPRw#rXcgh_LmJB-^gi7=d;|)pTWlMys*}x&A06G>2xR)$j#omVTV-=fIe%jQlmg~aMsFk
zQ5VLu%U>hsXvq&P0oHpXfzmfyym7
zo}(TAP(+;?B`nxcBl;mTY7D;uT}M)jzi8Fq1MFZx=vdGLJjPpqg{9J%k?ejC+J4f2
z<55%_!FenTPLBbn2XM&#<)If%tpmB?IiiMlDj1Cdb4`MF>sXMHr>t_Ben@58TbXjC
z3$oLld$*q~g55DCf5(|e2Fbb+2J9?9;Wsp&pj|46XV}N}DYfHasXism?$Vs1fEA?E
zPZCJ@IL?SEyC2d6DO{2eg<`+m@07Q@$ig5Q)S7&WzD6!Ru2G9*mh{{hyRB}x!bm5(
zjU=RQ*k#1+@}e=8oD=+XiGU!=O4v3rDuaiY^vjB5v&3A`Um|nCUh?QN?1SaK&I6QY
zN7{jtPKjx*eH6#?5M}aFMzy_Z)Z&el9HdCLSNr1_tEQBG`j`6EZuD!$F3HiJKTCFr
zDI15*j><-+Pf6~x>ycI^X?QGCFP5YI`=`{)$Q6yJ?EV`~caKS@b{r%4sU6hL-9|eS
zM>4nJQ`*U{=hDo2U&_=2em8wey-_@XUvP9?Fq#hh#-vwgvTit&K6dU8_?@jkA;szR^XDBi9eO1tv0X#hUK>&iLT5S$>JyEH#l6p2Ov*F$jdD(u
zD@3_VN6Rf7DffxlI3@Z2GqZ6aX5)+h=4?DV7oR$BF8)*WB*u4kf3q?DnAOi&>D`7t
zOrhgjD9>n
zzx%xWIY#|CA>JcKIFB7LILup)EJ!AtPcN5&NaZ@PKgNvNGDlnaff%SU^kj{UFVub#Jo!Gni*voZ6g%
z+DML8iq;?X4I8bqULV;NWxq~h9~gTt77muJ0UbL?$e|sy9POOW1vnS&4id}{v0}`I
z=>*IqR*ruSW{&ozzGQf1qXoS9-SB(s>{5-)daqD&w3z;gAOu92z!Ufs=^^)vbJoiOqnh~Fx+L(l#Q*qOOQ
zuev#5KS_OBn-B}=_DE9byYqTZa-s~)&6`Ek+M
z{#3~}@w7$EGXRno)4r-{39Y$GDci`jId)DHa*x{bBl`xN1-8gU&2t;meyTn-z!yl`
zPgKmx9;W4Vx;Cn|>-t?A!`A%Rz5)A4$)e7u1~`<=?{ux9k}1`-k=brUN!7X*ei_L0``;1Sm8V@T81&rHd)?HgbP76bR2BTpfGV>E8y{TS$A1vE0c
zR8ZE)w0l*i6*G5Bx9@JOchjd6y}MeNr=y)|-%|;0$7;LwjM08ayK4Jhzg^pVPD+m@
zvql`{YZRvaTE#2{8L(?VHp)X5#CbzociXjpF>08yWY!77rVS14nyDtYtE`e~d7Ysl
zbsp0ucYY9$E42o`Z$LOEas8*n@
z-|I}IIrCY3A5m)B#md#MQ9G5L9R4ouEC#P!Ewu{q%B>Z1Qi5YdZH=5C1&44xV2*yA
znhf?~Tt;d$Cj`&{BjePrRh^@L>{2t_qaGuUl>i*ThK>{yU0f+Bq
z;h?{hsSA8-h%$T)3SFRZf=Nd@ou$)NS1!^soS`&s0?op_p(?a@
zE81&L(;R-suH85ipEtb!aVnSUpYRT}pMmQF1J|%+^H3S;N?Ex65M@9QcGm44n)8!2E2VflmGX;lj$>~ZKLl9zFo6q)tfhT@-dA6k4Ed=
z`VQIQbWXmtM-0>@s~6;9Zs%>{S$1a5CEWJ<)W(kP06UYb%~k3Xb$PadZ{x(;jn&E=
zxgI*6oyi-xNw0PYJG%V~@U?5d{RsQE>#PCpOx_UXczih#yLRv+6&jr82hliHX1&KT
zGx45+=y9Cd@SaN|&ZklO6DNzM@i@-BHmwtDZqmhS4*O2DQj#!_EYL*sjf
zy2sZ|yWx&^jJ88kJ5DXp{mghQsw?-$s<|@P~`+!4m
zoXJfRmz;j^X_&1lc=30`=kCHeG_#)ex()pRdjM(cxYNA%M*|#BY25du1TVL1=XkGP
z#g3n{aa4mp%^5ZL?|JnKR=R%((sdA`I$g+l%gphQf$DwR$zPDXMKgj
z(-FSLA3)C?viTykyW!Fb`2JHIS_-|CwA0!Le_7>t_h7vq&tF`v*xg#(|rXb?~Ad2vd@=<
zyl3V?m*T~VEYGhAy+wFlD_~!Hr_Xwn!sQ4PMq)KM>Eg9{{QW-1D-|}ep0gbGrxR>TgrcKZ>Lvb{N!TQ0tVm$e8(Al=#^f#Dq*CJ16=BxAk2RNZ}VuY_O
zh(wPz#&=;h!pvP0=ipZ`a|UX4V^#QJdAS3w{XU6BvJU4IcvXC7{8$_r4x0w6=4>MYLM6Jv%6Pc^9``a0%NX
zNBB3M(y=~}5}htO5qVj!aTof31A9001l#fKpsi8d(GuXb7tU&Ij$-Y{jN9SyyP!EN
z@WgRx_rgLt?DVALuyQ2>9_>39VqOMq^#5o&?CY#_C)QD=b*Lepdw<|#ciNt|A6uO4
zft{YcItn7s#tCzAZsC4Ta*}P0|Fi2y$JFomME$-&zVNTr4~?l`bD{d~zgB<8nEKk%
z^YKUfwHK<-{GeYrrq{%Gt|?x7aL_XT=OIXd>yk5_vL*B2Y02mF*pFh4*YysppYP+l;K9K_1y_sE{Js^m#tW8mv-lO>
z6)mNmD_+;bPFmq`wc%6FQefm<#G#e)L#XXRj=*ERi@fn}wBpRM)B*mr&c4ATjuFd{&qWG*Pk1qtfI&`-S3@O#=}3{%3hc2?DPauO{>{bYdci1QW
z6tFMR$Vf`KUniTE+7+jitB^lZF2Tcp*#GqM*tM!&*eIZs-P+G^x94RW)4rxESVtWP
zZwhg8-q$`gf)nHoJALlRalOABFxEeZFNKdlArxcruqn3b8n+2}|+DS6nVyZ2#-==xsU9gYN`2f`uAh>1G&&54~Q|-(3
z(&~1t1|C_PmI{f&afPW(^MKd7;@%QJSH2Lr)Ow*GZ8#Bf(y2OynVX=LM&>KRWevxr
z>2I90XuLC@|9$mZzx$8oYd9s9J>bUDx8N}+?v!l32-W$h1QwGBd4&&osw!P&E@{HL=5M+M$Pq(^t&qt8$Ok
zC$5-%O^B;nn8t@KGx51N)M)X=N->TqjP|5uBqJ3yPQWF(7>5%e$L{DmhKyL}4c)c7
z;e?THd5Pr3QV|o^q8*MqeTAE^G}>{`4RMv1Q#(#C`qq?}i$ljmPs~Z}n7A5zu5gNG
zJLQd*KR}9)i4$UVYk{lZQpJ+(o#4w=Z=4h~Vcus2L133v1*FIhaZ$`lymB8CPXdP>
zqBpjc>bP;Xmi%J64s`t&Z#L>w25yNg6QzNTY7N?|*H|;jOM0xK_co{8yCD@FZ0ht>
z9Q)Wba!7tQ4^7tYchlhmE#pcD+Z8^;`#xAQ2{19zb8~lm~NiM6=x68z$
z*o!AViC2`$8hse|6JFIdd4WRlxtQ2$sb?WE$p!padiHU7!
z-x!N%znt1v@4eCBEA(pbr{|p%}-+|NiU603&@wE)$Hy$si@l{@kaM|utMmoW`Z1+19
zE^p-L4SjR>1e!Bu6CI;+xjD5N?R!iK5Qx(rNC1_;Yd16kKRvdUI5=ILx#YOXKWBcf
z(SKEeZ-k=Ug4iVBM|h_Dh;m0UP9EYW#6;@PaWtZGFrt{L52ltwhN}Xf-P6d`#BAxl
zd59x@(8x`X)lr>7(g#B%_oxGXaMfqhaz7_>jCo@dG2Ybk#`en@8et`kaFBbMMlAEh
z4&6>z98E(MH1U=%q~)&~I%WqW9aC)3YrxGK$Ik+;DH$f6G>(t4-(#NI!M+sZ+6mL2
z6WrN^DNcw-45grY=-vpK>O`rMX^1Q
zS#{Z18QX`lhVFx)5FHX!2Wk~D*hN@aXJ7kM>U
zW2IYadSXaz=gC%RGV{XxK?8f%)YZIr4X|4O#E`T(C)%iATaDBF*+POZ;)kU5gqN9r
zaP|EL9tWF^FVC-}HbmaHaxuQr`mR+*dQ+DX@8A!vL>w6Lt6ng^zEuR9M_*!<;-Wko
ze{j`eY4VXuFw#xm$dI~$((j|w$X}?M#z$_Z=5XD_VYIOhH!~EPM9p<4%He}kOsV4
z51dq`kKdnhU~?rKyiZ*`W!?;yyu0&_lSP`BeZ<`<{5$^9|FQJfjNK`mIxn6{&wLO4
zjr>fxPy0T^jh@>@aPNywf8j#~N}ulRYbBosqUi*0VJ{1B81zV1Y2cMDCO!Pqp#io1
z#y{ZiW;OY1;#C3D{tR9*c%a!vc;s!P)u;#_J+p=2-Ndipf5Jb;-^Qax`z^%t+tlQp
zR3AQKTc|#~j!txCc+8{1S#>i#y3(k-o>|$){KMP~eim=`=gn#Q
zeb1=ymzoKgP&YHJoMZ!Qh6hF$
z_!*{sm3UV#X+>FOL2)Bd#xyta1>dusjL!;&%6I?l|bllm|z#UIJx+`z532n6?e@CGA^Xw`7$|%W@DHwEt6t
zBst7cU)|g#q3l;W!)u6^JJYm$?wJgH!iR69K3Hw=XbqRoHE_$hYHlYREi;M(xCQB9
z+C&3~&v&WNWn;>%qh7$6AZf#QEj$w?ZEjaQtDJ$W*1-{GQ#(I;zxRx4S8>Lhfn!KN
zEZRctP4;=VjQyF7&EvgwuAx-0^r!w#iIjf~QL(o7NQ>b%0
zcaSC6!|6JwI?Xp&N$EP|)ZZ#p?;
z8+65?PWFlOXY~MZF}!Q-?eL}VfOkG5^_Qx>1@pozK7of@hNO;A7LN>^4cYy^fwPs>
zai!cXaC1JuOk5rNGW40ad@YTeliD)(iD-Nkl1?Da%W30XO>0WCcxKye*5d6~$4QpCLK<7|spO&hCqwqms)YYX?|*&2$@_=*^gwHsMKA+yo*A`g;St8l
z<87n#$M0YAH0vdNuqURFpN=ZfD<9+H;0^jcnlAOiGYjFDSf4uMwGvH=cbL^u$zO6@
zBHlrGW%u_lR69H+C3r8}Tf&1D7w-vcd(?~<5P3SN2f$;%e3GRAX5Vj1$BWYO&U8E%@i4nPW=hOMpo!w^((wn<@s@OaOFAA*$G?(}-<*zbFygAv
zn2ukwpWvy&qI7(AI_^!!s}QHLF>h%7<5z({6rLTUQ8I6+?eWXud$h<_m5#4`{4ygx
zt-lOB4)d3$Vch%_wZVjm>G+#Q8)3d69baVROM)#O52oAX`_0!k%+{`aoMKsWmDZ^f
zBc#o8BenYpmpWj0TcR^K0d);qDNAOlKh3mJX&6mA-`~Wvw9p>z-P1ic^M3wl{JeW_
z$&QSFk>m39PFZ!)9Xz_p
zq`EVZ;W=gKBD!ZRW!*E*PFKgIXZD@9rT3lLx(n?)*CoH5hU>$5LN09KGUL1bWWKY|
z&$mqSFHAE3VZ1}*O*lAjg7@AmPg0~7cWP6kH^E%Raxr{7WxR7>asZ_zlqT#oHH$9`
zlXfrCxkh*nKKKMLH^Qe8XBA~Wv{>ZmlF8m>-o6n&lAkZ?;HCm;#W6W4LJVa}i=WSBL#+=bwWt(kWf332}
zG68>|w@kv{ZI(;$H-~N!LdN-;XLV7fa;IY=g?p&<$(W16yQt2eV{{wQjBT^LiI_7T
z%dz#w?Cy2)Ggued-C`ME&P^xZ-p?qP*%tP$lN+AKty7yN%3PmO9>a|sT4(dFFXO(+
zV>S-0Z9u5aV(b5m@~$NZe;)(%Jd|aTchs48nOs`miFit_*WKbykLv)F1$gamF?qUYWfIOJ{I)!#
ziMW&2v0zRapJ;H3Wx1$TfIRBijC^0{}Hct@QLNTpp{w*DsI*J@Xw|Emg5gIVyW(EcvAX_pZgc_jCJ^OzfX6_
z80FXF#-D46;!EUOQvCAXGJKz;`+g00&4+Hc(~UqE<)-rl%6pA&ppT>tBTYrxrmVCh
z`lg0kAp?BcKb_=&RZ`E7BQ%L$?*#lAmP!gqMDuP-W=Q|{~S(-L{s*H<6YRhdGE
z@SUPiXbSPnU!Qo`dWkYMk!QI?Ca6?rnLe%ICw@Qv{u}5v{FFbRmc*8^@5Qhg@SBGe
zd&)W+sDv-Uc{_t03w$knf)jT5y$QjHgG)G717CLL`swdMyduTE*B9(-VLQStoSWfZ
zMrXn)aXn@`-EQE4S%LQvpJ_aeyzej~|9GipGJGxbCh2)KT$K>zUFIn53gn#5W4@%*
zIx*lN|MY2`J4esM8JAbKX!n1#4)a(}j1Ap$C+oFnT^~K_t3QgndN#dZN-}##OJDMH
z#lP2eCrj8Fr}eZyUEf;Z^~kjCRa$X^DX>iS<4ZOp|xf$ey2
zu>M=M(C1DL9@vAHB6+FaVb_=2Sa@lTe`
z;CHP1MRnY^yv}9YuIqeg+XJ0Px4qDr!IwDUIj?Tfr(iUm%4K2x*YL4uogb1!*hwPp
zuxR&uxXb5G%R@)YSUI@pugHNtp56aAmyQdrdQI}qQi6$Gu28C#MsxBHUgEh0(h
zREs8kSP2X!#)5clP^`0PbAZF_qqs2-nRLYIn-inIR^xA7uLm}m)RBY@R!P$8jOi&C
zC-Jaz3jGDp4bCFFL|({?>y{~b{$;Wfgd9u1)^*5h&jHVfoGL-wl{`Ri0zs4EUI%Jk
zjC%C897dFg5tX^4Kx4{6V@lkPHw}Sx1&t|7dQ8R71~X&o%QU8rpWWyCr=zlgKXU~Q
z9Q$>B1VAb}=rKq@rcXZ!BSXWB-G|h?Z9?aD+x(pm
zY}?ZL{I`*{^7Mwk4!ycWq99&tLs%Trd6lCALBe7lbp8x
z4y=#y9tYi=>v&YwPT<}R!m9kJY~*~xPV^=59tyl-`e2Vcpb5$g4<}bQa`M9A|0p~%
z{1=46u#Y*|$MlXW=4rfRNabn$fD>_br)BI;Uy?Z~-wSxT5#R7N?(py=l;Z~K
zYB^aN1B>h;v~QIEG