diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index d12b9643135..496d24beb0a 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -203,6 +203,7 @@ "stm32/stm32h750-weact-ministm32h7xx", "stm32/stm32h750-fk750m1-vbt6", "stm32/stm32h7s7-st-disco", + "stm32/stm32h7r7-atk", "stm32/stm32mp157a-st-discovery", "stm32/stm32mp157a-st-ev1", "stm32/stm32u575-st-nucleo", diff --git a/bsp/stm32/stm32h7r7-atk/.config b/bsp/stm32/stm32h7r7-atk/.config new file mode 100644 index 00000000000..b774f73edcd --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/.config @@ -0,0 +1,1439 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=384 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=9 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=15 +CONFIG_FINSH_THREAD_STACK_SIZE=8192 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=10 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +# end of elm-chan's FatFs, Generic FAT Filesystem Module + +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +# CONFIG_RT_USING_POSIX_DEVIO is not set +# CONFIG_RT_USING_POSIX_STDIO is not set +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_EVENTFD is not set +# CONFIG_RT_USING_POSIX_TIMERFD is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +CONFIG_RT_USING_SAL=y +# CONFIG_SAL_INTERNET_CHECK is not set + +# +# Docking with protocol stacks +# +# CONFIG_SAL_USING_LWIP is not set +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +# end of Docking with protocol stacks + +CONFIG_SAL_USING_POSIX=y +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +CONFIG_ULOG_USING_ISR_LOG=y +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +CONFIG_ULOG_OUTPUT_FLOAT=y +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +# end of log format + +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +CONFIG_PKG_USING_RT_VSNPRINTF_FULL=y +CONFIG_PKG_RT_VSNPRINTF_FULL_PATH="/packages/system/enhanced-kservice/rt_vsnprintf_full" +CONFIG_PKG_VSNPRINTF_SUPPORT_DECIMAL_SPECIFIERS=y +CONFIG_PKG_VSNPRINTF_SUPPORT_EXPONENTIAL_SPECIFIERS=y +CONFIG_PKG_VSNPRINTF_SUPPORT_WRITEBACK_SPECIFIER=y +CONFIG_PKG_VSNPRINTF_SUPPORT_LONG_LONG=y +CONFIG_PKG_VSNPRINTF_CHECK_FOR_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_PKG_VSNPRINTF_SUPPORT_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_PKG_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION=6 +CONFIG_PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_PKG_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SNPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_PRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSNPRINTF is not set +CONFIG_PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION=y +CONFIG_PKG_RT_VSNPRINTF_FULL_VER="latest" +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32H7RS=y +CONFIG_SOC_SERIES_STM32H7RS=y +# CONFIG_RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_SCB_ENABLE_I_CACHE=y +CONFIG_BSP_SCB_ENABLE_D_CACHE=y +# CONFIG_BSP_USING_USB_TO_USART is not set +# CONFIG_BSP_USING_XSPI_NORFLASH is not set +# CONFIG_BSP_USING_WIFI is not set +# CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_LVGL_DEMO is not set +# CONFIG_BSP_USING_FS is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +CONFIG_BSP_UART1_RX_BUFSIZE=512 +CONFIG_BSP_UART1_TX_BUFSIZE=512 +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_PSRAM=y +CONFIG_BSP_USING_PSRAM_TEST=y +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_DCMI is not set +# CONFIG_BSP_USING_FDCAN is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# end of On-chip Peripheral +# end of Hardware Drivers Config + +# +# External Libraries +# +# CONFIG_ART_PI_USING_WIFI_6212_LIB is not set +# CONFIG_ART_PI_TouchGFX_LIB is not set +# end of External Libraries + +CONFIG_FIRMWARE_EXEC_USING_OSPI_FLASH=y +CONFIG_RT_STUDIO_BUILT_IN=y diff --git a/bsp/stm32/stm32h7r7-atk/.gitignore b/bsp/stm32/stm32h7r7-atk/.gitignore new file mode 100644 index 00000000000..34f7681a001 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/.gitignore @@ -0,0 +1,37 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.pdb +*.idb +*.ilk +!*.old +build +Debug +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* diff --git a/bsp/stm32/stm32h7r7-atk/Kconfig b/bsp/stm32/stm32h7r7-atk/Kconfig new file mode 100644 index 00000000000..e224ae7e92f --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/Kconfig @@ -0,0 +1,32 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config PLATFORM_DIR + string + option env="PLATFORM_DIR" + default "F:/github/rtthread/workspace/rtthread-atk/platform" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$RTT_DIR/../libraries/Kconfig" + +config RT_STUDIO_BUILT_IN + bool + select ARCH_ARM_CORTEX_M7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/stm32/stm32h7r7-atk/README.md b/bsp/stm32/stm32h7r7-atk/README.md new file mode 100644 index 00000000000..02edcaacd64 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/README.md @@ -0,0 +1,130 @@ +# STM32H7r7-atk 开发板 BSP 说明 + +## 简介 + +本文档为 wenshan 为 STM32H7r7-atk开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +阿波罗 STM32H7r7 是正点原子推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H7r7 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32H7r7l8h，主频 600MHz，128K FLASH ，620K RAM +- 外部 HyperRam：W955K8MBYA，32MB +- 外部 SD NAND：MKDV4GCL，2GB +- 外部 HyperFlash：GD25LX256MEBFR，32MB +- 常用外设 + - LED：2个，DS0（红色，PB1），DS1（绿色，PB0） + - 按键：4个，KEY_UP（兼具唤醒功能，PA0），K0（PH3），K1（PH2），K2（PC13） +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口等 +- 调试接口，标准 SWD + +开发板更多详细信息请参考正点原子 [STM32阿波罗开发板介绍](https://eboard.taobao.com/index.htm)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :------------------------------------------------------ | +| USB 转串口 | 支持 | | +| ESP32接口 | 支持 | | +| hyperbus Flash | 支持 | | +| 以太网 | 支持 | | +| SD卡 | 支持 | | +| HyperRAM | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | | +| SPI | 支持 | | +| I2C | 支持 | 软件iic | +| ETH | 支持 | | +| CAN-FD | 支持 | HDR暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +**请注意！！！** + +在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）： + +```bash +pkgs --update +``` + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 DAP_LINK 仿真器下载程序，在通过 DAP_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Jun 2 2025 12:43:54 + 2006 - 2024 Copyright by RT-Thread team +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +1. UART暂未完成对DMA的支持，同时开启uart7和uart1的dma会进入hardfault，只打开uart1的dma会有概率进入hardfault。 +2. 开发板连接正点原子的esp32模块可能会报execute command (AT+CIPDNS?) failed错误，这是因为esp32的at固件不支持这个at指令，需要升级esp32的固件版本，详情参照网上教程。 +3. 正点原子暂未提供可以用在rtthread studio上的stldr下载文件，故在rtthread studio上只能编译还不能下载，现在只有在keil上用的flm下载文件。 +4. 如果使用eth的话，hal库一定要是1.3版本以上！ +5. 核心板有四种，这里使用的是正点原子的h7r7的高配板。 +6. 需要先下载对应的bootloader，在[Wenshan-736/stm32h7r7-atk](https://github.com/Wenshan-736/stm32h7r7-atk/tree/main)里面有工程，文件atk-bootloader.bin是编译后的二进制文件 + +## 联系人信息 + +维护人:[Wenshan-736](https://github.com/Wenshan-736), 邮箱：<736810738@qq.com> diff --git a/bsp/stm32/stm32h7r7-atk/SConscript b/bsp/stm32/stm32h7r7-atk/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32h7r7-atk/SConstruct b/bsp/stm32/stm32h7r7-atk/SConstruct new file mode 100644 index 00000000000..bd9421d2a53 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/SConstruct @@ -0,0 +1,57 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except Exception as e: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + sys.exit(-1) + +TARGET = 'rt-thread.elf' + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +env.AppendUnique(CPPDEFINES = []) + +Export('RTT_ROOT') +Export('rtconfig') + +if os.path.exists('libraries'): + libraries_path_prefix = 'libraries' +else: + libraries_path_prefix = '../../libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32H7RSxx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +if not os.path.exists('libraries'): + # include libraries + objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript'))) + + # include applications + #objs.extend(SConscript(os.path.join(APP_ROOT, 'applications', 'SConscript'))) + +#objs += PrepareBuilding(env, LIB_ROOT, has_libcpu=False) +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32h7r7-atk/applications/SConscript b/bsp/stm32/stm32h7r7-atk/applications/SConscript new file mode 100644 index 00000000000..114bfbabf21 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/applications/SConscript @@ -0,0 +1,10 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +path = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/stm32/stm32h7r7-atk/applications/main.c b/bsp/stm32/stm32h7r7-atk/applications/main.c new file mode 100644 index 00000000000..33e82b0d2d9 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/applications/main.c @@ -0,0 +1,37 @@ +/* + * @Author : wenshan + * @Date : 2025-05-14 20:21:24 + * @LastEditors: Do not edit + * @LastEditTime: 2025-06-05 14:32:18 + * @Description : + * @FilePath: \undefinedf:\github\rtthread\rt-thread\bsp\stm32\stm32h7r7-atk\applications\main.c + */ + +#include +#include +#include "drv_common.h" + + +#define LED_PIN GET_PIN(D, 14) + +int main(void) +{ + while(1) + { + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + } + return RT_EOK; +} + +#include "stm32h7rsxx.h" +static int vtor_config(void) +{ + /* Vector Table Relocation in Internal XSPI1_BASE */ + SCB->VTOR = XSPI1_BASE; + return 0; +} +INIT_BOARD_EXPORT(vtor_config); + diff --git a/bsp/stm32/stm32h7r7-atk/board/.ignore_format.yml b/bsp/stm32/stm32h7r7-atk/board/.ignore_format.yml new file mode 100644 index 00000000000..0d7f3e360c6 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- CubeMX_Config diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject new file mode 100644 index 00000000000..dbd6af51bdd --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/.mxproject @@ -0,0 +1,105 @@ +[Boot:PreviousLibFiles] +LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[Boot:PreviousUsedKeilFiles] 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+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Boot\Core\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousLibFiles] +LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_eth_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_fdcan.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_sdmmc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_dlyb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pcd_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_ll_usb.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_eth_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_fdcan.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_sdmmc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dlyb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_sd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pcd_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usb.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_xspi.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[Appli:PreviousUsedKeilFiles] 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+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Appli\Core\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Eloader:PreviousLibFiles] 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+ +[Eloader:PreviousUsedKeilFiles] +SourceFiles=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;; +HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousLibFiles] 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+ +[PreviousUsedKeilFiles] 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+HeaderPath=..\Drivers\STM32H7RSxx_HAL_Driver\Inc;..\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Boot\Core\Inc;..\Appli\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Eloader:PreviousGenFiles] +SourceFiles=; + +[ExtMemLoader:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7r7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[ExtMemLoader:PreviousUsedKeilFiles] +SourceFiles=..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;; +HeaderPath=..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;..\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7R7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Boot:PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=..\Boot\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#1=..\Boot\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#2=..\Boot\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Boot\Core\Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=..\Boot\Core\Src\stm32h7rsxx_it.c +SourceFiles#1=..\Boot\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#2=..\Boot\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Boot\Core\Src +SourceFiles=; + +[Appli:PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=..\Appli\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#1=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#2=..\Appli\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Appli\Core\Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=..\Appli\Core\Src\stm32h7rsxx_it.c +SourceFiles#1=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#2=..\Appli\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Appli\Core\Src +SourceFiles=; + +[ExtMemLoader:PreviousGenFiles] +SourceFiles=; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\Boot\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#1=..\Boot\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#2=..\Boot\Core\Inc\main.h +HeaderFiles#3=..\Appli\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#4=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#5=..\Appli\Core\Inc\main.h +HeaderFolderListSize=2 +HeaderPath#0=..\Boot\Core\Inc +HeaderPath#1=..\Appli\Core\Inc +HeaderFiles=; +SourceFileListSize=6 +SourceFiles#0=..\Boot\Core\Src\stm32h7rsxx_it.c +SourceFiles#1=..\Boot\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#2=..\Boot\Core\Src\main.c +SourceFiles#3=..\Appli\Core\Src\stm32h7rsxx_it.c +SourceFiles#4=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#5=..\Appli\Core\Src\main.c +SourceFolderListSize=2 +SourcePath#0=..\Boot\Core\Src +SourcePath#1=..\Appli\Core\Src +SourceFiles=; + diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h new file mode 100644 index 00000000000..439921be213 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "drv_common.h" +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h new file mode 100644 index 00000000000..bc8de5225ea --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h @@ -0,0 +1,501 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DCMIPP_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_GFXTIM_MODULE_ENABLED */ +/* #define HAL_GPU2D_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I3C_MODULE_ENABLED */ +/* #define HAL_ICACHE_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_MCE_MODULE_ENABLED */ +/* #define HAL_MDF_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_PKA_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RCC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_XSPI_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ + #if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ + #endif /* HSI48_VALUE */ + +/** +* @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* LSI_VALUE */ + +/** +* @brief External Low Speed oscillator (LSE) value. +*/ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** +* @brief Uncomment the line below to expanse the "assert_param" macro in the +* HAL drivers code +*/ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** +* @brief Set below the peripheral configuration to "1U" to add the support +* of HAL callback registration/unregistration feature for the HAL +* driver(s). This allows user application to provide specific callback +* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting +* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file +* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef +* for each PPP peripheral). +*/ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED + #include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED + #include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ + diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c new file mode 100644 index 00000000000..e05d2b5223b --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/main.c @@ -0,0 +1,514 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x24020000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x24020080 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x24020000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x24020080))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif (defined ( __GNUC__ ) || defined ( __ARMCC_VERSION )) /* GNU Compiler */ + +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDescripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDescripSection"))); /* Ethernet Tx DMA Descriptors */ +#endif + +ETH_TxPacketConfigTypeDef TxConfig; + +ETH_HandleTypeDef heth; + +FDCAN_HandleTypeDef hfdcan1; + +SD_HandleTypeDef hsd1; + +UART_HandleTypeDef huart7; +UART_HandleTypeDef huart1; + +PCD_HandleTypeDef hpcd_USB_OTG_HS; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +static void MPU_Config(void); +static void MX_GPIO_Init(void); +static void MX_FLASH_Init(void); +static void MX_USB_OTG_HS_PCD_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_FDCAN1_Init(void); +static void MX_ETH_Init(void); +static void MX_SDMMC1_SD_Init(void); +static void MX_UART7_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Update SystemCoreClock variable according to RCC registers values. */ + SystemCoreClockUpdate(); + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_FLASH_Init(); + MX_USB_OTG_HS_PCD_Init(); + MX_USART1_UART_Init(); + MX_FDCAN1_Init(); + MX_ETH_Init(); + MX_SDMMC1_SD_Init(); + MX_UART7_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfigTypeDef)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief FDCAN1 Initialization Function + * @param None + * @retval None + */ +static void MX_FDCAN1_Init(void) +{ + + /* USER CODE BEGIN FDCAN1_Init 0 */ + + /* USER CODE END FDCAN1_Init 0 */ + + /* USER CODE BEGIN FDCAN1_Init 1 */ + + /* USER CODE END FDCAN1_Init 1 */ + hfdcan1.Instance = FDCAN1; + hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV6; + hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; + hfdcan1.Init.AutoRetransmission = DISABLE; + hfdcan1.Init.TransmitPause = DISABLE; + hfdcan1.Init.ProtocolException = DISABLE; + hfdcan1.Init.NominalPrescaler = 2; + hfdcan1.Init.NominalSyncJumpWidth = 1; + hfdcan1.Init.NominalTimeSeg1 = 19; + hfdcan1.Init.NominalTimeSeg2 = 5; + hfdcan1.Init.DataPrescaler = 1; + hfdcan1.Init.DataSyncJumpWidth = 1; + hfdcan1.Init.DataTimeSeg1 = 1; + hfdcan1.Init.DataTimeSeg2 = 1; + hfdcan1.Init.StdFiltersNbr = 0; + hfdcan1.Init.ExtFiltersNbr = 0; + hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN1_Init 2 */ + + /* USER CODE END FDCAN1_Init 2 */ + +} + +/** + * @brief FLASH Initialization Function + * @param None + * @retval None + */ +static void MX_FLASH_Init(void) +{ + + /* USER CODE BEGIN FLASH_Init 0 */ + + /* USER CODE END FLASH_Init 0 */ + + /* USER CODE BEGIN FLASH_Init 1 */ + + /* USER CODE END FLASH_Init 1 */ + /* USER CODE BEGIN FLASH_Init 2 */ + + /* USER CODE END FLASH_Init 2 */ + +} + +/** + * @brief SDMMC1 Initialization Function + * @param None + * @retval None + */ +static void MX_SDMMC1_SD_Init(void) +{ + + /* USER CODE BEGIN SDMMC1_Init 0 */ + + /* USER CODE END SDMMC1_Init 0 */ + + /* USER CODE BEGIN SDMMC1_Init 1 */ + + /* USER CODE END SDMMC1_Init 1 */ + hsd1.Instance = SDMMC1; + hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; + hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + hsd1.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDMMC1_Init 2 */ + + /* USER CODE END SDMMC1_Init 2 */ + +} + +/** + * @brief UART7 Initialization Function + * @param None + * @retval None + */ +static void MX_UART7_Init(void) +{ + + /* USER CODE BEGIN UART7_Init 0 */ + + /* USER CODE END UART7_Init 0 */ + + /* USER CODE BEGIN UART7_Init 1 */ + + /* USER CODE END UART7_Init 1 */ + huart7.Instance = UART7; + huart7.Init.BaudRate = 115200; + huart7.Init.WordLength = UART_WORDLENGTH_8B; + huart7.Init.StopBits = UART_STOPBITS_1; + huart7.Init.Parity = UART_PARITY_NONE; + huart7.Init.Mode = UART_MODE_TX_RX; + huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart7.Init.OverSampling = UART_OVERSAMPLING_16; + huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart7) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART7_Init 2 */ + + /* USER CODE END UART7_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USB_OTG_HS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_HS_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_HS_Init 0 */ + + /* USER CODE END USB_OTG_HS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_HS_Init 1 */ + + /* USER CODE END USB_OTG_HS_Init 1 */ + hpcd_USB_OTG_HS.Instance = USB_OTG_HS; + hpcd_USB_OTG_HS.Init.dev_endpoints = 9; + hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_HIGH; + hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY; + hpcd_USB_OTG_HS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE; + hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_HS_Init 2 */ + + /* USER CODE END USB_OTG_HS_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOM_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + + /* MPU Configuration */ + +static void MPU_Config(void) +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c new file mode 100644 index 00000000000..3e6d03b1553 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c @@ -0,0 +1,605 @@ + +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ +#include +#include +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* Enable the XSPIM_P1 interface */ + HAL_PWREx_EnableXSPIM1(); + + /* Enable the XSPIM_P2 interface */ + HAL_PWREx_EnableXSPIM2(); + + /* Enable USB Voltage detector */ + if(HAL_PWREx_EnableUSBVoltageDetector() != HAL_OK) + { + /* Initialization error */ + Error_Handler(); + } + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH1REF|RCC_PERIPHCLK_ETH1PHY; + PeriphClkInit.Eth1RefClockSelection = RCC_ETH1REFCLKSOURCE_PHY; + PeriphClkInit.Eth1PhyClockSelection = RCC_ETH1PHYCLKSOURCE_PLL3S; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ETH GPIO Configuration + PD7 ------> ETH_RMII_REF_CLK + PG14 ------> ETH_RMII_TXD1 + PG11 ------> ETH_RMII_TX_EN + PG13 ------> ETH_RMII_TXD0 + PC1 ------> ETH_MDC + PC4 ------> ETH_RMII_RXD0 + PA4 ------> ETH_MDIO + PA7 ------> ETH_RMII_CRS_DV + PC5 ------> ETH_RMII_RXD1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_ETH; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH1MAC_CLK_DISABLE(); + __HAL_RCC_ETH1TX_CLK_DISABLE(); + __HAL_RCC_ETH1RX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PD7 ------> ETH_RMII_REF_CLK + PG14 ------> ETH_RMII_TXD1 + PG11 ------> ETH_RMII_TX_EN + PG13 ------> ETH_RMII_TXD0 + PC1 ------> ETH_MDC + PC4 ------> ETH_RMII_RXD0 + PA4 ------> ETH_MDIO + PA7 ------> ETH_RMII_CRS_DV + PC5 ------> ETH_RMII_RXD1 + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_11|GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_7); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief FDCAN MSP Initialization +* This function configures the hardware resources used in this example +* @param hfdcan: FDCAN handle pointer +* @retval None +*/ +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hfdcan->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspInit 0 */ + + /* USER CODE END FDCAN1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; + PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL1Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_FDCAN_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**FDCAN1 GPIO Configuration + PD1 ------> FDCAN1_TX + PD0 ------> FDCAN1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN FDCAN1_MspInit 1 */ + + /* USER CODE END FDCAN1_MspInit 1 */ + + } + +} + +/** +* @brief FDCAN MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hfdcan: FDCAN handle pointer +* @retval None +*/ +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan) +{ + if(hfdcan->Instance==FDCAN1) + { + /* USER CODE BEGIN FDCAN1_MspDeInit 0 */ + + /* USER CODE END FDCAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_FDCAN_CLK_DISABLE(); + + /**FDCAN1 GPIO Configuration + PD1 ------> FDCAN1_TX + PD0 ------> FDCAN1_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_1|GPIO_PIN_0); + + /* USER CODE BEGIN FDCAN1_MspDeInit 1 */ + + /* USER CODE END FDCAN1_MspDeInit 1 */ + } + +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + + /* USER CODE END SDMMC1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; + PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL2T; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**SDMMC1 GPIO Configuration + PD2 ------> SDMMC1_CMD + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* SDMMC1 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC1_IRQn, 6, 0); + HAL_NVIC_EnableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspInit 1 */ + + /* USER CODE END SDMMC1_MspInit 1 */ + + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + + /* USER CODE END SDMMC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC1_CLK_DISABLE(); + + /**SDMMC1 GPIO Configuration + PD2 ------> SDMMC1_CMD + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8 + |GPIO_PIN_9); + + /* SDMMC1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + + /* USER CODE END SDMMC1_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(huart->Instance==UART7) + { + /* USER CODE BEGIN UART7_MspInit 0 */ + + /* USER CODE END UART7_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART234578; + PeriphClkInit.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_UART7_CLK_ENABLE(); + + __HAL_RCC_GPIOM_CLK_ENABLE(); + /**UART7 GPIO Configuration + PM9 ------> UART7_TX + PM8 ------> UART7_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_UART7; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + /* USER CODE BEGIN UART7_MspInit 1 */ + + /* USER CODE END UART7_MspInit 1 */ + } + else if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB14 ------> USART1_TX + PB15 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==UART7) + { + /* USER CODE BEGIN UART7_MspDeInit 0 */ + + /* USER CODE END UART7_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART7_CLK_DISABLE(); + + /**UART7 GPIO Configuration + PM9 ------> UART7_TX + PM8 ------> UART7_RX + */ + HAL_GPIO_DeInit(GPIOM, GPIO_PIN_9|GPIO_PIN_8); + + /* USER CODE BEGIN UART7_MspDeInit 1 */ + + /* USER CODE END UART7_MspDeInit 1 */ + } + else if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB14 ------> USART1_TX + PB15 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/** +* @brief PCD MSP Initialization +* This function configures the hardware resources used in this example +* @param hpcd: PCD handle pointer +* @retval None +*/ +void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hpcd->Instance==USB_OTG_HS) + { + /* USER CODE BEGIN USB_OTG_HS_MspInit 0 */ + + /* USER CODE END USB_OTG_HS_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHYC; + PeriphClkInit.UsbPhycClockSelection = RCC_USBPHYCCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /** Enable USB Voltage detector + */ + HAL_PWREx_EnableUSBVoltageDetector(); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USBPHYC_CLK_ENABLE(); + /* USER CODE BEGIN USB_OTG_HS_MspInit 1 */ + + /* USER CODE END USB_OTG_HS_MspInit 1 */ + + } + +} + +/** +* @brief PCD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hpcd: PCD handle pointer +* @retval None +*/ +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) +{ + if(hpcd->Instance==USB_OTG_HS) + { + /* USER CODE BEGIN USB_OTG_HS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_HS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_HS_CLK_DISABLE(); + __HAL_RCC_USBPHYC_CLK_DISABLE(); + /* USER CODE BEGIN USB_OTG_HS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_HS_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 00000000000..4ff2224a309 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,597 @@ +#MicroXplorer Configuration settings - do not modify +Appli.IPs=CORTEX_M7_APPLI\:I,GPDMA1\:I,HPDMA1\:I,LINKEDLIST\:I,RCC\:I,GPIO,NVIC2\:I,FLASH,USB_OTG_HS,GFXTIM,USART1,XSPI1,XSPI2,FDCAN1,ETH,SDMMC1,UART7 +Boot.IPs=CORTEX_M7_BOOT\:I,GPDMA1,HPDMA1,LINKEDLIST,RCC,GPIO,NVIC1\:I,MEMORYMAP\:I,USB_OTG_HS +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M7_APPLI.IPParameters=default_mode_Activation +CORTEX_M7_APPLI.default_mode_Activation=1 +CORTEX_M7_BOOT.IPParameters=default_mode_Activation +CORTEX_M7_BOOT.default_mode_Activation=1 +ETH.IPParameters=MediaInterface,TxDescAddress,RxBufferAddress +ETH.MediaInterface=HAL_ETH_RMII_MODE +ETH.RxBufferAddress=0x24020200 +ETH.TxDescAddress=0x24020080 +ExtMemLoader.IPs=EXTMEM_LOADER\:I,EXTMEM_MANAGER\:I,GPIO\:I +FDCAN1.CalculateBaudRateNominal=2000000 +FDCAN1.CalculateTimeBitNominal=500 +FDCAN1.CalculateTimeQuantumNominal=20.0 +FDCAN1.ClockDivider=FDCAN_CLOCK_DIV6 +FDCAN1.FrameFormat=FDCAN_FRAME_CLASSIC +FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,FrameFormat,ClockDivider +FDCAN1.NominalPrescaler=2 +FDCAN1.NominalTimeSeg1=19 +FDCAN1.NominalTimeSeg2=5 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +MMTAppReg1.MEMORYMAP.AppRegionName=DTCM +MMTAppReg1.MEMORYMAP.ContextName=Boot +MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg1.MEMORYMAP.DefaultDataRegion=true +MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name +MMTAppReg1.MEMORYMAP.Name=DTCM +MMTAppReg1.MEMORYMAP.Size=65536 +MMTAppReg1.MEMORYMAP.StartAddress=0x20000000 +MMTAppReg2.MEMORYMAP.AppRegionName=RAM +MMTAppReg2.MEMORYMAP.ContextName=Boot +MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg2.MEMORYMAP.DefaultDataRegion=true +MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name +MMTAppReg2.MEMORYMAP.Name=RAM +MMTAppReg2.MEMORYMAP.Size=465920 +MMTAppReg2.MEMORYMAP.StartAddress=0x24000000 +MMTAppReg3.MEMORYMAP.AppRegionName=ITCM +MMTAppReg3.MEMORYMAP.Cacheability=WTRA +MMTAppReg3.MEMORYMAP.ContextName=Boot +MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg3.MEMORYMAP.DefaultDataRegion=false +MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,Cacheability +MMTAppReg3.MEMORYMAP.Name=ITCM +MMTAppReg3.MEMORYMAP.Size=65536 +MMTAppReg3.MEMORYMAP.StartAddress=0x00000000 +MMTAppReg4.MEMORYMAP.AP=RO_priv_only +MMTAppReg4.MEMORYMAP.AppRegionName=FLASH +MMTAppReg4.MEMORYMAP.Cacheability=WTRA +MMTAppReg4.MEMORYMAP.ContextName=Boot +MMTAppReg4.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg4.MEMORYMAP.DefaultCodeRegion=true +MMTAppReg4.MEMORYMAP.DefaultDataRegion=false +MMTAppReg4.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion +MMTAppReg4.MEMORYMAP.MemType=ROM +MMTAppReg4.MEMORYMAP.Name=FLASH +MMTAppReg4.MEMORYMAP.Size=65536 +MMTAppReg4.MEMORYMAP.StartAddress=0x08000000 +MMTAppReg5.MEMORYMAP.AppRegionName=DTCM +MMTAppReg5.MEMORYMAP.ContextName=Appli +MMTAppReg5.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg5.MEMORYMAP.DefaultDataRegion=true +MMTAppReg5.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name +MMTAppReg5.MEMORYMAP.Name=DTCM +MMTAppReg5.MEMORYMAP.Size=65536 +MMTAppReg5.MEMORYMAP.StartAddress=0x20000000 +MMTAppReg6.MEMORYMAP.AppRegionName=RAM +MMTAppReg6.MEMORYMAP.ContextName=Appli +MMTAppReg6.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg6.MEMORYMAP.DefaultDataRegion=true +MMTAppReg6.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name +MMTAppReg6.MEMORYMAP.Name=RAM +MMTAppReg6.MEMORYMAP.Size=465920 +MMTAppReg6.MEMORYMAP.StartAddress=0x24000000 +MMTAppReg7.MEMORYMAP.AppRegionName=ITCM +MMTAppReg7.MEMORYMAP.Cacheability=WTRA +MMTAppReg7.MEMORYMAP.ContextName=Appli +MMTAppReg7.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg7.MEMORYMAP.DefaultDataRegion=false +MMTAppReg7.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,Cacheability +MMTAppReg7.MEMORYMAP.Name=ITCM +MMTAppReg7.MEMORYMAP.Size=65536 +MMTAppReg7.MEMORYMAP.StartAddress=0x00000000 +MMTAppReg8.MEMORYMAP.AP=RO_priv_only +MMTAppReg8.MEMORYMAP.AppRegionName=FLASH +MMTAppReg8.MEMORYMAP.Cacheability=WTRA +MMTAppReg8.MEMORYMAP.ContextName=Appli +MMTAppReg8.MEMORYMAP.CoreName=ARM Cortex-M7 +MMTAppReg8.MEMORYMAP.DefaultCodeRegion=true +MMTAppReg8.MEMORYMAP.DefaultDataRegion=false +MMTAppReg8.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion +MMTAppReg8.MEMORYMAP.MemType=ROM +MMTAppReg8.MEMORYMAP.Name=FLASH +MMTAppReg8.MEMORYMAP.Size=65536 +MMTAppReg8.MEMORYMAP.StartAddress=0x08000000 +MMTAppRegionsCount=8 +MMTConfigApplied=false +Mcu.CPN=STM32H7R7L8H6H +Mcu.Context0=Boot +Mcu.Context1=Appli +Mcu.Context2=ExtMemLoader +Mcu.ContextNb=3 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7_APPLI +Mcu.IP1=CORTEX_M7_BOOT +Mcu.IP10=UART7 +Mcu.IP11=USART1 +Mcu.IP12=USB_OTG_HS +Mcu.IP13=XSPI1 +Mcu.IP14=XSPI2 +Mcu.IP2=ETH +Mcu.IP3=FDCAN1 +Mcu.IP4=FLASH +Mcu.IP5=MEMORYMAP +Mcu.IP6=NVIC2 +Mcu.IP7=NVIC1 +Mcu.IP8=RCC +Mcu.IP9=SDMMC1 +Mcu.IPNb=15 +Mcu.Name=STM32H7R7L8HxH +Mcu.Package=TFBGA225 HEXA SMPS +Mcu.Pin0=PM6 +Mcu.Pin1=PD2 +Mcu.Pin10=PC15-OSC32_OUT(OSC32_OUT) +Mcu.Pin11=PC14-OSC32_IN(OSC32_IN) +Mcu.Pin12=PC12 +Mcu.Pin13=PC8 +Mcu.Pin14=PD6 +Mcu.Pin15=PC9 +Mcu.Pin16=PG14 +Mcu.Pin17=PG11 +Mcu.Pin18=PN1 +Mcu.Pin19=PG13 +Mcu.Pin2=PD7 +Mcu.Pin20=PN3 +Mcu.Pin21=PN0 +Mcu.Pin22=PN11 +Mcu.Pin23=PN10 +Mcu.Pin24=PN9 +Mcu.Pin25=PN2 +Mcu.Pin26=PF10 +Mcu.Pin27=PN7 +Mcu.Pin28=PN6 +Mcu.Pin29=PH0-OSC_IN(PH0) +Mcu.Pin3=PM9 +Mcu.Pin30=PH1-OSC_OUT(PH1) +Mcu.Pin31=PN8 +Mcu.Pin32=PN4 +Mcu.Pin33=PN5 +Mcu.Pin34=PC1 +Mcu.Pin35=PC4 +Mcu.Pin36=PD14 +Mcu.Pin37=PN12 +Mcu.Pin38=PA4 +Mcu.Pin39=PA7 +Mcu.Pin4=PM5 +Mcu.Pin40=PB14 +Mcu.Pin41=PB15 +Mcu.Pin42=PC5 +Mcu.Pin43=PP2 +Mcu.Pin44=PP5 +Mcu.Pin45=PO2 +Mcu.Pin46=PP1 +Mcu.Pin47=PP3 +Mcu.Pin48=PP0 +Mcu.Pin49=PP7 +Mcu.Pin5=PD1 +Mcu.Pin50=PP4 +Mcu.Pin51=PO4 +Mcu.Pin52=PP6 +Mcu.Pin53=PO0 +Mcu.Pin54=VP_FLASH_SIG_Activate_FlashIP +Mcu.Pin55=VP_RCC_VS_RMII +Mcu.Pin56=VP_XSPI1_VS_octo +Mcu.Pin57=VP_XSPI2_VS_octo +Mcu.Pin58=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin6=PC10 +Mcu.Pin7=PC11 +Mcu.Pin8=PM8 +Mcu.Pin9=PD0 +Mcu.PinsNb=59 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H7R7L8HxH +MxCube.Version=6.12.0 +MxDb.Version=DB.6.0.120 +NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.ForceEnableDMAVector=true +NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.ETH_IRQn=true\:7\:0\:true\:false\:true\:true\:true\:true +NVIC2.ForceEnableDMAVector=true +NVIC2.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC2.SDMMC1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true +NVIC2.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC2.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA4.GPIOParameters=PinAttribute +PA4.Locked=true +PA4.Mode=RMII +PA4.PinAttribute=Appli +PA4.Signal=ETH_MDIO +PA7.GPIOParameters=PinAttribute +PA7.Mode=RMII +PA7.PinAttribute=Appli +PA7.Signal=ETH_RMII_CRS_DV +PB14.GPIOParameters=PinAttribute +PB14.Locked=true +PB14.Mode=Asynchronous +PB14.PinAttribute=Appli +PB14.Signal=USART1_TX +PB15.GPIOParameters=PinAttribute +PB15.Locked=true +PB15.Mode=Asynchronous +PB15.PinAttribute=Appli +PB15.Signal=USART1_RX +PC1.GPIOParameters=PinAttribute +PC1.Mode=RMII +PC1.PinAttribute=Appli +PC1.Signal=ETH_MDC +PC10.GPIOParameters=PinAttribute +PC10.Mode=SD_4_bits_Wide_bus +PC10.PinAttribute=Appli +PC10.Signal=SDMMC1_D2 +PC11.GPIOParameters=PinAttribute +PC11.Mode=SD_4_bits_Wide_bus +PC11.PinAttribute=Appli +PC11.Signal=SDMMC1_D3 +PC12.GPIOParameters=PinAttribute +PC12.Mode=SD_4_bits_Wide_bus +PC12.PinAttribute=Appli +PC12.Signal=SDMMC1_CK +PC14-OSC32_IN(OSC32_IN).Mode=LSE-External-Oscillator +PC14-OSC32_IN(OSC32_IN).Signal=RCC_OSC32_IN +PC15-OSC32_OUT(OSC32_OUT).Mode=LSE-External-Oscillator +PC15-OSC32_OUT(OSC32_OUT).Signal=RCC_OSC32_OUT +PC4.GPIOParameters=PinAttribute +PC4.Mode=RMII +PC4.PinAttribute=Appli +PC4.Signal=ETH_RMII_RXD0 +PC5.GPIOParameters=PinAttribute +PC5.Mode=RMII +PC5.PinAttribute=Appli +PC5.Signal=ETH_RMII_RXD1 +PC8.GPIOParameters=PinAttribute +PC8.Mode=SD_4_bits_Wide_bus +PC8.PinAttribute=Appli +PC8.Signal=SDMMC1_D0 +PC9.GPIOParameters=PinAttribute +PC9.Mode=SD_4_bits_Wide_bus +PC9.PinAttribute=Appli +PC9.Signal=SDMMC1_D1 +PD0.GPIOParameters=PinAttribute +PD0.Locked=true +PD0.Mode=FDCAN_Activate +PD0.PinAttribute=Appli +PD0.Signal=FDCAN1_RX +PD1.GPIOParameters=PinAttribute +PD1.Locked=true +PD1.Mode=FDCAN_Activate +PD1.PinAttribute=Appli +PD1.Signal=FDCAN1_TX +PD14.GPIOParameters=GPIO_PuPd,GPIO_Label,PinAttribute +PD14.GPIO_Label=LED0 +PD14.GPIO_PuPd=GPIO_PULLDOWN +PD14.Locked=true +PD14.PinAttribute=Free +PD14.Signal=GPIO_Output +PD2.GPIOParameters=PinAttribute +PD2.Mode=SD_4_bits_Wide_bus +PD2.PinAttribute=Appli +PD2.Signal=SDMMC1_CMD +PD6.GPIOParameters=PinAttribute +PD6.Mode=Digital_ClockEthClk +PD6.PinAttribute=Free +PD6.Signal=ETH_CLK +PD7.GPIOParameters=PinAttribute +PD7.Mode=RMII +PD7.PinAttribute=Appli +PD7.Signal=ETH_RMII_REF_CLK +PF10.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,PinAttribute +PF10.GPIO_Label=ETH_RESET +PF10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PF10.Locked=true +PF10.PinAttribute=Free +PF10.PinState=GPIO_PIN_SET +PF10.Signal=GPIO_Output +PG11.GPIOParameters=PinAttribute +PG11.Mode=RMII +PG11.PinAttribute=Appli +PG11.Signal=ETH_RMII_TX_EN +PG13.GPIOParameters=PinAttribute +PG13.Mode=RMII +PG13.PinAttribute=Appli +PG13.Signal=ETH_RMII_TXD0 +PG14.GPIOParameters=PinAttribute +PG14.Locked=true +PG14.Mode=RMII +PG14.PinAttribute=Appli +PG14.Signal=ETH_RMII_TXD1 +PH0-OSC_IN(PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN(PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT(PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT(PH1).Signal=RCC_OSC_OUT +PM5.GPIOParameters=PinAttribute +PM5.Locked=true +PM5.Mode=Internal_Phy_Device +PM5.PinAttribute=Appli +PM5.Signal=USB_OTG_HS_DM +PM6.GPIOParameters=PinAttribute +PM6.Locked=true +PM6.Mode=Internal_Phy_Device +PM6.PinAttribute=Appli +PM6.Signal=USB_OTG_HS_DP +PM8.GPIOParameters=PinAttribute +PM8.Locked=true +PM8.Mode=Asynchronous +PM8.PinAttribute=Appli +PM8.Signal=UART7_RX +PM9.GPIOParameters=PinAttribute +PM9.Mode=Asynchronous +PM9.PinAttribute=Appli +PM9.Signal=UART7_TX +PN0.GPIOParameters=PinAttribute +PN0.Mode=XSPI2_Port2Octo +PN0.PinAttribute=Appli +PN0.Signal=XSPIM_P2_DQS0 +PN1.GPIOParameters=PinAttribute +PN1.Mode=XSPI2_NCS1_Port2 +PN1.PinAttribute=Appli +PN1.Signal=XSPIM_P2_NCS1 +PN10.GPIOParameters=PinAttribute +PN10.Mode=XSPI2_Port2Octo +PN10.PinAttribute=Appli +PN10.Signal=XSPIM_P2_IO6 +PN11.GPIOParameters=PinAttribute +PN11.Mode=XSPI2_Port2Octo +PN11.PinAttribute=Appli +PN11.Signal=XSPIM_P2_IO7 +PN12.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,PinAttribute +PN12.GPIO_Label=HyperRam_RST +PN12.GPIO_PuPd=GPIO_PULLUP +PN12.Locked=true +PN12.PinAttribute=Free +PN12.PinState=GPIO_PIN_SET +PN12.Signal=GPIO_Output +PN2.GPIOParameters=PinAttribute +PN2.Mode=XSPI2_Port2Octo +PN2.PinAttribute=Appli +PN2.Signal=XSPIM_P2_IO0 +PN3.GPIOParameters=PinAttribute +PN3.Mode=XSPI2_Port2Octo +PN3.PinAttribute=Appli +PN3.Signal=XSPIM_P2_IO1 +PN4.GPIOParameters=PinAttribute +PN4.Mode=XSPI2_Port2Octo +PN4.PinAttribute=Appli +PN4.Signal=XSPIM_P2_IO2 +PN5.GPIOParameters=PinAttribute +PN5.Mode=XSPI2_Port2Octo +PN5.PinAttribute=Appli +PN5.Signal=XSPIM_P2_IO3 +PN6.GPIOParameters=PinAttribute +PN6.Mode=XSPI2_Port2Octo +PN6.PinAttribute=Appli +PN6.Signal=XSPIM_P2_CLK +PN7.GPIOParameters=PinAttribute +PN7.Mode=XSPI2_Port2_NCLK +PN7.PinAttribute=Appli +PN7.Signal=XSPIM_P2_NCLK +PN8.GPIOParameters=PinAttribute +PN8.Mode=XSPI2_Port2Octo +PN8.PinAttribute=Appli +PN8.Signal=XSPIM_P2_IO4 +PN9.GPIOParameters=PinAttribute +PN9.Mode=XSPI2_Port2Octo +PN9.PinAttribute=Appli +PN9.Signal=XSPIM_P2_IO5 +PO0.GPIOParameters=PinAttribute +PO0.Mode=XSPI1_NCS1_Port1 +PO0.PinAttribute=Appli +PO0.Signal=XSPIM_P1_NCS1 +PO2.GPIOParameters=PinAttribute +PO2.Locked=true +PO2.Mode=XSPI1_Port1Octo +PO2.PinAttribute=Appli +PO2.Signal=XSPIM_P1_DQS0 +PO4.GPIOParameters=PinAttribute +PO4.Locked=true +PO4.Mode=XSPI1_Port1Octo +PO4.PinAttribute=Appli +PO4.Signal=XSPIM_P1_CLK +PP0.GPIOParameters=PinAttribute +PP0.Locked=true +PP0.Mode=XSPI1_Port1Octo +PP0.PinAttribute=Appli +PP0.Signal=XSPIM_P1_IO0 +PP1.GPIOParameters=PinAttribute +PP1.Locked=true +PP1.Mode=XSPI1_Port1Octo +PP1.PinAttribute=Appli +PP1.Signal=XSPIM_P1_IO1 +PP2.GPIOParameters=PinAttribute +PP2.Locked=true +PP2.Mode=XSPI1_Port1Octo +PP2.PinAttribute=Appli +PP2.Signal=XSPIM_P1_IO2 +PP3.GPIOParameters=PinAttribute +PP3.Locked=true +PP3.Mode=XSPI1_Port1Octo +PP3.PinAttribute=Appli +PP3.Signal=XSPIM_P1_IO3 +PP4.GPIOParameters=PinAttribute +PP4.Locked=true +PP4.Mode=XSPI1_Port1Octo +PP4.PinAttribute=Appli +PP4.Signal=XSPIM_P1_IO4 +PP5.GPIOParameters=PinAttribute +PP5.Locked=true +PP5.Mode=XSPI1_Port1Octo +PP5.PinAttribute=Appli +PP5.Signal=XSPIM_P1_IO5 +PP6.GPIOParameters=PinAttribute +PP6.Locked=true +PP6.Mode=XSPI1_Port1Octo +PP6.PinAttribute=Appli +PP6.Signal=XSPIM_P1_IO6 +PP7.GPIOParameters=PinAttribute +PP7.Locked=true +PP7.Mode=XSPI1_Port1Octo +PP7.PinAttribute=Appli +PP7.Signal=XSPIM_P1_IO7 +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H7R7L8HxH +ProjectManager.FirmwarePackage=STM32Cube FW_H7RS V1.1.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=App-0x200,Boot-0x200,ExtMemLoader-0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.ProjectStructure=Boot\:Boot Project\:true;App\:Appli Project\:true;ExtMemLoader\:ExtMemLoader Project\:false; +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=App-0x400,Boot-0x400,ExtMemLoader-0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.37 +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-Boot,2-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true-Boot,1-SystemClock_Config-RCC-false-HAL-false-Appli,2-MX_GPIO_Init-GPIO-false-HAL-true-Appli,3-MX_FLASH_Init-FLASH-false-HAL-true-Appli,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true-Appli,5-MX_USART1_UART_Init-USART1-false-HAL-true-Appli,false-6-MX_XSPI1_Init-XSPI1-false-HAL-true-Appli,false-7-MX_XSPI2_Init-XSPI2-false-HAL-true-Appli,8-MX_FDCAN1_Init-FDCAN1-false-HAL-true-Appli,9-MX_ETH_Init-ETH-false-HAL-true-Appli,10-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true-Appli,0-MX_CORTEX_M7_BOOT_Init-CORTEX_M7_BOOT-false-HAL-true-Boot,0-MX_CORTEX_M7_APPLI_Init-CORTEX_M7_APPLI-false-HAL-true-Appli,1-SystemClock_Config-RCC-false-HAL-false-ExtMemLoader +RCC.ADCFreq_Value=600000000 +RCC.ADFFreq_Value=300000000 +RCC.AHB1234Freq_Value=300000000 +RCC.AHB5ClockFreq_Value=300000000 +RCC.APB1Freq_Value=150000000 +RCC.APB2Freq_Value=150000000 +RCC.APB4Freq_Value=150000000 +RCC.APB5Freq_Value=150000000 +RCC.AXIClockFreq_Value=300000000 +RCC.BMPRE=RCC_HCLK_DIV2 +RCC.CECFreq_Value=32768 +RCC.CKPERFreq_Value=64000000 +RCC.CPREFreq_Value=600000000 +RCC.CortexFreq_Value=600000000 +RCC.CpuClockFreq_Value=600000000 +RCC.DIVM1=6 +RCC.DIVM2=6 +RCC.DIVM3=18 +RCC.DIVN1=300 +RCC.DIVN2=300 +RCC.DIVN3=300 +RCC.DIVP1Freq_Value=600000000 +RCC.DIVP2Freq_Value=600000000 +RCC.DIVP3Freq_Value=200000000 +RCC.DIVQ1Freq_Value=600000000 +RCC.DIVQ2Freq_Value=600000000 +RCC.DIVQ3Freq_Value=200000000 +RCC.DIVR1Freq_Value=600000000 +RCC.DIVR2Freq_Value=600000000 +RCC.DIVR3=1 +RCC.DIVR3Freq_Value=400000000 +RCC.DIVS1Freq_Value=600000000 +RCC.DIVS2Freq_Value=600000000 +RCC.DIVS3=8 +RCC.DIVS3Freq_Value=50000000 +RCC.DIVT1Freq_Value=600000000 +RCC.DIVT2=6 +RCC.DIVT2Freq_Value=200000000 +RCC.DIVT3Freq_Value=200000000 +RCC.DTSFreq_Value=32768 +RCC.ETH1Freq_Value=50000000 +RCC.ETHPHYCLockSelection=RCC_ETH1PHYCLKSOURCE_PLL3S +RCC.ETHPHYFreq_Value=50000000 +RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL1Q +RCC.FDCANFreq_Value=600000000 +RCC.FMCFreq_Value=300000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=300000000 +RCC.I2C23Freq_Value=150000000 +RCC.I2CI3C1Freq_Value=150000000 +RCC.IPParameters=ADCFreq_Value,ADFFreq_Value,AHB1234Freq_Value,AHB5ClockFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,BMPRE,CECFreq_Value,CKPERFreq_Value,CPREFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,DIVS1Freq_Value,DIVS2Freq_Value,DIVS3,DIVS3Freq_Value,DIVT1Freq_Value,DIVT2,DIVT2Freq_Value,DIVT3Freq_Value,DTSFreq_Value,ETH1Freq_Value,ETHPHYCLockSelection,ETHPHYFreq_Value,FDCANCLockSelection,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLKFreq_Value,I2C23Freq_Value,I2CI3C1Freq_Value,LPTIM1Freq_Value,LPTIM23Freq_Value,LPTIM45Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,OSPI1Freq_Value,OSPI2Freq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSource,PPRE1,PPRE2,PPRE4,PPRE5,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI1Freq_Value,SPI23Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TPIUFreq_Value,Tim1OutputFreq_Value,Tim2OutputFreq_Value,UCPDFreq_Value,USART1Freq_Value,USART234578Freq_Value,USBOFSFreq_Value,USBPHYFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,Xspi1ClockSelection,Xspi2ClockSelection +RCC.LPTIM1Freq_Value=150000000 +RCC.LPTIM23Freq_Value=150000000 +RCC.LPTIM45Freq_Value=150000000 +RCC.LPUART1Freq_Value=150000000 +RCC.LTDCFreq_Value=400000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=600000000 +RCC.OSPI1Freq_Value=600000000 +RCC.OSPI2Freq_Value=600000000 +RCC.PLL2FRACN=0 +RCC.PLL3FRACN=0 +RCC.PLLFRACN=0 +RCC.PLLSource=RCC_PLLSOURCE_HSE +RCC.PPRE1=RCC_APB1_DIV2 +RCC.PPRE2=RCC_APB2_DIV2 +RCC.PPRE4=RCC_APB4_DIV2 +RCC.PPRE5=RCC_APB5_DIV2 +RCC.PSSIFreq_Value=400000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=600000000 +RCC.SAI2Freq_Value=600000000 +RCC.SDMMC1CLockSelection=RCC_SDMMC12CLKSOURCE_PLL2T +RCC.SDMMCFreq_Value=200000000 +RCC.SPDIFRXFreq_Value=600000000 +RCC.SPI1Freq_Value=600000000 +RCC.SPI23Freq_Value=600000000 +RCC.SPI45Freq_Value=150000000 +RCC.SPI6Freq_Value=150000000 +RCC.SYSCLKFreq_VALUE=600000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TPIUFreq_Value=200000000 +RCC.Tim1OutputFreq_Value=300000000 +RCC.Tim2OutputFreq_Value=300000000 +RCC.UCPDFreq_Value=16000000 +RCC.USART1Freq_Value=150000000 +RCC.USART234578Freq_Value=150000000 +RCC.USBOFSFreq_Value=48000000 +RCC.USBPHYFreq_Value=24000000 +RCC.VCO1OutputFreq_Value=1200000000 +RCC.VCO2OutputFreq_Value=1200000000 +RCC.VCO3OutputFreq_Value=400000000 +RCC.VCOInput1Freq_Value=4000000 +RCC.VCOInput2Freq_Value=4000000 +RCC.VCOInput3Freq_Value=1333333.3333333333 +RCC.Xspi1ClockSelection=RCC_XSPI1CLKSOURCE_PLL2S +RCC.Xspi2ClockSelection=RCC_XSPI2CLKSOURCE_PLL2S +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USB_OTG_HS.IPParameters=VirtualMode +USB_OTG_HS.VirtualMode=Device_HS +VP_FLASH_SIG_Activate_FlashIP.Mode=Activate_FlashIP +VP_FLASH_SIG_Activate_FlashIP.Signal=FLASH_SIG_Activate_FlashIP +VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg +VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP +VP_RCC_VS_RMII.Mode=Digital_ClockIn +VP_RCC_VS_RMII.Signal=RCC_VS_RMII +VP_XSPI1_VS_octo.Mode=octo_mode +VP_XSPI1_VS_octo.Signal=XSPI1_VS_octo +VP_XSPI2_VS_octo.Mode=hyperbus_mode +VP_XSPI2_VS_octo.Signal=XSPI2_VS_octo +board=custom diff --git a/bsp/stm32/stm32h7r7-atk/board/Kconfig b/bsp/stm32/stm32h7r7-atk/board/Kconfig new file mode 100644 index 00000000000..b46762fb923 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/Kconfig @@ -0,0 +1,479 @@ +menu "Hardware Drivers Config" +config SOC_STM32H7RS + bool + select SOC_SERIES_STM32H7RS + select RT_USING_COMPONENTS_INIT + default y + +config SOC_SERIES_STM32H7RS + bool + select ARCH_ARM_CORTEX_M7 + select SOC_FAMILY_STM32 + default y + +menuconfig RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT + bool "Enable independent interrupt management" + default n + + if RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT + config RT_MAX_SYSCALL_INTERRUPT_PRIORITY + int "Set max syscall interrupt priority" + range 0 7 + default 6 + endif + +menu "Onboard Peripheral Drivers" + + config BSP_SCB_ENABLE_I_CACHE + bool "Enable ICACHE" + default y + + config BSP_SCB_ENABLE_D_CACHE + bool "Enable DCACHE" + default y + + config BSP_USING_USB_TO_USART + bool "Enable Debuger USART (uart4)" + select BSP_USING_UART + select BSP_USING_UART4 + default n + + config BSP_USING_XSPI_NORFLASH + bool "Enable XSPI octal norFLASH (w35t1nw) no-xip method" + select RT_USING_FAL + default n + + config BSP_USING_WIFI + bool "Enable wifi (CYWL6208 or AP6212)" + select ART_PI_USING_WIFI_6212_LIB + select ART_PI_USING_OTA_LIB + select BSP_USING_SPI_FLASH + select RT_USING_WIFI + select RT_USING_SAL + default n + + menuconfig BSP_USING_LVGL + bool "Enable LVGL for LCD" + select PKG_USING_LVGL + default n + if BSP_USING_LVGL + config BSP_USING_LCD_RGB + bool "Enable LVGL for LCD_RGB565" + select BSP_USING_LCD + select RT_TOUCH_PIN_IRQ + default n + if BSP_USING_LCD_RGB + config BSP_USING_TOUCH + bool "Enable Touch control" + select BSP_USING_I2C + select BSP_USING_I2C2 + select RT_USING_TOUCH + default n + if BSP_USING_TOUCH + choice + prompt "Choose Touch Driver" + default BSP_USING_GT9147 + config BSP_USING_GT9147 + select PKG_USING_GT9147 + bool "USING Touch IC GT9147" + + config BSP_USING_GT911 + select PKG_USING_GT911 + bool "USING Touch IC GT1151 GT1158" + default n + endchoice + endif + endif + endif + + menuconfig BSP_USING_LVGL_DEMO + bool "Enable LVGL demo for LCD" + if BSP_USING_LVGL_DEMO + config BSP_USING_LVGL_MUSIC_DEMO + bool "Enable LVGL music demo" + default n + config BSP_USING_LVGL_BENCHMARK_DEMO + select BSP_USING_LVGL_WIDGETS_DEMO + bool "Enable LVGL benchmark demo" + default n + config BSP_USING_LVGL_WIDGETS_DEMO + bool "Enable LVGL widgets demo" + default n + config BSP_USING_LVGL_STRESS_DEMO + bool "Enable LVGL stress demo" + default n + config BSP_USING_LVGL_RENDER_DEMO + bool "Enable LVGL render demo" + default n + endif + + menuconfig BSP_USING_FS + bool "Enable filesystem" + select RT_USING_DFS + select RT_USING_DFS_ROMFS + select RT_USING_POSIX_FS + default n + if BSP_USING_FS + config BSP_USING_SDCARD_FS + bool "Enable SDCARD filesystem" + select BSP_USING_SDIO + select BSP_USING_SDIO1 + select RT_USING_DFS_ELMFAT + default n + config BSP_USING_SPI_FLASH_FS + bool "Enable SPI FLASH filesystem" + select BSP_USING_SPI_FLASH + select RT_USING_MTD_NOR + select PKG_USING_LITTLEFS + default n + endif + +endmenu + +menu "On-chip Peripheral" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on BSP_USING_UART1 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on BSP_USING_UART1 + default 0 + endif + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on BSP_USING_UART7 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on BSP_USING_UART7 + default 0 + endif + + config BSP_USING_UART6 + bool "Enable UART6" + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI4 + bool "Enable SPI4" + default n + config BSP_USING_SPI5 + bool "Enable SPI5 on raspberrypi 40P port." + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + if BSP_USING_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + comment "Notice: PB8 --> 24; PB9 --> 25" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 175 + default 24 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 25 + endif + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + if BSP_USING_I2C2 + comment "Notice: PF0 --> 80; PF1 --> 81" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 176 + default 81 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 0 175 + default 80 + endif + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS (software simulation)" + default n + if BSP_USING_I2C3 + comment "Notice: PA4 --> 4; PA7 --> 7" + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 0 175 + default 7 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 0 175 + default 4 + endif + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PSRAM + bool "Enable PSRAM" + default n + if BSP_USING_PSRAM + config BSP_USING_PSRAM_TEST + bool "Use psram test sample" + default n + endif + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + if BSP_USING_ETH + config ETH_RESET_PIN + string "ETH RESET PIN" + default "PA.3" + endif + if BSP_USING_ETH + choice + prompt "Choose ETH PHY" + default PHY_USING_LAN8720A + config PHY_USING_LAN8720A + bool "USING LAN8720A" + config PHY_USING_DM9161CEP + bool "USING DM9161CEP" + config PHY_USING_DP83848C + bool "USING DP83848C" + config PHY_USING_YT8512C + bool "USING YT8512C" + endchoice + endif + + config BSP_USING_LCD + bool "Enable LCD" + select BSP_USING_GPIO + select BSP_USING_PSRAM + select RT_USING_MEMHEAP + default n + + if BSP_USING_LCD + choice + prompt "Choose LCD Type to config screen parameters and clock timing" + default BSP_USING_LCD_800_RGB + config BSP_USING_OLED_454_MIPI + bool "RT-Thread AMOLED 1.44 inch screen, 454*454 bridged by SSD2828" + config BSP_USING_LCD_800_RGB + bool "RT-Thread or atk 4.3 inch screen, 800*480 " + config BSP_USING_LCD_360_REDUCED + bool "RT-Thread or atk 4.3 inch screen, 800*480 , window to 360*360" + config BSP_USING_LCD_454_REDUCED + bool "RT-Thread or atk 4.3 inch screen, 800*480 , window to 454*454" + endchoice + endif + config BSP_USING_DCMI + bool "Enable DCMI" + default n + + menuconfig BSP_USING_FDCAN + bool "Enable FDCAN" + default n + select RT_USING_CAN + select RT_CAN_USING_CANFD + if BSP_USING_FDCAN + config BSP_USING_FDCAN1 + bool "Using FDCAN1" + default n + if BSP_USING_FDCAN1 + choice + prompt "Choice FDCAN1 Frame Format" + default BSP_FDCAN1_FRAME_FD_BRS + config BSP_FDCAN1_FRAME_CLASSIC + bool "Classic mode" + config BSP_FDCAN1_FRAME_FD + bool "FD mode without BitRate Switching" + config BSP_FDCAN1_FRAME_FD_BRS + bool "FD mode with BitRate Switching" + endchoice + endif + + config BSP_USING_FDCAN2 + bool "Using FDCAN2" + default n + if BSP_USING_FDCAN2 + choice + prompt "Choice FDCAN2 Frame Format" + default BSP_FDCAN2_FRAME_FD_BRS + config BSP_FDCAN2_FRAME_CLASSIC + bool "Classic mode" + config BSP_FDCAN2_FRAME_FD + bool "FD mode without BitRate Switching" + config BSP_FDCAN2_FRAME_FD_BRS + bool "FD mode with BitRate Switching" + endchoice + endif + endif + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM5 + bool "Enable Timer5 output pwm" + default n + if BSP_USING_PWM5 + config BSP_USING_PWM5_CH1 + bool "Enable PWM5 channel1" + default n + endif + config SAMPLES_USING_PWM + bool "SAMPLE PWM5 channel1" + default n + endif + + config BSP_USING_ONCHIP_RTC + bool "Enable Onchip RTC" + select RT_USING_RTC + default n +endmenu + +endmenu + +menu "External Libraries" + + config ART_PI_USING_WIFI_6212_LIB + bool "Using Wifi(AP6212) Library" + select BSP_USING_SDIO + select BSP_USING_SDIO2 + select RT_USING_LWIP + select RT_USING_WIFI + default n + + config ART_PI_TouchGFX_LIB + bool "Using TouchGFX Library" + select RT_USING_CPLUSPLUS + select RT_USING_MEMHEAP + select RT_USING_TOUCH + select RT_TOUCH_PIN_IRQ + select BSP_USING_PSRAM + select BSP_USING_I2C + select BSP_USING_I2C2 + select PKG_USING_GT911 + default n +endmenu + +choice + prompt "The target of download and execute firmware" + default FIRMWARE_EXEC_USING_OSPI_FLASH + + config FIRMWARE_EXEC_USING_OSPI_FLASH + bool "OSPI Flash" + +endchoice diff --git a/bsp/stm32/stm32h7r7-atk/board/SConscript b/bsp/stm32/stm32h7r7-atk/board/SConscript new file mode 100644 index 00000000000..062dac808a0 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/SConscript @@ -0,0 +1,23 @@ +import os +from building import * + +cwd = GetCurrentDir() +list = os.listdir(cwd) + +src = Glob('*.c') + +src += Split(''' +CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c +''') + +path = [cwd] +path += [cwd + '/port'] +path += [cwd + '/CubeMX_Config/Appli/Core/Inc'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32h7r7-atk/board/board.c b/bsp/stm32/stm32h7r7-atk/board/board.c new file mode 100644 index 00000000000..0a1579ec288 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/board.c @@ -0,0 +1,52 @@ +/* + * @Author: xx + * @Date: 2025-06-04 20:15:23 + * @LastEditors: Do not edit + * @LastEditTime: 2025-06-05 14:32:32 + * @Description: + * @FilePath: \undefinedf:\github\rtthread\rt-thread\bsp\stm32\stm32h7r7-atk\board\board.c + */ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-29 RealThread first version + */ + +#include "board.h" + +#define DBG_TAG "board" +#define DBG_LVL DBG_LOG +#include + +#ifdef RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT +#define RT_NVIC_PRO_BITS __NVIC_PRIO_BITS + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level = __get_BASEPRI(); + __set_BASEPRI(RT_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - RT_NVIC_PRO_BITS)); + + __ISB(); + __DSB(); + + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __set_BASEPRI(level); +} +#endif /* RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT */ + +/** + * @brief System Clock Configuration + * @retval None +*/ +void SystemClock_Config(void) +{ + return; +} diff --git a/bsp/stm32/stm32h7r7-atk/board/board.h b/bsp/stm32/stm32h7r7-atk/board/board.h new file mode 100644 index 00000000000..31a93bcd1f8 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/board.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-29 RealThread first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*-------------------------- CHIP CONFIG BEGIN --------------------------*/ + +#define CHIP_FAMILY_STM32 +#define CHIP_SERIES_STM32H7RS +#define CHIP_NAME_STM32H750XBHX + +/*-------------------------- CHIP CONFIG END --------------------------*/ + +/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/ +/** + * @brief H7RS7 SRAM MEMORY Layout + * 0x24060000 - 0x23071FFF AXI SRAM shared with ECC + * 0x24040000 - 0x2305FFFF AXI SRAM shared with DTCM + * 0x24020000 - 0x2403FFFF AXI SRAM + * 0x24000000 - 0x2401FFFF AXI SRAM shared with ITCM + */ +#define ROM_START ((uint32_t)0x90000000) +#define ROM_SIZE (131072) +#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE * 1024)) + +#define RAM_START (0x24000000) +#define RAM_SIZE (456) +#define RAM_END (RAM_START + RAM_SIZE * 1024) + +/*-------------------------- ROM/RAM CONFIG END --------------------------*/ + +/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/ + +#define BSP_CLOCK_SOURCE ("HSE") +#define BSP_CLOCK_SOURCE_FREQ_MHZ ((int32_t)0) +#define BSP_CLOCK_SYSTEM_FREQ_MHZ ((int32_t)480) + +/*-------------------------- CLOCK CONFIG END --------------------------*/ + +/*-------------------------- UART CONFIG BEGIN --------------------------*/ + +/** After configuring corresponding UART or UART DMA, you can use it. + * + * STEP 1, define macro define related to the serial port opening based on the serial port number + * such as #define BSP_USING_UATR1 + * + * STEP 2, according to the corresponding pin of serial port, define the related serial port information macro + * such as #define BSP_UART1_TX_PIN "PA9" + * #define BSP_UART1_RX_PIN "PA10" + * + * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings. + * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode + * + * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file + * such as #define BSP_UART1_RX_USING_DMA + * + */ + +#ifdef BSP_USING_UART1 +#define BSP_UART1_TX_PIN "PA9" +#define BSP_UART1_RX_PIN "PA10" +#endif + +#ifdef BSP_USING_UART4 +#define BSP_UART4_TX_PIN "PD0" +#define BSP_UART4_RX_PIN "PD1" +#endif + + +void SystemClock_Config(void); +void SystemClock_ReConfig(uint8_t mode); + +/*-------------------------- UART CONFIG END --------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c b/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c new file mode 100644 index 00000000000..3554e08a3ba --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/drv_mpu.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-14 whj4674672 first version + */ +#include +#include "stm32h7rsxx.h" +#include "board.h" + +int mpu_init(void) +{ + MPU_Region_InitTypeDef mpu_region_init_struct = {0}; + uint32_t region_index = 0; + + /* 关闭MPU */ + HAL_MPU_Disable(); + + /* 配置背景域（0x00000000~0xFFFFFFFF，4GB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x00000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_4GB; + mpu_region_init_struct.SubRegionDisable = 0x87; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL0; + mpu_region_init_struct.AccessPermission = MPU_REGION_NO_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置ITCM对应区域（0x00000000~0x0000FFFF，64KB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x00000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_64KB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置DTCM对应区域（0x20000000~0x2000FFFF，64KB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x20000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_64KB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置AXI-SRAM1~4对应区域（0x24000000~0x24071FFF，456KB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x24000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_512KB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置AHB-SRAM1~2对应区域（0x30000000~0x30007FFF，32KB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x30000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_32KB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置FMC LCD对应区域（0x60000000~0x63FFFFFF，64MB） */ +// mpu_region_init_struct.Enable = MPU_REGION_ENABLE; +// mpu_region_init_struct.Number = region_index++; +// mpu_region_init_struct.BaseAddress = 0x60000000; +// mpu_region_init_struct.Size = MPU_REGION_SIZE_64MB; +// mpu_region_init_struct.SubRegionDisable = 0x00; +// mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL0; +// mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; +// mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; +// mpu_region_init_struct.IsShareable = MPU_ACCESS_SHAREABLE; +// mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; +// mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; +// HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置XSPI NOR Flash对应区域（0x90000000~0x91FFFFFF，32MB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x90000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_32MB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 配置XSPI HyperRAM对应区域（0x70000000~0x71FFFFFF，32MB） */ + mpu_region_init_struct.Enable = MPU_REGION_ENABLE; + mpu_region_init_struct.Number = region_index++; + mpu_region_init_struct.BaseAddress = 0x70000000; + mpu_region_init_struct.Size = MPU_REGION_SIZE_32MB; + mpu_region_init_struct.SubRegionDisable = 0x00; + mpu_region_init_struct.TypeExtField = MPU_TEX_LEVEL1; + mpu_region_init_struct.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu_region_init_struct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + mpu_region_init_struct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + mpu_region_init_struct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + mpu_region_init_struct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&mpu_region_init_struct); + + /* 使能MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + + return RT_EOK; + +} +INIT_BOARD_EXPORT(mpu_init); diff --git a/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds new file mode 100644 index 00000000000..75ae499f2d1 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.lds @@ -0,0 +1,215 @@ +/* + * linker script for STM32H750XBHx with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ +ROM (rx) : ORIGIN =0x08000000,LENGTH =64k +QFLASH (rx) : ORIGIN =0x90000000,LENGTH =8192k +RAM (rw) : ORIGIN =0x24000000,LENGTH =456k +RxDecripSection (rw) : ORIGIN =0x24020000,LENGTH =32k +TxDecripSection (rw) : ORIGIN =0x24020200,LENGTH =32k +RxArraySection (rw) : ORIGIN =0x24020400,LENGTH =32k +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .onchip_rom : + { + . = ALIGN(4); + KEEP(*bootloader_img.o(.rodata*)) + . = ALIGN(4); + } > ROM + + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for at server */ + . = ALIGN(4); + __rtatcmdtab_start = .; + KEEP(*(RtAtCmdTab)) + __rtatcmdtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > QFLASH = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > QFLASH + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + .RxDecripSection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.RxDecripSection) + *(.RxDecripSection.*) + . = ALIGN(4); + __RxDecripSection_free__ = .; + } > RxDecripSection + + .TxDecripSection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.TxDecripSection) + *(.TxDecripSection.*) + . = ALIGN(4); + __TxDecripSection_free__ = .; + } > TxDecripSection + + .RxArraySection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.RxArraySection) + *(.RxArraySection.*) + . = ALIGN(4); + __RxArraySection_free__ = .; + } > RxArraySection + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct new file mode 100644 index 00000000000..ca8f610f3da --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/linker_scripts/link.sct @@ -0,0 +1,29 @@ +LR_EROM1 0x90000000 0x02000000 { + ER_IROM1 0x90000000 0x02000000 { ; ڲ64KBflash + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+XO) + .ANY (+RO) + } + RW_IDTCM 0x20000000 0x00010000 { ; ڲDTCM64KBӳչ2*32bit + .ANY (.RAM_DTCM) + *(STACK) + *(HEAP) + } + + RW_IITCM 0x00000000 0x00010000 { ; ڲITCM64KBӳչ,64bit + .ANY (.RAM_ITCM) + } + + RW_IRAM1 0x24000000 0x00072000 { ; ڲAXIϹ456KBSRAMĿڴͳһʹãӳ + .ANY (+RW +ZI) + } + + RW_IRAM2 0x30000000 0x00008000 { ; ڲAHBϹ32KBSRAMڴͳһʹ + .ANY (.RAM_SRAM2) + } + + RW_ERAM1 0x70000000 UNINIT 0x02000000 { ; ⲿչ32MBHyperBusӿڵRAM + .ANY (.RAM_HPRAM) + } +} diff --git a/bsp/stm32/stm32h7r7-atk/board/port/Kconfig b/bsp/stm32/stm32h7r7-atk/board/port/Kconfig new file mode 100644 index 00000000000..0a918c1ccd3 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/Kconfig @@ -0,0 +1,62 @@ +if BSP_USING_USBD + config BSP_USBD_TYPE_FS + bool + # "USB Full Speed (FS) Core" + config BSP_USBD_TYPE_HS + bool + # "USB High Speed (HS) Core" + + config BSP_USBD_SPEED_HS + bool + # "USB High Speed (HS) Mode" + config BSP_USBD_SPEED_HSINFS + bool + # "USB High Speed (HS) Core in FS mode" + + config BSP_USBD_PHY_EMBEDDED + bool + # "Using Embedded phy interface" + config BSP_USBD_PHY_UTMI + bool + # "UTMI: USB 2.0 Transceiver Macrocell Interace" + config BSP_USBD_PHY_ULPI + bool + # "ULPI: UTMI+ Low Pin Interface" +endif + +config BSP_USING_CRC + bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + # "Crypto device frame dose not support above 8-bits granularity" + # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4" + depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) + default n + +config BSP_USING_RNG + bool "Enable RNG (Random Number Generator)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_RNG + depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \ + SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1) + default n + +config BSP_USING_HASH + bool "Enable HASH (Hash House Harriers)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_HASH + depends on (SOC_SERIES_STM32MP1) + default n + +config BSP_USING_CRYP + bool "Enable CRYP (Encrypt And Decrypt Data)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRYP + depends on (SOC_SERIES_STM32MP1) + default n + +config BSP_USING_UDID + bool "Enable UDID (Unique Device Identifier)" + select RT_USING_HWCRYPTO + default n + diff --git a/bsp/stm32/stm32h7r7-atk/board/port/SConscript b/bsp/stm32/stm32h7r7-atk/board/port/SConscript new file mode 100644 index 00000000000..c715d19153d --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/SConscript @@ -0,0 +1,78 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() +# add general drivers +src = Split(''' +drv_common.c +drv_gpio.c +drv_spi.c +drv_psram.c +''') +#CubeMX_Config/Src/stm32h7xx_hal_msp.c + +if GetDepend(['RT_USING_SERIAL']): + if GetDepend(['RT_USING_SERIAL_V2']): + src += ['drv_usart_v2.c'] + else: + src += ['drv_usart.c'] + +if GetDepend(['BSP_USING_SDIO']): + src += Glob('drv_sdmmc.c') + +if GetDepend(['BSP_USING_ETH']): + src += Glob('drv_eth.c') + +if GetDepend(['BSP_USING_DCMI']): + src += Glob('drv_dcmi.c') + +if GetDepend(['BSP_USING_LCD']): + src += Glob('drv_lcd.c') + +if GetDepend(['BSP_USING_TIM']): + src += Glob('drv_hwtimer.c') + +if GetDepend(['RT_USING_PM']): + src += ['drv_pm.c'] + src += ['drv_lptim.c'] + +if GetDepend(['BSP_USING_SPI_LCD_ILI9488']): + src += Glob('drv_spi_ili9488.c') + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] + +if GetDepend(['BSP_USING_ONCHIP_RTC']): + src += Glob('drv_rtc.c') + +if GetDepend(['BSP_USING_USBD']): + src += Glob('drv_usbd.c') + +if GetDepend(['BSP_USING_USBH']): + src += ['drv_usbh.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['drv_fdcan.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['BSP_USING_XSPI_NORFLASH']): + src += ['drv_xspi_norflash.c'] + +path = [cwd] +path += [cwd + '/include'] +path += [cwd + '/include/config'] + +startup_path_prefix = SDK_LIB + +# STM32H7S7xx +# You can select chips from the list above +CPPDEFINES = ['STM32H7S7xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c new file mode 100644 index 00000000000..81f7c60a4b2 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_common.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-7 SummerGift first version + */ +#include "drv_common.h" +#include + +#ifdef RT_USING_PIN + #include +#endif + +#ifdef RT_USING_SERIAL + #ifdef RT_USING_SERIAL_V2 + #include + #else + #include + #endif /* RT_USING_SERIAL */ +#endif /* RT_USING_SERIAL_V2 */ + +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +extern __IO uint32_t uwTick; +static uint32_t _systick_ms = 1; + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + // Updates the variable SystemCoreClock + SystemCoreClockUpdate(); + + HAL_SYSTICK_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + NVIC_SetPriority(SysTick_IRQn, 0xFF); + + _systick_ms = 1000u / RT_TICK_PER_SECOND; + if (_systick_ms == 0) + _systick_ms = 1; +} +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + HAL_IncTick(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +uint32_t HAL_GetTick(void) +{ + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + HAL_IncTick(); + + return uwTick; +} + +void HAL_IncTick(void) +{ + uwTick += _systick_ms; +} + +void HAL_SuspendTick(void) +{ +} + +void HAL_ResumeTick(void) +{ +} + +void HAL_Delay(__IO uint32_t Delay) +{ + if (rt_thread_self()) + { + rt_thread_mdelay(Delay); + } + else + { + for (rt_uint32_t count = 0; count < Delay; count++) + { + rt_hw_us_delay(1000); + } + } +} + +/* re-implement tick interface for STM32 HAL */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + rt_hw_systick_init(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void _Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint64_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * (reload / (1000000 / RT_TICK_PER_SECOND)); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial STM32 board. + */ +rt_weak void rt_hw_board_init(void) +{ + /* HAL_Init() function is called at the beginning of the program */ + HAL_Init(); + + /* System clock initialization */ + SystemClock_Config(); + +#if defined(RT_USING_HEAP) + /* Heap initialization */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + /* Set the shell console output device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO) + extern void rt_hw_console_init(void); + rt_hw_console_init(); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* Board underlying hardware initialization */ + rt_components_board_init(); +#endif + +#ifdef BSP_SCB_ENABLE_I_CACHE + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); +#endif + +#ifdef BSP_SCB_ENABLE_D_CACHE + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); +#endif +} diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c new file mode 100644 index 00000000000..14695686245 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_eth.c @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-19 SummerGift first version + * 2018-12-25 zylx fix some bugs + * 2019-06-10 SummerGift optimize PHY state detection process + * 2019-09-03 xiaofan optimize link change detection process + * 2020-07-17 wanghaijing support h7 + * 2020-11-30 wanghaijing add phy reset + */ + +#include +#include +#include "board.h" +#include "drv_config.h" + +#ifdef BSP_USING_ETH + +#include +#include "lwipopts.h" +#include "drv_eth.h" + +/* +* Emac driver uses CubeMX tool to generate emac and phy's configuration, +* the configuration files can be found in CubeMX_Config folder. +*/ + +/* debug option */ +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP +//#define DRV_DEBUG +#define LOG_TAG "drv_eth.c" +#include + +#define MAX_ADDR_LEN (6) + + + +struct rt_stm32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; +#ifndef PHY_USING_INTERRUPT_MODE + rt_timer_t poll_link_timer; +#endif + + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* ETH_Speed */ + uint32_t ETH_Speed; + /* ETH_Duplex_Mode */ + uint32_t ETH_Mode; +}; + +typedef struct +{ + struct pbuf pbuf; + uint8_t buff[ETH_RX_BUFFER_SIZE]; +} RxBuff_t; + +static ETH_HandleTypeDef EthHandle = {0}; +static ETH_TxPacketConfig TxConfig; +static struct rt_stm32_eth stm32_eth_device; +static uint8_t PHY_ADDR = BSP_ETH_PHY_ADDR; +static rt_uint32_t reset_pin = 0; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x24020000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x24020100 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ +#pragma location=0x24020200 +uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ +__attribute__((at(0x24020000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x24020100))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ +__attribute__((at(0x24020200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ +RxBuff_t Rx_Buff[ETH_RX_DESC_CNT] __attribute__((section(".RxArraySection")))__attribute__((aligned(32))); /* Ethernet Receive Buffers */ +#endif + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} +#endif + +static void phy_reset(void) +{ + rt_pin_write(reset_pin, PIN_LOW); + rt_thread_mdelay(50); + rt_pin_write(reset_pin, PIN_HIGH); +} + + +/* EMAC initialization function */ +static rt_err_t rt_stm32_eth_init(rt_device_t dev) +{ + ETH_MACConfigTypeDef MACConf; + uint32_t regvalue = 0; + uint8_t status = RT_EOK; + + + /* ETHERNET Configuration */ + EthHandle.Instance = ETH; + EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0]; + EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE; + EthHandle.Init.TxDesc = DMATxDscrTab; + EthHandle.Init.RxDesc = DMARxDscrTab; + EthHandle.Init.RxBuffLen = ETH_MAX_PACKET_SIZE; + + SCB_InvalidateDCache(); + + HAL_ETH_DeInit(&EthHandle); + + /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ + if (HAL_ETH_Init(&EthHandle) != HAL_OK) + { + LOG_E("eth hardware init failed"); + } + else + { + LOG_D("eth hardware init success"); + } + + phy_reset(); + + rt_memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + + HAL_ETH_SetMDIOClockRange(&EthHandle); + + PHY_ADDR = BSP_ETH_PHY_ADDR; + + /* soft reset */ + if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK) + { + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value); + + uint32_t tickstart = rt_tick_get(); + + /* wait until software reset is done or timeout occured */ + while(regvalue & PHY_RESET_MASK) + { + if((rt_tick_get() - tickstart) <= 500) + { + if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) != HAL_OK) + { + status = RT_ERROR; + break; + } + } + else + { + status = RT_ETIMEOUT; + } + } + } + + rt_thread_delay(2000); + + /* Enable automatic negotiation */ + if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) == HAL_OK) + { + regvalue |= PHY_AUTO_NEGOTIATION_MASK; + HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, regvalue); + + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + HAL_ETH_GetMACConfig(&EthHandle, &MACConf); + MACConf.DuplexMode = ETH_FULLDUPLEX_MODE; + MACConf.Speed = ETH_SPEED_100M; + HAL_ETH_SetMACConfig(&EthHandle, &MACConf); + + HAL_ETH_Start_IT(&EthHandle); + SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef)); + } + else + { + status = RT_ERROR; + } + + return status; +} + +static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("emac open"); + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_close(rt_device_t dev) +{ + LOG_D("emac close"); + return RT_EOK; +} + +static rt_ssize_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("emac read"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_ssize_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("emac write"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* ethernet device interface */ +/* transmit data*/ +rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t ret = RT_ERROR; + HAL_StatusTypeDef state; + uint32_t i = 0, framelen = 0; + struct pbuf *q; + ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0}; + + rt_memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef)); + + for (q = p; q != NULL; q = q->next) + { + if (i >= ETH_TX_DESC_CNT) + return ERR_IF; + + Txbuffer[i].buffer = q->payload; + Txbuffer[i].len = q->len; + framelen += q->len; + + if (i > 0) + { + Txbuffer[i - 1].next = &Txbuffer[i]; + } + + if (q->next == NULL) + { + Txbuffer[i].next = NULL; + } + + i++; + } + + TxConfig.Length = framelen; + TxConfig.TxBuffer = Txbuffer; + TxConfig.pData = p; + +#ifdef ETH_TX_DUMP + rt_kprintf("Tx dump, len= %d\r\n", framelen); + dump_hex(&Txbuffer[0]); +#endif + + if (stm32_eth_device.parent.link_status) + { + SCB_CleanInvalidateDCache(); + state = HAL_ETH_Transmit(&EthHandle, &TxConfig, 1000); + if (state != HAL_OK) + { + LOG_W("eth transmit frame faild: %d", EthHandle.ErrorCode); + EthHandle.ErrorCode = HAL_ETH_STATE_READY; + EthHandle.gState = HAL_ETH_STATE_READY; + } + } + else + { + LOG_E("eth transmit frame faild, netif not up"); + } + HAL_ETH_ReleaseTxPacket(&EthHandle); + ret = ERR_OK; + + return ret; +} + +/* receive data*/ +struct pbuf *rt_stm32_eth_rx(rt_device_t dev) +{ + uint32_t framelength = 0; + rt_uint16_t l; + struct pbuf *p = RT_NULL; + uint32_t alignedAddr; + RxBuff_t *pStart = RT_NULL, *q; + + SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef)); + /* Here, pStart actually points to the address of RxBuff_t */ + if(HAL_ETH_ReadData(&EthHandle, (void**)&pStart) == HAL_OK) + { + SCB_CleanInvalidateDCache_by_Addr(&DMARxDscrTab, ETH_RX_DESC_CNT * sizeof(ETH_DMADescTypeDef)); + framelength = EthHandle.RxDescList.RxDataLength; + /* Invalidate data cache for ETH Rx Buffers */ + /* The Rx_Buff pointed to by pStart was already 32 aligned when defined */ + SCB_InvalidateDCache_by_Addr((uint32_t *)pStart->buff, framelength); + + p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM); + if (p != NULL) + { + for (q = pStart, l = 0; q != NULL; q = (RxBuff_t *)q->pbuf.next) + { + rt_memcpy(&(((rt_uint8_t*)(p->payload))[l]), q->buff, q->pbuf.len); + l = l + q->pbuf.len; + } + } + } + + return p; +} + +/* interrupt service routine */ +void ETH_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_ETH_IRQHandler(&EthHandle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_ETH_TxFreeCallback(uint32_t * buff) +{ +/* USER CODE BEGIN HAL ETH TxFreeCallback */ + + pbuf_free((struct pbuf *)buff); + +/* USER CODE END HAL ETH TxFreeCallback */ +} + +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* * + * ppstart is a member of pRxStart in the descriptor list, here + * The address defined as pbuf is also the address of RxBuff_t, and buff is + * The address saved by the Ethernet frame. This function is mainly to link the relevant + * All the pbuf of * are connected. + */ + struct pbuf **ppStart = (struct pbuf **)pStart; + struct pbuf **ppEnd = (struct pbuf **)pEnd; + struct pbuf *p = NULL; + + /* Get the struct pbuf from the buff address. */ + p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff)); + p->next = NULL; + p->tot_len = 0; + p->len = Length; + + /* Chain the buffer. */ + /* Normally, the first time you enter a new package, pstart should be empty */ + if (!*ppStart) + { + /* The first buffer sets pstart. */ + *ppStart = p; + } + else + { + /* Here, "pEnd" points to the "pbuf" that entered the HAL_ETH_RxLinkCallback + last time, which is also "RX_BUFF_T" */ + (*ppEnd)->next = p; + } + /* Set pEnd to the current pbuf */ + *ppEnd = p; + + /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len + * set to its own length, plus the length of all the following pbufs in the chain. */ + for (p = *ppStart; p != NULL; p = p->next) + { + p->tot_len += Length; + } + + /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */ + SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length); + +} + +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + rt_err_t result; + result = eth_device_ready(&(stm32_eth_device.parent)); + if (result != RT_EOK) + LOG_I("RxCpltCallback err = %d", result); +} + +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + if ((HAL_ETH_GetDMAError(heth) & ETH_DMACSR_RBU) == ETH_DMACSR_RBU) + { + LOG_E("eth err:ETH_DMACSR_RBU"); + } + + if((HAL_ETH_GetDMAError(heth) & ETH_DMACSR_TBU) == ETH_DMACSR_TBU) + { + LOG_E("eth err:ETH_DMACSR_TBU"); + } + LOG_E("eth err"); +} + +void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + + /* Use the circular buffer index */ + static uint16_t buf_index = 0; + + /* Check the descriptor ownership before updating the index */ + if((DMARxDscrTab[buf_index].DESC3 & ETH_DMARXNDESCRF_OWN) == 0) { + *buff = Rx_Buff[buf_index].buff; + buf_index = (buf_index + 1) % ETH_RX_DESC_CNT; + } else { + LOG_W("Buffer %d not released!", buf_index); + *buff = RT_NULL; + } +} + +enum { + PHY_LINK = (1 << 0), + PHY_100M = (1 << 1), + PHY_FULL_DUPLEX = (1 << 2), +}; + +static void phy_linkchange() +{ + static rt_uint8_t phy_speed = 0; + rt_uint8_t phy_speed_new = 0; + rt_uint32_t status; + + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_STATUS_REG, (uint32_t *)&status); + LOG_D("phy basic status reg is 0x%X", status); + + /* If the automatic negotiation is completed or the connection is established */ + if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK)) + { + rt_uint32_t SR = 0; + + + + /* Read the special status register to check the network speed and duplex status */ + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_Status_REG, (uint32_t *)&SR); + LOG_D("phy control status reg is 0x%X", SR); + + if(PHY_Status_LINK_UP(SR)) + { + phy_speed_new |= PHY_LINK; + } + + if (PHY_Status_SPEED_100M(SR)) + { + phy_speed_new |= PHY_100M; + } + + if (PHY_Status_FULL_DUPLEX(SR)) + { + phy_speed_new |= PHY_FULL_DUPLEX; + } + } + + /* If the link is on or 100 megabits, it is in full-duplex mode and ready to be set up */ + if (phy_speed != phy_speed_new) + { + phy_speed = phy_speed_new; + + /* Link establishment */ + if (phy_speed & PHY_LINK) + { + LOG_D("link up"); + if (phy_speed & PHY_100M) + { + LOG_D("100Mbps"); + stm32_eth_device.ETH_Speed = ETH_SPEED_100M; + } + else + { + stm32_eth_device.ETH_Speed = ETH_SPEED_10M; + LOG_D("10Mbps"); + } + + if (phy_speed & PHY_FULL_DUPLEX) + { + LOG_D("full-duplex"); + stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE; + } + else + { + LOG_D("half-duplex"); + stm32_eth_device.ETH_Mode = ETH_HALFDUPLEX_MODE; + } + + /* send link up. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + } + else + { + LOG_I("link down"); + eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); + } + } +} + +#ifdef PHY_USING_INTERRUPT_MODE +static void eth_phy_isr(void *args) +{ + rt_uint32_t status = 0; + + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status); + LOG_D("phy interrupt status reg is 0x%X", status); + + phy_linkchange(); +} +#endif /* PHY_USING_INTERRUPT_MODE */ + +static void phy_monitor_thread_entry(void *parameter) +{ + phy_linkchange(); +#ifdef PHY_USING_INTERRUPT_MODE + /* configuration intterrupt pin */ + rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs"); + rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE); + + /* enable phy interrupt */ + HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK); +#if defined(PHY_INTERRUPT_CTRL_REG) + HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN); +#endif +#else /* PHY_USING_INTERRUPT_MODE */ + stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange, + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK) + { + LOG_E("Start link change detection timer failed"); + } +#endif /* PHY_USING_INTERRUPT_MODE */ +} + +/* Register the EMAC device */ +static int rt_hw_stm32_eth_init(void) +{ + rt_err_t state = RT_EOK; + reset_pin = rt_pin_get(ETH_RESET_PIN); + + rt_pin_mode(reset_pin, PIN_MODE_OUTPUT); + rt_pin_write(reset_pin, PIN_HIGH); + + stm32_eth_device.ETH_Speed = ETH_SPEED_100M; + stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE; + + /* OUI 00-80-E1 STMICROELECTRONICS. */ + stm32_eth_device.dev_addr[0] = 0x00; + stm32_eth_device.dev_addr[1] = 0x80; + stm32_eth_device.dev_addr[2] = 0xE1; + /* generate MAC addr from 96bit unique ID (only for test). */ + stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4); + stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2); + stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0); + + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; + + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + + /* register eth device */ + /* The device name format of netif is rtthread_e0, and the first two characters are taken */ + state = eth_device_init(&(stm32_eth_device.parent), "e0"); + if (RT_EOK == state) + { + LOG_D("emac device init success"); + } + else + { + LOG_E("emac device init faild: %d", state); + state = -RT_ERROR; + } + + /* start phy monitor */ + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 1024, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + state = -RT_ERROR; + } + + return state; +} +INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init); + +#endif /* BSP_USING_ETH */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_fdcan.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_fdcan.c new file mode 100644 index 00000000000..1f4b166847c --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_fdcan.c @@ -0,0 +1,883 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-24 heyuan the first version + * 2020-08-17 malongwei Fix something + */ + +#include "board.h" +#include +#include + +#ifdef RT_USING_CAN + +#if defined(BSP_USING_FDCAN1) || defined(BSP_USING_FDCAN2) + +#include "drv_fdcan.h" + +#define LOG_TAG "drv_can" +#define DBG_LVL LOG_LVL_DBG +#include + +#ifdef BSP_USING_FDCAN1 +static _stm32_fdcan_t st_DrvCan1 = {0}; +#endif + +#ifdef BSP_USING_FDCAN2 +static _stm32_fdcan_t st_DrvCan2 = {0}; +#endif + + +/* + * note:After frequency division, the working clock of the fdcan is 100mhz + */ +static const _stm32_fdcan_NTconfig_t st_CanNTconfig[]= +/*baud brp sjw tseg1 tseg2*/ +{ + {BSP_FDCAN_BAUD_DATA_5M, 1,8,15,4}, /* Only the data segments of these four can be used */ + {BSP_FDCAN_BAUD_DATA_4M, 1,8,19,5}, + {BSP_FDCAN_BAUD_DATA_2M5, 2,8,15,4}, + {BSP_FDCAN_BAUD_DATA_2M, 2,8,19,5}, + {CAN1MBaud, 5,8,15,4}, /* All of the following are fine. */ + {CAN800kBaud, 1,8,99,25}, + {CAN500kBaud, 10,8,15,4}, + {CAN250kBaud, 10,8,35,4}, + {CAN125kBaud, 20,8,35,4}, + {CAN100kBaud, 20,8,44,5}, + {CAN50kBaud, 40,8,44,5}, + {CAN20kBaud, 100,8,44,5}, + {CAN10kBaud, 200,8,44,5} +}; + +/* +*function name:_inline_get_NTbaud_index +*Inf: Return the index value of the above st_CanNTconfig timing configuration +* structure array based on the passed-in baud rate size. +* +*#param: Baud rate: Decimal number +* +*#return: Index value If not found, return 0xff +*/ +static uint32_t _inline_get_NTbaud_index(uint32_t baud_rate) +{ + uint32_t len, index; + + len = sizeof(st_CanNTconfig) / sizeof(st_CanNTconfig[0]); + + for (index = 0; index < len; index++) + { + if (st_CanNTconfig[index].u32NBaudrate == baud_rate) + + return index; + } + + return 0xff; +} + +static void _inline_can_tx_header_init(_stm32_fdcan_t *pCan) +{ + /* Prepare Tx Header */ + pCan->TxHeader.Identifier = 0x000000; + pCan->TxHeader.IdType = FDCAN_EXTENDED_ID; + pCan->TxHeader.TxFrameType = FDCAN_DATA_FRAME; + pCan->TxHeader.DataLength = FDCAN_DLC_BYTES_8; + pCan->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE; + pCan->TxHeader.BitRateSwitch = FDCAN_BRS_OFF; + pCan->TxHeader.FDFormat = FDCAN_CLASSIC_CAN; + pCan->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS; + pCan->TxHeader.MessageMarker = 0; +} + + +/* + * note:When the clock is input here, it is pll1q, 600mhz. First, it is divided to 100m. The atk + * says the maximum is 125m, but I haven't found it. For now, I believe it + */ +static rt_err_t _inline_can_config(struct rt_can_device *can, struct can_configure *cfg) +{ + _stm32_fdcan_t *pdrv_can; + rt_uint32_t tmp_u32Index; + FDCAN_FilterTypeDef canx_rxfilter = {0}; + + RT_ASSERT(can); + RT_ASSERT(cfg); + + pdrv_can = (_stm32_fdcan_t *)can->parent.user_data; + + RT_ASSERT(pdrv_can); + /* The peripheral clock input is 600MHZ, and after 6 frequency divisions, it becomes 100MHZ */ + pdrv_can->fdcanHandle.Init.ClockDivider = FDCAN_CLOCK_DIV6; + + /* config FrameFormat */ + if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_CLASSIC) + { + pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + pdrv_can->fdcanHandle.Init.AutoRetransmission = DISABLE; + }else if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS) + { + pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_NO_BRS; + pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE; + }else if (cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_BRS) + { + pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_BRS; + pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE; + }else return -RT_ERROR; + + pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL; + pdrv_can->fdcanHandle.Init.TransmitPause = DISABLE; + pdrv_can->fdcanHandle.Init.ProtocolException = DISABLE; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL; + break; + case RT_CAN_MODE_LISTEN: + pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_BUS_MONITORING; + break; + case RT_CAN_MODE_LOOPBACK: + pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK; + break; + default: + pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL; + break; + } + + /* Configure the classic CAN or arbitration segment rate */ + tmp_u32Index = _inline_get_NTbaud_index(cfg->baud_rate); + + /* The data segment rate cannot exceed 1M */ + if(tmp_u32Index <= 3 || tmp_u32Index == 0xff) + return -RT_ERROR; + + pdrv_can->fdcanHandle.Init.NominalPrescaler = st_CanNTconfig[tmp_u32Index].u16Nbrp; + pdrv_can->fdcanHandle.Init.NominalSyncJumpWidth = st_CanNTconfig[tmp_u32Index].u8Nsjw; + pdrv_can->fdcanHandle.Init.NominalTimeSeg1 = st_CanNTconfig[tmp_u32Index].u8Ntseg1; + pdrv_can->fdcanHandle.Init.NominalTimeSeg2 = st_CanNTconfig[tmp_u32Index].u8Ntseg2; + + /* Configure the data segment rate */ + if(cfg->enable_canfd == BSP_FDCAN_FRAMEFORMAT_FD_BRS) + { + tmp_u32Index = _inline_get_NTbaud_index(cfg->baud_rate_fd); + /* The data segment rate cannot be lower than 1M due to the current timing setting issue */ + if(tmp_u32Index > 4 || tmp_u32Index == 0xff) + return -RT_ERROR; + + pdrv_can->fdcanHandle.Init.DataPrescaler = st_CanNTconfig[tmp_u32Index].u16Nbrp; + pdrv_can->fdcanHandle.Init.DataSyncJumpWidth = st_CanNTconfig[tmp_u32Index].u8Nsjw; + pdrv_can->fdcanHandle.Init.DataTimeSeg1 = st_CanNTconfig[tmp_u32Index].u8Ntseg1; + pdrv_can->fdcanHandle.Init.DataTimeSeg2 = st_CanNTconfig[tmp_u32Index].u8Ntseg2; + } + + /* Filter */ + pdrv_can->fdcanHandle.Init.StdFiltersNbr = 28; + pdrv_can->fdcanHandle.Init.ExtFiltersNbr = 8; + + if (HAL_FDCAN_Init(&pdrv_can->fdcanHandle) != HAL_OK) + { + return -RT_ERROR; + } + + /* Install the filter */ +#if defined(RT_CAN_USING_HDR) + HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig); +#else/* If HDR support is not enabled, it will be accepted by default */ + + /* Configure the CAN filter */ + canx_rxfilter.IdType = FDCAN_STANDARD_ID; + canx_rxfilter.FilterIndex = 0; + canx_rxfilter.FilterType = FDCAN_FILTER_MASK; + canx_rxfilter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + canx_rxfilter.FilterID1 = 0x0000; + canx_rxfilter.FilterID2 = 0x0000; + /* Filter configuration */ + if (HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &canx_rxfilter) != HAL_OK) + { + return -RT_ERROR; + } + + /* Extended ID */ + canx_rxfilter.IdType = FDCAN_EXTENDED_ID; + if (HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &canx_rxfilter) != HAL_OK) + { + return -RT_ERROR; + } +#endif + + if (HAL_FDCAN_ConfigGlobalFilter(&pdrv_can->fdcanHandle, FDCAN_REJECT, FDCAN_REJECT, FDCAN_FILTER_REMOTE, FDCAN_FILTER_REMOTE) != HAL_OK) + { + return -RT_ERROR; + } + + /* Initialize the sending head */ + _inline_can_tx_header_init(pdrv_can); + + /* Start peripheral devices */ + HAL_FDCAN_Start(&pdrv_can->fdcanHandle); + return RT_EOK; +} + +/* There is a temporary problem with HDR, can't use */ +#ifdef RT_CAN_USING_HDR +static rt_err_t _inline_can_filter_config(_stm32_fdcan_t *pdrv_can,struct rt_can_filter_config *puser_can_filter_config) +{ + int tmp_i32IndexCount; + + RT_ASSERT(pdrv_can); + RT_ASSERT(puser_can_filter_config); + + pdrv_can->ext_filter_num = 0; + pdrv_can->std_filter_num = 0; + + /* get default filter */ + for (tmp_i32IndexCount = 0; tmp_i32IndexCount < puser_can_filter_config->count; tmp_i32IndexCount++) + { + if(puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank < 0) continue; + + _FilterIndex = (rt_uint32_t)puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank; + + if(puser_can_filter_config->items[tmp_i32IndexCount].ide == RT_CAN_EXTID) + { + pdrv_can->FilterConfig.IdType = FDCAN_EXTENDED_ID; + if(_FilterIndex > 7) return -RT_ERROR; + } + else + { + pdrv_can->FilterConfig.IdType = FDCAN_STANDARD_ID; + if(_FilterIndex > 27) return -RT_ERROR; + } + + pdrv_can->FilterConfig.FilterIndex = _FilterIndex; + pdrv_can->FilterConfig.FilterID1 = puser_can_filter_config->items[tmp_i32IndexCount].id; + pdrv_can->FilterConfig.FilterID2 = puser_can_filter_config->items[tmp_i32IndexCount].mask; + + pdrv_can->FilterConfig.FilterType = FDCAN_FILTER_MASK; + pdrv_can->FilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + if(HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig) != HAL_OK) + { + return -RT_ERROR; + } + } + return RT_EOK; +} +#endif + +static rt_err_t _inline_can_control(struct rt_can_device *can, int cmd, void *arg) +{ + + rt_uint32_t argval; + _stm32_fdcan_t *pdrv_can; + rt_uint32_t tmp_u32Errcount; + rt_uint32_t tmp_u32status; + + RT_ASSERT(can != RT_NULL); + pdrv_can = (_stm32_fdcan_t *)can->parent.user_data; + RT_ASSERT(pdrv_can != RT_NULL); + + switch (cmd) + { + + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_FIFO_EMPTY); + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING); + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE); + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_LOGGING_OVERFLOW); + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF); + HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR); + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, FDCAN_INTERRUPT_LINE0); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); + + if(FDCAN1 == pdrv_can->fdcanHandle.Instance) + { + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); + } + else + { + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + } + + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_INTERRUPT_LINE1); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER0); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER1); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER2); + + if(FDCAN1 == pdrv_can->fdcanHandle.Instance) + { + HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn); + } + else + { + HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn); + } + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, FDCAN_INTERRUPT_LINE1); + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, FDCAN_INTERRUPT_LINE1); + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, FDCAN_INTERRUPT_LINE1); + HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, FDCAN_INTERRUPT_LINE1); + + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, 0); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, 0); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, 0); + HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, 0); + if(FDCAN1 == pdrv_can->fdcanHandle.Instance) + { + HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn); + } + else + { + HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn); + } + } + break; + +#ifdef RT_CAN_USING_HDR + case RT_CAN_CMD_SET_FILTER: + if (RT_NULL == arg) + { + /* default filter config */ + HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig); + } + else + { + filter_cfg = (struct rt_can_filter_config *)arg; + _inline_can_filter_config(pdrv_can, filter_cfg); + } + break; +#endif + + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISTEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISTEN) + { + return -RT_ERROR; + } + if (argval != pdrv_can->device.config.mode) + { + pdrv_can->device.config.mode = argval; + return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t ) arg; + /*just low to 50kbit/s*/ + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != pdrv_can->device.config.baud_rate) + { + pdrv_can->device.config.baud_rate = argval; + return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config); + } + break; + + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -RT_ERROR; + } + if (argval != pdrv_can->device.config.privmode) + { + pdrv_can->device.config.privmode = argval; + + return RT_EOK; + } + break; + + case RT_CAN_CMD_GET_STATUS: + tmp_u32Errcount = pdrv_can->fdcanHandle.Instance->ECR; + tmp_u32status = pdrv_can->fdcanHandle.Instance->PSR; + + pdrv_can->device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff; + pdrv_can->device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff; + pdrv_can->device.status.lasterrtype = tmp_u32status&0x000000007; + + rt_memcpy(arg, &pdrv_can->device.status, sizeof(pdrv_can->device.status)); + break; + + case BSP_CAN_CMD_SET_BRS_BAUD: + argval = (rt_uint32_t ) arg; + /*just low to 50kbit/s*/ + if (argval != BSP_FDCAN_BAUD_DATA_2M && + argval != BSP_FDCAN_BAUD_DATA_2M5 && + argval != BSP_FDCAN_BAUD_DATA_4M && + argval != BSP_FDCAN_BAUD_DATA_5M) + { + return -RT_ERROR; + } + if (argval != pdrv_can->device.config.baud_rate_fd) + { + pdrv_can->device.config.baud_rate_fd = argval; + return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config); + } + break; + } + + return RT_EOK; +} + +static rt_ssize_t _inline_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + + _stm32_fdcan_t *pdrv_can; + struct rt_can_msg *pmsg; + uint32_t tmp_u32DataLen; + RT_ASSERT(can); + RT_ASSERT(buf); + + pdrv_can = (_stm32_fdcan_t *)can->parent.user_data; + + RT_ASSERT(pdrv_can); + + pmsg = (struct rt_can_msg *) buf; + + /* Check the parameters */ + tmp_u32DataLen = pmsg->len; +#ifndef RT_CAN_USING_CANFD + if(pmsg->len > 8) + { + tmp_u32DataLen = 8; + } +#else + if(pmsg->len > 64) + { + tmp_u32DataLen = 64; + } +#endif + /* id */ + pdrv_can->TxHeader.Identifier = pmsg->id; + + /* id-type */ + if(pmsg->ide == RT_CAN_EXTID) + { + pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID; + } + else + { + pdrv_can->TxHeader.IdType = FDCAN_STANDARD_ID; + } + + /* tx-frame-type */ + if (pmsg->rtr == RT_CAN_DTR) + { + pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME; + } + else + { + pdrv_can->TxHeader.TxFrameType = FDCAN_REMOTE_FRAME; + } + + /* data-length */ + if(tmp_u32DataLen <= 8){ + pdrv_can->TxHeader.DataLength = tmp_u32DataLen; + }else if (tmp_u32DataLen <= 12) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_12; + }else if (tmp_u32DataLen <= 16) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_16; + }else if (tmp_u32DataLen <= 20) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_20; + }else if (tmp_u32DataLen <= 24) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_24; + }else if (tmp_u32DataLen <= 32) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_32; + }else if (tmp_u32DataLen <= 48) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_48; + }else if (tmp_u32DataLen <= 64) { + pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_64; + } + + /* brs */ + if (pmsg->brs == 1) + { + pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_ON; + } + else + { + pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_OFF; + } + + /* FDFormat */ + if (pmsg->fd_frame == 1) + { + pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN; + } + else + { + pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN; + } + + pdrv_can->TxHeader.MessageMarker = 0; + pdrv_can->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS; + pdrv_can->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE; + + if(HAL_FDCAN_AddMessageToTxFifoQ(&pdrv_can->fdcanHandle, &pdrv_can->TxHeader, pmsg->data) != HAL_OK) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_ssize_t _inline_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + + struct rt_can_msg *pmsg; + _stm32_fdcan_t *pdrv_can; + + RT_ASSERT(can); + RT_ASSERT(buf); + + pdrv_can = (_stm32_fdcan_t *)can->parent.user_data; + pmsg = (struct rt_can_msg *) buf; + if(HAL_FDCAN_GetRxMessage(&pdrv_can->fdcanHandle, FDCAN_RX_FIFO0, &pdrv_can->RxHeader, pmsg->data) != HAL_OK) + { + return -RT_ERROR; + } + else + { + pmsg->id = pdrv_can->RxHeader.Identifier; + if(pdrv_can->RxHeader.IdType == FDCAN_EXTENDED_ID) + { + pmsg->ide = RT_CAN_EXTID; + } + else + { + pmsg->ide = RT_CAN_STDID; + } + + if(pdrv_can->RxHeader.RxFrameType == FDCAN_DATA_FRAME) + { + pmsg->rtr = RT_CAN_DTR; + } + else + { + pmsg->rtr = RT_CAN_RTR; + } + + /* length */ + if(pdrv_can->RxHeader.DataLength <= 8) + { + pmsg->len = pdrv_can->RxHeader.DataLength; + } + else + { + switch(pdrv_can->RxHeader.DataLength) + { + case FDCAN_DLC_BYTES_12: + pmsg->len = 12; + break; + + case FDCAN_DLC_BYTES_16: + pmsg->len = 16; + break; + + case FDCAN_DLC_BYTES_20: + pmsg->len = 20; + break; + + case FDCAN_DLC_BYTES_24: + pmsg->len = 24; + break; + + case FDCAN_DLC_BYTES_32: + pmsg->len = 32; + break; + + case FDCAN_DLC_BYTES_48: + pmsg->len = 48; + break; + + case FDCAN_DLC_BYTES_64: + pmsg->len = 64; + break; + + default: + pmsg->len = 0; + break; + } + } + + + if(pdrv_can->RxHeader.FDFormat == FDCAN_FD_CAN) + { + pmsg->fd_frame = 1; + }else pmsg->fd_frame = 0; + + if(pdrv_can->RxHeader.BitRateSwitch == FDCAN_BRS_ON) + { + pmsg->brs = 1; + }else pmsg->brs = 0; + + pmsg->hdr_index = pdrv_can->RxHeader.FilterIndex; + return RT_EOK; + + } +} + +static const struct rt_can_ops _can_ops = +{ + _inline_can_config, + _inline_can_control, + _inline_can_sendmsg, + _inline_can_recvmsg, +}; + +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + if((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET) + { + if(hfdcan->Instance == FDCAN1) + { +#ifdef BSP_USING_FDCAN1 + //CAN1 + /* Retreive Rx messages from RX FIFO0 */ + rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_RX_IND | 0 << 8); +#endif + } + else + { +#ifdef BSP_USING_FDCAN2 + //CAN2 + /* Retreive Rx messages from RX FIFO0 */ + rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_RX_IND | 0 << 8); +#endif + } + } +} + +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + if(hfdcan->Instance == FDCAN1) + { +#ifdef BSP_USING_FDCAN1 + //can1 + rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE | (((0) << 8))); +#endif + } + else + { +#ifdef BSP_USING_FDCAN2 + //can2 + rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8)); +#endif + } + +} + + +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + if(hfdcan->Instance == FDCAN1) + { + //can1 + } + else + { + //can2 + } +} + +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + +} + +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + rt_uint32_t tmp_u32Errcount; + rt_uint32_t tmp_u32status; + uint32_t ret = HAL_FDCAN_GetError(hfdcan); + + if(hfdcan->Instance == FDCAN1) + { +#ifdef BSP_USING_FDCAN1 + //can1 + if( (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) && + (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk)) + { + hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk; + st_DrvCan1.device.status.errcode = 0xff; + } + else + { + tmp_u32Errcount = st_DrvCan1.fdcanHandle.Instance->ECR; + tmp_u32status = st_DrvCan1.fdcanHandle.Instance->PSR; + + st_DrvCan1.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff; + st_DrvCan1.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff; + st_DrvCan1.device.status.lasterrtype = tmp_u32status&0x000000007; + } +#endif /*BSP_USING_FDCAN1*/ + } + else + { +#ifdef BSP_USING_FDCAN2 + if( (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) && + (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk)) + { + hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk; + st_DrvCan2.device.status.errcode = 0xff; + } + else + { + //can2 + tmp_u32Errcount = st_DrvCan2.fdcanHandle.Instance->ECR; + tmp_u32status = st_DrvCan2.fdcanHandle.Instance->PSR; + st_DrvCan2.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff; + st_DrvCan2.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff; + st_DrvCan2.device.status.lasterrtype = tmp_u32status&0x000000007; + } +#endif /*BSP_USING_FDCAN2*/ + } +} + +#ifdef BSP_USING_FDCAN1 + +void FDCAN1_IT0_IRQHandler(void) /* FDCAN2 interrupt line 0 */ +{ + rt_interrupt_enter(); + HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle); + rt_interrupt_leave(); +} + +void FDCAN1_IT1_IRQHandler(void) /* FDCAN2 interrupt line 1 */ +{ + rt_interrupt_enter(); + HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle); + rt_interrupt_leave(); +} + +#endif /*BSP_USING_FDCAN1*/ + +#ifdef BSP_USING_FDCAN2 +void FDCAN2_IT0_IRQHandler(void) /* FDCAN2 interrupt line 0 */ +{ + rt_interrupt_enter(); + HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle); + rt_interrupt_leave(); +} + +void FDCAN2_IT1_IRQHandler(void) /* FDCAN2 interrupt line 1 */ +{ + rt_interrupt_enter(); + HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle); + rt_interrupt_leave(); +} +#endif/*BSP_USING_FDCAN2*/ + + +static int rt_hw_can_init(void) +{ + struct can_configure config; + config.baud_rate = CAN500kBaud; + config.msgboxsz = 30; + config.sndboxnumber = 1; + config.mode = RT_CAN_MODE_NORMAL; + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; + config.baud_rate_fd = BSP_FDCAN_BAUD_DATA_2M; + config.use_bit_timing = 0; // does not use the timing in config + +#ifdef RT_CAN_USING_HDR + config.maxhdr = 36; + FDCAN_FilterTypeDef sFilterConfig; + sFilterConfig.IdType = FDCAN_STANDARD_ID; + sFilterConfig.FilterIndex = 0; + sFilterConfig.FilterType = FDCAN_FILTER_MASK; + sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + sFilterConfig.FilterID1 = 0; + sFilterConfig.FilterID2 = 0; +#endif + +#ifdef BSP_USING_FDCAN1 +#if defined(BSP_FDCAN1_FRAME_CLASSIC) + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_CLASSIC; +#elif defined(BSP_FDCAN1_FRAME_FD) + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS; +#else + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_BRS; +#endif + +#ifdef RT_CAN_USING_HDR + st_DrvCan1.FilterConfig = sFilterConfig; +#endif + + st_DrvCan1.name = "can1"; + st_DrvCan1.fdcanHandle.Instance = FDCAN1; + st_DrvCan1.device.config = config; + + /* register FDCAN1 device */ + rt_hw_can_register(&st_DrvCan1.device, st_DrvCan1.name, &_can_ops, &st_DrvCan1); +#endif /* BSP_USING_FDCAN1 */ + +#ifdef BSP_USING_FDCAN2 +#if defined(BSP_FDCAN2_FRAME_CLASSIC) + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_CLASSIC; +#elif defined(BSP_FDCAN2_FRAME_FD) + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS; +#else + config.enable_canfd = BSP_FDCAN_FRAMEFORMAT_FD_BRS; +#endif + +#ifdef RT_CAN_USING_HDR + st_DrvCan2.FilterConfig = sFilterConfig; +#endif + st_DrvCan2.name = "can2"; + st_DrvCan2.fdcanHandle.Instance = FDCAN2; + st_DrvCan2.device.config = config; + + /* register FDCAN1 device */ + rt_hw_can_register(&st_DrvCan2.device, st_DrvCan2.name, &_can_ops, &st_DrvCan2); +#endif /* BSP_USING_FDCAN2 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_FDCAN1 || BSP_USING_FDCAN2 */ +#endif /* RT_USING_CAN */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c new file mode 100644 index 00000000000..704b106d202 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_gpio.c @@ -0,0 +1,829 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + * 2019-04-23 WillianChan Fix GPIO serial number disorder + * 2020-06-16 thread-liu add STM32MP1 + * 2020-09-01 thread-liu add GPIOZ + * 2020-09-18 geniusgogo optimization design pin-index algorithm + */ + +#include +#include "drv_gpio.h" + +#ifdef BSP_USING_GPIO + +#define PIN_NUM(port, no) (((((port)&0xFu) << 4) | ((no)&0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin)&0xFu)) + +#if defined(SOC_SERIES_STM32MP1) +#if defined(GPIOZ) +#define gpioz_port_base (175) /* PIN_STPORT_MAX * 16 - 16 */ +#define PIN_STPORT(pin) ((pin > gpioz_port_base) ? ((GPIO_TypeDef *)(GPIOZ_BASE)) : ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin))))) +#else +#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin)))) +#endif /* GPIOZ */ +#else +#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) +#endif /* SOC_SERIES_STM32MP1 */ + +#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +#if defined(GPIOZ) +#define __STM32_PORT_MAX 16u +#elif defined(GPIOP) +#define __STM32_PORT_MAX 15u +#elif defined(GPIOO) +#define __STM32_PORT_MAX 14u +#elif defined(GPION) +#define __STM32_PORT_MAX 13u +#elif defined(GPIOM) +#define __STM32_PORT_MAX 12u +#elif defined(GPIOK) +#define __STM32_PORT_MAX 11u +#elif defined(GPIOJ) +#define __STM32_PORT_MAX 10u +#elif defined(GPIOI) +#define __STM32_PORT_MAX 9u +#elif defined(GPIOH) +#define __STM32_PORT_MAX 8u +#elif defined(GPIOG) +#define __STM32_PORT_MAX 7u +#elif defined(GPIOF) +#define __STM32_PORT_MAX 6u +#elif defined(GPIOE) +#define __STM32_PORT_MAX 5u +#elif defined(GPIOD) +#define __STM32_PORT_MAX 4u +#elif defined(GPIOC) +#define __STM32_PORT_MAX 3u +#elif defined(GPIOB) +#define __STM32_PORT_MAX 2u +#elif defined(GPIOA) +#define __STM32_PORT_MAX 1u +#else +#define __STM32_PORT_MAX 0u +#error Unsupported STM32 GPIO peripheral. +#endif + +#define PIN_STPORT_MAX __STM32_PORT_MAX + +static const struct pin_irq_map pin_irq_map[] = +{ +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) + {GPIO_PIN_0, EXTI0_1_IRQn}, + {GPIO_PIN_1, EXTI0_1_IRQn}, + {GPIO_PIN_2, EXTI2_3_IRQn}, + {GPIO_PIN_3, EXTI2_3_IRQn}, + {GPIO_PIN_4, EXTI4_15_IRQn}, + {GPIO_PIN_5, EXTI4_15_IRQn}, + {GPIO_PIN_6, EXTI4_15_IRQn}, + {GPIO_PIN_7, EXTI4_15_IRQn}, + {GPIO_PIN_8, EXTI4_15_IRQn}, + {GPIO_PIN_9, EXTI4_15_IRQn}, + {GPIO_PIN_10, EXTI4_15_IRQn}, + {GPIO_PIN_11, EXTI4_15_IRQn}, + {GPIO_PIN_12, EXTI4_15_IRQn}, + {GPIO_PIN_13, EXTI4_15_IRQn}, + {GPIO_PIN_14, EXTI4_15_IRQn}, + {GPIO_PIN_15, EXTI4_15_IRQn}, +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) \ + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_IRQn}, + {GPIO_PIN_6, EXTI6_IRQn}, + {GPIO_PIN_7, EXTI7_IRQn}, + {GPIO_PIN_8, EXTI8_IRQn}, + {GPIO_PIN_9, EXTI9_IRQn}, + {GPIO_PIN_10, EXTI10_IRQn}, + {GPIO_PIN_11, EXTI11_IRQn}, + {GPIO_PIN_12, EXTI12_IRQn}, + {GPIO_PIN_13, EXTI13_IRQn}, + {GPIO_PIN_14, EXTI14_IRQn}, + {GPIO_PIN_15, EXTI15_IRQn}, +#elif defined(SOC_SERIES_STM32F3) + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_TSC_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +#else + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +#endif +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) + +/* e.g. PE.7 */ +static rt_base_t stm32_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) + { + goto out; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + goto out; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + goto out; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; + +out: + rt_kprintf("Px.y x:A~Z y:0-15, e.g. PA.0\n"); + return -RT_EINVAL; +} + +static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) + { + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + + HAL_GPIO_WritePin(gpio_port, gpio_pin, (GPIO_PinState)value); + } +} + +static rt_ssize_t stm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + GPIO_PinState state = GPIO_PIN_RESET; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) + { + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + state = HAL_GPIO_ReadPin(gpio_port, gpio_pin); + } + else + { + return -RT_EINVAL; + } + + return (state == GPIO_PIN_RESET) ? PIN_LOW : PIN_HIGH; +} + +static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = PIN_STPIN(pin); + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_int32_t i; + for (i = 0; i < 32; i++) + { + if (((rt_uint32_t)0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = PIN_STPIN(pin); + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; + break; + } + HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct); + + HAL_NVIC_SetPriority(irqmap->irqno, 5, 0); + HAL_NVIC_EnableIRQ(irqmap->irqno); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(PIN_STPIN(pin)); + if (irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + HAL_GPIO_DeInit(PIN_STPORT(pin), PIN_STPIN(pin)); + + pin_irq_enable_mask &= ~irqmap->pinbit; +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) + if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1))) + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3))) + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } +#else + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + HAL_NVIC_DisableIRQ(irqmap->irqno); + } +#endif + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +static const struct rt_pin_ops _stm32_pin_ops = +{ + stm32_pin_mode, + stm32_pin_write, + stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_dettach_irq, + stm32_pin_irq_enable, + stm32_pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} + +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} +#else +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} +#endif + +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32L0) +void EXTI0_1_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + rt_interrupt_leave(); +} + +void EXTI2_3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + rt_interrupt_leave(); +} +void EXTI4_15_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS) +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0); + rt_interrupt_leave(); +} + +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + rt_interrupt_leave(); +} + +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2); + rt_interrupt_leave(); +} + +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + rt_interrupt_leave(); +} + +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); + rt_interrupt_leave(); +} + +void EXTI5_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); + rt_interrupt_leave(); +} + +void EXTI6_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); + rt_interrupt_leave(); +} + +void EXTI7_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); + rt_interrupt_leave(); +} + +void EXTI8_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + rt_interrupt_leave(); +} + +void EXTI9_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); + rt_interrupt_leave(); +} + +void EXTI10_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); + rt_interrupt_leave(); +} + +void EXTI11_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + rt_interrupt_leave(); +} + +void EXTI12_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + rt_interrupt_leave(); +} + +void EXTI13_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + rt_interrupt_leave(); +} + +void EXTI14_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); + rt_interrupt_leave(); +} + +void EXTI15_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#else + +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0); + rt_interrupt_leave(); +} + +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + rt_interrupt_leave(); +} + +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2); + rt_interrupt_leave(); +} + +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + rt_interrupt_leave(); +} + +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); + rt_interrupt_leave(); +} + +void EXTI9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); + rt_interrupt_leave(); +} + +void EXTI15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); + rt_interrupt_leave(); +} +#endif + +int rt_hw_pin_init(void) +{ +#if defined(__HAL_RCC_GPIOA_CLK_ENABLE) + __HAL_RCC_GPIOA_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOB_CLK_ENABLE) + __HAL_RCC_GPIOB_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOC_CLK_ENABLE) + __HAL_RCC_GPIOC_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOD_CLK_ENABLE) + __HAL_RCC_GPIOD_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOE_CLK_ENABLE) + __HAL_RCC_GPIOE_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOF_CLK_ENABLE) + __HAL_RCC_GPIOF_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOG_CLK_ENABLE) +#ifdef SOC_SERIES_STM32L4 + HAL_PWREx_EnableVddIO2(); +#endif + __HAL_RCC_GPIOG_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOH_CLK_ENABLE) + __HAL_RCC_GPIOH_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOI_CLK_ENABLE) + __HAL_RCC_GPIOI_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE) + __HAL_RCC_GPIOJ_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOK_CLK_ENABLE) + __HAL_RCC_GPIOK_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOM_CLK_ENABLE) + __HAL_RCC_GPIOM_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPION_CLK_ENABLE) + __HAL_RCC_GPION_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOO_CLK_ENABLE) + __HAL_RCC_GPIOO_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOP_CLK_ENABLE) + __HAL_RCC_GPIOP_CLK_ENABLE(); +#endif + + return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); +} + +#endif /* BSP_USING_GPIO */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c new file mode 100644 index 00000000000..a8a369dd17b --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_psram.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-24 yuanjie first version + */ + +#include +#include + +#ifdef BSP_USING_PSRAM +#include + +#define DRV_DEBUG +#define LOG_TAG "drv.psram" +#include + +#ifdef RT_USING_MEMHEAP_AS_HEAP +struct rt_memheap system_heap; +#endif + +static int PSRAM_Init(void) +{ + LOG_D("hyperram init success, mapped at 0x%X, size is %d bytes, data width is %d", PSRAM_BANK_ADDR, PSRAM_SIZE, PSRAM_DATA_WIDTH); +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "hyperram", (void *)PSRAM_BANK_ADDR, PSRAM_SIZE); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(PSRAM_Init); + +// #ifdef DRV_DEBUG +#if (defined(FINSH_USING_MSH) && defined(BSP_USING_PSRAM_TEST)) +int psram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if PSRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; +#elif PSRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; +#else + char data_width = 4; + uint32_t data = 0; +#endif + + /* write data */ + LOG_D("Writing the %ld bytes data, waiting....", PSRAM_SIZE); + start_time = rt_tick_get(); + for (i = 0; i < PSRAM_SIZE / data_width; i++) + { +#if PSRAM_DATA_WIDTH == 8 + *(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint8_t)0x5A; +#elif PSRAM_DATA_WIDTH == 16 + *(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5AA5; +#else + *(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width) = (uint32_t)0x5AA55AA5; +#endif + } + time_cast = rt_tick_get() - start_time; + LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND, + time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000)); + + /* read data */ + LOG_D("start Reading and verifying data, waiting...."); + for (i = 0; i < PSRAM_SIZE / data_width; i++) + { +#if PSRAM_DATA_WIDTH == 8 + data = *(__IO uint8_t *)(PSRAM_BANK_ADDR + i * data_width); + if (data != 0x5A) + { + LOG_E("PSRAM test failed!"); + break; + } +#elif PSRAM_DATA_WIDTH == 16 + data = *(__IO uint16_t *)(PSRAM_BANK_ADDR + i * data_width); + if (data != 0x5AA5) + { + LOG_E("PSRAM test failed!"); + break; + } +#else + data = *(__IO uint32_t *)(PSRAM_BANK_ADDR + i * data_width); + if (data != 0x5AA55AA5) + { + LOG_E("PSRAM test failed!"); + break; + } +#endif + } + + if (i >= PSRAM_SIZE / data_width) + { + LOG_D("PSRAM test success!"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(psram_test, psram test) +#endif /* FINSH_USING_MSH */ +#endif /* BSP_USING_PSRAM */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c new file mode 100644 index 00000000000..8016d4086e0 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_sdmmc.c @@ -0,0 +1,742 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-30 Evlers first version + */ + +#include "board.h" + +#ifdef RT_USING_SDIO + +#if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2) + #error "Please define at least one BSP_USING_SDIOx" +#endif + +#include "drv_sdmmc.h" + +#define DBG_TAG "drv.sdmmc" +#ifdef DRV_DEBUG + #define DBG_LVL DBG_LOG +#else + #define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include + +static struct rt_mmcsd_host *host1; +static struct rt_mmcsd_host *host2; + +#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000) + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct stm32_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + rt_uint8_t *cache_buf; + struct sdio_pkg *pkg; +}; + +#ifdef BSP_USING_SDIO1 +rt_align(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf1[SDIO_BUFF_SIZE]; +#endif + +#ifdef BSP_USING_SDIO2 +rt_align(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf2[SDIO_BUFF_SIZE]; +#endif + +/** + * @brief This function get order from sdio. + * @param data + * @retval sdio order + */ +static int get_order(rt_uint32_t data) +{ + int order = 0; + + switch (data) + { + case 1: + order = 0; + break; + + case 2: + order = 1; + break; + + case 4: + order = 2; + break; + + case 8: + order = 3; + break; + + case 16: + order = 4; + break; + + case 32: + order = 5; + break; + + case 64: + order = 6; + break; + + case 128: + order = 7; + break; + + case 256: + order = 8; + break; + + case 512: + order = 9; + break; + + case 1024: + order = 10; + break; + + case 2048: + order = 11; + break; + + case 4096: + order = 12; + break; + + case 8192: + order = 13; + break; + + case 16384: + order = 14; + break; + + default : + order = 0; + break; + } + + return order; +} + +/** + * @brief This function wait sdio cmd completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(5000), &status) != RT_EOK) + { + LOG_E("wait cmd completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + /* Get Card Specific Data */ + cmd->resp[0] = hsd->RESP1; + if (resp_type(cmd) == RESP_R2) + { + cmd->resp[1] = hsd->RESP2; + cmd->resp[2] = hsd->RESP3; + cmd->resp[3] = hsd->RESP4; + } + /* Check for error conditions */ + if (status & SDIO_ERRORS) + { + if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + } + else + { + cmd->err = RT_EOK; + } + + if (status & SDMMC_IT_CTIMEOUT) + { + cmd->err = -RT_ETIMEOUT; + } + if (status & SDMMC_IT_DCRCFAIL) + { + data->err = -RT_ERROR; + } + + if (status & SDMMC_IT_DTIMEOUT) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status & SDMMC_STA_CCRCFAIL ? "CCRCFAIL " : "", + status & SDMMC_STA_DCRCFAIL ? "DCRCFAIL " : "", + status & SDMMC_STA_CTIMEOUT ? "CTIMEOUT " : "", + status & SDMMC_STA_DTIMEOUT ? "DTIMEOUT " : "", + status & SDMMC_STA_TXUNDERR ? "TXUNDERR " : "", + status & SDMMC_STA_RXOVERR ? "RXOVERR " : "", + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance; + rt_uint32_t reg_cmd; + + rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL); + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0 + ); + + /* open irq */ + __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDIO_MASKR_ALL); + reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN; + + /* data pre configuration */ + if (data != RT_NULL) + { + if (data->flags & DATA_DIR_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)sdio->cache_buf, data->blks * data->blksize); + } + else + { + SCB_InvalidateDCache_by_Addr((uint32_t*)sdio->cache_buf, data->blks * data->blksize + 32); + } + + reg_cmd |= SDMMC_CMD_CMDTRANS; + __HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE); + hsd->DTIMER = HW_SDIO_DATATIMEOUT; + hsd->DLEN = data->blks * data->blksize; + hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0) | \ + (data->flags & DATA_STREAM ? SDMMC_DCTRL_DTMODE_0 : 0); + hsd->IDMABASER = (rt_uint32_t)sdio->cache_buf; + hsd->IDMACTRL = SDMMC_IDMA_IDMAEN; + } + /* config cmd reg */ + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= SDMMC_RESPONSE_NO; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= SDMMC_RESPONSE_LONG; + else + reg_cmd |= SDMMC_RESPONSE_SHORT; + + hsd->ARG = cmd->arg; + hsd->CMD = reg_cmd; + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* Waiting for data to be sent to completion */ + if (data != RT_NULL) + { + volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS; + + while (count && (hsd->STA & SDMMC_STA_DPSMACT)) + { + count--; + } + + if ((count == 0) || (hsd->STA & SDIO_ERRORS)) + { + cmd->err = -RT_ERROR; + } + } + + /* data post configuration */ + if (data != RT_NULL) + { + if (data->flags & DATA_DIR_READ) + { + SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)sdio->cache_buf & ~(32U - 1U)), data->blks * data->blksize + 32U); + rt_memcpy(data->buf, sdio->cache_buf, data->blks * data->blksize); + } + } +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + if (data->flags & DATA_DIR_WRITE) + { + rt_memcpy(sdio->cache_buf, data->buf, size); + } + } + + rthw_sdio_send_command(sdio, &pkg); + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + SD_HandleTypeDef *hsd = &sdio->sdio_des.hw_sdio; + SDMMC_InitTypeDef Init = {0}; + rt_uint32_t sdmmc_clk = sdio->sdio_des.clk_get(); + + if (sdmmc_clk < SD_INIT_FREQ) + { + LOG_E("The clock rate is too low! rata:%d", sdmmc_clk); + return; + } + + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk > sdmmc_clk) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = sdmmc_clk; + } + + LOG_D("clk:%dK width:%s%s%s power:%s%s%s", + clk / 1000, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : "" + ); + + if (sdmmc_clk != 0U) + { + hsd->Init.ClockDiv = sdmmc_clk / (2U * clk); + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + Init.BusWide = SDMMC_BUS_WIDE_4B; + } + else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + Init.BusWide = SDMMC_BUS_WIDE_8B; + } + else + { + Init.BusWide = SDMMC_BUS_WIDE_1B; + } + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + //CARD_ULTRA_HIGH_SPEED :UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01 + else if (MMCSD_TIMING_UHS_SDR50 <= io_cfg->timing && io_cfg->timing <= MMCSD_TIMING_UHS_DDR50) + { + /* UltraHigh speed SD card,user Clock div */ + Init.ClockDiv = hsd->Init.ClockDiv; + } + //CARD_HIGH_SPEED: High Speed Card <25Mo/s , Spec version 2.00 + else if (io_cfg->timing == MMCSD_TIMING_SD_HS) + { + /* High speed SD card, Max Frequency = 50Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + //CARD_NORMAL_SPEED: Normal Speed Card <12.5Mo/s , Spec Version 1.01 + else if (io_cfg->timing == MMCSD_TIMING_LEGACY) + { + /* No High speed SD card, Max Frequency = 25Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + (void)SDMMC_Init(hsd->Instance, Init); + } + switch ((io_cfg->power_mode)&0X03) + { + case MMCSD_POWER_OFF: + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsd->Instance); + break; + case MMCSD_POWER_UP: + /* In F4 series chips, 0X01 is reserved bit and has no practical effect. + For F7 series chips, 0X01 is power-on after power-off,The SDMMC disables the function and the card clock stops. + For H7 series chips, 0X03 is the power-on function. + */ + case MMCSD_POWER_ON: + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsd->Instance); + break; + default: + LOG_W("unknown power mode %d", io_cfg->power_mode); + break; + } +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + + if (enable) + { + LOG_D("enable sdio irq"); + __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT); + } + else + { + LOG_D("disable sdio irq"); + __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT); + } +} + +/** + * @brief This function detect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + struct rthw_sdio *sdio = host->private_data; + rt_uint32_t intstatus = sdio->sdio_des.hw_sdio.Instance->STA; + + /* clear irq flag*/ + __HAL_SD_CLEAR_FLAG(&sdio->sdio_des.hw_sdio, intstatus); + rt_event_send(&sdio->event, intstatus); +} + +static const struct rt_mmcsd_host_ops ops = +{ + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sd_detect, + rthw_sdio_irq_update, +}; + +/** + * @brief This function create mmcsd host. + * @param sdio_des stm32_sdio_des + * @retval rt_mmcsd_host + */ +struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if (sdio_des == RT_NULL) + { + LOG_E("L:%d F:%s",(sdio_des == RT_NULL ? "sdio_des is NULL" : "")); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); +#ifdef BSP_USING_SDIO1 + if(sdio_des->hw_sdio.Instance == SDMMC1) + { + sdio->cache_buf = cache_buf1; + rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_PRIO); + } +#endif /* BSP_USING_SDIO1 */ +#ifdef BSP_USING_SDIO2 + if(sdio_des->hw_sdio.Instance == SDMMC2) + { + sdio->cache_buf = cache_buf2; + rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_PRIO); + } +#endif /* BSP_USING_SDIO2 */ + + /* set host default attributes */ + host->ops = &ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */ + +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +/** + * @brief This function get stm32 sdio clock. + * @param hw_sdio: stm32_sdio + * @retval PCLK2Freq + */ +static rt_uint32_t stm32_sdio_clock_get(void) +{ + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12); +} + +void SDMMC1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host1); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void SDMMC2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host2); + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ +#ifdef BSP_USING_SDIO1 + struct stm32_sdio_des sdio_des1 = {0}; + sdio_des1.hw_sdio.Instance = SDMMC1; + + HAL_SD_MspInit(&sdio_des1.hw_sdio); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDMMC1_IRQn); + + sdio_des1.clk_get = stm32_sdio_clock_get; + + host1 = sdio_host_create(&sdio_des1); + + if (host1 == RT_NULL) + { + LOG_E("host1 create fail"); + return -RT_ERROR; + } +#endif /* BSP_USING_SDIO1 */ + +#ifdef BSP_USING_SDIO2 + struct stm32_sdio_des sdio_des2 = {0}; + sdio_des2.hw_sdio.Instance = SDMMC2; + + HAL_SD_MspInit(&sdio_des2.hw_sdio); + HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDMMC2_IRQn); + + sdio_des2.clk_get = stm32_sdio_clock_get; + + host2 = sdio_host_create(&sdio_des2); + + if (host2 == RT_NULL) + { + LOG_E("host2 create fail"); + return -RT_ERROR; + } +#endif /* BSP_USING_SDIO2 */ + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +void stm32_mmcsd_change(void) +{ +#ifdef BSP_USING_SDIO1 + mmcsd_change(host1); +#endif /* BSP_USING_SDIO2 */ +#ifdef BSP_USING_SDIO2 + mmcsd_change(host2); +#endif /* BSP_USING_SDIO2 */ +} + +#endif /* RT_USING_SDIO */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c new file mode 100644 index 00000000000..b5e8473a9f1 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_soft_i2c.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-08 balanceTWK first version + */ + +#include +#include "drv_soft_i2c.h" +#include "drv_config.h" +#include +#include + +#ifdef RT_USING_I2C + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) +#error "Please define at least one BSP_USING_I2Cx" +#endif + +static const struct stm32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +}; + +static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/** + * This function initializes the i2c pin. + * + * @param Stm32 i2c dirver class. + */ +static void stm32_i2c_gpio_init(struct stm32_i2c *i2c) +{ + struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param Stm32 config class. + * @param The sda pin state. + */ +static void stm32_set_sda(void *data, rt_int32_t state) +{ + struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param Stm32 config class. + * @param The scl pin state. + */ +static void stm32_set_scl(void *data, rt_int32_t state) +{ + struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t stm32_get_sda(void *data) +{ + struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data; + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t stm32_get_scl(void *data) +{ + struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data; + return rt_pin_read(cfg->scl); +} +/** + * The time delay function. + * + * @param microseconds. + */ +static void stm32_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops stm32_bit_ops_default = +{ + .data = RT_NULL, + .set_sda = stm32_set_sda, + .set_scl = stm32_set_scl, + .get_sda = stm32_get_sda, + .get_scl = stm32_get_scl, + .udelay = stm32_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/** + * if i2c is locked, this function will unlock it + * + * @param stm32 config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t stm32_i2c_bus_unlock(const struct stm32_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + stm32_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + stm32_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct stm32_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = stm32_bit_ops_default; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops; + stm32_i2c_gpio_init(&i2c_obj[i]); + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + stm32_i2c_bus_unlock(&soft_i2c_config[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, + soft_i2c_config[i].sda); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c new file mode 100644 index 00000000000..cc9ad0448b4 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart.c @@ -0,0 +1,1294 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2020-03-16 SummerGift add device close feature + * 2020-03-20 SummerGift fix bug caused by ORE + * 2020-05-02 whj4674672 support stm32h7 uart dma + * 2020-09-09 forest-rain support stm32wl uart + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +#include "board.h" +#include "drv_usart.h" +#include "drv_config.h" + +#ifdef RT_USING_SERIAL + +//#define DRV_DEBUG +#define LOG_TAG "drv.usart" +#include + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +#ifdef RT_SERIAL_USING_DMA +static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +/* Number of while blocking timeouts for the stm32_putc */ +#define TX_BLOCK_TIMEOUT 0x0FFFFFFF + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +}; + +static struct stm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif +#ifdef BSP_USING_UART6 + UART6_CONFIG, +#endif +#ifdef BSP_USING_UART7 + UART7_CONFIG, +#endif +#ifdef BSP_USING_UART8 + UART8_CONFIG, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_CONFIG, +#endif +}; + +static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) +{ + rt_uint32_t mask = 0x00FFU; + if (word_length == UART_WORDLENGTH_8B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x00FFU ; + } + else + { + mask = 0x007FU ; + } + } +#ifdef UART_WORDLENGTH_9B + else if (word_length == UART_WORDLENGTH_9B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x01FFU ; + } + else + { + mask = 0x00FFU ; + } + } +#endif +#ifdef UART_WORDLENGTH_7B + else if (word_length == UART_WORDLENGTH_7B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x007FU ; + } + else + { + mask = 0x003FU ; + } + } + else + { + mask = 0x0000U; + } +#endif + return mask; +} + +static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + uart->handle.Instance = uart->config->Instance; + uart->handle.Init.BaudRate = cfg->baud_rate; + uart->handle.Init.Mode = UART_MODE_TX_RX; +#ifdef USART_CR1_OVER8 + uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16; +#else + uart->handle.Init.OverSampling = UART_OVERSAMPLING_16; +#endif /* USART_CR1_OVER8 */ + + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; + break; + default: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + else + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + break; + default: + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->handle.Init.StopBits = UART_STOPBITS_2; + break; + default: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + uart->handle.Init.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->handle.Init.Parity = UART_PARITY_EVEN; + break; + default: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + } + +#ifdef RT_SERIAL_USING_DMA + if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) { + uart->dma_rx.remaining_cnt = cfg->bufsz; + } +#endif + + if (HAL_UART_Init(&uart->handle) != HAL_OK) + { + return -RT_ERROR; + } + uart->DR_mask = stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity); + uart->tx_block_timeout = TX_BLOCK_TIMEOUT; + + return RT_EOK; +} + +static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct stm32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + { + /* disable uart irq */ + NVIC_DisableIRQ(uart->config->irq_type); + rt_uint32_t direction = (rt_uint32_t)arg; + if(direction == RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); + } + +#ifdef RT_SERIAL_USING_DMA + /* disable DMA */ + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); + if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } + else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { + HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); + if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } +#endif + break; + } + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + { + /* enable uart irq */ + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + rt_uint32_t direction = (rt_uint32_t)arg; + if(direction == RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE); + } + break; + } + +#ifdef RT_SERIAL_USING_DMA + case RT_DEVICE_CTRL_CONFIG: + { + stm32_dma_config(serial, ctrl_arg); + break; + } +#endif + + case RT_DEVICE_CTRL_CLOSE: + { + if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK ) + { + RT_ASSERT(0) + } + break; + } + + case UART_CTRL_SET_BLOCK_TIMEOUT: + { + rt_uint32_t block_timeout = (rt_uint32_t)arg; + if(block_timeout > 0) + { + uart->tx_block_timeout = block_timeout; + } + else + { + return -RT_ERROR; + } + break; + } + + default: + break; + } + return RT_EOK; +} + +static int stm32_putc(struct rt_serial_device *serial, char c) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + rt_uint32_t block_timeout = uart->tx_block_timeout; + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + uart->handle.Instance->TDR = c; +#else + uart->handle.Instance->DR = c; +#endif + while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET && --block_timeout); + return (block_timeout != 0) ? 1 : -1; +} + +static int stm32_getc(struct rt_serial_device *serial) +{ + int ch; + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + ch = -1; + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + { +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + ch = uart->handle.Instance->RDR & uart->DR_mask; +#else + ch = uart->handle.Instance->DR & uart->DR_mask; +#endif + } + return ch; +} + +static rt_ssize_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (size == 0) + { + return 0; + } + + if (RT_SERIAL_DMA_TX == direction) + { + if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK) + { + return size; + } + else + { + return 0; + } + } + return 0; +} + +#ifdef RT_SERIAL_USING_DMA +static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + struct stm32_uart *uart; + rt_base_t level; + rt_size_t recv_len, counter; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + level = rt_hw_interrupt_disable(); + recv_len = 0; + counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle)); + + switch (isr_flag) + { + case UART_RX_DMA_IT_IDLE_FLAG: + if (counter <= uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + else + recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_HT_FLAG: + if (counter < uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_TC_FLAG: + if(counter >= uart->dma_rx.remaining_cnt) + recv_len = serial->config.bufsz + uart->dma_rx.remaining_cnt - counter; + + default: + break; + } + + if (recv_len) + { + uart->dma_rx.remaining_cnt = counter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + rt_hw_interrupt_enable(level); + +} + +#endif + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + /* UART in mode Receiver -------------------------------------------------*/ + if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET)) + { + if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0) + { + HAL_UART_IRQHandler(&(uart->handle)); + } + else + { + /* Transmission complete interrupt disable ( CR1 Register) */ + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + } +#ifdef RT_SERIAL_USING_DMA + else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) + && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET)) + { + dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); + __HAL_UART_CLEAR_IDLEFLAG(&uart->handle); + } +#endif + else + { + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET) + { + __HAL_UART_CLEAR_OREFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET) + { + __HAL_UART_CLEAR_NEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET) + { + __HAL_UART_CLEAR_FEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET) + { + __HAL_UART_CLEAR_PEFLAG(&uart->handle); + } +#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ + && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ + && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \ + && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) +#ifdef SOC_SERIES_STM32F3 + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF); + } +#else + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD); + } +#endif +#endif + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE); + } + } +} + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void UART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) +void UART1_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void UART2_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) +void UART2_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void UART3_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) +void UART3_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */ +#endif /* BSP_USING_UART3*/ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void UART4_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ + +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) +void UART4_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */ +#endif /* BSP_USING_UART4*/ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void UART5_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) +void UART5_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */ +#endif /* BSP_USING_UART5*/ + +#if defined(BSP_USING_UART6) +void USART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) +void UART6_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) +void UART6_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */ +#endif /* BSP_USING_UART6*/ + +#if defined(BSP_USING_UART7) +void UART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART7_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) +void UART7_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) +void UART7_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */ +#endif /* BSP_USING_UART7*/ + +#if defined(BSP_USING_UART8) +void UART8_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART8_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) +void UART8_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) +void UART8_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */ +#endif /* BSP_USING_UART8*/ + +#if defined(BSP_USING_LPUART1) +void LPUART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[LPUART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) +void LPUART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */ +#endif /* BSP_USING_LPUART1*/ + +#if defined(SOC_SERIES_STM32G0) +#if defined(BSP_USING_UART2) +#if defined(STM32G0B1xx) || defined(STM32G0C1xx) +void USART2_LPUART2_IRQHandler(void) +{ + USART2_IRQHandler(); +} +#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */ +#endif /* defined(BSP_USING_UART2) */ +#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \ + || defined(BSP_USING_LPUART1) +#if defined(STM32G070xx) +void USART3_4_IRQHandler(void) +#elif defined(STM32G071xx) || defined(STM32G081xx) +void USART3_4_LPUART1_IRQHandler(void) +#elif defined(STM32G0B0xx) +void USART3_4_5_6_IRQHandler(void) +#elif defined(STM32G0B1xx) || defined(STM32G0C1xx) +void USART3_4_5_6_LPUART1_IRQHandler(void) +#endif /* defined(STM32G070xx) */ +{ +#if defined(BSP_USING_UART3) + USART3_IRQHandler(); +#endif +#if defined(BSP_USING_UART4) + UART4_IRQHandler(); +#endif +#if defined(BSP_USING_UART5) + UART5_IRQHandler(); +#endif +#if defined(BSP_USING_UART6) + USART6_IRQHandler(); +#endif +#if defined(BSP_USING_LPUART1) + LPUART1_IRQHandler(); +#endif +} +#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */ +#if defined(RT_SERIAL_USING_DMA) +void UART_DMA_RX_TX_IRQHandler(void) +{ +#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA) + UART1_DMA_TX_IRQHandler(); +#endif +#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA) + UART1_DMA_RX_IRQHandler(); +#endif +#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA) + UART2_DMA_TX_IRQHandler(); +#endif +#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA) + UART2_DMA_RX_IRQHandler(); +#endif +} +#endif /* defined(RT_SERIAL_USING_DMA) */ +#endif /* defined(SOC_SERIES_STM32G0) */ + +static void stm32_uart_get_dma_config(void) +{ +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART3 + uart_obj[UART3_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif +#ifdef BSP_UART3_TX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART4 + uart_obj[UART4_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif +#ifdef BSP_UART4_TX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART5 + uart_obj[UART5_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; +#endif +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; +#endif +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART8 + uart_obj[UART8_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART8_RX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; +#endif +#ifdef BSP_UART8_TX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; +#endif +#endif + +#ifdef BSP_USING_LPUART1 + uart_obj[LPUART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_LPUART1_RX_USING_DMA + uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; + uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx; +#endif +#endif +} + +#ifdef RT_SERIAL_USING_DMA +static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else /* RT_DEVICE_FLAG_DMA_TX == flag */ + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + LOG_D("%s dma config start", uart->config->name); + + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ + || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32MP1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); +#endif + +#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1) + /* enable DMAMUX clock for L4+ and G4 */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); +#elif defined(SOC_SERIES_STM32MP1) + __HAL_RCC_DMAMUX_CLK_ENABLE(); +#endif + + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle); + } + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) + DMA_Handle->Instance = dma_config->Instance; +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Channel = dma_config->channel; +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Request = dma_config->request; +#endif + DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE; + DMA_Handle->Init.MemInc = DMA_MINC_ENABLE; + DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; + DMA_Handle->Init.Mode = DMA_CIRCULAR; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; + DMA_Handle->Init.Mode = DMA_NORMAL; + } + + DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; +#endif + if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); + } + + /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ + HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(dma_config->dma_irq); + + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + + LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance); + LOG_D("%s dma config done", uart->config->name); +} + +/** + * @brief UART error callbacks + * @param huart: UART handle + * @note This example shows a simple way to report transfer error, and you can + * add your own implementation. + * @retval None + */ +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + RT_ASSERT(huart != NULL); + struct stm32_uart *uart = (struct stm32_uart *)huart; + LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode); + UNUSED(uart); +} + +/** + * @brief Rx Transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx transfer, and + * you can add your own implementation. + * @retval None + */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG); +} + +/** + * @brief Rx Half transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx Half transfer, + * and you can add your own implementation. + * @retval None + */ +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG); +} + +static void _dma_tx_complete(struct rt_serial_device *serial) +{ + struct stm32_uart *uart; + rt_size_t trans_total_index; + rt_base_t level; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + level = rt_hw_interrupt_disable(); + trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle)); + rt_hw_interrupt_enable(level); + + if (trans_total_index == 0) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * @brief HAL_UART_TxCpltCallback + * @param huart: UART handle + * @note This callback can be called by two functions, first in UART_EndTransmit_IT when + * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode. + * @retval None + */ +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + _dma_tx_complete(&uart->serial); +} +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops stm32_uart_ops = +{ + .configure = stm32_configure, + .control = stm32_control, + .putc = stm32_putc, + .getc = stm32_getc, + .dma_transmit = stm32_dma_transmit +}; + +int rt_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + stm32_uart_get_dma_config(); + + for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct stm32_uart); i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &stm32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c new file mode 100644 index 00000000000..0eed8aebc3d --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/drv_usart_v2.c @@ -0,0 +1,1363 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#include "board.h" +#include "drv_usart_v2.h" + +#ifdef RT_USING_SERIAL_V2 + +//#define DRV_DEBUG +#define DBG_TAG "drv.usart" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +#ifdef RT_SERIAL_USING_DMA + static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif + +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif + +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif + +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif + +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif + +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif + +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif + +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +}; + +static struct stm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif + +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif + +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif + +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif + +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif + +#ifdef BSP_USING_UART6 + UART6_CONFIG, +#endif + +#ifdef BSP_USING_UART7 + UART7_CONFIG, +#endif + +#ifdef BSP_USING_UART8 + UART8_CONFIG, +#endif + +#ifdef BSP_USING_LPUART1 + LPUART1_CONFIG, +#endif +}; + + +static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + uart->handle.Instance = uart->config->Instance; + uart->handle.Init.BaudRate = cfg->baud_rate; + uart->handle.Init.Mode = UART_MODE_TX_RX; +#ifdef USART_CR1_OVER8 + uart->handle.Init.OverSampling = cfg->baud_rate > 5000000 ? UART_OVERSAMPLING_8 : UART_OVERSAMPLING_16; +#else + uart->handle.Init.OverSampling = UART_OVERSAMPLING_16; +#endif /* USART_CR1_OVER8 */ + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + else + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + uart->handle.Init.WordLength = UART_WORDLENGTH_9B; + break; + default: + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->handle.Init.StopBits = UART_STOPBITS_2; + break; + default: + uart->handle.Init.StopBits = UART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + uart->handle.Init.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->handle.Init.Parity = UART_PARITY_EVEN; + break; + default: + uart->handle.Init.Parity = UART_PARITY_NONE; + break; + } + + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; + break; + default: + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + break; + } + +#ifdef RT_SERIAL_USING_DMA + uart->dma_rx.remaining_cnt = serial->config.rx_bufsz; +#endif + + if (HAL_UART_Init(&uart->handle) != HAL_OK) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct stm32_uart *uart; + + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } + else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + + NVIC_DisableIRQ(uart->config->irq_type); + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); + else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE); +#ifdef RT_SERIAL_USING_DMA + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE); + + HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); + if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } + else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); + + HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); + if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK) + { + RT_ASSERT(0); + } + } +#endif + break; + + case RT_DEVICE_CTRL_SET_INT: + + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE); + else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE); + break; + + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) + { + +#ifdef RT_SERIAL_USING_DMA + stm32_dma_config(serial, ctrl_arg); +#endif + } + else + stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg); + break; + + case RT_DEVICE_CHECK_OPTMODE: + { + if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) + return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + else + return RT_SERIAL_TX_BLOCKING_BUFFER; + } + case RT_DEVICE_CTRL_CLOSE: + if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK ) + { + RT_ASSERT(0) + } + break; + + } + return RT_EOK; +} + +static int stm32_putc(struct rt_serial_device *serial, char c) +{ + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct stm32_uart, serial); + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + UART_SET_TDR(&uart->handle, c); + while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET); + + return 1; +} + +rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) +{ + rt_uint32_t mask = 0; + if (word_length == UART_WORDLENGTH_8B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x00FFU ; + } + else + { + mask = 0x007FU ; + } + } +#ifdef UART_WORDLENGTH_9B + else if (word_length == UART_WORDLENGTH_9B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x01FFU ; + } + else + { + mask = 0x00FFU ; + } + } +#endif +#ifdef UART_WORDLENGTH_7B + else if (word_length == UART_WORDLENGTH_7B) + { + if (parity == UART_PARITY_NONE) + { + mask = 0x007FU ; + } + else + { + mask = 0x003FU ; + } + } + else + { + mask = 0x0000U; + } +#endif + return mask; +} + +static int stm32_getc(struct rt_serial_device *serial) +{ + int ch; + struct stm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + ch = -1; + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + ch = UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity)); + return ch; +} + +static rt_ssize_t stm32_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) +{ + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + HAL_UART_Transmit_DMA(&uart->handle, buf, size); + return size; + } + + stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag); + + return size; +} + +#ifdef RT_SERIAL_USING_DMA +static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + struct stm32_uart *uart; + rt_size_t recv_len, counter; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + + recv_len = 0; + counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle)); + + if (counter <= uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + else + recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter; + if (recv_len) + { +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; + SCB_InvalidateDCache_by_Addr((uint32_t *)rx_fifo->buffer, serial->config.rx_bufsz); +#endif + uart->dma_rx.remaining_cnt = counter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} +#endif /* RT_SERIAL_USING_DMA */ + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct stm32_uart, serial); + /* If the Read data register is not empty and the RXNE interrupt is enabled (RDR) */ + if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET)) + { + struct rt_serial_rx_fifo *rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + rt_ringbuffer_putchar(&(rx_fifo->rb), UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity))); + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + /* If the Transmit data register is empty and the TXE interrupt enable is enabled (TDR) */ + else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE)) != RESET) + { + struct rt_serial_tx_fifo *tx_fifo; + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + rt_uint8_t put_char = 0; + if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char)) + { + UART_SET_TDR(&uart->handle, put_char); + } + else + { + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE); + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TC); + } + } + else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) && + (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + /* The HAL_UART_TxCpltCallback will be triggered */ + HAL_UART_IRQHandler(&(uart->handle)); + } + else + { + /* Transmission complete interrupt disable ( CR1 Register) */ + __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + /* Clear Transmission complete interrupt flag ( ISR Register ) */ + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + } + +#ifdef RT_SERIAL_USING_DMA + else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) + && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET)) + { + dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); + __HAL_UART_CLEAR_IDLEFLAG(&uart->handle); + } +#endif + else + { + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET) + { + LOG_E("(%s) serial device Overrun error!", serial->parent.parent.name); + __HAL_UART_CLEAR_OREFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET) + { + __HAL_UART_CLEAR_NEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET) + { + __HAL_UART_CLEAR_FEFLAG(&uart->handle); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET) + { + __HAL_UART_CLEAR_PEFLAG(&uart->handle); + } +#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ + && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32H7RS) \ + && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD); + } +#endif + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC); + } + if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) + { + UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE); + } + } +} + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void UART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) +void UART1_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void UART2_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) +void UART2_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void UART3_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) +void UART3_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */ +#endif /* BSP_USING_UART3*/ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void UART4_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ + +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) +void UART4_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */ +#endif /* BSP_USING_UART4*/ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void UART5_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) +void UART5_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */ +#endif /* BSP_USING_UART5*/ + +#if defined(BSP_USING_UART6) +void USART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) +void UART6_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) +void UART6_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */ +#endif /* BSP_USING_UART6*/ + +#if defined(BSP_USING_UART7) +void UART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART7_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) +void UART7_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) +void UART7_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */ +#endif /* BSP_USING_UART7*/ + +#if defined(BSP_USING_UART8) +void UART8_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART8_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) +void UART8_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) +void UART8_DMA_TX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */ +#endif /* BSP_USING_UART8*/ + +#if defined(BSP_USING_LPUART1) +void LPUART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[LPUART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) +void LPUART1_DMA_RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */ +#endif /* BSP_USING_LPUART1*/ + +#if defined(SOC_SERIES_STM32G0) +#if defined(BSP_USING_UART2) +#if defined(STM32G0B1xx) || defined(STM32G0C1xx) +void USART2_LPUART2_IRQHandler(void) +{ + USART2_IRQHandler(); +} +#endif /* defined(STM32G0B1xx) || defined(STM32G0C1xx) */ +#endif /* defined(BSP_USING_UART2) */ +#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) \ + || defined(BSP_USING_LPUART1) +#if defined(STM32G070xx) +void USART3_4_IRQHandler(void) +#elif defined(STM32G071xx) || defined(STM32G081xx) +void USART3_4_LPUART1_IRQHandler(void) +#elif defined(STM32G0B0xx) +void USART3_4_5_6_IRQHandler(void) +#elif defined(STM32G0B1xx) || defined(STM32G0C1xx) +void USART3_4_5_6_LPUART1_IRQHandler(void) +#endif /* defined(STM32G070xx) */ +{ +#if defined(BSP_USING_UART3) + USART3_IRQHandler(); +#endif +#if defined(BSP_USING_UART4) + UART4_IRQHandler(); +#endif +#if defined(BSP_USING_UART5) + UART5_IRQHandler(); +#endif +#if defined(BSP_USING_UART6) + USART6_IRQHandler(); +#endif +#if defined(BSP_USING_LPUART1) + LPUART1_IRQHandler(); +#endif +} +#endif /* defined(BSP_USING_UART3) || defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) */ +#if defined(RT_SERIAL_USING_DMA) +void UART_DMA_RX_TX_IRQHandler(void) +{ +#if defined(BSP_USING_UART1) && defined(BSP_UART1_TX_USING_DMA) + UART1_DMA_TX_IRQHandler(); +#endif +#if defined(BSP_USING_UART1) && defined(BSP_UART1_RX_USING_DMA) + UART1_DMA_RX_IRQHandler(); +#endif +#if defined(BSP_USING_UART2) && defined(BSP_UART2_TX_USING_DMA) + UART2_DMA_TX_IRQHandler(); +#endif +#if defined(BSP_USING_UART2) && defined(BSP_UART2_RX_USING_DMA) + UART2_DMA_RX_IRQHandler(); +#endif +} +#endif /* defined(RT_SERIAL_USING_DMA) */ +#endif /* defined(SOC_SERIES_STM32G0) */ + +static void stm32_uart_get_config(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].serial.config = config; + uart_obj[UART1_INDEX].uart_dma_flag = 0; + + uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE; + uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE; + +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif + +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].serial.config = config; + uart_obj[UART2_INDEX].uart_dma_flag = 0; + + uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE; + uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE; + +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif + +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART3 + uart_obj[UART3_INDEX].serial.config = config; + uart_obj[UART3_INDEX].uart_dma_flag = 0; + + uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE; + uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE; + +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif + +#ifdef BSP_UART3_TX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART4 + uart_obj[UART4_INDEX].serial.config = config; + uart_obj[UART4_INDEX].uart_dma_flag = 0; + + uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE; + uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE; + +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif + +#ifdef BSP_UART4_TX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART5 + uart_obj[UART5_INDEX].serial.config = config; + uart_obj[UART5_INDEX].uart_dma_flag = 0; + + uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE; + uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE; + +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif + +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].serial.config = config; + uart_obj[UART6_INDEX].uart_dma_flag = 0; + + uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE; + uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE; + +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; +#endif + +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].serial.config = config; + uart_obj[UART7_INDEX].uart_dma_flag = 0; + + uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE; + uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE; + +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; +#endif + +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART8 + uart_obj[UART8_INDEX].serial.config = config; + uart_obj[UART8_INDEX].uart_dma_flag = 0; + + uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE; + uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE; + +#ifdef BSP_UART8_RX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; +#endif + +#ifdef BSP_UART8_TX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; +#endif +#endif + +#ifdef BSP_USING_LPUART1 + uart_obj[LPUART1_INDEX].serial.config = config; + uart_obj[LPUART1_INDEX].uart_dma_flag = 0; + + uart_obj[LPUART1_INDEX].serial.config.rx_bufsz = BSP_LPUART1_RX_BUFSIZE; + uart_obj[LPUART1_INDEX].serial.config.tx_bufsz = BSP_LPUART1_TX_BUFSIZE; + +#ifdef BSP_LPUART1_RX_USING_DMA + uart_obj[LPUART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG; + uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx; +#endif +#endif +} + +#ifdef RT_SERIAL_USING_DMA +static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct stm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); + uart = rt_container_of(serial, struct stm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else /* RT_DEVICE_FLAG_DMA_TX == flag */ + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + LOG_D("%s dma config start", uart->config->name); + + { + rt_uint32_t tmpreg = 0x00U; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32L0) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHBENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ + || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32WB) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); +#elif defined(SOC_SERIES_STM32MP1) + /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ + SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); + tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc); +#endif + +#if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) + /* enable DMAMUX clock for L4+ and G4 */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); +#elif defined(SOC_SERIES_STM32MP1) + __HAL_RCC_DMAMUX_CLK_ENABLE(); +#endif + + UNUSED(tmpreg); /* To avoid compiler warnings */ + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle); + } + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) + DMA_Handle->Instance = dma_config->Instance; +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Channel = dma_config->channel; +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Request = dma_config->request; +#elif !defined(SOC_SERIES_STM32H7RS) + DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE; + DMA_Handle->Init.MemInc = DMA_MINC_ENABLE; + DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; + DMA_Handle->Init.Mode = DMA_CIRCULAR; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; + DMA_Handle->Init.Mode = DMA_NORMAL; + } + + DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM; +#endif + +#if defined(SOC_SERIES_STM32H7RS) + DMA_Handle->Instance = dma_config->Instance; + DMA_Handle->Init.Request = dma_config->request; + DMA_Handle->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST; + + DMA_Handle->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE; + DMA_Handle->Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE; + DMA_Handle->Init.Priority = DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_Handle->Init.SrcBurstLength = 1; + DMA_Handle->Init.DestBurstLength = 1; + DMA_Handle->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0; + DMA_Handle->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER; + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.SrcInc = DMA_SINC_FIXED; + DMA_Handle->Init.DestInc = DMA_DINC_INCREMENTED; + DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY; + DMA_Handle->Init.Mode = DMA_NORMAL; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.SrcInc = DMA_SINC_INCREMENTED; + DMA_Handle->Init.DestInc = DMA_DINC_FIXED; + DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH; + } +#endif /* SOC_SERIES_STM32F1 */ + +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) + DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE; +#endif + if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.rx_bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); + __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE); + } + + /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ + HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0); + HAL_NVIC_EnableIRQ(dma_config->dma_irq); + + HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + HAL_NVIC_EnableIRQ(uart->config->irq_type); + + LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance); + LOG_D("%s dma config done", uart->config->name); +} + +/** + * @brief UART error callbacks + * @param huart: UART handle + * @note This example shows a simple way to report transfer error, and you can + * add your own implementation. + * @retval None + */ +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + RT_ASSERT(huart != NULL); + struct stm32_uart *uart = (struct stm32_uart *)huart; + LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode); + UNUSED(uart); +} + +/** + * @brief Rx Transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx transfer, and + * you can add your own implementation. + * @retval None + */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG); +} + +/** + * @brief Rx Half transfer completed callback + * @param huart: UART handle + * @note This example shows a simple way to report end of DMA Rx Half transfer, + * and you can add your own implementation. + * @retval None + */ +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG); +} + +/** + * @brief HAL_UART_TxCpltCallback + * @param huart: UART handle + * @note This callback can be called by two functions, first in UART_EndTransmit_IT when + * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode. + * @retval None + */ +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + struct stm32_uart *uart; + struct rt_serial_device *serial; + rt_size_t trans_total_index; + rt_base_t level; + + RT_ASSERT(huart != NULL); + uart = (struct stm32_uart *)huart; + serial = &uart->serial; + RT_ASSERT(serial != RT_NULL); + + level = rt_hw_interrupt_disable(); + trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle)); + rt_hw_interrupt_enable(level); + + if (trans_total_index) return; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + +} +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops stm32_uart_ops = +{ + .configure = stm32_configure, + .control = stm32_control, + .putc = stm32_putc, + .getc = stm32_getc, + .transmit = stm32_transmit +}; + +int rt_hw_usart_init(void) +{ + rt_err_t result = 0; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart); + + stm32_uart_get_config(); + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &stm32_uart_ops; + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR, + NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL_V2 */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h b/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h new file mode 100644 index 00000000000..e70e7ad171d --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/fal_cfg.h @@ -0,0 +1,53 @@ +/* + * File : fal_cfg.h + * This file is part of FAL (Flash Abstraction Layer) package + * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-05-17 armink the first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define NOR_FLASH_DEV_NAME "norflash0" + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME, 0, 512*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "bt_image", NOR_FLASH_DEV_NAME, 512*1024, 512*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 1024*1024, 2*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 3*1024*1024, 1*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c b/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c new file mode 100644 index 00000000000..08644405175 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/filesystem.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + * 2019-06-11 WillianChan Add SD card hot plug detection + */ + +#include + +#ifdef BSP_USING_FS +#if DFS_FILESYSTEMS_MAX < 4 +#error "Please define DFS_FILESYSTEMS_MAX more than 4" +#endif +#if DFS_FILESYSTEM_TYPES_MAX < 4 +#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" +#endif + +#ifdef BSP_USING_SPI_FLASH_FS +#include "fal.h" +#endif + +#include +#include "dfs_romfs.h" +#include "drv_sdmmc.h" + +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include + +static const struct romfs_dirent _romfs_root[] = { + {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}}; + +const struct romfs_dirent romfs_root = { + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])}; + +#ifdef BSP_USING_SDCARD_FS + +/* SD Card hot plug detection pin */ +#define SD_CHECK_PIN GET_PIN(F, 2) + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find("sd0"); + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + stm32_mmcsd_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + device = rt_device_find("sd0"); + } + if (device != RT_NULL) + { + if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/sdcard'"); + } + else + { + LOG_W("sd card mount to '/sdcard' failed!"); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount("/sdcard"); + LOG_I("Unmount \"/sdcard\""); + + mmcsd_wait_cd_changed(0); + stm32_mmcsd_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); +} + +static void sd_mount(void *parameter) +{ + rt_uint8_t re_sd_check_pin = 1; + rt_thread_mdelay(200); + if (rt_pin_read(SD_CHECK_PIN)) + { + _sdcard_mount(); + } + while (1) + { + rt_thread_mdelay(200); + if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0) + { + _sdcard_mount(); + } + + if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0) + { + _sdcard_unmount(); + } + } +} + +#endif /* BSP_USING_SDCARD_FS */ + +int mount_init(void) +{ + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0) + { + LOG_E("rom mount to '/' failed!"); + } +#ifdef BSP_USING_SPI_FLASH_FS + struct rt_device *flash_dev = RT_NULL; + +#ifndef RT_USING_WIFI + fal_init(); +#endif + + flash_dev = fal_mtd_nor_device_create("filesystem"); + + if (flash_dev) + { + //mount filesystem + if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0) + { + LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name); + dfs_mkfs("lfs", flash_dev->parent.name); + if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0) + { + LOG_I("mount to '/flash' success!"); + } + } + else + { + LOG_I("mount to '/flash' success!"); + } + } + else + { + LOG_E("Can't create block device filesystem or bt_image partition."); + } + +#endif + +#ifdef BSP_USING_SDCARD_FS + rt_thread_t tid; + + rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP); + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } +#endif + return RT_EOK; +} +INIT_APP_EXPORT(mount_init); + +#endif /* BSP_USING_FS */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h new file mode 100644 index 00000000000..69095851e9b --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/dma_config.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* GPDMA1_Channel2 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler GPDMA1_Channel2_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN +#define UART1_RX_DMA_INSTANCE GPDMA1_Channel2 +#define UART1_RX_DMA_REQUEST GPDMA1_REQUEST_USART1_RX +#define UART1_RX_DMA_IRQ GPDMA1_Channel2_IRQn +#endif + +/* GPDMA1_Channel */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_DMA_TX_IRQHandler GPDMA1_Channel3_IRQHandler +#define UART1_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN +#define UART1_TX_DMA_INSTANCE GPDMA1_Channel3 +#define UART1_TX_DMA_REQUEST GPDMA1_REQUEST_USART1_TX +#define UART1_TX_DMA_IRQ GPDMA1_Channel3_IRQn +#endif + +/* GPDMA1_Channel0 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_DMA_TX_IRQHandler GPDMA1_Channel0_IRQHandler +#define UART7_TX_DMA_RCC RCC_AHB1ENR_GPDMA1EN +#define UART7_TX_DMA_INSTANCE GPDMA1_Channel0 +#define UART7_TX_DMA_REQUEST GPDMA1_REQUEST_UART7_TX +// #define UART7_TX_DMA_CHANNEL GPDMA1_Channel0 +#define UART7_TX_DMA_IRQ GPDMA1_Channel0_IRQn +#endif + +/* GPDMA1_Channel1 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_DMA_RX_IRQHandler GPDMA1_Channel1_IRQHandler +#define UART7_RX_DMA_RCC RCC_AHB1ENR_GPDMA1EN +#define UART7_RX_DMA_INSTANCE GPDMA1_Channel1 +#define UART7_RX_DMA_REQUEST GPDMA1_REQUEST_UART7_RX +// #define UART7_RX_DMA_CHANNEL GPDMA1_Channel11 +#define UART7_RX_DMA_IRQ GPDMA1_Channel1_IRQn +#endif + +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +#endif + +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +#endif + + +/* DMA1 stream5 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream5 +#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn +#endif + +/* DMA1 stream6 */ + +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif + +/* DMA2 stream0 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream2 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_11 +#define QSPI_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream5 +#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream7 +#define QSPI_DMA_CHANNEL DMA_CHANNEL_3 +#define QSPI_DMA_IRQ DMA2_Stream7_IRQn +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h new file mode 100644 index 00000000000..3ddfb26a516 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/sdio_config.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32h7xx_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDMMC1, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h new file mode 100644 index 00000000000..da318d0dde0 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/tim_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h new file mode 100644 index 00000000000..f48cab32d18 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/config/uart_config.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2019-01-03 zylx modify dma support + * 2020-12-08 wanghaijing Adaptive stm32h7 uart dma + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .request = UART1_RX_DMA_REQUEST, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .request = UART1_TX_DMA_REQUEST, \ + .dma_rcc = UART1_TX_DMA_RCC, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .request = UART2_RX_DMA_REQUEST, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .request = UART2_TX_DMA_REQUEST, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .tx_pin_name = BSP_UART3_TX_PIN, \ + .rx_pin_name = BSP_UART3_RX_PIN, \ + } +#endif /* UART3_CONFIG */ + +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .request = UART3_RX_DMA_REQUEST, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .request = UART3_TX_DMA_REQUEST, \ + .dma_rcc = UART3_TX_DMA_RCC, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ + } +#endif /* UART4_CONFIG */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .request = UART4_RX_DMA_REQUEST, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .request = UART4_TX_DMA_REQUEST, \ + .dma_rcc = UART4_TX_DMA_RCC, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + .tx_pin_name = BSP_UART5_TX_PIN, \ + .rx_pin_name = BSP_UART5_RX_PIN, \ + } +#endif /* UART5_CONFIG */ + +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_RX_CONFIG +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .request = UART5_RX_DMA_REQUEST, \ + .dma_rcc = UART5_RX_DMA_RCC, \ + .dma_irq = UART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_RX_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + +#if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_DMA_TX_CONFIG +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .request = UART5_TX_DMA_REQUEST, \ + .dma_rcc = UART5_TX_DMA_RCC, \ + .dma_irq = UART5_TX_DMA_IRQ, \ + } +#endif /* UART5_DMA_TX_CONFIG */ +#endif /* BSP_UART5_TX_USING_DMA */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = USART6, \ + .irq_type = USART6_IRQn, \ + .tx_pin_name = BSP_UART6_TX_PIN, \ + .rx_pin_name = BSP_UART6_RX_PIN, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .request = UART6_RX_DMA_REQUEST, \ + .dma_rcc = UART6_RX_DMA_RCC, \ + .dma_irq = UART6_RX_DMA_IRQ, \ + } +#endif /* UART6_DMA_RX_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .request = UART6_TX_DMA_REQUEST, \ + .dma_rcc = UART6_TX_DMA_RCC, \ + .dma_irq = UART6_TX_DMA_IRQ, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = UART7, \ + .irq_type = UART7_IRQn, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .request = UART7_RX_DMA_REQUEST, \ + .dma_rcc = UART7_RX_DMA_RCC, \ + .dma_irq = UART7_RX_DMA_IRQ, \ + } +#endif /* UART7_DMA_RX_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .request = UART7_TX_DMA_REQUEST, \ + .dma_rcc = UART7_TX_DMA_RCC, \ + .dma_irq = UART7_TX_DMA_IRQ, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = UART8, \ + .irq_type = UART8_IRQn, \ + .tx_pin_name = BSP_UART8_TX_PIN, \ + .rx_pin_name = BSP_UART8_RX_PIN, \ + } +#endif /* UART8_CONFIG */ + +#if defined(BSP_UART8_RX_USING_DMA) +#ifndef UART8_DMA_RX_CONFIG +#define UART8_DMA_RX_CONFIG \ + { \ + .Instance = UART8_RX_DMA_INSTANCE, \ + .request = UART8_RX_DMA_REQUEST, \ + .dma_rcc = UART8_RX_DMA_RCC, \ + .dma_irq = UART8_RX_DMA_IRQ, \ + } +#endif /* UART8_DMA_RX_CONFIG */ +#endif /* BSP_UART8_RX_USING_DMA */ + +#if defined(BSP_UART8_TX_USING_DMA) +#ifndef UART8_DMA_TX_CONFIG +#define UART8_DMA_TX_CONFIG \ + { \ + .Instance = UART8_TX_DMA_INSTANCE, \ + .request = UART8_TX_DMA_REQUEST, \ + .dma_rcc = UART8_TX_DMA_RCC, \ + .dma_irq = UART8_TX_DMA_IRQ, \ + } +#endif /* UART8_DMA_TX_CONFIG */ +#endif /* BSP_UART8_TX_USING_DMA */ +#endif /* BSP_USING_UART8 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h new file mode 100644 index 00000000000..a9276b16ab9 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_common.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-7 SummerGift first version + */ + +#ifndef __DRV_COMMON_H__ + +#define __DRV_COMMON_H__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +void _Error_Handler(void); + +#ifndef Error_Handler +#define Error_Handler(msg) _Error_Handler(msg) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#define __STM32_PORT(port) GPIO##port##_BASE +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) +#define STM32_FLASH_START_ADRESS ROM_START +#define STM32_FLASH_SIZE ROM_SIZE +#define STM32_FLASH_END_ADDRESS ROM_END + +#define STM32_SRAM1_SIZE RAM_SIZE +#define STM32_SRAM1_START RAM_START +#define STM32_SRAM1_END RAM_END + +#define STM32_PSRAM_SIZE ((uint32_t)32*1024*1024) +#define STM32_PSRAM_START ((uint32_t)0x90000000) +#define STM32_PSRAM_END ((uint32_t)(STM32_PSRAM_START + STM32_PSRAM_SIZE)) + +#define PSRAM_HEAP_BEGIN STM32_PSRAM_START +#define PSRAM_HEAP_SIZE STM32_PSRAM_SIZE +#define PSRAM_HEAP_END STM32_PSRAM_END + +#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END STM32_SRAM1_END +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h new file mode 100644 index 00000000000..23085d85bf2 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_config.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SOC_SERIES_STM32F0) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/tim_config.h" +#include "config/pwm_config.h" +#include "config/adc_config.h" +#elif defined(SOC_SERIES_STM32F1) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/usbd_config.h" +#include "config/pulse_encoder_config.h" +#elif defined(SOC_SERIES_STM32F2) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#elif defined(SOC_SERIES_STM32F4) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/qspi_config.h" +#include "config/usbd_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/pulse_encoder_config.h" +#elif defined(SOC_SERIES_STM32F7) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/qspi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#elif defined(SOC_SERIES_STM32L0) +#include "config/dma_config.h" +#include "config/uart_config.h" +#elif defined(SOC_SERIES_STM32L1) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/usbd_config.h" +#elif defined(SOC_SERIES_STM32L4) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/qspi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/usbd_config.h" +#elif defined(SOC_SERIES_STM32G0) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/pwm_config.h" +#elif defined(SOC_SERIES_STM32G4) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/qspi_config.h" +#include "config/usbd_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/pulse_encoder_config.h" +#elif defined(SOC_SERIES_STM32H7) +#include "config/dma_config.h" +#include "config/uart_config.h" +#include "config/spi_config.h" +#include "config/qspi_config.h" +#include "config/adc_config.h" +#include "config/tim_config.h" +#include "config/sdio_config.h" +#include "config/pwm_config.h" +#include "config/usbd_config.h" +#elif defined(SOC_SERIES_STM32H7RS) +#include "config/uart_config.h" +#include "config/spi_config.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h new file mode 100644 index 00000000000..59a9aedeb7a --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_dma.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-10 SummerGift first version + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +#ifndef __DRV_DMA_H_ +#define __DRV_DMA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\ + || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) +#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) +#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef +#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */ + +struct dma_config { + DMA_INSTANCE_TYPE *Instance; + uint32_t request; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3) + rt_uint32_t channel; +#endif + +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) + rt_uint32_t request; +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_DMA_H_ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h new file mode 100644 index 00000000000..c74cfb6ba7a --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_eth.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-25 zylx first version + * 2020-07-18 wanghaijing add SPECIAL_MODES_REG + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#include +#include +#include +#include + +#define ETH_RX_BUFFER_SIZE (1536) +#define BSP_ETH_PHY_ADDR (0x00) +//#define BSP_ETH_USING_DEBUG + +/* The PHY basic control register */ +#define PHY_BASIC_CONTROL_REG 0x00U +#define PHY_RESET_MASK (1<<15) +#define PHY_AUTO_NEGOTIATION_MASK (1<<12) + +/* The PHY basic status register */ +#define PHY_BASIC_STATUS_REG 0x01U +#define PHY_LINKED_STATUS_MASK (1<<2) +#define PHY_AUTONEGO_COMPLETE_MASK (1<<5) + +/* The PHY ID one register */ +#define PHY_ID1_REG 0x02U + +/* The PHY ID two register */ +#define PHY_ID2_REG 0x03U + +/* The PHY auto-negotiate advertise register */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U + +/* The PHY SPECIAL MODES REGISTER */ +#define PHY_SPECIAL_MODES_REG 0x12U + + +//#define PHY_Status_REG 0x1FU +//#define PHY_FULL_DUPLEX_MASK (1<<4) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +#define PHY_Status_LINK_UP(sr) ((sr) & PHY_LINK_STATUS_MASK) + +#ifdef PHY_USING_LAN8720A +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x1DU +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x1EU +#define PHY_LINK_DOWN_MASK (1<<4) +#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) + +/* The PHY status register. */ +#define PHY_Status_REG 0x1FU +#define PHY_10M_MASK (1<<2) +#define PHY_100M_MASK (1<<3) +#define PHY_FULL_DUPLEX_MASK (1<<4) +#endif /* PHY_USING_LAN8720A */ + +#ifdef PHY_USING_DM9161CEP +#define PHY_Status_REG 0x11U +#define PHY_10M_MASK ((1<<12) || (1<<13)) +#define PHY_100M_MASK ((1<<14) || (1<<15)) +#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x15U +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x15U +#define PHY_LINK_CHANGE_FLAG (1<<2) +#define PHY_LINK_CHANGE_MASK (1<<9) +#define PHY_INT_MASK 0 + +#endif /* PHY_USING_DM9161CEP */ + +#ifdef PHY_USING_DP83848C +#define PHY_Status_REG 0x10U +#define PHY_10M_MASK (1<<1) +#define PHY_FULL_DUPLEX_MASK (1<<2) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr)) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +#define PHY_INTERRUPT_FLAG_REG 0x12U +#define PHY_LINK_CHANGE_FLAG (1<<13) +#define PHY_INTERRUPT_CTRL_REG 0x11U +#define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) +#define PHY_INTERRUPT_MASK_REG 0x12U +#define PHY_INT_MASK (1<<5) +#endif /* PHY_USING_DP83848C */ + +#ifdef PHY_USING_YT8512C +/* The PHY status register. */ +#define PHY_Status_REG 0x11U +/* The function corresponding to the 10m mask has not been used and can be ignored */ +/* The following several masks are all in the special state register */ +#define PHY_10M_MASK (1<<14) +#define PHY_100M_MASK (1<<14) +#define PHY_FULL_DUPLEX_MASK (1<<13) +#define PHY_LINK_STATUS_MASK (1<<10) +/* The PHY interrupt mask register */ +//#define PHY_INTERRUPT_MASK_REG 0x12U +//#define PHY_LINK_CHANGE_FLAG (1<<2) +//#define PHY_LINK_CHANGE_MASK (1<<9) +//#define PHY_INT_MASK 0 + +#endif /* PHY_USING_LAN8720A */ + +#endif /* __DRV_ETH_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h new file mode 100644 index 00000000000..43a1457058d --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_fdcan.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-24 heyuan the first version + * 2020-08-17 malongwei Fix something + */ + +#ifndef __DRV_FDCAN_H__ +#define __DRV_FDCAN_H__ + +#include +#include + +#ifdef RT_USING_CAN + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FDCAN_FRAMEFORMAT_CLASSIC (0) +#define BSP_FDCAN_FRAMEFORMAT_FD_NO_BRS (1) +#define BSP_FDCAN_FRAMEFORMAT_FD_BRS (2) + +enum _BSP_FDCAN_DATA_BAUD{ + BSP_FDCAN_BAUD_DATA_2M=(2*1000*1000), + BSP_FDCAN_BAUD_DATA_2M5=(2500*1000), + BSP_FDCAN_BAUD_DATA_4M=(4*1000*1000), + BSP_FDCAN_BAUD_DATA_5M=(5*1000*1000) +}; + +#define BSP_CAN_CMD_SET_BRS_BAUD (0x30) + +typedef struct +{ + const char *name; + FDCAN_HandleTypeDef fdcanHandle; + FDCAN_RxHeaderTypeDef RxHeader; + FDCAN_TxHeaderTypeDef TxHeader; + uint8_t u8RxDataBuffer[8]; + uint8_t u8TxDataBuufer[8]; + +#ifdef RT_CAN_USING_HDR + FDCAN_FilterTypeDef FilterConfig; /*FDCAN filter*/ + uint8_t std_filter_num; + uint8_t ext_filter_num; +#endif + + struct rt_can_device device; /* inherit from can device */ +} _stm32_fdcan_t; + +/* h7r The first one is the arbitration period time element, and the second one is the data period time element */ +typedef struct +{ + uint32_t u32NBaudrate; /* <1M, ? */ + uint16_t u16Nbrp; /* 1-512, 1-32 */ + uint8_t u8Nsjw; /* 1-128, 1-16 */ + uint8_t u8Ntseg1; /* 1-256, 1-32 */ + uint8_t u8Ntseg2; /* 1-128, 1-16 */ +} _stm32_fdcan_NTconfig_t; + + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_CAN */ +#endif /* __DRV_FDCAN_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h new file mode 100644 index 00000000000..fa3c7a01f81 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_gpio.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + * 2020-06-16 thread-liu add stm32mp1 + * 2020-09-01 thread-liu add GPIOZ + * 2020-09-18 geniusgogo optimization design pin-index algorithm + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __STM32_PORT(port) GPIO##port##_BASE + +#if defined(SOC_SERIES_STM32MP1) +#define GET_PIN(PORTx,PIN) (GPIO##PORTx == GPIOZ) ? (176 + PIN) : ((rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN)) +#else +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) +#endif + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h new file mode 100644 index 00000000000..7d888bfc5ce --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h new file mode 100644 index 00000000000..4ad86b6bfa2 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_sdmmc.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-30 Evlers first version + */ + +#ifndef __DRV_SDMMC_H__ +#define __DRV_SDMMC_H__ + +#include +#include "rtdevice.h" +#include +#include +#include +#include +#include + +#define SDIO_BUFF_SIZE 16384 +#define SDIO_ALIGN_LEN 32 + +#define SDIO1_BASE_ADDRESS (SDMMC1_BASE) +#define SDIO2_BASE_ADDRESS (SDMMC2_BASE) + +#ifndef SDIO_CLOCK_FREQ +#define SDIO_CLOCK_FREQ (200U * 1000 * 1000) +#endif + +#ifndef SDIO_BUFF_SIZE +#define SDIO_BUFF_SIZE (4096) +#endif + +#ifndef SDIO_ALIGN_LEN +#define SDIO_ALIGN_LEN (32) +#endif + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (50 * 1000 * 1000) +#endif + +/* Frequencies used in the driver for clock divider calculation */ +#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define SD_NORMAL_SPEED_FREQ 50000000U /* Normal speed phase : 50 MHz max */ +#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */ + +#define SDIO_ERRORS \ + (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \ + SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \ + SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \ + SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL) + +#define SDIO_MASKR_ALL \ + (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \ + SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \ + SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE) + +#define HW_SDIO_DATATIMEOUT (0xFFFFFFFFU) + +typedef rt_uint32_t (*sdio_clk_get)(void); + +struct stm32_sdio_des +{ + SD_HandleTypeDef hw_sdio; + sdio_clk_get clk_get; +}; + +extern void stm32_mmcsd_change(void); + +#endif /* __DRV_SDMMC_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h new file mode 100644 index 00000000000..5cca0920215 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_soft_i2c.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-08 balanceTWK first version + */ + +#ifndef __DRV_I2C__ +#define __DRV_I2C__ + +#include +#include +#include + +#ifdef RT_USING_I2C + +/* stm32 config class */ +struct stm32_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; +/* stm32 i2c dirver class */ +struct stm32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif +int rt_hw_i2c_init(void); + +#endif + +#endif /* RT_USING_I2C */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h new file mode 100644 index 00000000000..a9d42f3680a --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2019-03-05 whj4674672 add stm32h7 + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" + +int rt_hw_usart_init(void); + +#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) +#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef +#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ + || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) +#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef +#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */ + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \ + || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \ + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG +#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32MP1) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT +#endif + +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_HT_FLAG 0x01 +#define UART_RX_DMA_IT_TC_FLAG 0x02 + +#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20 + +/* stm32 config class */ +struct stm32_uart_config +{ + const char *name; + USART_TypeDef *Instance; + IRQn_Type irq_type; + struct dma_config *dma_rx; + struct dma_config *dma_tx; +}; + +/* stm32 uart dirver class */ +struct stm32_uart +{ + UART_HandleTypeDef handle; + struct stm32_uart_config *config; + rt_uint32_t DR_mask; + rt_uint32_t tx_block_timeout; + +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t remaining_cnt; + } dma_rx; + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h new file mode 100644 index 00000000000..46b81596c9f --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/drv_usart_v2.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-01 KyleChan first version + */ + +#ifndef __DRV_USART_V2_H__ +#define __DRV_USART_V2_H__ + +#include +#include +#include +#include +#include +#include + +int rt_hw_usart_init(void); + +#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ + || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32G4) +#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TDR = (__DATA__)) +#define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->RDR & MASK) + +#else +#define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->DR = (__DATA__)) +#define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->DR & MASK) +#endif + + +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \ + || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ + || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG +#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ + || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32MP1) +#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT +#endif + +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_HT_FLAG 0x01 +#define UART_RX_DMA_IT_TC_FLAG 0x02 + + +/* stm32 config class */ +struct stm32_uart_config +{ + const char *name; + USART_TypeDef *Instance; + IRQn_Type irq_type; + +#ifdef RT_SERIAL_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif +}; + +/* stm32 uart dirver class */ +struct stm32_uart +{ + UART_HandleTypeDef handle; + struct stm32_uart_config *config; + +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t remaining_cnt; + } dma_rx; + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h b/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h new file mode 100644 index 00000000000..cefc1742e7d --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/board/port/include/psram_port.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-24 yuanjie The first version for STM32H7RSxx + */ + +#ifndef __PSRAM_PORT_H__ +#define __PSRAM_PORT_H__ + +/* parameters for psram peripheral */ +#define PSRAM_BANK_ADDR ((uint32_t)0x70000000) +/* data width: 8, 16, 32 */ +#define PSRAM_DATA_WIDTH 32 +#define PSRAM_SIZE ((uint32_t)0x2000000) // 256Mbits, 32MB + +#endif diff --git a/bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h b/bsp/stm32/stm32h7r7-atk/board/port/include/rttlogo.h new file mode 100644 index 00000000000..752703417d4 --- /dev/null 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### uVision Project, (C) Keil Software
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1 + board\port\drv_psram.c + + + drv_spi.c + 1 + board\port\drv_spi.c + + + drv_usart_v2.c + 1 + board\port\drv_usart_v2.c + + + + + Filesystem + + + devfs.c + 1 + rt-thread\components\dfs\dfs_v1\filesystems\devfs\devfs.c + + + dfs_elm.c + 1 + rt-thread\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c + + + ff.c + 1 + rt-thread\components\dfs\dfs_v1\filesystems\elmfat\ff.c + + + ffunicode.c + 1 + rt-thread\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c + + + dfs_romfs.c + 1 + rt-thread\components\dfs\dfs_v1\filesystems\romfs\dfs_romfs.c + + + dfs.c + 1 + rt-thread\components\dfs\dfs_v1\src\dfs.c + + + dfs_file.c + 1 + rt-thread\components\dfs\dfs_v1\src\dfs_file.c + + + dfs_fs.c + 1 + rt-thread\components\dfs\dfs_v1\src\dfs_fs.c + + + dfs_posix.c + 1 + rt-thread\components\dfs\dfs_v1\src\dfs_posix.c + + + + + Finsh + + + msh_file.c + 1 + rt-thread\components\finsh\msh_file.c + + + msh.c + 1 + rt-thread\components\finsh\msh.c + + + msh_parse.c + 1 + rt-thread\components\finsh\msh_parse.c + + + cmd.c + 1 + rt-thread\components\finsh\cmd.c + + + shell.c + 1 + rt-thread\components\finsh\shell.c + + + + + Kernel + + + clock.c + 1 + rt-thread\src\clock.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + components.c + 1 + rt-thread\src\components.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + idle.c + 1 + rt-thread\src\idle.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + ipc.c + 1 + rt-thread\src\ipc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + irq.c + 1 + rt-thread\src\irq.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kstdio.c + 1 + rt-thread\src\klibc\kstdio.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kstring.c + 1 + rt-thread\src\klibc\kstring.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kservice.c + 1 + rt-thread\src\kservice.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 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__RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_up.c + 1 + rt-thread\src\scheduler_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + rt-thread\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + rt-thread\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + libcpu + + + div0.c + 1 + rt-thread\libcpu\arm\common\div0.c + + + showmem.c + 1 + rt-thread\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + rt-thread\libcpu\arm\cortex-m7\context_rvds.S + + + cpu_cache.c + 1 + rt-thread\libcpu\arm\cortex-m7\cpu_cache.c + + + cpuport.c + 1 + rt-thread\libcpu\arm\cortex-m7\cpuport.c + + + + + rt_kprintf + + + rt_vsnprintf.c + 1 + packages\rt_vsnprintf_full-latest\rt_vsnprintf.c + + + + + SAL + + + netdev.c + 1 + rt-thread\components\net\netdev\src\netdev.c + + + netdev_ipaddr.c + 1 + rt-thread\components\net\netdev\src\netdev_ipaddr.c + + + dfs_net.c + 1 + rt-thread\components\net\sal\dfs_net\dfs_net.c + + + net_netdb.c + 1 + rt-thread\components\net\sal\socket\net_netdb.c + + + net_sockets.c + 1 + rt-thread\components\net\sal\socket\net_sockets.c + + + sal_socket.c + 1 + rt-thread\components\net\sal\src\sal_socket.c + + + + + STM32_HAL + + + stm32h7rsxx_hal_uart.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c + + + stm32h7rsxx_hal_crc.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_crc.c + + + stm32h7rsxx_hal_dma_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c + + + stm32h7rsxx_hal_adc_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_adc_ex.c + + + stm32h7rsxx_hal_sram.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sram.c + + + stm32h7rsxx_hal_adc.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_adc.c + + + stm32h7rsxx_hal_pwr.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c + + + stm32h7rsxx_hal_rng.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rng.c + + + stm32h7rsxx_hal_cryp_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cryp_ex.c + + + stm32h7rsxx_hal_crc_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_crc_ex.c + + + stm32h7rsxx_hal_gpio.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c + + + stm32h7rsxx_hal_cec.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cec.c + + + stm32h7rsxx_hal_xspi.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c + + + stm32h7rsxx_hal_usart.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_usart.c + + + stm32h7rsxx_hal.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c + + + stm32h7rsxx_hal_rcc.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c + + + stm32h7rsxx_hal_uart_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c + + + system_stm32h7rsxx.c + 1 + libraries\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c + + + stm32h7rsxx_hal_pwr_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c + + + stm32h7rsxx_hal_flash.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c + + + stm32h7rsxx_hal_cortex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c + + + stm32h7rsxx_hal_dma.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c + + + stm32h7rsxx_hal_flash_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c + + + stm32h7rsxx_hal_rcc_ex.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c + + + stm32h7rsxx_hal_cryp.c + 1 + libraries\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cryp.c + + + startup_stm32h7r7xx.s + 2 + libraries\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\arm\startup_stm32h7r7xx.s + + + + + Utilities + + + ulog.c + 1 + rt-thread\components\utilities\ulog\ulog.c + + + console_be.c + 1 + rt-thread\components\utilities\ulog\backend\console_be.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/stm32/stm32h7r7-atk/rtconfig.h b/bsp/stm32/stm32h7r7-atk/rtconfig.h new file mode 100644 index 00000000000..7c4bf58de77 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/rtconfig.h @@ -0,0 +1,436 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +/* end of kservice optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 384 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 9 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 15 +#define FINSH_THREAD_STACK_SIZE 8192 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 10 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using USB */ + +/* end of Using USB */ +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +#define RT_USING_SAL + +/* Docking with protocol stacks */ + +/* end of Docking with protocol stacks */ +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_USING_ISR_LOG +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 128 + +/* log format */ + +#define ULOG_OUTPUT_FLOAT +#define ULOG_USING_COLOR +#define ULOG_OUTPUT_TIME +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +/* end of log format */ +#define ULOG_BACKEND_USING_CONSOLE +/* end of Utilities */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +#define PKG_USING_RT_VSNPRINTF_FULL +#define PKG_VSNPRINTF_SUPPORT_DECIMAL_SPECIFIERS +#define PKG_VSNPRINTF_SUPPORT_EXPONENTIAL_SPECIFIERS +#define PKG_VSNPRINTF_SUPPORT_WRITEBACK_SPECIFIER +#define PKG_VSNPRINTF_SUPPORT_LONG_LONG +#define PKG_VSNPRINTF_CHECK_FOR_NUL_IN_FORMAT_SPECIFIER +#define PKG_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION 6 +#define PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define PKG_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +#define PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_STM32H7RS +#define SOC_SERIES_STM32H7RS + +/* Onboard Peripheral Drivers */ + +#define BSP_SCB_ENABLE_I_CACHE +#define BSP_SCB_ENABLE_D_CACHE +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_UART1_RX_BUFSIZE 512 +#define BSP_UART1_TX_BUFSIZE 512 +#define BSP_USING_PSRAM +#define BSP_USING_PSRAM_TEST +/* end of On-chip Peripheral */ +/* end of Hardware Drivers Config */ + +/* External Libraries */ + +/* end of External Libraries */ +#define FIRMWARE_EXEC_USING_OSPI_FLASH +#define RT_STUDIO_BUILT_IN + +#endif diff --git a/bsp/stm32/stm32h7r7-atk/rtconfig.py b/bsp/stm32/stm32h7r7-atk/rtconfig.py new file mode 100644 index 00000000000..bb6c39efa1c --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/rtconfig.py @@ -0,0 +1,135 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 ' + CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv5-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board/linker_scripts/STM32H750XBHx/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32h7r7-atk/rtconfig_preinc.h b/bsp/stm32/stm32h7r7-atk/rtconfig_preinc.h new file mode 100644 index 00000000000..eee4d1203a0 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/rtconfig_preinc.h @@ -0,0 +1,15 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define STM32H7S7xx +#define USE_HAL_DRIVER +#define _POSIX_C_SOURCE 1 +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/stm32/stm32h7r7-atk/template.uvoptx b/bsp/stm32/stm32h7r7-atk/template.uvoptx new file mode 100644 index 00000000000..d9a44d17140 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/template.uvoptx @@ -0,0 +1,194 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"ATK-FS-HID-CMSIS-DAP" -UATK-03262021 -O206 -S9 -C0 -P00000001 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC600000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC10000 -FN2 -FF0STM32H7Rx_64k.FLM -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) -FF1ATK-DNH7R7_XSPI_MULTIPLE -FS190000000 -FL12000000 + + + 0 + ST-LINKIII-KEIL_SWO + -U0672FF363658393143205347 -O206 -SF5000 -C0 -A1 -I0 -HNlocalhost -HP7184 -P1 -N00("") -D00(00000000) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCFFFC -FN2 -FF0STM32H7Rx_64k.FLM -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) -FF1ART-Pi2_winbond_64MB -FS170000000 -FL14000000 -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32H7Rx_64k -FL010000 -FS08000000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) + + + 0 + JL2CM3 + -U932000685 -O78 -S5 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO11 -FD20000000 -FC8000 -FN1 -FF0MX66UW1G45G_STM32H7S78-DK.FLM -FS070000000 -FL08000000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\MX66UW1G45G_STM32H7S78-DK.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/stm32/stm32h7r7-atk/template.uvprojx b/bsp/stm32/stm32h7r7-atk/template.uvprojx new file mode 100644 index 00000000000..a199f53a507 --- /dev/null +++ b/bsp/stm32/stm32h7r7-atk/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 1 + + + STM32H7S7L8Hx + STMicroelectronics + Keil.STM32H7RSxx_DFP.1.0.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x20000) IROM(0x08000000,0x010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7Rx_64k -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM)) + 0 + + + + + + + + + + + $$Device:STM32H7S7L8Hx$CMSIS\SVD\STM32H7RSxx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x30000000 + 0x48000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + + + + template + 1 + + + + +