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The L2 cache is composed of a number of distinct channels (32 on MI100 and MI2XX series CDNA accelerators at 256B address interleaving) which can largely operate independently.
I couldn't find anywhere else this information about 256B address interleaving. What does it means exactly? Does it mean that for example on MI200 every two cachelines (128B) a different channel is used for L2 memory requests?
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In the L2 cache documentation it is stated:
The L2 cache is composed of a number of distinct channels (32 on MI100 and MI2XX series CDNA accelerators at 256B address interleaving) which can largely operate independently.
I couldn't find anywhere else this information about 256B address interleaving. What does it means exactly? Does it mean that for example on MI200 every two cachelines (128B) a different channel is used for L2 memory requests?
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