From d72d1aaf701a5c0bdf6224df583e676f888ab8a0 Mon Sep 17 00:00:00 2001 From: Peter Park Date: Wed, 22 Jan 2025 15:32:56 -0500 Subject: [PATCH] update l2 cache line size note for mi300 --- docs/conceptual/l2-cache.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/conceptual/l2-cache.rst b/docs/conceptual/l2-cache.rst index 805e9999d..b34ef6bc7 100644 --- a/docs/conceptual/l2-cache.rst +++ b/docs/conceptual/l2-cache.rst @@ -284,9 +284,9 @@ This section details the incoming requests to the L2 cache from the .. note:: All requests to the L2 are for a single cache line's worth of data. The size - of a cache line may vary depending on the accelerator, however on an AMD - Instinct CDNA2 :ref:`MI200 ` accelerator, it is 128B, while on - an MI100, it is 64B. + of a cache line may vary depending on the accelerator. The L2 cache line + size is 128B on :ref:`MI300 and MI200 ` accelerators, while on + MI100, it is 64B. .. _l2-fabric: