The current way the trigger time is constructed is insufficient!
The sub-second part is determined from the counter values (sysclk) of a ~100 MHz oscillator stored upon trigger and the last two PPS pulses. There is a long-standing issue which might be solvable in firmware, and an approximate solution which can be applied in mattak here: #3
Now here is another issue:
The second part is determined from the readout time (minus one if the subsecond part of the trigger time > subsecond part of the readout time) here:
|
if (1e-9 * head->readout_time_nsecs < this->trigger_time) this->trigger_time += head->readout_time_secs-1; |
. The simple "minus 1" by comparing the two is insufficient, due to time passing between trigger and readout.
Here is a demonstration, trigger times inconsistent with the events before/after are marked in red:

The current way the trigger time is constructed is insufficient!
The sub-second part is determined from the counter values (
sysclk) of a ~100 MHz oscillator stored upon trigger and the last two PPS pulses. There is a long-standing issue which might be solvable in firmware, and an approximate solution which can be applied in mattak here: #3Now here is another issue:
The second part is determined from the readout time (minus one if the subsecond part of the trigger time > subsecond part of the readout time) here:
mattak/src/Header.cc
Line 36 in 0143ee2
Here is a demonstration, trigger times inconsistent with the events before/after are marked in red:
