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fixup! cpu/esp32/irq_arch: migration to ESP-IDF v5.4
1 parent ea86161 commit 9a69c42

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4 files changed

+56
-49
lines changed

4 files changed

+56
-49
lines changed

‎cpu/esp32/include/irq_arch.h‎

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -36,24 +36,30 @@ extern "C" {
3636
*
3737
* @{
3838
*/
39+
40+
/* While interrupt 0 is reserved for WiFi on Xtensa-based ESP32x SoCs and
41+
* interrupt 1 is available, interrupt 1 is reserved for WiFi on RISC-V-based
42+
* ESP32x SoCs and interrupt 0 is available. */
43+
#if defined(__riscv)
44+
#define CPU_INUM_RMT 0 /**< Level interrupt with low priority 1 */
45+
#else
3946
#define CPU_INUM_RMT 1 /**< Level interrupt with low priority 1 */
47+
#endif
4048
#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
41-
#define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */
42-
#define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */
43-
#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */
49+
#define CPU_INUM_BLE 5 /**< Level interrupt with low priority 1 */
4450
#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
45-
#define CPU_INUM_SERIAL_JTAG 10 /**< Level interrupt with low priority 1 */
51+
#define CPU_INUM_SERIAL_JTAG 10 /**< Edge interrupt with low priority 1 */
4652
#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
47-
#define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */
48-
#define CPU_INUM_SOFTWARE 17 /**< Level interrupt with low priority 1 */
53+
#define CPU_INUM_UART 13 /**< Level interrupt with low priority 1 */
54+
#define CPU_INUM_CAN 17 /**< Level interrupt with low priority 1 */
4955
#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
50-
#define CPU_INUM_LCD 18 /**< Level interrupt with low priority 1 */
51-
#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
56+
#define CPU_INUM_USB 18 /**< Level interrupt with low priority 1 */
5257
#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
5358
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
54-
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */
55-
#define CPU_INUM_SDMMC 23 /**< Level interrupt with medium priority 3 */
56-
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
59+
#define CPU_INUM_SDMMC 21 /**< Level interrupt with medium priority 2 */
60+
#define CPU_INUM_TIMER 22 /**< Edge interrupt with medium priority 2 */
61+
#define CPU_INUM_WDT 23 /**< Level interrupt with medium priority 3 */
62+
#define CPU_INUM_SOFTWARE 29 /**< Software interrupt with medium priority 3 */
5763
/** @} */
5864

5965
/**

‎cpu/esp32/irq_arch.c‎

Lines changed: 32 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
*/
2020

2121
#include "irq_arch.h"
22+
#include "log.h"
2223

2324
#include "esp_attr.h"
2425
#include "esp_bit_defs.h"
@@ -46,72 +47,66 @@ typedef struct intr_handle_data_t {
4647

4748
/* TODO change to a clearer approach */
4849
static const struct intr_handle_data_t _irq_data_table[] = {
50+
#ifndef __XTENSA__
4951
{ ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE, 1 },
52+
#endif
5053
{ ETS_TG0_WDT_LEVEL_INTR_SOURCE, CPU_INUM_WDT, 1 },
5154
{ ETS_TG0_T0_LEVEL_INTR_SOURCE, CPU_INUM_RTT, 1 },
52-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
55+
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
5356
{ ETS_TG0_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
5457
#endif
55-
#if !defined(CPU_FAM_ESP32C2)
58+
#if SOC_TIMER_GROUPS > 1
5659
{ ETS_TG1_T0_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
57-
#endif
58-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
60+
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
5961
{ ETS_TG1_T1_LEVEL_INTR_SOURCE, CPU_INUM_TIMER, 2 },
62+
#endif /* SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1 */
63+
#endif /* SOC_TIMER_GROUPS > 1 */
64+
#if defined(CPU_FAM_ESP32)
65+
{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
66+
#elif defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
67+
{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
68+
#else
69+
#error "Platform implementation is missing"
6070
#endif
6171
{ ETS_UART0_INTR_SOURCE, CPU_INUM_UART, 1 },
6272
{ ETS_UART1_INTR_SOURCE, CPU_INUM_UART, 1 },
63-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
73+
#if SOC_UART_NUM > 2
6474
{ ETS_UART2_INTR_SOURCE, CPU_INUM_UART, 1 },
6575
#endif
6676
{ ETS_GPIO_INTR_SOURCE, CPU_INUM_GPIO, 1 },
6777
{ ETS_I2C_EXT0_INTR_SOURCE, CPU_INUM_I2C, 1 },
68-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
78+
#if SOC_I2C_NUM > 1
6979
{ ETS_I2C_EXT1_INTR_SOURCE, CPU_INUM_I2C, 1 },
7080
#endif
71-
#if defined(CPU_FAM_ESP32)
72-
{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH, 1 },
73-
#endif
74-
#if !defined(CPU_FAM_ESP32C2)
75-
{ ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN, 1 },
76-
{ ETS_TIMER2_INTR_SOURCE, CPU_INUM_FRC2, 2 },
77-
#endif
78-
#if defined(CPU_FAM_ESP32)
79-
{ ETS_TG0_LACT_LEVEL_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
80-
#elif defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
81-
{ ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
82-
#else
83-
#error "Platform implementation is missing"
84-
#endif
85-
#if SOC_BLE_SUPPORTED
81+
#if defined(SOC_BLE_SUPPORTED)
8682
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3) || defined(CPU_FAM_ESP32C3)
8783
{ ETS_RWBLE_INTR_SOURCE, CPU_INUM_BLE, 2 },
8884
#else
8985
#error "Platform implementation is missing"
9086
#endif
9187
#endif /* SOC_BLE_SUPPORTED */
92-
#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
93-
{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
94-
#endif
95-
#if defined(ETS_USB_SERIAL_JTAG_INTR_SOURCE)
96-
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 },
88+
#if defined(SOC_EMAC_SUPPORTED)
89+
{ ETS_ETH_MAC_INTR_SOURCE, CPU_INUM_ETH, 1 },
9790
#endif
91+
#if defined(SOC_RMT_SUPPORTED)
9892
{ ETS_RMT_INTR_SOURCE, CPU_INUM_RMT, 1 },
99-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
100-
{ ETS_I2S0_INTR_SOURCE, CPU_INUM_LCD, 1 },
101-
#elif defined(CPU_FAM_ESP32S3)
102-
{ ETS_LCD_CAM_INTR_SOURCE, CPU_INUM_LCD, 1 },
10393
#endif
104-
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
94+
#if defined(SOC_SDMMC_HOST_SUPPORTED)
10595
{ ETS_SDIO_HOST_INTR_SOURCE, CPU_INUM_SDMMC, 2 },
10696
#endif
97+
#if defined(SOC_TWAI_SUPPORTED)
98+
{ ETS_TWAI_INTR_SOURCE, CPU_INUM_CAN, 1 },
99+
#endif
100+
#if defined(SOC_USB_OTG_SUPPORTED)
101+
{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
102+
#endif
103+
#if defined(SOC_USB_SERIAL_JTAG_SUPPORTED)
104+
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 },
105+
#endif
107106
};
108107

109108
#define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table)
110109

111-
#if defined(CPU_FAM_ESP32) && MODULE_ESP_LCD && MODULE_ESP_ETH
112-
#error "esp_eth and esp_lcd can't be used at the same time because of an interrupt conflict"
113-
#endif
114-
115110
void esp_irq_init(void)
116111
{
117112
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
@@ -169,8 +164,8 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler,
169164
}
170165

171166
if (i == IRQ_DATA_TABLE_SIZE) {
172-
DEBUG("%s source=%d not found in interrupt allocation table\n",
173-
__func__, source);
167+
LOG_ERROR("%s source=%d not found in interrupt allocation table\n",
168+
__func__, source);
174169
return ESP_ERR_NOT_FOUND;
175170
}
176171

‎cpu/esp32/startup.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -309,8 +309,11 @@ static NORETURN void IRAM system_init (void)
309309
extern void board_init(void);
310310
board_init();
311311

312-
/* route a software interrupt source to CPU as trigger for thread yields */
312+
#ifndef __XTENSA__
313+
/* route a software interrupt source to CPU as trigger for thread yields,
314+
* we use an internal software interrupt on Xtensa-based ESP32x SoCs */
313315
intr_matrix_set(PRO_CPU_NUM, ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE);
316+
#endif
314317
/* set thread yield handler and enable the software interrupt */
315318
esp_cpu_intr_set_handler(CPU_INUM_SOFTWARE, thread_yield_isr, NULL);
316319
esp_cpu_intr_enable(BIT(CPU_INUM_SOFTWARE));

‎cpu/esp_common/esp-xtensa/thread_arch.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -286,6 +286,9 @@ void IRAM_ATTR thread_yield_higher(void)
286286
ets_soft_int_type = ETS_SOFT_INT_YIELD;
287287
WSR(BIT(ETS_SOFT_INUM), interrupt);
288288
critical_exit();
289+
#elif defined(__XTENSA__)
290+
/* generate the software interrupt to switch the context */
291+
WSR(BIT(CPU_INUM_SOFTWARE), interrupt);
289292
#elif defined(DPORT_CPU_INTR_FROM_CPU_0_REG)
290293
/* generate the software interrupt to switch the context */
291294
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);

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