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h7: add timer pins (betaflight#14153)
1 parent 3d9dcbc commit 9ab3aa1

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2 files changed

+26
-16
lines changed

2 files changed

+26
-16
lines changed

src/platform/STM32/timer_def.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -747,6 +747,11 @@
747747
#define DEF_TIM_AF__PB14__TCH_TIM12_CH1 D(2, 12)
748748
#define DEF_TIM_AF__PB15__TCH_TIM12_CH2 D(2, 12)
749749

750+
#define DEF_TIM_AF__PB0__TCH_TIM8_CH2N D(3, 8)
751+
#define DEF_TIM_AF__PB1__TCH_TIM8_CH3N D(3, 8)
752+
#define DEF_TIM_AF__PB14__TCH_TIM8_CH2N D(3, 8)
753+
#define DEF_TIM_AF__PB15__TCH_TIM8_CH3N D(3, 8)
754+
750755
//PORTC
751756
#define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3)
752757
#define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3)
@@ -1142,7 +1147,7 @@
11421147

11431148
#elif defined(STM32H7)
11441149

1145-
#define FULL_TIMER_CHANNEL_COUNT 87
1150+
#define FULL_TIMER_CHANNEL_COUNT 91
11461151
#define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(12) | TIM_N(13) | TIM_N(14) | TIM_N(15) | TIM_N(16) | TIM_N(17) )
11471152
#define HARDWARE_TIMER_DEFINITION_COUNT 17
11481153
#define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) )

src/platform/STM32/timer_stm32h7xx.c

Lines changed: 20 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,8 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
7171
DEF_TIM(TIM5, CH4, PA3, 0, 0, 0),
7272
DEF_TIM(TIM3, CH1, PA6, 0, 0, 0),
7373
DEF_TIM(TIM3, CH2, PA7, 0, 0, 0),
74-
7574
DEF_TIM(TIM8, CH1N, PA5, 0, 0, 0),
7675
DEF_TIM(TIM8, CH1N, PA7, 0, 0, 0),
77-
7876
DEF_TIM(TIM13, CH1, PA6, 0, 0, 0),
7977
DEF_TIM(TIM14, CH1, PA7, 0, 0, 0),
8078

@@ -104,16 +102,19 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
104102
DEF_TIM(TIM4, CH2, PB7, 0, 0, 0),
105103
DEF_TIM(TIM4, CH3, PB8, 0, 0, 0),
106104
DEF_TIM(TIM4, CH4, PB9, 0, 0, 0),
107-
108105
DEF_TIM(TIM12, CH1, PB14, 0, 0, 0),
109106
DEF_TIM(TIM12, CH2, PB15, 0, 0, 0),
110107

108+
DEF_TIM(TIM8, CH2N, PB0, 0, 0, 0),
109+
DEF_TIM(TIM8, CH3N, PB1, 0, 0, 0),
110+
DEF_TIM(TIM8, CH2N, PB14, 0, 0, 0),
111+
DEF_TIM(TIM8, CH3N, PB15, 0, 0, 0),
112+
111113
// Port C
112114
DEF_TIM(TIM3, CH1, PC6, 0, 0, 0),
113115
DEF_TIM(TIM3, CH2, PC7, 0, 0, 0),
114116
DEF_TIM(TIM3, CH3, PC8, 0, 0, 0),
115117
DEF_TIM(TIM3, CH4, PC9, 0, 0, 0),
116-
117118
DEF_TIM(TIM8, CH1, PC6, 0, 0, 0),
118119
DEF_TIM(TIM8, CH2, PC7, 0, 0, 0),
119120
DEF_TIM(TIM8, CH3, PC8, 0, 0, 0),
@@ -133,7 +134,6 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
133134
DEF_TIM(TIM1, CH3N, PE12, 0, 0, 0),
134135
DEF_TIM(TIM1, CH3, PE13, 0, 0, 0),
135136
DEF_TIM(TIM1, CH4, PE14, 0, 0, 0),
136-
137137
DEF_TIM(TIM15, CH1N, PE4, 0, 0, 0),
138138
DEF_TIM(TIM15, CH1, PE5, 0, 0, 0),
139139
DEF_TIM(TIM15, CH2, PE6, 0, 0, 0),
@@ -143,20 +143,25 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
143143
DEF_TIM(TIM17, CH1, PF7, 0, 0, 0),
144144
DEF_TIM(TIM16, CH1N, PF8, 0, 0, 0),
145145
DEF_TIM(TIM17, CH1N, PF9, 0, 0, 0),
146-
147146
DEF_TIM(TIM13, CH1N, PF8, 0, 0, 0),
148147
DEF_TIM(TIM14, CH1N, PF9, 0, 0, 0),
149148

150149
// Port H
151-
// Port H is not available for LPQFP-100 or 144 and TFBGA-100 package
152-
// DEF_TIM(TIM12, CH1, PH6, 0, 0, 0),
153-
// DEF_TIM(TIM12, CH2, PH9, 0, 0, 0),
154-
// DEF_TIM(TIM5, CH1, PH10, 0, 0, 0),
155-
// DEF_TIM(TIM5, CH2, PH11, 0, 0, 0),
156-
// DEF_TIM(TIM5, CH3, PH12, 0, 0, 0),
157-
// DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0),
158-
// DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0),
159-
// DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0),
150+
DEF_TIM(TIM5, CH1, PH10, 0, 0, 0),
151+
DEF_TIM(TIM5, CH2, PH11, 0, 0, 0),
152+
DEF_TIM(TIM5, CH3, PH12, 0, 0, 0),
153+
DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0),
154+
DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0),
155+
DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0),
156+
DEF_TIM(TIM12, CH1, PH6, 0, 0, 0),
157+
DEF_TIM(TIM12, CH2, PH9, 0, 0, 0),
158+
159+
// Port I
160+
DEF_TIM(TIM5, CH4, PI0, 0, 0, 0),
161+
DEF_TIM(TIM8, CH4, PI2, 0, 0, 0),
162+
DEF_TIM(TIM8, CH1, PI5, 0, 0, 0),
163+
DEF_TIM(TIM8, CH2, PI6, 0, 0, 0),
164+
DEF_TIM(TIM8, CH3, PI7, 0, 0, 0),
160165
};
161166
#endif
162167

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