@@ -71,10 +71,8 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
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DEF_TIM (TIM5 , CH4 , PA3 , 0 , 0 , 0 ),
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DEF_TIM (TIM3 , CH1 , PA6 , 0 , 0 , 0 ),
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DEF_TIM (TIM3 , CH2 , PA7 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM8 , CH1N , PA5 , 0 , 0 , 0 ),
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DEF_TIM (TIM8 , CH1N , PA7 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM13 , CH1 , PA6 , 0 , 0 , 0 ),
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DEF_TIM (TIM14 , CH1 , PA7 , 0 , 0 , 0 ),
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@@ -104,16 +102,19 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
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DEF_TIM (TIM4 , CH2 , PB7 , 0 , 0 , 0 ),
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DEF_TIM (TIM4 , CH3 , PB8 , 0 , 0 , 0 ),
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DEF_TIM (TIM4 , CH4 , PB9 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM12 , CH1 , PB14 , 0 , 0 , 0 ),
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DEF_TIM (TIM12 , CH2 , PB15 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH2N , PB0 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH3N , PB1 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH2N , PB14 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH3N , PB15 , 0 , 0 , 0 ),
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+
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// Port C
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DEF_TIM (TIM3 , CH1 , PC6 , 0 , 0 , 0 ),
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DEF_TIM (TIM3 , CH2 , PC7 , 0 , 0 , 0 ),
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DEF_TIM (TIM3 , CH3 , PC8 , 0 , 0 , 0 ),
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DEF_TIM (TIM3 , CH4 , PC9 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM8 , CH1 , PC6 , 0 , 0 , 0 ),
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DEF_TIM (TIM8 , CH2 , PC7 , 0 , 0 , 0 ),
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DEF_TIM (TIM8 , CH3 , PC8 , 0 , 0 , 0 ),
@@ -133,7 +134,6 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
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DEF_TIM (TIM1 , CH3N , PE12 , 0 , 0 , 0 ),
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DEF_TIM (TIM1 , CH3 , PE13 , 0 , 0 , 0 ),
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DEF_TIM (TIM1 , CH4 , PE14 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM15 , CH1N , PE4 , 0 , 0 , 0 ),
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DEF_TIM (TIM15 , CH1 , PE5 , 0 , 0 , 0 ),
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DEF_TIM (TIM15 , CH2 , PE6 , 0 , 0 , 0 ),
@@ -143,20 +143,25 @@ const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
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DEF_TIM (TIM17 , CH1 , PF7 , 0 , 0 , 0 ),
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DEF_TIM (TIM16 , CH1N , PF8 , 0 , 0 , 0 ),
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DEF_TIM (TIM17 , CH1N , PF9 , 0 , 0 , 0 ),
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-
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DEF_TIM (TIM13 , CH1N , PF8 , 0 , 0 , 0 ),
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DEF_TIM (TIM14 , CH1N , PF9 , 0 , 0 , 0 ),
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// Port H
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- // Port H is not available for LPQFP-100 or 144 and TFBGA-100 package
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- // DEF_TIM(TIM12, CH1, PH6, 0, 0, 0),
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- // DEF_TIM(TIM12, CH2, PH9, 0, 0, 0),
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- // DEF_TIM(TIM5, CH1, PH10, 0, 0, 0),
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- // DEF_TIM(TIM5, CH2, PH11, 0, 0, 0),
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- // DEF_TIM(TIM5, CH3, PH12, 0, 0, 0),
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- // DEF_TIM(TIM8, CH1N, PH13, 0, 0, 0),
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- // DEF_TIM(TIM8, CH2N, PH14, 0, 0, 0),
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- // DEF_TIM(TIM8, CH3N, PH15, 0, 0, 0),
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+ DEF_TIM (TIM5 , CH1 , PH10 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM5 , CH2 , PH11 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM5 , CH3 , PH12 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH1N , PH13 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH2N , PH14 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH3N , PH15 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM12 , CH1 , PH6 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM12 , CH2 , PH9 , 0 , 0 , 0 ),
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+
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+ // Port I
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+ DEF_TIM (TIM5 , CH4 , PI0 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH4 , PI2 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH1 , PI5 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH2 , PI6 , 0 , 0 , 0 ),
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+ DEF_TIM (TIM8 , CH3 , PI7 , 0 , 0 , 0 ),
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};
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#endif
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