Merge branch 'rc-1.8.6'

shtaxxx · shtaxxx · commit f1d92f4f541b · 2021-04-20T23:39:30.000+09:00
diff --git a/tests/extension/thread_/multiport_memorymodel/Makefile b/tests/extension/thread_/multiport_memorymodel/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py b/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_multiport_memorymodel
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_multiport_memorymodel.run(filename=None, simtype=simtype,
+                                            outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py b/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py
@@ -0,0 +1,198 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi0 = vthread.AXIM(m, 'myaxi0', clk, rst, datawidth)
+    myaxi1 = vthread.AXIM(m, 'myaxi1', clk, rst, datawidth)
+    myram = vthread.RAM(m, 'myram', clk, rst, datawidth, addrwidth)
+
+    saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, datawidth)
+
+    all_ok = m.TmpReg(initval=0)
+
+    def blink(size):
+        # wait start
+        saxi.wait_flag(0, value=1, resetvalue=0)
+        # reset done
+        saxi.write(1, 0)
+
+        all_ok.value = True
+
+        for i in range(4):
+            print('# iter %d start' % i)
+            # Test for 4KB boundary check
+            offset = i * 1024 * 16 + (myaxi0.boundary_size - 4)
+            body(size, offset)
+            print('# iter %d end' % i)
+
+        if all_ok:
+            print('# verify (local): PASSED')
+        else:
+            print('# verify (local): FAILED')
+
+        # result
+        saxi.write(2, all_ok)
+
+        # done
+        saxi.write_flag(1, 1, resetvalue=0)
+
+    def body(size, offset):
+        # write
+        for i in range(size):
+            wdata = i + 100
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = offset
+        myaxi0.dma_write(myram, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # write
+        for i in range(size):
+            wdata = i + 1000
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi1.dma_write(myram, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # read
+        laddr = 0
+        gaddr = offset
+        myaxi0.dma_read(myram, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i)
+            if vthread.verilog.NotEql(rdata, i + 100):
+                print('rdata[%d] = %d' % (i, rdata))
+                all_ok.value = False
+
+        # read
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi1.dma_read(myram, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i)
+            if vthread.verilog.NotEql(rdata, i + 1000):
+                print('rdata[%d] = %d' % (i, rdata))
+                all_ok.value = False
+
+    th = vthread.Thread(m, 'th_blink', clk, rst, blink)
+    fsm = th.start(16)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMultiportMemoryModel(m, 'memory', clk, rst, numports=2,
+                                         memimg_name=memimg_name)
+    memory.connect(0, ports, 'myaxi0')
+    memory.connect(1, ports, 'myaxi1')
+
+    # AXI-Slave controller
+    _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True)
+    _saxi.connect(ports, 'saxi')
+
+    def ctrl():
+        for i in range(100):
+            pass
+
+        for i in range(16):
+            # byte addressing
+            v = memory.read(i * 4)
+            print('read:  mem[%d] -> %x' % (i, v))
+            v = v + 1024
+            # byte addressing
+            memory.write(i * 4, v)
+            print('write: mem[%d] <- %x' % (i, v))
+
+        awaddr = 0
+        _saxi.write(awaddr, 1)
+
+        araddr = 4
+        v = _saxi.read(araddr)
+        while v == 0:
+            v = _saxi.read(araddr)
+
+        araddr = 8
+        v = _saxi.read(araddr)
+        if v:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl)
+    fsm = th.start()
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py
@@ -2898,23 +2898,24 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
             self.rdata.ruser.assign(rdata_user_mode)
 
         self.fsm = FSM(self.m, '_'.join(['', self.name, 'fsm']), clk, rst)
+        self.seq = self.fsm.seq
 
         # write response
         if self.wresp.bid is not None:
-            self.fsm.seq.If(self.waddr.awvalid, self.waddr.awready,
+            self.seq.If(self.waddr.awvalid, self.waddr.awready,
                             vtypes.Not(self.wresp.bvalid))(
                 self.wresp.bid(self.waddr.awid if self.waddr.awid is not None else 0)
             )
 
         if self.rdata.rid is not None:
-            self.fsm.seq.If(self.raddr.arvalid, self.raddr.arready)(
+            self.seq.If(self.raddr.arvalid, self.raddr.arready)(
                 self.rdata.rid(self.raddr.arid if self.raddr.arid is not None else 0)
             )
 
-        self.fsm.seq.If(self.wresp.bvalid, self.wresp.bready)(
+        self.seq.If(self.wresp.bvalid, self.wresp.bready)(
             self.wresp.bvalid(0)
         )
-        self.fsm.seq.If(self.wdata.wvalid, self.wdata.wready, self.wdata.wlast)(
+        self.seq.If(self.wdata.wvalid, self.wdata.wready, self.wdata.wlast)(
             self.wresp.bvalid(1)
         )
 
@@ -2997,21 +2998,21 @@ def _make_fsm(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
                 sub_sleep_count = self.m.Reg(
                     '_'.join(['', 'sub_sleep_count']), self.addrwidth + 1, initval=0)
 
-                self.fsm.seq.If(sleep_count == sleep - 1)(
+                self.seq.If(sleep_count == sleep - 1)(
                     sub_sleep_count.inc()
                 )
-                self.fsm.seq.If(sleep_count == sleep - 1,
+                self.seq.If(sleep_count == sleep - 1,
                                 sub_sleep_count == sub_sleep - 1)(
                     sub_sleep_count(0)
                 )
                 cond = sub_sleep_count == sub_sleep - 1
             else:
                 cond = None
 
-            self.fsm.seq.If(sleep_count < sleep - 1)(
+            self.seq.If(sleep_count < sleep - 1)(
                 sleep_count.inc()
             )
-            self.fsm.seq.If(cond, sleep_count == sleep - 1)(
+            self.seq.If(cond, sleep_count == sleep - 1)(
                 sleep_count(0)
             )
 
@@ -3155,7 +3156,7 @@ def write(self, fsm, addr, wdata):
         wdata_wire.assign(wdata)
 
         for i in range(num_bytes):
-            self.fsm.seq.If(cond)(
+            self.seq.If(cond)(
                 self.mem[addr + i](wdata_wire[i * 8:i * 8 + 8])
             )
 
@@ -3211,7 +3212,7 @@ def write_word(self, fsm, word_index, byte_offset, wdata, bits=8):
         raw_data_wire.assign(raw_data)
 
         for i in range(num_bytes):
-            self.fsm.seq.If(cond)(
+            self.seq.If(cond)(
                 self.mem[addr + i](raw_data_wire[i * 8:i * 8 + 8])
             )
 
@@ -3351,8 +3352,6 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
         self._make_fsms(write_delay, read_delay, sleep, sub_sleep)
 
     def _make_fsms(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
-        write_mode = 0
-        read_mode = 0
 
         for i, (fsm, waddr, wdata, wresp, raddr, rdata) in enumerate(
                 zip(self.fsms, self.waddrs, self.wdatas, self.wresps, self.raddrs, self.rdatas)):
@@ -3392,12 +3391,8 @@ def _make_fsms(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
                     sleep_count(0)
                 )
 
-            offset = 100 * i
-            while offset <= read_mode + read_delay + 10:
-                offset += 100
-
-            write_mode = offset + 100
-            read_mode = offset + 200
+            write_mode = 100
+            read_mode = 200
             while read_mode <= write_mode + write_delay + 10:
                 read_mode += 100
 
