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Added new example/test codes for ExtRAM/ExtFIFO and RAM/FIFO with Tmp names.
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‎examples/thread_matmul_ext_onchip_ram/Makefile

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

‎examples/thread_matmul_ext_onchip_ram/test_thread_matmul_ext_onchip_ram.py

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_matmul_ext_onchip_ram
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_matmul_ext_onchip_ram.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

‎examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import numpy as np
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.abspath(__file__)))))
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from veriloggen import *
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import veriloggen.thread as vthread
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import veriloggen.types.axi as axi
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datawidth = 8
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addrwidth = 8
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matrix_size = 8
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a_offset = 16
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b_offset = a_offset + matrix_size * matrix_size
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c_offset = b_offset + matrix_size * matrix_size
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def mkLed():
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m = Module('user_module')
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clk = m.Input('clk')
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rst = m.Input('rst')
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start = m.Input('start')
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busy = m.OutputReg('busy', initval=0)
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ram = vthread.ExtRAM(m, 'ram', clk, rst, datawidth, addrwidth)
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def matmul():
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while True:
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wait()
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matrix_size = read_matrix_size()
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offset_a = read_matrix_a_offset()
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offset_b = read_matrix_b_offset()
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offset_c = read_matrix_c_offset()
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comp(matrix_size, offset_a, offset_b, offset_c)
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done()
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def wait():
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while not start:
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pass
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busy.value = 1
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def read_matrix_size():
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size0 = ram.read(0)
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size1 = ram.read(1)
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size = (size1 << 8) | size0
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return size
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def read_matrix_a_offset():
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offset0 = ram.read(4) & 0xff
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offset1 = ram.read(5) & 0xff
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offset = (offset1 << 8) | offset0
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return offset
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def read_matrix_b_offset():
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offset0 = ram.read(8) & 0xff
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offset1 = ram.read(9) & 0xff
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offset = (offset1 << 8) | offset0
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return offset
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def read_matrix_c_offset():
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offset0 = ram.read(12) & 0xff
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offset1 = ram.read(13) & 0xff
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offset = (offset1 << 8) | offset0
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return offset
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def comp(matrix_size, a_offset, b_offset, c_offset):
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a_addr, c_addr = a_offset, c_offset
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for i in range(matrix_size):
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b_addr = b_offset
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for j in range(matrix_size):
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sum = 0
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for k in range(matrix_size):
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x = ram.read(a_addr + k)
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y = ram.read(b_addr + k)
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sum += x * y
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ram.write(c_addr + j, sum)
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b_addr += matrix_size * (datawidth // 8)
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a_addr += matrix_size * (datawidth // 8)
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c_addr += matrix_size * (datawidth // 8)
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def done():
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busy.value = 0
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th = vthread.Thread(m, 'th_matmul', clk, rst, matmul, datawidth=16)
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fsm = th.start()
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return m
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def mkTest(memimg_name=None):
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a_shape = (matrix_size, matrix_size)
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b_shape = (matrix_size, matrix_size)
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c_shape = (a_shape[0], b_shape[0])
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n_raw_a = axi.shape_to_length(a_shape)
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n_raw_b = axi.shape_to_length(b_shape)
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n_a = axi.shape_to_memory_size(a_shape, datawidth)
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n_b = axi.shape_to_memory_size(b_shape, datawidth)
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a = np.zeros(a_shape, dtype=np.int64)
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b = np.zeros(b_shape, dtype=np.int64)
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value = 1
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for y in range(a_shape[0]):
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for x in range(a_shape[1]):
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if x == y:
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a[y][x] = value
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value += 1
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else:
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a[y][x] = 0
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for y in range(b_shape[0]):
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for x in range(b_shape[1]):
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if x == y:
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b[y][x] = 2
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else:
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b[y][x] = 0
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a_addr = a_offset
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size_a = n_a * datawidth // 8
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b_addr = b_offset
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size_b = n_b * datawidth // 8
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mem = np.zeros([2 ** addrwidth * (8 // datawidth)], dtype=np.int64)
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axi.set_memory(mem, a, datawidth, datawidth, a_addr)
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axi.set_memory(mem, b, datawidth, datawidth, b_addr)
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led = mkLed()
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m = Module('test')
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['clk']
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rst = ports['rst']
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start = ports['start']
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busy = ports['busy']
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start.initval = 0
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memory = vthread.RAM(m, 'memory', clk, rst, datawidth, addrwidth,
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numports=2, initvals=mem.tolist())
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memory.connect_rtl(0, ports['ram_0_addr'], ports['ram_0_wdata'],
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ports['ram_0_wenable'], ports['ram_0_rdata'],
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ports['ram_0_enable'])
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# Timer
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counter = m.Reg('counter', 32, initval=0)
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seq = Seq(m, 'seq', clk, rst)
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seq(
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counter.inc()
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)
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def ctrl():
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for i in range(100):
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pass
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awaddr = 0
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v = (matrix_size & 0xff)
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print('# matrix_size[7:0] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 1
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v = ((matrix_size >> 8) & 0xff)
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print('# matrix_size[15:8] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 4
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v = (a_offset & 0xff)
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print('# a_offset[7:0] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 5
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v = ((a_offset >> 8) & 0xff)
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print('# a_offset[15:8] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 8
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v = (b_offset & 0xff)
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print('# b_offset[7:0] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 9
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v = ((b_offset >> 8) & 0xff)
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print('# b_offset[15:8] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 12
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v = (c_offset & 0xff)
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print('# c_offset[7:0] = %d' % v)
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memory.write(awaddr, v, port=1)
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awaddr = 13
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v = ((c_offset >> 8) & 0xff)
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print('# c_offset[15:8] = %d' % v)
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memory.write(awaddr, v, port=1)
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start_time = counter
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print('# start time = %d' % start_time)
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start.value = 1
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for _ in range(10):
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pass
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start.value = 0
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while True:
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if not busy:
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break
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end_time = counter
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print('# end time = %d' % end_time)
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time = end_time - start_time
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print('# exec time = %d' % time)
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all_ok = True
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for y in range(matrix_size):
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for x in range(matrix_size):
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v = memory.read(
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c_offset + (y * matrix_size + x) * datawidth // 8, port=1)
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if y == x and vthread.verilog.NotEql(v, (y + 1) * 2):
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all_ok = False
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print("NG [%d,%d] = %d" % (y, x, v))
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if y != x and vthread.verilog.NotEql(v, 0):
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all_ok = False
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print("NG [%d,%d] = %d" % (y, x, v))
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if all_ok:
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print('# verify: PASSED')
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else:
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print('# verify: FAILED')
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vthread.finish()
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th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl)
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fsm = th.start()
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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# vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
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# simulation.setup_waveform(m, uut, dumpfile=vcd_name)
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000000),
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Systask('finish'),
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)
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# return m
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# for VCD dump
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top = Module('top')
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uut = Submodule(top, m, name='test')
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vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
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simulation.setup_waveform(top, uut, dumpfile=vcd_name)
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return top
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def run(filename='tmp.v', simtype='iverilog', outputfile=None):
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if outputfile is None:
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outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
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memimg_name = 'memimg_' + outputfile
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test = mkTest(memimg_name=memimg_name)
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if filename is not None:
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test.to_verilog(filename)
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sim = simulation.Simulator(test, sim=simtype)
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rslt = sim.run(outputfile=outputfile)
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lines = rslt.splitlines()
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if simtype == 'verilator' and lines[-1].startswith('-'):
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rslt = '\n'.join(lines[:-1])
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return rslt
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if __name__ == '__main__':
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rslt = run(filename='tmp.v')
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print(rslt)

‎tests/extension/thread_/ext_fifo/Makefile

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

‎tests/extension/thread_/ext_fifo/test_thread_ext_fifo.py

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_ext_fifo
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_ext_fifo.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

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