All setup_waveform lines are commented out.

Author: shtaxxx

tests/core/submodule_/get/submodule_get.py

@@ -89,7 +89,7 @@ def mkTest():
     clk = uut['CLK']
     rst = uut['RST']
 
-    simulation.setup_waveform(m, uut, m.get_vars())
+    # simulation.setup_waveform(m, uut, m.get_vars())
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/core/submodule_/get/test_submodule_get.py

@@ -28,12 +28,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, top, top_CLK, top_RST, top_LED, top_inst_blinkled_dummy_out0, top_inst_blinkled_dummy_in0);
-  end
-
-
   initial begin
     top_CLK = 0;
     forever begin

tests/core/submodule_/getattr/submodule_getattr.py

@@ -82,7 +82,7 @@ def mkTest():
     clk = uut.CLK
     rst = uut.RST
 
-    simulation.setup_waveform(m, uut, m.get_vars())
+    # simulation.setup_waveform(m, uut, m.get_vars())
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/core/submodule_/getattr/test_submodule_getattr.py

@@ -28,12 +28,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, top, top_CLK, top_RST, top_LED, top_inst_blinkled_dummy_out0, top_inst_blinkled_dummy_in0);
-  end
-
-
   initial begin
     top_CLK = 0;
     forever begin

tests/core/submodule_/sim/submodule_sim.py

@@ -81,7 +81,7 @@ def mkTest():
     clk = uut['CLK']
     rst = uut['RST']
 
-    simulation.setup_waveform(m, uut, m.get_vars())
+    # simulation.setup_waveform(m, uut, m.get_vars())
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/core/submodule_/sim/test_submodule_sim.py

@@ -25,12 +25,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, top, top_CLK, top_RST, top_LED, top_inst_blinkled_dummy_out0, top_inst_blinkled_dummy_in0);
-  end
-
-
   initial begin
     top_CLK = 0;
     forever begin

tests/extension/fsm_/as_module_delayed/fsm_as_module_delayed.py

@@ -54,7 +54,7 @@ def mkTest():
     uut = m.Instance(mkLed(), 'uut',
                      ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
 
-    simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, period=100)
 

tests/extension/fsm_/as_module_delayed/test_fsm_as_module_delayed.py

@@ -19,12 +19,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, uut);
-  end
-
-
   initial begin
     CLK = 0;
     forever begin

tests/extension/fsm_/delayed/fsm_delayed.py

@@ -4,18 +4,20 @@
 import os
 
 # the next line can be removed after installation
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
 
 from veriloggen import *
 
+
 def mkLed():
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
     valid = m.OutputReg('valid', initval=0)
 
     fsm = FSM(m, 'fsm', clk, rst)
-    
+
     for i in range(2):
         fsm.goto_next()
 
@@ -26,7 +28,7 @@ def mkLed():
     fsm.Delay(1)(
         valid(0)
     )
-    
+
     for i in range(4):
         fsm.goto_next()
 
@@ -39,11 +41,12 @@ def mkLed():
             valid(0)
         )
         fsm.goto_next()
-    
+
     fsm.make_always()
 
     return m
 
+
 def mkTest():
     m = Module('test')
     clk = m.Reg('CLK')
@@ -53,7 +56,7 @@ def mkTest():
     uut = m.Instance(mkLed(), 'uut',
                      ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
 
-    simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, period=100)
 
@@ -63,7 +66,8 @@ def mkTest():
     )
 
     return m
-    
+
+
 if __name__ == '__main__':
     test = mkTest()
     verilog = test.to_verilog('tmp.v')

tests/extension/fsm_/delayed/test_fsm_delayed.py

@@ -19,12 +19,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, uut);
-  end
-
-
   initial begin
     CLK = 0;
     forever begin
@@ -162,6 +156,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = fsm_delayed.mkTest()

tests/extension/fsm_/delayed_cond/fsm_delayed_cond.py

@@ -4,19 +4,21 @@
 import os
 
 # the next line can be removed after installation
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
 
 from veriloggen import *
 
+
 def mkLed():
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
     valid = m.OutputReg('valid', initval=0)
     count = m.Reg('count', width=32, initval=0)
-    
+
     fsm = FSM(m, 'fsm', clk, rst)
-    
+
     for i in range(4):
         fsm.goto_next()
 
@@ -32,7 +34,7 @@ def mkLed():
         valid(0)
     )
     fsm.If(c).goto_next()
-    
+
     for i in range(8):
         fsm.goto_next()
 
@@ -50,10 +52,11 @@ def mkLed():
         )
         fsm.If(c).goto_next()
 
-    fsm.make_always(reset=[count.reset()], body=[count(count+1)])
-        
+    fsm.make_always(reset=[count.reset()], body=[count(count + 1)])
+
     return m
 
+
 def mkTest():
     m = Module('test')
     clk = m.Reg('CLK')
@@ -63,7 +66,7 @@ def mkTest():
     uut = m.Instance(mkLed(), 'uut',
                      ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
 
-    simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, period=100)
 
@@ -73,7 +76,8 @@ def mkTest():
     )
 
     return m
-    
+
+
 if __name__ == '__main__':
     test = mkTest()
     verilog = test.to_verilog('tmp.v')

tests/extension/fsm_/delayed_cond/test_fsm_delayed_cond.py

@@ -19,12 +19,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, uut);
-  end
-
-
   initial begin
     CLK = 0;
     forever begin

tests/extension/fsm_/delayed_eager_val/fsm_delayed_eager_val.py

@@ -4,27 +4,29 @@
 import os
 
 # the next line can be removed after installation
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
 
 from veriloggen import *
 
+
 def mkLed():
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
     valid = m.Output('valid')
     count = m.Reg('count', width=32, initval=0)
-    
+
     valid_reg = m.Reg('valid_reg', 8, initval=0)
     m.Assign(valid(valid_reg[0]))
-    
+
     up = m.Wire('up')
     down = m.Wire('down')
     m.Assign(up(1))
     m.Assign(down(0))
-    
+
     fsm = FSM(m, 'fsm', clk, rst)
-    
+
     for i in range(4):
         fsm.goto_next()
 
@@ -40,7 +42,7 @@ def mkLed():
         valid_reg(down)
     )
     fsm.If(c).goto_next()
-    
+
     for i in range(8):
         fsm.goto_next()
 
@@ -57,11 +59,12 @@ def mkLed():
             valid_reg(down)
         )
         fsm.If(c).goto_next()
-    
-    fsm.make_always(reset=[count.reset()], body=[count(count+1)])
+
+    fsm.make_always(reset=[count.reset()], body=[count(count + 1)])
 
     return m
 
+
 def mkTest():
     m = Module('test')
     clk = m.Reg('CLK')
@@ -71,7 +74,7 @@ def mkTest():
     uut = m.Instance(mkLed(), 'uut',
                      ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
 
-    simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, period=100)
 
@@ -81,7 +84,8 @@ def mkTest():
     )
 
     return m
-    
+
+
 if __name__ == '__main__':
     test = mkTest()
     verilog = test.to_verilog('tmp.v')

tests/extension/fsm_/delayed_eager_val/test_fsm_delayed_eager_val.py

@@ -19,12 +19,6 @@
   );
 
 
-  initial begin
-    $dumpfile("uut.vcd");
-    $dumpvars(0, uut);
-  end
-
-
   initial begin
     CLK = 0;
     forever begin