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ExtFIFO class is introduced to utilize an external FIFO. Signal types of itype and otype are now customizable. The use of connect_ports method replaced with dedicated signal-name pairs.
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veriloggen/thread/fifo.py

Lines changed: 94 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,11 @@ class FIFO(_MutexFunction):
1818
'is_empty', 'is_almost_empty',
1919
'is_full', 'is_almost_full') + _MutexFunction.__intrinsics__
2020

21-
def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=4, sync=True):
21+
def __init__(self, m, name, clk, rst,
22+
datawidth=32, addrwidth=4, sync=True,
23+
external_write=False, external_read=False,
24+
itype='Wire', otype='Wire',
25+
ext_itype='Input', ext_otype='Output'):
2226

2327
self.m = m
2428
self.name = name
@@ -29,20 +33,44 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=4, sync=True):
2933
self.addrwidth = addrwidth
3034
self.sync = sync
3135

32-
self.wif = FifoWriteInterface(self.m, name, datawidth, itype='Wire', otype='Wire')
33-
self.rif = FifoReadInterface(self.m, name, datawidth, itype='Wire', otype='Wire')
36+
if external_write:
37+
self.wif = FifoWriteInterface(self.m, name, datawidth,
38+
itype=ext_itype, otype=ext_otype)
39+
else:
40+
self.wif = FifoWriteInterface(self.m, name, datawidth,
41+
itype=itype, otype=otype)
42+
43+
if external_read:
44+
self.rif = FifoReadInterface(self.m, name, datawidth,
45+
itype=ext_itype, otype=ext_otype)
46+
else:
47+
self.rif = FifoReadInterface(self.m, name, datawidth,
48+
itype=itype, otype=otype)
3449

3550
# default values
36-
self.wif.enq.assign(0)
37-
self.wif.wdata.assign(vtypes.IntX())
38-
self.rif.deq.assign(0)
51+
if not external_write:
52+
self.wif.enq.assign(0)
53+
self.wif.wdata.assign(vtypes.IntX())
54+
55+
if not external_read:
56+
self.rif.deq.assign(0)
3957

4058
self.definition = mkFifoDefinition(name, datawidth, addrwidth, sync=sync)
4159

4260
ports = collections.OrderedDict()
4361
ports['CLK'] = self.clk
4462
ports['RST'] = self.rst
45-
ports.update(m.connect_ports(self.definition))
63+
64+
ports[name + '_enq'] = self.wif.enq
65+
ports[name + '_wdata'] = self.wif.wdata
66+
ports[name + '_full'] = self.wif.full
67+
ports[name + '_almost_full'] = self.wif.almost_full
68+
69+
ports[name + '_deq'] = self.rif.deq
70+
ports[name + '_rdata'] = self.rif.rdata
71+
ports[name + '_empty'] = self.rif.empty
72+
ports[name + '_almost_empty'] = self.rif.almost_empty
73+
4674
self.inst = self.m.Instance(self.definition, 'inst_' + name,
4775
ports=ports)
4876

@@ -70,6 +98,25 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=4, sync=True):
7098
def _id(self):
7199
return id(self)
72100

101+
def connect_enq_rtl(self, enq, wdata, full=None, almost_full=None):
102+
""" connect native signals to the internal FIFO interface """
103+
util.overwrite_assign(self.wif.enq, enq)
104+
util.overwrite_assign(self.wif.wdata, wdata)
105+
if full is not None:
106+
full.connect(self.wif.full)
107+
if almost_full is not None:
108+
almost_full.connect(self.wif.almost_full)
109+
110+
def connect_deq_rtl(self, deq, rdata=None, empty=None, almost_empty=None):
111+
""" connect native signals to the internal FIFO interface """
112+
util.overwrite_assign(self.rif.deq, deq)
113+
if rdata is not None:
114+
rdata.connect(self.rif.rdata)
115+
if empty is not None:
116+
empty.connect(self.rif.empty)
117+
if almost_empty is not None:
118+
almost_empty.connect(self.rif.almost_empty)
119+
73120
def enq_rtl(self, wdata, cond=None):
74121
""" Enque """
75122

@@ -229,10 +276,16 @@ def is_full(self, fsm):
229276
class FixedFIFO(FIFO):
230277

231278
def __init__(self, m, name, clk, rst,
232-
datawidth=32, addrwidth=4, point=0):
279+
datawidth=32, addrwidth=4, point=0, sync=True,
280+
external_write=False, external_read=False,
281+
itype='Wire', otype='Wire',
282+
ext_itype='Input', ext_otype='Output'):
233283

234284
FIFO.__init__(self, m, name, clk, rst,
235-
datawidth, addrwidth)
285+
datawidth, addrwidth, sync,
286+
external_read, external_write,
287+
itype, otype,
288+
ext_itype, ext_otype)
236289

237290
self.point = point
238291

@@ -264,3 +317,35 @@ def try_deq(self, fsm, raw=False):
264317
if raw:
265318
return raw_data, raw_valid
266319
return fxd.reinterpret_cast_to_fixed(raw_data, self.point), raw_valid
320+
321+
322+
class ExtFIFO(FIFO):
323+
""" Only external FIFO interface is synthesized. No FIFO instance is synthesized."""
324+
325+
def __init__(self, m, name, clk, rst,
326+
datawidth=32, addrwidth=4, sync=True,
327+
itype='Output', otype='Input'):
328+
329+
self.m = m
330+
self.name = name
331+
self.clk = clk
332+
self.rst = rst
333+
334+
self.datawidth = datawidth
335+
self.addrwidth = addrwidth
336+
self.sync = sync
337+
338+
self.wif = FifoWriteInterface(self.m, name, datawidth,
339+
itype=itype, otype=otype)
340+
341+
self.rif = FifoReadInterface(self.m, name, datawidth,
342+
itype=itype, otype=otype)
343+
344+
# default values
345+
self.wif.enq.assign(0)
346+
self.wif.wdata.assign(vtypes.IntX())
347+
self.rif.deq.assign(0)
348+
349+
self.seq = Seq(m, name, clk, rst)
350+
351+
self.mutex = None

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