Merge branch 'feature_setup' into develop

Author: shtaxxx

MANIFEST.in

@@ -5,7 +5,8 @@ include .travis.yml
 include Makefile
 include docker/Dockerfile
 include hello_led.py
-recursive-include utils *
+include veriloggen/Makefile
+include veriloggen/VERSION
 recursive-include tests *
 recursive-include examples *
 recursive-include img *

setup.cfg

@@ -1,19 +1,15 @@
 from setuptools import setup, find_packages
 
-import re
 import os
 
 
 def read(filename):
-    return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read()
+    # return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read()
+    return open(os.path.join(os.path.dirname(__file__), filename)).read()
 
 
-m = re.search(r'(\d+\.\d+\.\d+(-.+)?)',
-              read('veriloggen/utils/VERSION').splitlines()[0])
-version = m.group(1) if m is not None else '0.0.0'
-
 setup(name='veriloggen',
-      version=version,
+      version=read('veriloggen/VERSION'),
       description='A Mixed-Paradigm Hardware Construction Framework',
       long_description=read('README.md'),
       long_description_content_type="text/markdown",
@@ -22,8 +18,9 @@ def read(filename):
       license="Apache License 2.0",
       url='https://github.com/PyHDI/veriloggen',
       packages=find_packages(),
-      package_data={'veriloggen.utils': ['VERSION'],
-                    'veriloggen.simulation': ['*.cpp'], },
+      package_data={'veriloggen': ['VERSION'],
+                    'veriloggen.simulation': ['*.cpp'],
+                    },
       install_requires=['Jinja2>=2.10',
                         'pyverilog>=1.2.0',
                         'numpy>=1.17'],

setup.py

@@ -19,8 +19,13 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
-# expand the recursive call limit for python 3.6 and later
+import os
 import sys
+
+
+__version__ = open(os.path.join(os.path.dirname(__file__), "VERSION")).read().splitlines()[0]
+
+# expand the recursive call limit for python 3.6 and later
 sys.setrecursionlimit(1000 * 10)
 
 # Verilog HDL Core