lib-interface is an example of how to use Interface abstraction.

Author: shtaxxx

sample/Makefile

@@ -3,6 +3,4 @@ all: clean
 
 .PHONY: clean
 clean:
-	make clean -C bram
-	make clean -C led
-	make clean -C test
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 

sample/bram/bram.py

@@ -7,25 +7,30 @@
 #-------------------------------------------------------------------------------
 # BRAM interface
 #-------------------------------------------------------------------------------
-class BramInterface(Interface):
-    def __init__(self, m, prefix='', postfix='', addrwidth=10, datawidth=32, direction='in'):
-        Interface.__init__(self, m, prefix, postfix)
+class BramInterface(lib.Interface):
+    def __init__(self, m, prefix='', postfix='', addrwidth=10, datawidth=32, direction='child'):
+        lib.Interface.__init__(self, m, prefix, postfix)
 
-        if direction != 'in' and direction != 'out':
-            raise ValueError("direction should be 'in or 'out''")
+        if direction != 'child' and direction != 'parent':
+            raise ValueError("direction should be 'in or 'parent''")
         self.direction = direction
 
         self.addrwidth = self.Parameter('ADDR_WIDTH', addrwidth)
         self.datawidth = self.Parameter('DATA_WIDTH', datawidth)
 
-        In = self.Input if self.direction == 'in' else self.Reg # self.Wire
-        Out = self.Output if self.direction == 'in' else self.Wire 
+        In = self.Input if self.direction == 'child' else self.Reg # self.Wire
+        Out = self.Output if self.direction == 'child' else self.Wire 
 
         self.addr = In('addr', addrwidth)
         self.datain = In('datain', datawidth)
         self.write = In('write')
         self.dataout = Out('dataout', datawidth)
-    
+
+    def init(self):
+        if self.direction == 'parent':
+            return self.addr(0), self.datain(0), self.write(0)
+        raise Exception("init() is not allowed.")
+        
 #-------------------------------------------------------------------------------
 # BRAM module
 #-------------------------------------------------------------------------------
@@ -36,7 +41,7 @@ def mkBram(name):
     datawidth = m.Parameter('DATA_WIDTH', 32)
 
     clk = m.Input('CLK')
-    bramif = BramInterface(m, addrwidth=addrwidth, datawidth=datawidth, direction='in')
+    bramif = BramInterface(m, addrwidth=addrwidth, datawidth=datawidth, direction='child')
 
     d_addr = m.Reg('d_' + bramif.addr.name, datawidth)
     mem = m.Reg('mem', datawidth, Int(2)**addrwidth)
@@ -61,7 +66,7 @@ def mkTop():
     rst = m.Input('RST')
 
     bramif = BramInterface(m, prefix='bram_',
-                           addrwidth=addrwidth, datawidth=datawidth, direction='out')
+                           addrwidth=addrwidth, datawidth=datawidth, direction='parent')
 
     params = collections.OrderedDict()
     params.update(bramif.connect_all_parameters())
@@ -76,7 +81,7 @@ def mkTop():
     fsm = lib.FSM(m, 'fsm')
     init = fsm.get_index()
 
-    fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() )
+    fsm( bramif.init(), fsm.next() )
     first = fsm.get_index()
 
     fsm( bramif.datain(bramif.datain + 4), fsm.next() )

sample/test/Makefile

@@ -1,15 +1,7 @@
 .PHONY: clean
 clean:
-	make clean -C cat
-	make clean -C class
-	make clean -C function
-	make clean -C lib-fsm
-	make clean -C slice
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 
 
 .PHONY: test
 test:
-	make test -C cat
-	make test -C class
-	make test -C function
-	make test -C lib-fsm
-	make test -C slice
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {} 

sample/test/lib-interface/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/lib-interface/led.py

@@ -0,0 +1,79 @@
+import sys
+import os
+import collections
+
+from veriloggen import *
+
+class LedInterface(lib.Interface):
+    def __init__(self, m, prefix='', postfix='', width=8, maxvalue=1024, direction='child'):
+        lib.Interface.__init__(self, m, prefix, postfix)
+
+        if direction != 'child' and direction != 'parent':
+            raise ValueError("direction should be 'in or 'parent''")
+        self.direction = direction
+
+        self.width = width
+        self.maxvalue = maxvalue
+        
+        In = self.Input if self.direction == 'child' else self.Wire
+        Out = self.OutputReg if self.direction == 'child' else self.Output
+
+        self.led = Out('LED', self.width)
+        if direction == 'child':
+            self.count = self.Reg('count', 32)
+
+    def init(self):
+        if self.direction == 'child':
+            return self.count(0), self.led(0)
+        raise Exception("init() is not allowed.")
+
+    def step(self):
+        ret = If( self.count == self.maxvalue -1 )(
+            self.count( 0 ),
+            self.led( self.led + 1 )
+        ).Else(
+            self.count( self.count + 1 )
+        )
+        return ret
+    
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    ledif = LedInterface(m, width=width, direction='child')
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            *ledif.init()
+
+        ).Else(
+            ledif.step()
+        ))
+
+    return m
+
+def mkTop(wid=8):
+    m = Module('top')
+    width = m.Parameter('WIDTH', wid)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    ledif = LedInterface(m, width=width, direction='parent')
+    
+    params = collections.OrderedDict()
+    params.update(width.connect())
+    params.update(ledif.connect_all_parameters())
+    
+    ports = collections.OrderedDict()
+    ports.update(clk.connect())
+    ports.update(rst.connect())
+    ports.update(ledif.connect_all_ports())
+    
+    m.Instance(mkLed(), 'inst_led', params, ports)
+    
+    return m
+
+if __name__ == '__main__':
+    led_module = mkTop()
+    led_code = led_module.to_verilog()
+    print(led_code)

sample/test/lib-interface/test_led.py

@@ -0,0 +1,62 @@
+import led
+
+expected_verilog = """
+module top # 
+  (
+   parameter WIDTH = 8
+   )
+  (
+   input CLK, 
+   input RST, 
+   output [WIDTH-1:0] LED
+   );
+  blinkled #
+    ( 
+      .WIDTH(WIDTH) 
+    )
+  inst_led
+    ( 
+      .CLK(CLK),
+      .RST(RST),
+      .LED(LED)
+    );
+endmodule
+
+module blinkled #
+  (
+   parameter WIDTH = 8
+   )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+   );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+         count <= 0;
+         LED <= LED + 1;
+      end else begin
+         count <= count + 1;
+      end
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkTop()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(led_code == expected_code)

sample/test/lib-interface/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen

veriloggen/__init__.py

@@ -16,7 +16,6 @@
 import vtypes
 
 from module import Module
-from interface import Interface
 from function import Function
 from vtypes import *
 

veriloggen/lib/__init__.py

@@ -1,5 +1,16 @@
+#-------------------------------------------------------------------------------
+# lib/__init__.py
+#
+# Veriloggen library
+# 
+# Copyright (C) 2015, Shinya Takamaeda-Yamazaki
+# License: Apache 2.0
+#-------------------------------------------------------------------------------
+
 import os
 import sys
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 
+## Please add import notations here for additional library
+from interface import Interface
 from fsm import FSM

veriloggen/lib/fsm.py

@@ -1,11 +1,11 @@
 import os
 import sys
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
-
 import collections
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 import vtypes
 
-class FSM(object):
+class FSM(vtypes.VeriloggenNode):
     """ Finite State Machine Generator """
     def __init__(self, m, name, width=32, initname='init'):
         self.m = m

veriloggen/interface.py renamed to veriloggen/lib/interface.py

@@ -2,8 +2,7 @@
 import sys
 import collections
 import re
-
-sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 
 import vtypes
 import module