Sample include path is updated.

shtaxxx · shtaxxx · commit 688fc133ad8d · 2015-06-26T11:11:05.000+09:00
diff --git a/sample/bram/bram.py b/sample/bram/bram.py
@@ -1,7 +1,5 @@
 import sys
 import os
-
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 from veriloggen import *
 
 def mkBramInterface(m, addrwidth, datawidth):
diff --git a/sample/bram/veriloggen b/sample/bram/veriloggen
@@ -0,0 +1 @@
+../../veriloggen
diff --git a/sample/led/led.py b/sample/led/led.py
@@ -1,7 +1,5 @@
 import sys
 import os
-
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 from veriloggen import *
 
 def mkLed():
diff --git a/sample/led/veriloggen b/sample/led/veriloggen
@@ -0,0 +1 @@
+../../veriloggen
