Skip to content

Commit 5aca33d

Browse files
committed
pipeline test
1 parent d7f6340 commit 5aca33d

File tree

4 files changed

+88
-0
lines changed

4 files changed

+88
-0
lines changed

sample/test/pipeline/Makefile

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
TARGET=led.py
2+
TEST=test_led.py
3+
ARGS=
4+
5+
PYTHON=python3
6+
#PYTHON=python
7+
#OPT=-m pdb
8+
#OPT=-m cProfile -s time
9+
#OPT=-m cProfile -o profile.rslt
10+
11+
.PHONY: all
12+
all: test
13+
14+
.PHONY: run
15+
run:
16+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
17+
18+
.PHONY: test
19+
test:
20+
$(PYTHON) -m pytest -vv $(TEST)
21+
22+
.PHONY: check
23+
check:
24+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
25+
iverilog -tnull -Wall tmp.v
26+
rm -f tmp.v
27+
28+
.PHONY: clean
29+
clean:
30+
rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/pipeline/led.py

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
import sys
2+
import os
3+
from veriloggen import *
4+
5+
def mkLed(pipe=True):
6+
m = Module('blinkled')
7+
width = m.Parameter('WIDTH', 8)
8+
clk = m.Input('CLK')
9+
rst = m.Input('RST')
10+
led = m.Output('LED', width)
11+
12+
value = m.Reg('value', width) if pipe else m.Wire('value', width)
13+
next_value = value(10)
14+
15+
if pipe: m.Always(Posedge(clk))( next_value )
16+
else: m.Assign( next_value )
17+
18+
m.Assign(led(value))
19+
return m
20+
21+
if __name__ == '__main__':
22+
led = mkLed(True)
23+
# led.to_verilog(filename='tmp.v')
24+
verilog = led.to_verilog()
25+
print(verilog)

sample/test/pipeline/test_led.py

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
import led
2+
3+
expected_verilog = """
4+
module blinkled #
5+
(
6+
parameter WIDTH = 8
7+
)
8+
(
9+
input CLK,
10+
input RST,
11+
output [WIDTH-1:0] LED
12+
);
13+
reg [WIDTH-1:0] value;
14+
always @(posedge CLK) begin
15+
value <= 10;
16+
end
17+
assign LED = value;
18+
endmodule
19+
"""
20+
21+
def test_led():
22+
led_module = led.mkLed()
23+
led_code = led_module.to_verilog()
24+
25+
from pyverilog.vparser.parser import VerilogParser
26+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
27+
parser = VerilogParser()
28+
expected_ast = parser.parse(expected_verilog)
29+
codegen = ASTCodeGenerator()
30+
expected_code = codegen.visit(expected_ast)
31+
32+
assert(expected_code == led_code)

sample/test/pipeline/veriloggen

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
../../../veriloggen

0 commit comments

Comments
 (0)