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+ TARGET =led.py
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+ TEST =test_led.py
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+ ARGS =
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+
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+ PYTHON =python3
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+ # PYTHON=python
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+ # OPT=-m pdb
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+ # OPT=-m cProfile -s time
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+ # OPT=-m cProfile -o profile.rslt
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+
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+ .PHONY : all
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+ all : test
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+
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+ .PHONY : run
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+ run :
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+ $(PYTHON ) $(OPT ) $(TARGET ) $(ARGS )
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+
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+ .PHONY : test
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+ test :
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+ $(PYTHON ) -m pytest -vv $(TEST )
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+
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+ .PHONY : check
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+ check :
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+ $(PYTHON ) $(OPT ) $(TARGET ) $(ARGS ) > tmp.v
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+ iverilog -tnull -Wall tmp.v
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+ rm -f tmp.v
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+
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+ .PHONY : clean
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+ clean :
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+ rm -rf * .pyc __pycache__ parsetab.py * .out
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+ import sys
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+ import os
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+ from veriloggen import *
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+
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+ def mkLed (pipe = True ):
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+ m = Module ('blinkled' )
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+ width = m .Parameter ('WIDTH' , 8 )
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+ clk = m .Input ('CLK' )
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+ rst = m .Input ('RST' )
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+ led = m .Output ('LED' , width )
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+
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+ value = m .Reg ('value' , width ) if pipe else m .Wire ('value' , width )
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+ next_value = value (10 )
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+
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+ if pipe : m .Always (Posedge (clk ))( next_value )
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+ else : m .Assign ( next_value )
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+
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+ m .Assign (led (value ))
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+ return m
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+
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+ if __name__ == '__main__' :
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+ led = mkLed (True )
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+ # led.to_verilog(filename='tmp.v')
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+ verilog = led .to_verilog ()
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+ print (verilog )
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+ import led
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+
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+ expected_verilog = """
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+ module blinkled #
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+ (
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+ parameter WIDTH = 8
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+ )
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+ (
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+ input CLK,
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+ input RST,
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+ output [WIDTH-1:0] LED
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+ );
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+ reg [WIDTH-1:0] value;
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+ always @(posedge CLK) begin
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+ value <= 10;
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+ end
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+ assign LED = value;
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+ endmodule
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+ """
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+
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+ def test_led ():
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+ led_module = led .mkLed ()
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+ led_code = led_module .to_verilog ()
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+
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+ from pyverilog .vparser .parser import VerilogParser
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+ from pyverilog .ast_code_generator .codegen import ASTCodeGenerator
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+ parser = VerilogParser ()
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+ expected_ast = parser .parse (expected_verilog )
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+ codegen = ASTCodeGenerator ()
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+ expected_code = codegen .visit (expected_ast )
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+
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+ assert (expected_code == led_code )
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+ ../../../veriloggen
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