sorting network

Author: shtaxxx

sample/sort/Makefile

@@ -0,0 +1,30 @@
+TARGET=sort.py
+TEST=test_sort.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/sort/sim_sort.v

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+
+module test;
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut);
+  end
+
+  parameter WIDTH = 32;
+  
+  reg CLK;
+  reg RST;
+  reg [(WIDTH - 1):0] input_0;
+  reg [(WIDTH - 1):0] input_1;
+  reg [(WIDTH - 1):0] input_2;
+  reg [(WIDTH - 1):0] input_3;
+  wire [(WIDTH - 1):0] output_0;
+  wire [(WIDTH - 1):0] output_1;
+  wire [(WIDTH - 1):0] output_2;
+  wire [(WIDTH - 1):0] output_3;
+  reg kick;
+  wire busy;
+      
+  sort uut(
+           CLK,
+           RST,
+           input_0,
+           input_1,
+           input_2,
+           input_3,
+           output_0,
+           output_1,
+           output_2,
+           output_3,
+           kick,
+           busy
+           );
+
+  initial begin
+    CLK = 0;
+    forever #5 CLK = ~CLK;
+  end
+
+  initial begin
+    RST = 0;
+    kick = 0;
+    input_0 = 4;
+    input_1 = 3;
+    input_2 = 2;
+    input_3 = 1;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    
+    @(posedge CLK);
+    #1;
+    
+    @(posedge CLK);
+    #1;
+    
+    @(posedge CLK);
+    #1;
+
+    kick = 1;
+
+    @(posedge CLK);
+    #1;
+
+    kick = 0;
+
+    #500;
+    $finish;
+  end
+  
+endmodule

sample/sort/sort.py

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+import sys
+import os
+from veriloggen import *
+
+def mkSort(numports=4):
+    m = Module('sort')
+    width = m.Parameter('WIDTH', 32)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    inputs = [ m.Input('input_' + str(i), width) for i in range(numports) ] 
+    outputs = [ m.Output('output_' + str(i), width) for i in range(numports) ]
+    kick = m.Input('kick')
+    busy = m.OutputReg('busy')
+    registers = [ m.Reg('registers_' + str(i), width) for i in range(numports) ]
+    for i in range(numports): m.Assign(outputs[i](registers[i]))
+    
+    _i = [0]
+    def mk_pair():
+        s = m.Wire('small_' + str(_i[0]), width)
+        l = m.Wire('large_' + str(_i[0]), width)
+        _i[0] += 1
+        return s, l
+
+    def prim_net(a, b):
+        s, l = mk_pair()
+        m.Assign(s( Cond(a < b, a, b) )) # small
+        m.Assign(l( Cond(a < b, b, a) )) # large
+        return s, l
+
+    def chain_net(regs, fsm, e):
+        x = regs[0]
+        bind = []
+        for i in range(e):
+            s, l = prim_net(x, regs[i+1])
+            bind.append( regs[i](s) )
+            x = l
+        bind.append( regs[e](x) )
+        for i in range(e + 1, len(regs)):
+            bind.append( regs[i](regs[i]) )
+        fsm( bind, fsm.next() )
+    
+    fsm = lib.FSM(m, 'fsm')
+    idle = fsm.get_index()
+
+    fsm([ If(kick)([ registers[i](inputs[i]) for i in range(numports) ] +
+                   [ busy(1), fsm.next()] ) ])
+
+    for i in range(numports):
+        chain_net(registers, fsm, numports-i-1)
+
+    fsm( busy(0), fsm.goto(idle) )
+
+    init = [ busy(0) ] + [ r(0) for r in registers ] + [ fsm.init() ]
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            *init
+        ).Else(
+            fsm.to_case()
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkSort()
+    verilog = led.to_verilog()
+    print(verilog)

sample/sort/test_sort.py

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+import sort
+
+expected_verilog = """
+module sort #
+ (
+  parameter WIDTH = 32
+ )
+ (
+  input CLK,
+  input RST,
+  input [WIDTH-1:0] input_0,
+  input [WIDTH-1:0] input_1,
+  input [WIDTH-1:0] input_2,
+  input [WIDTH-1:0] input_3,
+  output [WIDTH-1:0] output_0,
+  output [WIDTH-1:0] output_1,
+  output [WIDTH-1:0] output_2,
+  output [WIDTH-1:0] output_3,
+  input kick,
+  output reg busy
+ );
+
+  reg [WIDTH-1:0] registers_0;
+  reg [WIDTH-1:0] registers_1;
+  reg [WIDTH-1:0] registers_2;
+  reg [WIDTH-1:0] registers_3;
+
+  assign output_0 = registers_0;
+  assign output_1 = registers_1;
+  assign output_2 = registers_2;
+  assign output_3 = registers_3;
+
+  reg [(32 - 1):0] fsm;
+
+  localparam fsm_init = 0;
+
+  localparam fsm_1 = 1;
+  wire [(WIDTH - 1):0] small_0;
+  wire [(WIDTH - 1):0] large_0;
+  assign small_0 = (((registers_0 < registers_1))? registers_0 : registers_1);
+  assign large_0 = (((registers_0 < registers_1))? registers_1 : registers_0);
+
+  wire [(WIDTH - 1):0] small_1;
+  wire [(WIDTH - 1):0] large_1;
+  assign small_1 = (((large_0 < registers_2))? large_0 : registers_2);
+  assign large_1 = (((large_0 < registers_2))? registers_2 : large_0);
+
+  wire [(WIDTH - 1):0] small_2;
+  wire [(WIDTH - 1):0] large_2;
+  assign small_2 = (((large_1 < registers_3))? large_1 : registers_3);
+  assign large_2 = (((large_1 < registers_3))? registers_3 : large_1);
+
+  localparam fsm_2 = 2;
+  wire [(WIDTH - 1):0] small_3;
+  wire [(WIDTH - 1):0] large_3;
+  assign small_3 = (((registers_0 < registers_1))? registers_0 : registers_1);
+  assign large_3 = (((registers_0 < registers_1))? registers_1 : registers_0);
+
+  wire [(WIDTH - 1):0] small_4;
+  wire [(WIDTH - 1):0] large_4;
+  assign small_4 = (((large_3 < registers_2))? large_3 : registers_2);
+  assign large_4 = (((large_3 < registers_2))? registers_2 : large_3);
+
+  localparam fsm_3 = 3;
+  wire [(WIDTH - 1):0] small_5;
+  wire [(WIDTH - 1):0] large_5;
+  assign small_5 = (((registers_0 < registers_1))? registers_0 : registers_1);
+  assign large_5 = (((registers_0 < registers_1))? registers_1 : registers_0);
+
+  localparam fsm_4 = 4;
+
+  localparam fsm_5 = 5;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      busy <= 0;
+      registers_0 <= 0;
+      registers_1 <= 0;
+      registers_2 <= 0;
+      registers_3 <= 0;
+      fsm <= fsm_init;
+    end else begin
+      case(fsm)
+      fsm_init: begin
+        begin
+          if(kick) begin
+            begin
+              registers_0 <= input_0;
+              registers_1 <= input_1;
+              registers_2 <= input_2;
+              registers_3 <= input_3;
+              busy <= 1;
+              fsm <= fsm_1;
+            end
+          end 
+        end
+      end
+      fsm_1: begin
+        begin
+          registers_0 <= small_0;
+          registers_1 <= small_1;
+          registers_2 <= small_2;
+          registers_3 <= large_2;
+        end
+        fsm <= fsm_2;
+      end
+      fsm_2: begin
+        begin
+          registers_0 <= small_3;
+          registers_1 <= small_4;
+          registers_2 <= large_4;
+          registers_3 <= registers_3;
+        end
+        fsm <= fsm_3;
+      end
+      fsm_3: begin
+        begin
+          registers_0 <= small_5;
+          registers_1 <= large_5;
+          registers_2 <= registers_2;
+          registers_3 <= registers_3;
+        end
+        fsm <= fsm_4;
+      end
+      fsm_4: begin
+        begin
+          registers_0 <= registers_0;
+          registers_1 <= registers_1;
+          registers_2 <= registers_2;
+          registers_3 <= registers_3;
+        end
+        fsm <= fsm_5;
+      end
+      fsm_5: begin
+        busy <= 0;
+        fsm <= fsm_init;
+      end
+      endcase
+    end
+  end
+endmodule
+"""
+
+def test_sort():
+    sort_module = sort.mkSort()
+    sort_code = sort_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == sort_code)