logic

Author: shtaxxx

tests/core/logic/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/core/logic/logic.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+
+def mkLed():
+    m = Module('blinkled')
+    a = m.Input('a')
+    b = m.Input('b')
+    c = m.Input('c')
+    exp = m.Output('exp')
+
+    exp.assign(a & b ^ ~c)
+
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)

tests/core/logic/test_logic.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import logic
+
+expected_verilog = """
+module blinkled
+(
+  input a,
+  input b,
+  input c,
+  output exp
+);
+
+  assign exp = a & b ^ ~c;
+
+endmodule
+"""
+
+def test():
+    veriloggen.reset()
+    test_module = logic.mkLed()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)