diff --git a/.gitmodules b/.gitmodules index 362bc8a..1072404 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "resources"] path = resources - url = https://github.com/PyFPGA/resources + url = https://github.com/PyFPGA/resources.git diff --git a/clean.sh b/clean.sh new file mode 100644 index 0000000..f96b779 --- /dev/null +++ b/clean.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +set -e + +for DIR in */ ; do + if test -f "$DIR/Makefile"; then + make -C $DIR clean + fi +done diff --git a/ghdl-yosys/Makefile b/ghdl-yosys/Makefile new file mode 100644 index 0000000..836c4a5 --- /dev/null +++ b/ghdl-yosys/Makefile @@ -0,0 +1,11 @@ +#!/usr/bin/make + +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash + +all: vhdl vhdl-top vlog-top + +vhdl vhdl-top vlog-top: + $(COMMAND) $@.sh + +clean: + rm -fr *.cf diff --git a/ghdl-yosys/vhdl-top.sh b/ghdl-yosys/vhdl-top.sh new file mode 100644 index 0000000..571f2ad --- /dev/null +++ b/ghdl-yosys/vhdl-top.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +DIR=../resources/mix + +yosys -Q -m ghdl -p " +ghdl $DIR/top.vhdl -e; +read_verilog $DIR/blink.v; +synth -top Top +" diff --git a/ghdl-yosys/vhdl.sh b/ghdl-yosys/vhdl.sh new file mode 100644 index 0000000..9fe4057 --- /dev/null +++ b/ghdl-yosys/vhdl.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -e + +DIR=../resources/vhdl + +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" + +GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" + +ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl +ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl +ghdl -a $FLAGS $DIR/top.vhdl + +yosys -Q -m ghdl -p " +ghdl $FLAGS $GENERICS Top ARCH_SEL; +synth -top Top +" diff --git a/ghdl-yosys/vlog-top.sh b/ghdl-yosys/vlog-top.sh new file mode 100644 index 0000000..5463d46 --- /dev/null +++ b/ghdl-yosys/vlog-top.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +DIR=../resources/mix + +yosys -Q -m ghdl -p " +ghdl $DIR/blink.vhdl -e; +read_verilog $DIR/top.v; +synth -top Top +" diff --git a/ghdl/Makefile b/ghdl/Makefile new file mode 100644 index 0000000..6c6fbfc --- /dev/null +++ b/ghdl/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash + +vhdl: + $(COMMAND) $@.sh + +clean: + rm -fr *.cf diff --git a/ghdl/README.md b/ghdl/README.md new file mode 100644 index 0000000..a328644 --- /dev/null +++ b/ghdl/README.md @@ -0,0 +1,6 @@ +# Notes about GHDL + +> Last update: Nov 2021 + +* Specify a REAL generic is not supported (`unhandled override for generic "rea"`) + * As a workaround, I set SKIP_REA diff --git a/ghdl/vhdl.sh b/ghdl/vhdl.sh new file mode 100644 index 0000000..7273ae4 --- /dev/null +++ b/ghdl/vhdl.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +set -e + +DIR=../resources/vhdl + +FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" + +GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1" + +############################################################################### +# Alternative 1 +############################################################################### + +# This alternative is better to specify particular options per file + +ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl +ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl +ghdl -a $FLAGS $DIR/top.vhdl + +# --out=raw-vhdl generate a VHDL 93 netlist + +ghdl synth $FLAGS --out=raw-vhdl $GENERICS Top ARCH_SEL + +# This alternative creates .cf files + +rm -fr *.cf + +############################################################################### +# Alternative 2 +############################################################################### + +# This alternative is more concise + +# --work= applies to the following files +# --out=verilog generate a Verilog netlist + +ghdl synth $FLAGS --out=verilog $GENERICS \ + --work=blink_lib $DIR/blink.vhdl $DIR/blink_pkg.vhdl \ + --work=work $DIR/top.vhdl -e Top ARCH_SEL diff --git a/openflow/Makefile b/openflow/Makefile deleted file mode 100644 index 18774a5..0000000 --- a/openflow/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/make - -DOCKER_CMD=docker run --rm -it -v $$HOME:$$HOME -w $$PWD ghdl/synth:beta - -COMMAND=bash - -flow ghdl mix params yosys: - $(COMMAND) $@.sh - -clean: - rm -fr *.cf *.edif diff --git a/openflow/flow.sh b/openflow/flow.sh deleted file mode 100644 index 2782ef6..0000000 --- a/openflow/flow.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -############################################################################### - -msg "* Yosys + nextpnr + IceStorm" - -cat ../resources/constraints/edu-ciaa-fpga/clk.pcf ../resources/constraints/edu-ciaa-fpga/led.pcf > edu-ciaa-fpga.pcf - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -p ' -read_verilog -defer ../resources/verilog/blink.v; -synth_ice40 -top Blink -json blink.json -'" - -$DOCKER hdlc/nextpnr:ice40 /bin/bash -c " -nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf edu-ciaa-fpga.pcf --asc blink.asc -" - -rm -f edu-ciaa-fpga.pcf - -$DOCKER hdlc/icestorm /bin/bash -c " -icepack blink.asc blink.bit -icetime -d hx8k -mtr blink.rpt blink.asc -" - -# $DOCKER --device /dev/bus/usb hdlc/prog iceprog blink.bit - -rm -fr *.asc *.bit *.json *.rpt - -################################################################################## - -msg "* Yosys + nextpnr + Trellis" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -p ' -read_verilog -defer ../resources/verilog/blink.v; -synth_ecp5 -top Blink -json blink.json -'" - -$DOCKER hdlc/nextpnr:ecp5 /bin/bash -c " -nextpnr-ecp5 --json blink.json --25k --package CSFBGA285 --lpf ../resources/constraints/orangecrab/clk.lpf --lpf ../resources/constraints/orangecrab/led.lpf --textcfg blink.config -" - -$DOCKER hdlc/prjtrellis /bin/bash -c " -ecppack --svf blink.svf blink.config blink.bit -" - -# $DOCKER --device /dev/bus/usb hdlc/prog openocd -f ${TRELLIS}/misc/openocd/ecp5-evn.cfg -c "transport select jtag; init; svf blink.svf; exit" -# tinyprog -p aux.bit - -rm -fr *.bit *.config *.json *.svf diff --git a/openflow/ghdl.sh b/openflow/ghdl.sh deleted file mode 100644 index c2c6ada..0000000 --- a/openflow/ghdl.sh +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -############################################################################### - -msg "* GHDL Flow" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl -ghdl --synth $FLAGS Top -" - -rm -fr *.cf - -############################################################################### - -msg "* Parameters in GHDL" - -$DOCKER hdlc/ghdl:yosys ghdl -a $FLAGS ../resources/vhdl/generics.vhdl -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" Params -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC="11111111" Params -#$DOCKER hdlc/ghdl:yosys ghdl --synth $FLAGS -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gREA=1.1 Params - -rm -fr *.cf diff --git a/openflow/mix.sh b/openflow/mix.sh deleted file mode 100644 index 2ecf68e..0000000 --- a/openflow/mix.sh +++ /dev/null @@ -1,54 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -function synth () { -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -yosys -Q -m ghdl -p ' -ghdl $FLAGS $1 -e; -read_verilog $2; -synth_ice40 -top $3 -json blink.json -'" > /dev/null -} - -############################################################################### - -msg "* Verilog Top" -synth "../resources/mix/blink.vhdl" "../resources/mix/top.v" "Top" - -msg "* VHDL Top" -synth "../resources/mix/top.vhdl" "../resources/mix/blink.v" "Top" - -############################################################################### - -msg "* Verilog Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a ../resources/mix/blink.vhdl -yosys -Q -m ghdl -p ' -ghdl Blink; -read_verilog ../resources/mix/top.v; -synth_ice40 -top Top -json blink.json -'" > /dev/null - -rm -fr *.cf *.edif *.json - -msg "* VHDL Top (alternative)" - -$DOCKER hdlc/ghdl:yosys /bin/bash -c " -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl -ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl -ghdl -a $FLAGS ../resources/vhdl/top.vhdl -yosys -Q -m ghdl -p ' -ghdl $FLAGS Top; -synth_xilinx -family xc7; -write_edif -pvector bra yosys.edif -'" > /dev/null - -rm -fr *.cf *.edif *.json diff --git a/openflow/yosys.sh b/openflow/yosys.sh deleted file mode 100644 index 6c3eb08..0000000 --- a/openflow/yosys.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/bash - -set -e - -DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" - -function msg () { tput setaf 6; echo "$1"; tput sgr0; } - -################################################################################# - -msg "* Yosys Flow" - -$DOCKER hdlc/ghdl:yosys yosys -Q -p ' -verilog_defaults -add -I../resources/verilog/path1; -verilog_defaults -add -I../resources/verilog/path2; -read_verilog -defer ../resources/verilog/paths.v; -synth_xilinx -top Paths -family xc7; -write_edif -pvector bra yosys.edif -' - -rm -fr *.edif - -############################################################################### - -msg "* Parameters in Yosys" - -$DOCKER hdlc/ghdl:yosys yosys -Q -p " -read_verilog -defer ../resources/verilog/parameters.v; -chparam -set BOO 1 -set INT 255 -set LOG 1 -set VEC 8'b11111111 -set STR \"WXYZ\" -set REA \"1.1\" Params -" diff --git a/resources b/resources index c6b2a78..6a58bba 160000 --- a/resources +++ b/resources @@ -1 +1 @@ -Subproject commit c6b2a782e78e4ca3628ef81d3665a780628600d9 +Subproject commit 6a58bba3b1c36d238d1111e910db02f0b284aef7 diff --git a/vivado/Makefile b/vivado/Makefile index 075452b..24673e5 100644 --- a/vivado/Makefile +++ b/vivado/Makefile @@ -2,7 +2,9 @@ COMMAND=vivado -mode batch -notrace -quiet -source -flow params: +all: vhdl vlog + +vhdl vlog prog detect: $(COMMAND) $@.tcl version: @@ -10,4 +12,4 @@ version: clean: rm -fr *.bit *.cache *.hw *.runs *.xpr *.jou *.ip_user_files - rm -fr *.html *.log *.txt *.xml .Xil + rm -fr *.html *.log *.txt *.xml .Xil *.zip diff --git a/vivado/README.md b/vivado/README.md new file mode 100644 index 0000000..e342dcf --- /dev/null +++ b/vivado/README.md @@ -0,0 +1,17 @@ +# Notes about Vivado + +> Last update: Vivado 2021.2 + +* FREQ=125MHz to match the employed clock of the ZYBO. + +VHDL: +* Support to specify a REAL generic was added/fixed in the Vivado 2020.2 version + * https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 +* Specify an architecture is supported, but not working + * https://support.xilinx.com/s/question/0D52E00006r9kHiSAI/specify-a-vhdl-architecture-seems-not-working + * As a workaround, I set SKIP_ARCH +* Values are specified following Verilog notation. + * In case of character, is needed to specify the ASCII value + +Verilog: +* `$finish` is ignored, but fortunatly `$error("some text")` produces the desired result. diff --git a/vivado/flow.tcl b/vivado/flow.tcl deleted file mode 100644 index 35fee20..0000000 --- a/vivado/flow.tcl +++ /dev/null @@ -1,21 +0,0 @@ -create_project -force example - -set_property "part" xc7z010-1-clg400 [current_project] - -add_files ../resources/vhdl/blink.vhdl -add_files ../resources/constraints/zybo/clk.xdc -add_files ../resources/constraints/zybo/led.xdc - -set_property top Blink [current_fileset] - -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -launch_runs impl_1 -wait_on_run impl_1 - -open_run impl_1 -write_bitstream -force example - -close_project diff --git a/vivado/params.tcl b/vivado/params.tcl deleted file mode 100644 index 16eb079..0000000 --- a/vivado/params.tcl +++ /dev/null @@ -1,30 +0,0 @@ -create_project -force example - -set_property "part" xc7z010-1-clg400 [current_project] - -# When specifying binary values for boolean or std_logic VHDL generic types, -# you must specify the value using the Verilog bit format, rather than -# standard VHDL format. - -add_files ../resources/verilog/parameters.v -set_property top Params [current_fileset] -set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] - -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -# To avoid re-synthesis of the Verilog version -remove_files [get_files] - -add_files ../resources/vhdl/generics.vhdl -set_property top Params [current_fileset] -# NOTE: support to specify a REAL generic (VHDL) was added into the Vivado 2020.2 version -# https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581 -set_property "generic" "BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 STR=WXYZ REA=1.1" -objects [get_filesets sources_1] - -reset_run synth_1 -launch_runs synth_1 -wait_on_run synth_1 - -close_project diff --git a/vivado/prog.tcl b/vivado/prog.tcl new file mode 100644 index 0000000..fa9c537 --- /dev/null +++ b/vivado/prog.tcl @@ -0,0 +1,14 @@ +if { [ catch { open_hw_manager } ] } { open_hw } +connect_hw_server +open_hw_target + +puts "* Devices detected in the JTAG chain" +puts [get_hw_devices] + +puts "* Programming the FPGA" + +set obj [lindex [get_hw_devices [current_hw_device]] 0] +set_property PROGRAM.FILE project.bit $obj +program_hw_devices $obj + +puts "* Done" diff --git a/vivado/vhdl.tcl b/vivado/vhdl.tcl new file mode 100644 index 0000000..29d6840 --- /dev/null +++ b/vivado/vhdl.tcl @@ -0,0 +1,33 @@ +create_project -force vhdl-project + +set_property "part" xc7z010-1-clg400 [current_project] + +add_files ../resources/vhdl/blink.vhdl +set_property library blink_lib [get_files ../resources/vhdl/blink.vhdl] + +add_files ../resources/vhdl/blink_pkg.vhdl +set_property library blink_lib [get_files ../resources/vhdl/blink_pkg.vhdl] + +add_files ../resources/vhdl/top.vhdl +add_files ../resources/constraints/zybo/clk.xdc +add_files ../resources/constraints/zybo/led.xdc + +set_property top Top [current_fileset] +set_property top_arch ARCH_SEL [current_fileset] + +set GENERICS "FREQ=125000000 BOO=true INT=255 LOG=1'b1 VEC=8'b11111111 CHR=8'd90 STR=WXYZ REA=1.1 SKIP_ARCH=1" +set_property "generic" $GENERICS -objects [get_filesets sources_1] + +set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] + +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 + +launch_runs impl_1 +wait_on_run impl_1 + +open_run impl_1 +write_bitstream -force project + +close_project diff --git a/vivado/vlog.tcl b/vivado/vlog.tcl new file mode 100644 index 0000000..9467322 --- /dev/null +++ b/vivado/vlog.tcl @@ -0,0 +1,31 @@ +create_project -force vlog-project + +set_property "part" xc7z010-1-clg400 [current_project] + +add_files ../resources/vlog/blink.v + +add_files ../resources/vlog/top.v +add_files ../resources/constraints/zybo/clk.xdc +add_files ../resources/constraints/zybo/led.xdc + +set_property top Top [current_fileset] + +set_property verilog_define {ARCH_SEL=1 FREQ=125000000} [current_fileset] + +set_property "include_dirs" "../resources/vlog/path1 ../resources/vlog/path2" [current_fileset] + +set_property "generic" "BOO=1 INT=255 LOG=1'b1 VEC=8'b11111111 CHR=Z STR=WXYZ REA=1.1" -objects [get_filesets sources_1] + +set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] + +reset_run synth_1 +launch_runs synth_1 +wait_on_run synth_1 + +launch_runs impl_1 +wait_on_run impl_1 + +open_run impl_1 +write_bitstream -force project + +close_project diff --git a/yosys/Makefile b/yosys/Makefile new file mode 100644 index 0000000..4f532c6 --- /dev/null +++ b/yosys/Makefile @@ -0,0 +1,13 @@ +#!/usr/bin/make + +COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash + +all: vlog + +vlog: + $(COMMAND) $@.sh + +clean: + rm -fr *.cf + make -C icestorm clean + make -C trellis clean diff --git a/yosys/README.md b/yosys/README.md new file mode 100644 index 0000000..cf1b90d --- /dev/null +++ b/yosys/README.md @@ -0,0 +1,6 @@ +# Notes about Yosys + +> Last update: Nov 2021 + +* Specify a REAL parameter is not supported (`ERROR: Can't decode value '1.1'!`) + * As a workaround, I set SKIP_REA diff --git a/yosys/icestorm/Makefile b/yosys/icestorm/Makefile new file mode 100644 index 0000000..01b1fbf --- /dev/null +++ b/yosys/icestorm/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +all: vlog + +vlog prog: + bash $@.sh + +clean: + rm -fr *.asc *.bit *.json *.rpt *.pcf diff --git a/yosys/icestorm/prog.sh b/yosys/icestorm/prog.sh new file mode 100644 index 0000000..539e9b8 --- /dev/null +++ b/yosys/icestorm/prog.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER --device /dev/bus/usb hdlc/prog iceprog blink.bit diff --git a/yosys/icestorm/vlog.sh b/yosys/icestorm/vlog.sh new file mode 100644 index 0000000..d463228 --- /dev/null +++ b/yosys/icestorm/vlog.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +cat ../../resources/constraints/icestick/clk.pcf ../../resources/constraints/icestick/led.pcf > icestick.pcf + +$DOCKER hdlc/ghdl:yosys /bin/bash -c " +yosys -Q -p ' +read_verilog -defer ../../resources/vlog/blink.v; +synth_ice40 -top Blink -json blink.json +'" + +$DOCKER hdlc/nextpnr:ice40 /bin/bash -c " +nextpnr-ice40 --json blink.json --hx8k --package tq144:4k --pcf icestick.pcf --asc blink.asc +" + +$DOCKER hdlc/icestorm /bin/bash -c " +icepack blink.asc blink.bit +icetime -d hx8k -mtr blink.rpt blink.asc +" diff --git a/yosys/trellis/Makefile b/yosys/trellis/Makefile new file mode 100644 index 0000000..53756b8 --- /dev/null +++ b/yosys/trellis/Makefile @@ -0,0 +1,9 @@ +#!/usr/bin/make + +all: vlog + +vlog prog: + bash $@.sh + +clean: + rm -fr *.bit *.config *.json *.svf diff --git a/yosys/trellis/prog.sh b/yosys/trellis/prog.sh new file mode 100644 index 0000000..7035499 --- /dev/null +++ b/yosys/trellis/prog.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER --device /dev/bus/usb hdlc/prog openocd -f ${TRELLIS}/misc/openocd/ecp5-evn.cfg -c "transport select jtag; init; svf blink.svf; exit" +# tinyprog -p aux.bit diff --git a/yosys/trellis/vlog.sh b/yosys/trellis/vlog.sh new file mode 100644 index 0000000..eaf8030 --- /dev/null +++ b/yosys/trellis/vlog.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +set -e + +DOCKER="docker run --rm -v $HOME:$HOME -w $PWD" + +$DOCKER hdlc/ghdl:yosys /bin/bash -c " +yosys -Q -p ' +read_verilog -defer ../../resources/vlog/blink.v; +synth_ecp5 -top Blink -json blink.json +'" + +$DOCKER hdlc/nextpnr:ecp5 /bin/bash -c " +nextpnr-ecp5 --json blink.json --25k --package CSFBGA285 --lpf ../../resources/constraints/orangecrab/clk.lpf --lpf ../../resources/constraints/orangecrab/led.lpf --textcfg blink.config +" + +$DOCKER hdlc/prjtrellis /bin/bash -c " +ecppack --svf blink.svf blink.config blink.bit +" diff --git a/yosys/vlog.sh b/yosys/vlog.sh new file mode 100644 index 0000000..d561bd6 --- /dev/null +++ b/yosys/vlog.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +set -e + +yosys -Q -p ' +verilog_defaults -add -I../resources/vlog/path1; +verilog_defaults -add -I../resources/vlog/path2; +verilog_defines -DARCH_SEL=1; +read_verilog -defer ../resources/vlog/blink.v; +read_verilog -defer ../resources/vlog/top.v; +chparam -set BOO 1 -set INT 255 -set LOG 1 -set VEC 255 -set CHR "Z" -set STR "WXYZ" -set SKIP_REA 1 Top; +synth -top Top +'