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set -e
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- FLAGS= " --std=08 -fsynopsys -fexplicit -frelaxed "
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+ DIR=../resources/vhdl
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- ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink.vhdl
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- ghdl -a $FLAGS --work=blink_lib ../resources/vhdl/blink_pkg.vhdl
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- ghdl -a $FLAGS ../resources/vhdl/top.vhdl
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+ FLAGS=" --std=08 -fsynopsys -fexplicit -frelaxed"
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GENERICS=" -gBOO=true -gINT=255 -gLOG='1' -gVEC=" 11111111" -gCHR='Z' -gSTR=" WXYZ" -gSKIP_REA=1"
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- ghdl --synth $FLAGS $GENERICS Top ARCH_SEL
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+
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+ # ##############################################################################
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+ # Alternative 1
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+ # ##############################################################################
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+
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+ # This alternative is better to specify particular options per file
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+
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+ ghdl -a $FLAGS --work=blink_lib $DIR /blink.vhdl
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+ ghdl -a $FLAGS --work=blink_lib $DIR /blink_pkg.vhdl
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+ ghdl -a $FLAGS $DIR /top.vhdl
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+
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+ ghdl synth $FLAGS $GENERICS Top ARCH_SEL
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+
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+ # This alternative creates .cf files due the ghdl -a
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+ rm -fr * .cf
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+
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+ # ##############################################################################
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+ # Alternative 2
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+ # ##############################################################################
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+
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+ # This alternative is more concise
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+
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+ # --work=<LIBNAME> applies to the following files
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+ # The output in this case is a synthesized Verilog (VHDL is the default)
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+
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+ ghdl synth $FLAGS --out=verilog $GENERICS \
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+ --work=blink_lib $DIR /blink.vhdl $DIR /blink_pkg.vhdl \
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+ --work=work $DIR /top.vhdl -e Top ARCH_SEL
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