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target/ppc: Implement hashst(p) and hashchk(p) instructions
Implementation for instructions hashst, hashchk, and its privileged versions. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
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Lines changed: 147 additions & 0 deletions

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‎linux-headers/asm-powerpc/kvm.h‎

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@@ -646,6 +646,9 @@ struct kvm_ppc_cpu_char {
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#define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
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#define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
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#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
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/* FIXME: KVM hasn't exposed these registers yet */
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#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
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#define KVM_REG_PPC_HASHPKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
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/* Transactional Memory checkpointed state:
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* This is all GPRs, all VSX regs and a subset of SPRs

‎target/ppc/cpu.h‎

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@@ -1674,6 +1674,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
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#define SPR_BOOKE_GIVOR14 (0x1BD)
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#define SPR_TIR (0x1BE)
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#define SPR_PTCR (0x1D0)
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#define SPR_POWER_HASHKEYR (0x1D4)
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#define SPR_POWER_HASHPKEYR (0x1D5)
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#define SPR_BOOKE_SPEFSCR (0x200)
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#define SPR_Exxx_BBEAR (0x201)
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#define SPR_Exxx_BBTAR (0x202)

‎target/ppc/cpu_init.c‎

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@@ -6478,6 +6478,13 @@ static void init_proc_POWER10(CPUPPCState *env)
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spr_read_generic, spr_write_generic,
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KVM_REG_PPC_PSSCR, 0);
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spr_register_kvm(env, SPR_POWER_HASHKEYR, "HASHPKEYR",
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SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_HASHKEYR, 0x0);
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spr_register_kvm(env, SPR_POWER_HASHPKEYR, "HASHPKEYR",
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SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_HASHPKEYR, 0x0);
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/* env variables */
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env->dcache_line_size = 128;
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env->icache_line_size = 128;

‎target/ppc/excp_helper.c‎

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Original file line numberDiff line numberDiff line change
@@ -2172,6 +2172,92 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
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#endif
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#endif
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static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
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{
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uint32_t c = 0xfffc;
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uint64_t z0 = 0xfa2561cdf44ac398;
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uint16_t z = 0, temp;
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uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
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for (int i = 3; i >= 0; i--) {
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k[i] = key & 0xffff;
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key >>= 16;
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}
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xleft[0] = x & 0xffff;
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xright[0] = (x >> 16) & 0xffff;
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for (int i = 0; i < 28; i++) {
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z |= ((z0 >> (63 - i)) & 1) << 48;
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temp = ror16(k[i + 3], 3) ^ k[i + 1];
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k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
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}
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for (int i = 0; i < 8; i++)
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{
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eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
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eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
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eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
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eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
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}
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for (int i = 0; i < 32; i++)
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{
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fxleft[i] = (rol16(xleft[i], 1) &
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rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
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xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
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xright[i + 1] = xleft[i];
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}
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return (((uint32_t)xright[32]) << 16) | xleft[32];
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}
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2214+
/* TODO: check this implementation correctness; make it better */
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static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
2216+
{
2217+
uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
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uint64_t stage1_h, stage1_l;
2219+
2220+
for (int i = 0; i < 4; i++) {
2221+
stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
2222+
stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
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stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i +1));
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stage0_l |= (ra & 0xff) << (8 * 2 * i);
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rb >>= 8;
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ra >>= 8;
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}
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stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
2230+
stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
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stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
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stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
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return (stage1_h ^ stage1_l);
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}
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2237+
#define HELPER_HASH(op, key, store) \
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void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
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target_ulong rb) \
2240+
{ \
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uint64_t chash = hash_digest(ra, rb, key), lhash; \
2242+
\
2243+
if (store) { \
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cpu_stq_data_ra(env, ea, chash, GETPC()); \
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} \
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else { \
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lhash = cpu_ldq_data_ra(env, ea, GETPC()); \
2248+
if (lhash != chash) { \
2249+
/* hashes don't match, trap */ \
2250+
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, \
2251+
POWERPC_EXCP_TRAP, GETPC()); \
2252+
} \
2253+
} \
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}
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2256+
HELPER_HASH(HASHST, env->spr[SPR_POWER_HASHKEYR], true)
2257+
HELPER_HASH(HASHCHK, env->spr[SPR_POWER_HASHKEYR], false)
2258+
HELPER_HASH(HASHSTP, env->spr[SPR_POWER_HASHPKEYR], true)
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HELPER_HASH(HASHCHKP, env->spr[SPR_POWER_HASHPKEYR], false)
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#if !defined(CONFIG_USER_ONLY)
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#ifdef CONFIG_TCG

‎target/ppc/helper.h‎

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Original file line numberDiff line numberDiff line change
@@ -4,6 +4,10 @@ DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
44
#if defined(TARGET_PPC64)
55
DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
66
#endif
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DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
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DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
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DEF_HELPER_4(HASHSTP, void, env, tl, tl, tl)
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DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
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#if !defined(CONFIG_USER_ONLY)
812
DEF_HELPER_2(store_msr, void, env, tl)
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DEF_HELPER_1(rfi, void, env)

‎target/ppc/insn32.decode‎

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@@ -142,6 +142,9 @@
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@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
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@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
144144

145+
%x_dw 0:1 21:5 !function=dw_compose_ea
146+
@X_DW ...... ..... ra:5 rb:5 .......... . &X rt=%x_dw
147+
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&X_frtp_vrb frtp vrb
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@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
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@@ -281,6 +284,13 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
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PDEPD 011111 ..... ..... ..... 0010011100 - @X
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PEXTD 011111 ..... ..... ..... 0010111100 - @X
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287+
# Fixed-Point Hash Instructions
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289+
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
290+
HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
291+
HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
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HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
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### Float-Point Load Instructions
285295

286296
LFS 110000 ..... ..... ................ @D

‎target/ppc/translate.c‎

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@@ -6547,6 +6547,12 @@ static int times_16(DisasContext *ctx, int x)
65476547
return x * 16;
65486548
}
65496549

6550+
static int64_t dw_compose_ea(DisasContext *ctx, int x)
6551+
{
6552+
int64_t ea = 0xfffffffffffffe00 | (x << 3);
6553+
return ea;
6554+
}
6555+
65506556
/*
65516557
* Helpers for trans_* functions to check for specific insns flags.
65526558
* Use token pasting to ensure that we use the proper flag with the

‎target/ppc/translate/fixedpoint-impl.c.inc‎

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Original file line numberDiff line numberDiff line change
@@ -492,3 +492,32 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
492492
#endif
493493
return true;
494494
}
495+
496+
static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
497+
void (*helper)(TCGv_ptr, TCGv, TCGv, TCGv))
498+
{
499+
TCGv ea = tcg_temp_new();
500+
501+
if (!(ctx->insns_flags2 & PPC2_ISA310)) {
502+
/* if version is before v3.1, this operation is a nop */
503+
return true;
504+
}
505+
506+
if (unlikely(priv && ctx->pr)) {
507+
/* if instruction is privileged but the context is in user space */
508+
gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
509+
return 0;
510+
}
511+
512+
tcg_gen_addi_tl(ea, cpu_gpr[a->ra], a->rt);
513+
helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
514+
515+
tcg_temp_free(ea);
516+
517+
return true;
518+
}
519+
520+
TRANS(HASHST, do_hash, false, gen_helper_HASHST)
521+
TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
522+
TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
523+
TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)

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