We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Setting DC size to 16K causes some vector size warnings, and fails sim (X's after ~1K cycles).
`ifdef DC_32 `define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported `define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ `define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE `else `define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported `define DC_SIZE 14 // 14 => 16K L1D$, 15 => 32K L1D$ `define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE `endif
The text was updated successfully, but these errors were encountered:
No branches or pull requests
Setting DC size to 16K causes some vector size warnings, and fails sim (X's after ~1K cycles).
The text was updated successfully, but these errors were encountered: