Hardware documentation

[wimalopaan]

The other day I stumbled across kind of HW documentation: it was a table describing the connection of the µC pins.

Unfortunately I can't find that ressource anymore.

Maybe one can link that into the wiki?

[ajjjjjjjj]

Was it this one?
stmicroelectronics-stm32f072c8t7-datasheets-0135.pdf

[wimalopaan]

No, I mean a Excel or OO sheet with the connection on the i6x mainboard and some explanation.

[wimalopaan]

I'm noit familiar with the F0 series. But in common/arm/stm32/aux_serial_driver.cpp the DMA is only activated it it is not a F0 series MCU. The datasheet list a 7-channel dma controller. So: are all channels used? This kind of docu I'm looking for also.

[ajjjjjjjj]

I have only this (shared by @marianomd )

---

DMA

Channel 2: TX1, TX3
Channel 3: RX1, RX3
Channel 4: TX1, TX2
Channel 5: RX1, RX2
Channel 6: RX2, RX3, RX4
Channel 7: TX2, TX3, TX4

---

Exposed PADS

PB8 TIM16_CH1, I2C1_SCL
PB9 TIM17_CH1, I2C1_SDA

USARTS

PA9 USART1_TX
PA10 USART1_RX

PD5 USART2_TX
PA15 USART2_RX

[wimalopaan]

Ok, that's a beginning!

Is there a survey regarding the timers? (I need a 1ms timer like in EdgeTx)

[ajjjjjjjj]

Timers are defined in board.cpp: 2MHz and 5ms one. In EdgeTX 1ms is only for hall gimballs pulling, i wonder why is it needed here? Is functionality you're trying to implement already in EdgeTX/OpenTX to take a look?

[wimalopaan]

Thank you.
I need this, for the SBUS parsing code. This part is wrong in EdgeTx as i can*t detect psauses < 5ms (Some receivers produce only 5ms pauses inSBus protocol. Whithout the pause Sbus can't be parsed unabigously) (I make a PR in EdgeTx which added also the possibility to accept IBus: IBus is a non-inverted proto so no one needs an inverter).
A 2ms timer will be also ok.

[ajjjjjjjj]

Hi @wimalopaan , i have done some research.
There is a third UART exposed on the unpopulated module on right side of PCB, which may make DMA possible using Channels 6 and 7:

PC10    USART3/4_TX
PC11    USART3/4_RX

Fell free to change 5ms timer to 2ms one.