uart.sv

`timescale 1ns/1ps

`include "uart_reader.sv"
`include "uart_writer.sv"


module uart(
  input logic clk, rst_i, RXD,
  output logic TXD,
  output logic [5:0] led,
  output logic tmds_clk_p,
  output logic tmds_clk_n
  );


logic [7:0] bits;
logic end_read, end_write, error_read;
logic led_state = 0;

uart_reader uart_reader(
    .clk(clk),
    .reset(!rst_i),
    .rx(RXD),
    .bits(bits),
    .clk_per_tick(32'd2808),
    .end_transmission(end_read),
    .error(error_read)
);

uart_writer uart_writer(
    .clk(clk),
    .reset(!rst_i),
    .tx(TXD),
    .start_transmission(end_read),
    .bits(bits),
    .clk_per_tick(32'd2808),
    .end_transmission(end_write),
    .error(error_write)
);
always_ff @(posedge clk)
  if(end_read)
    led_state = ~led_state;

always_comb
begin
  tmds_clk_p = RXD;
  tmds_clk_n = bits[0];
end


endmodule